Potential clamping silicon carbide floating island device with zero dynamic resistance degradation
By introducing P-type locally heavily doped semiconductor floating islands into silicon carbide floating island devices and utilizing built-in potential clamping to achieve hole transport, the problem of dynamic resistance rise during the switching process of silicon carbide floating island devices is solved, achieving zero dynamic resistance degradation and excellent breakdown voltage-on resistance relationship, and reducing switching losses.
Patent Information
- Application Number
- CN202511739089.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-02-24
AI Technical Summary
Existing silicon carbide floating island devices exhibit a significant increase in dynamic resistance during switching, leading to increased switching losses and making it difficult to achieve an excellent trade-off between breakdown voltage and on-resistance.
A potential-clamped silicon carbide floating island device with zero dynamic resistance degradation is designed. By introducing P-type locally heavily doped semiconductor floating islands into an N-type doped semiconductor epitaxial layer, potential clamping is achieved using the built-in potential, allowing hole transport, reducing the number of ion implantation-epitaxy processes, and simplifying the manufacturing process.
This achieves a difference of less than 1% between the dynamic resistance of the device after the switching process and the static resistance before the switching process, thus improving the contradictory relationship between breakdown voltage and on-resistance, reducing switching losses, and enhancing the static and dynamic characteristics of the device.
Smart Images
Figure CN121568418A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon carbide power device technology, and in particular to a potential-clamped silicon carbide floating island device with zero dynamic resistance degradation. Background Technology
[0002] With the continuous development of power electronics technology, an increasing number of fields, such as aerospace, military, and new energy, are demanding power semiconductor devices that operate under extreme environments such as high temperature, high voltage, high frequency, high power, and strong radiation. First-generation semiconductor devices, represented by silicon, have matured in terms of structural design, layout optimization, and manufacturing processes, with their performance approaching or even exceeding the theoretical limits of silicon materials. Further breakthroughs in device performance are difficult, and significant reliability risks exist, limiting the development of power devices. Therefore, it is necessary to find new materials to meet the high-performance requirements of power semiconductor devices in today's power electronics development.
[0003] Silicon carbide (SiC), as a promising semiconductor material, has been widely used in high-voltage, high-temperature power devices due to its superior physical properties, including wide bandgap characteristics and excellent thermal conductivity. Compared with traditional silicon-based devices, SiC power devices have significantly improved the trade-off between breakdown voltage and characteristic on-resistance, thus achieving better performance indicators. To break the "SiC limit," many innovative methods have been proposed, such as superjunction (SJ) and floating island structures. SJ structures effectively modulate the electric field distribution, further increasing the doping concentration in the drift region, thereby achieving better breakdown voltage (BV) and characteristic on-resistance (R). on,sp A better trade-off can be achieved between [the two]. However, due to the relatively immature manufacturing process and the low diffusion rate of dopants in SiC, the fabrication of superjunction devices becomes more complex and challenging. Floating island devices, as an alternative, allow for the use of thicker epitaxial layers, effectively reducing the number of ion implantation-epitaxy processes, thus simplifying the manufacturing process while maintaining excellent device performance. However, during switching, floating island devices experience a significant increase in dynamic resistance and switching losses because holes within the floating islands cannot be continuously transported through adjacent floating islands. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a potential-clamped silicon carbide floating island device with zero dynamic resistance degradation. This potential-clamped silicon carbide floating island device with zero dynamic resistance degradation can achieve a difference of less than 1% between the dynamic resistance after the switching process and the static resistance before the switching process, that is, to achieve zero dynamic resistance degradation. At the same time, it improves the contradictory relationship between the device's breakdown voltage and on-resistance.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0006] A potential-clamped silicon carbide floating island device with zero dynamic resistance degradation includes an N-type doped semiconductor epitaxial layer, a P-type doped semiconductor well, and M P-type locally heavily doped semiconductor floating islands; wherein M≥2.
[0007] P-type doped semiconductor wells are arranged on top of N-type doped semiconductor epitaxial layers.
[0008] M P-type locally heavily doped semiconductor floating islands are arranged at equal intervals from top to bottom within the N-type doped semiconductor epitaxial layer below the P-type doped semiconductor well; wherein, the upper surface of the top P-type locally heavily doped semiconductor floating island is in contact with the lower surface of the P-type doped semiconductor well.
[0009] Each P-type locally heavily doped semiconductor island includes a bottom island region, a middle island region, and a top island region arranged from bottom to top; wherein the P-type doping concentration of the bottom island region and the top island region is greater than that of the middle island region.
[0010] M = 2~10. When the breakdown voltage of the device increases, the value of M increases accordingly.
[0011] Let the vertical depth of each P-type locally heavily doped semiconductor floating island be H, and the vertical depths of the bottom floating island region, the middle floating island region, and the top floating island region be H1, H2, and H3, respectively; then the settings of H1, H2, and H3 must simultaneously satisfy the following requirements:
[0012] H1 < H2 and H1 < 0.4H
[0013] H3 < H2 and H2 < 0.4H.
[0014] Assume the spacing between two adjacent P-type locally heavily doped semiconductor floating islands is 1. ,but:
[0015]
[0016] In the formula, The width of the depletion region formed by the bottom floating island region and the N-type doped semiconductor epitaxial layer.
[0017] The width of the depletion region formed by the top floating island region and the N-type doped semiconductor epitaxial layer.
[0018] H1=H3, the P-type doping concentration is equal in the bottom floating island region and the top floating island region.
[0019] Let the difference between the P-type doping concentration in the bottom or top floating island region and the P-type doping concentration in the middle floating island region be _____. ,but The method for obtaining the optimal value includes the following steps:
[0020] Step A: Design several values that gradually increase in size. and several more in succession value.
[0021] Step B, Build each The degree of degradation of dynamic on-resistance varies with different The change curve A.
[0022] Step C: Compare each variation curve A with the set zero dynamic resistance degradation line to obtain the variation curves A that do not exceed the zero dynamic resistance degradation line. Quantity A; will The curves corresponding to the largest number of variations A The value is recorded as better. ; will be better The maximum value located at the zero dynamic resistance degradation line , recorded as The optimal value.
[0023] By designing several N-type doped semiconductor epitaxial layers with gradually increasing concentrations, each optimal layer is constructed. The curve B representing the variation of device quality factor with different N-type doped semiconductor epitaxial layer concentrations is selected; the curve B corresponding to the highest device quality factor is chosen. Record as best and will be the best The N-type doped semiconductor epitaxial layer concentration corresponding to the highest point of device quality factor is denoted as the optimal N-type doped semiconductor epitaxial layer concentration.
[0024] In step A, several values gradually increase. They are respectively: 0cm -3 0.5 10 12 cm -3 1.5 10 13 cm -3 and 2.5 10 13 cm -3 Several increasing ones The values are 0µm, 0.1µm, 0.2µm, 0.3µm, 0.4µm, 0.5µm, 0.6µm, 0.7µm, 0.8µm, 0.9µm and 1µm, respectively.
[0025] In step C, the preferred method is... 0.5 respectively 1012 cm -3 1.5 10 13 cm -3 and 2.5 10 13 cm -3 ; The optimal value is 0.5µm; the concentrations of several N-type doped semiconductor epitaxial layers range from 0.5 to 6 cm⁻¹. -3 Between 0.5 cm -3 The optimal value is obtained by taking 10 concentration values in ascending order. It is 0.5 10 12 cm -3 The optimal N-type doped semiconductor epitaxial layer concentration is 4.5 cm⁻¹. -3 .
[0026] All bottom, middle, and top floating island regions have the same width, and none exceed the width of the P-type doped semiconductor well.
[0027] The present invention has the following beneficial effects:
[0028] 1. This invention introduces P-type locally heavily doped semiconductor floating islands into an N-type doped semiconductor epitaxial layer, thereby increasing the concentration difference and built-in potential between the P-type locally heavily doped semiconductor floating islands and the N-type doped semiconductor epitaxial layer. This results in the complete depletion of the N-type doped semiconductor epitaxial layer between the P-type locally heavily doped semiconductor floating islands under static conditions, thus achieving potential clamping. Holes can be transported through the built-in potential, thereby achieving zero dynamic on-resistance degradation of the device.
[0029] 2. The locally heavily doped floating island-assisted depletion drift region in this invention allows the doping concentration of the N-type doped semiconductor epitaxial layer to increase further, thereby improving the contradictory relationship between the device breakdown voltage and on-resistance.
[0030] 3. Compared with superjunction devices, the present invention reduces the number of ion implantation-epitaxy processes and has better static and dynamic characteristics, while achieving zero dynamic resistance degradation and low loss during switching. Attached Figure Description
[0031] Figure 1 A schematic diagram of the structure of a potential-clamped silicon carbide floating island device with zero dynamic resistance degradation (the device provided in this embodiment) of the present invention is shown.
[0032] Figure 2 A schematic diagram of the structure of a conventional SiC superjunction device (conventional device) is shown.
[0033] Figure 3Showing different and different Below, the embodiments of the present invention provide a curve of the dynamic resistance degradation degree of the device.
[0034] Figure 4 The diagram shows a comparison of the breakdown voltage and on-resistance of the device provided in this embodiment under different doping concentrations of the N-type doped semiconductor epitaxial layer.
[0035] Figure 5 The figure shows a comparison of the quality factor of the device provided in this embodiment under different doping concentrations of N-type doped semiconductor epitaxial layers.
[0036] Figure 6 The forward conduction and blocking characteristics of the device provided in this embodiment are shown.
[0037] Figure 7 The reverse recovery capacitance characteristics of the device provided in this embodiment are shown.
[0038] Figure 8 This diagram shows a partial N-type doped semiconductor epitaxial layer growth completed in step 1.
[0039] Figure 9 This diagram shows the bottom region of the fourth floating island of the P-type locally heavily doped semiconductor after step 2 has been fabricated.
[0040] Figure 10 This diagram shows the completed fabrication of the central region of the fourth floating island of the P-type locally heavily doped semiconductor in step 3.
[0041] Figure 11 This diagram shows the top region of the fourth floating island of the P-type locally heavily doped semiconductor after step 4 has been fabricated.
[0042] Figure 12 The diagram shows the completed fabrication of the first, second, and third floating islands of the P-type locally heavily doped semiconductor in step 7.
[0043] Figure 13 The diagram shows a schematic after step 8, in which an N-type doped semiconductor epitaxial layer is grown and the gate trench is etched.
[0044] Figure 14 The diagram shows the result after the P-type doped semiconductor shielding layer is fabricated in step 9.
[0045] Figure 15 This diagram shows the result after the P-type doped semiconductor well is fabricated in step 10.
[0046] Figure 16 This diagram shows the completed fabrication of the P-type doped semiconductor ohmic contact region in step 11.
[0047] Figure 17 This diagram shows a complete N-type doped semiconductor source contact region fabrication in step 12.
[0048] Figure 18 The diagram shows the result after the first deposition of the insulating medium in step 13 is completed.
[0049] Figure 19 This diagram shows the result after the gate metal deposition is completed in step 14.
[0050] Figure 20 The diagram shows the result after the secondary deposition of the insulating medium in step 15 is completed.
[0051] Figure 21 This diagram shows a complete deposition of the source and drain metals in step 16.
[0052] Among them are:
[0053] 1. Drain metal; 2. N-type doped semiconductor substrate; 3. N-type doped semiconductor epitaxial layer; 4. Bottom floating island region; 5. Middle floating island region; 6. Top floating island region; 7. P-type doped semiconductor columnar strip; 8. P-type doped semiconductor shielding layer; 9. P-type doped semiconductor well; 10. P-type doped semiconductor ohmic contact region; 11. N-type doped semiconductor source contact region; 12. Insulating dielectric; 13. Gate metal; 14. Source metal. Detailed Implementation
[0054] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.
[0055] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.
[0056] like Figure 2 As shown, a conventional SiC superjunction device, also known as a conventional device, includes a drain metal 1, an N-type doped semiconductor substrate 2, an N-type doped semiconductor epitaxial layer 3, a P-type doped semiconductor columnar strip 7, a P-type doped semiconductor shielding layer 8, a P-type doped semiconductor well 9, an N-type doped semiconductor source contact region 10, a P-type doped semiconductor ohmic contact region 11, an insulating dielectric 12, a gate metal 13, and a source metal 14.
[0057] The drain metal, N-type doped semiconductor substrate, N-type doped semiconductor epitaxial layer, P-type doped semiconductor well and source metal are arranged sequentially from bottom to top.
[0058] The gate trench is located to the right of the P-type doped semiconductor well, and its bottom extends into the N-type doped semiconductor epitaxial layer directly below it. The trench is filled with an insulating dielectric, and the depth of the gate trench is greater than the depth of the P-type doped semiconductor well.
[0059] The gate metal is suspended in an insulating medium, and its vertical depth exceeds that of the P-type doped semiconductor well. The width of the gate metal is smaller than the width of the gate trench; therefore, the gate metal does not directly contact the P-type doped semiconductor well.
[0060] The N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region are arranged side by side on the top of the P-type doped semiconductor well. The right side of the N-type doped semiconductor source contact region is in close contact with the left side of the P-type doped semiconductor ohmic contact region, and both are completely surrounded by the P-type doped semiconductor well.
[0061] The insulating medium filling the gate trench is preferably SiO2.
[0062] The aforementioned conventional devices feature P-type doped semiconductor pillars 7 disposed in an N-type doped semiconductor epitaxial layer beneath the P-type doped semiconductor well. This effectively modulates the electric field distribution, further increasing the doping concentration in the drift region, thereby achieving a better trade-off between breakdown voltage and characteristic on-resistance. However, conventional SiC superjunction devices are often fabricated through multiple epitaxial-ion implantation processes, a relatively immature manufacturing process. Furthermore, the low diffusion rate of dopants in SiC makes device fabrication more complex and challenging. Additionally, the N-type doped semiconductor epitaxial layer has a small thickness and a low breakdown voltage.
[0063] like Figure 1 As shown, a potential-clamped silicon carbide floating island device with zero dynamic resistance degradation, also known as the device provided in this embodiment, includes a drain metal 1, an N-type doped semiconductor substrate 2, an N-type doped semiconductor epitaxial layer 3, M locally heavily doped P-type semiconductor floating islands, a P-type doped semiconductor shielding layer 8, a P-type doped semiconductor well 9, an N-type doped semiconductor source contact region 10, a P-type doped semiconductor ohmic contact region 11, an insulating dielectric 12, a gate metal 13, and a source metal 14. The structural design of the drain metal 1, N-type doped semiconductor substrate 2, N-type doped semiconductor epitaxial layer 3, P-type doped semiconductor shielding layer 8, P-type doped semiconductor well 9, N-type doped semiconductor source contact region 10, P-type doped semiconductor ohmic contact region 11, insulating dielectric 12, gate metal 13, and source metal 14 is similar to... Figure 2 The traditional components are basically the same, so I will not go into details here.
[0064] Furthermore, the upper surface of the P-type doped semiconductor shielding layer and the lower surface of the gate trench are in close contact, and its width is greater than or equal to the width of the gate trench. In this embodiment, the width of the P-type doped semiconductor shielding layer is set to be equal to the width of the gate trench, and the doping concentration is preferably 1×10⁻⁶. 17 cm -3 .
[0065] The number of P-type locally heavily doped semiconductor floating islands, M ≥ 2, preferably M = 2~10. The value of M increases accordingly as the device breakdown voltage increases. In this embodiment, the device breakdown voltage is designed to be 1200V, so M = 4. The four P-type locally heavily doped semiconductor floating islands are, from top to bottom, designated as the first floating island, the second floating island, the third floating island, and the fourth floating island.
[0066] M P-type locally heavily doped semiconductor floating islands are arranged at equal intervals from top to bottom. The N-type doped semiconductor epitaxial layer is arranged in the form of a P-type doped semiconductor well below the N-type doped semiconductor well; wherein the upper surface of the top P-type locally heavily doped semiconductor island is in contact with the lower surface of the P-type doped semiconductor well.
[0067] Each P-type locally heavily doped semiconductor island includes a bottom island region 4, a middle island region 5, and a top island region 6 arranged from bottom to top.
[0068] The widths of the bottom floating island region, the middle floating island region, and the top floating island region are preferably equal and do not exceed the width of the P-type doped semiconductor well.
[0069] Let the vertical depth of each P-type locally heavily doped semiconductor floating island be H, and the vertical depths of the bottom floating island region, the middle floating island region, and the top floating island region be H1, H2, and H3, respectively; then the settings of H1, H2, and H3 must simultaneously satisfy the following requirements:
[0070] H1 < H2 and H1 < 0.4H
[0071] H3 < H2 and H2 < 0.4H.
[0072] The P-type doping concentrations in the bottom and top floating island regions are both greater than those in the middle floating island region.
[0073] The device provided in this embodiment introduces P-type locally heavily doped semiconductor floating islands into the N-type doped semiconductor epitaxial layer, which increases the concentration difference and built-in potential between the P-type locally heavily doped semiconductor floating islands and the N-type doped semiconductor epitaxial layer. Under static conditions, the N-type doped semiconductor epitaxial layer between adjacent P-type locally heavily doped semiconductor floating islands is completely depleted, thereby achieving potential clamping. Holes can be transported through the built-in potential, thus achieving zero dynamic on-resistance degradation of the device.
[0074] Let the width of the depletion region formed by the bottom floating island region and the N-type doped semiconductor epitaxial layer be . The width of the depletion region formed by the top floating island region and the N-type doped semiconductor epitaxial layer is ,but and The calculation formulas are as follows:
[0075]
[0076]
[0077] in:
[0078]
[0079]
[0080] In the formula, k is the Boltzmann constant, T is the ambient temperature, and n i denoted as the intrinsic carrier concentration of SiC, and denoted as a constant.
[0081] V bi1 V is the built-in potential of the bottom floating island region; bi2 This represents the built-in potential of the top floating island region.
[0082] N A1 The P-type doping concentration in the bottom floating island region; N A2 This represents the P-type doping concentration in the top floating island region.
[0083] N D ε represents the concentration of the N-type doped semiconductor epitaxial layer; s q is the dielectric constant of SiC; q is the elementary charge.
[0084] a1 is the slope of the net doping concentration as a function of spatial position; where net doping is the absolute value of the difference between the P-type doping concentration and the N-type doped semiconductor epitaxial layer concentration in the bottom floating island region.
[0085] a2 is the slope of the net doping concentration as a function of spatial position; where net doping concentration is the absolute value of the difference between the P-type doping concentration and the N-type doped semiconductor epitaxial layer concentration in the top floating island region.
[0086] Under the premise of achieving zero dynamic on-resistance degradation of the device, the above The following conditions must be met:
[0087]
[0088] In this embodiment, H1=H3=0.25H is preferred, and the P-type doping concentration is equal in the bottom floating island region and the top floating island region, both being 1×10⁻⁶. 17 cm -3 ,thus, = = , .
[0089] This invention selects the best This allows for the optimal thickness of the N-type doped semiconductor epitaxial layer, thereby improving the breakdown voltage. Let the difference between the P-type doping concentration in the bottom or top floating island region and the P-type doping concentration in the middle floating island region be _____. ,but The method for obtaining the optimal value includes the following steps.
[0090] Step A: Design several values that gradually increase in size. and several more in succession Values. In this embodiment, several values gradually increase. They are respectively: 0cm -3 0.5 10 12 cm -3 1.5 10 13 cm -3 and 2.5 10 13 cm -3 Several increasing ones The values are 0µm, 0.1µm, 0.2µm, 0.3µm, 0.4µm, 0.5µm, 0.6µm, 0.7µm, 0.8µm, 0.9µm and 1µm, respectively.
[0091] Step B, Build each The degree of degradation of dynamic on-resistance varies with different The change curve A, as shown Figure 3 As shown.
[0092] Step C: Compare each variation curve A with the set zero dynamic resistance degradation line to obtain the variation curves A that do not exceed the zero dynamic resistance degradation line. Quantity A; will The curves corresponding to the largest number of variations A The value is recorded as better. ; will be better The maximum value located at the zero dynamic resistance degradation line , recorded as The optimal value.
[0093] In this embodiment Figure 3 In the middle, with ∆D pi As the dynamic on-resistance of the device increases, its degradation becomes increasingly significant. Traditional devices, due to the connection between their superjunction pillars and source, do not exhibit this dynamic resistance degradation issue. Therefore, when the dynamic resistance degradation of the device provided in this embodiment is less than that of the superjunction device, it is considered to have achieved zero dynamic resistance degradation. Figure 3 It can be seen that 0.5 10 12 cm -3 1.5 10 13 cm -3 and 2.5 10 13 cm -3 The corresponding change curve A contains six curves that do not exceed the zero dynamic resistance degradation line. Quantity A, and 0cm -3 The corresponding change curve A contains only four curves that do not exceed the zero dynamic resistance degradation line. Quantity A, therefore, is better 0.5 respectively 10 12 cm -3 1.5 10 13 cm -3 and 2.5 10 13 cm -3 , The optimal value is 0.5µm, at which point dynamic on-resistance degradation will not occur.
[0094] Next, by designing several N-type doped semiconductor epitaxial layers with gradually increasing concentrations, preferably 0.5~6 cm⁻¹ in this embodiment. -3 Between 0.5 cm -3 Ten concentration values were selected in ascending order.
[0095] Then, a comparison chart of the breakdown voltage and on-resistance of devices under different N-type doped semiconductor epitaxial layer doping concentrations is constructed, as follows: Figure 4 As shown. In Figure 4 In (a), as the doping concentration of the N-type doped semiconductor epitaxial layer increases, the breakdown voltage of the device shows a trend of first increasing and then decreasing. When the doping concentration of the N-type doped semiconductor epitaxial layer is 4.5 × 10⁻⁶, the breakdown voltage... 16 cm -3 At this point, the device's breakdown voltage is at its highest, reaching 1991V. For example... Figure 4 As shown in (b), with the increase of the doping concentration of the N-type doped semiconductor epitaxial layer, ∆Dpi The increase has a relatively small impact on the specific on-resistance of the device.
[0096] Furthermore, reconstruct each better The device quality factor curve B, under the given value, varies with the concentration of different N-type doped semiconductor epitaxial layers, as shown in Figure B. Figure 5 As shown; select the curve B corresponding to the highest component quality factor. Record as best and will be the best The N-type doped semiconductor epitaxial layer concentration corresponding to the highest device quality factor is denoted as the optimal N-type doped semiconductor epitaxial layer concentration. Figure 5 In the middle, 0.5 10 12 cm -3 In an N-type doped semiconductor epitaxial layer with a concentration of 4.5 cm⁻¹ -3 The breakdown voltage at that time, and the quality factor can reach 2318 MW / cm. 2 Compared to the 1699 MW / cm² of traditional devices 2 Significantly improved, therefore optimal It is 0.5 10 12 cm -3 The optimal N-type doped semiconductor epitaxial layer concentration is 4.5 cm⁻¹. -3 .
[0097] In summary, the P-type locally heavily doped semiconductor floating islands in this invention, which assist in the depletion drift region, allow for a further increase in the doping concentration of the N-type doped semiconductor epitaxial layer, thereby improving the contradictory relationship between the device's breakdown voltage and on-resistance. Furthermore, since the device provided in this embodiment can increase the maximum distance between adjacent P-type locally heavily doped semiconductor floating islands to 0.5 μm while maintaining zero dynamic resistance degradation, the epitaxial thickness of the device is thicker than that of conventional devices, enabling the achievement of a higher breakdown voltage. The device's forward conduction and reverse blocking characteristics are as follows: Figure 6 As shown.
[0098] The reverse recovery capacitance characteristics of the device are as follows Figure 7 As shown. Due to the depletion of the partitions of the P-type locally heavily doped semiconductor floating islands, they exhibit lower reverse recovery capacitance, which means that the device provided in this embodiment can achieve faster switching speeds.
[0099] A method for fabricating a potential-clamped silicon carbide floating island device with zero dynamic resistance degradation includes the following steps.
[0100] Step 1: Growing a partial N-type doped semiconductor epitaxial layer: such as Figure 8 As shown, an N-type doped semiconductor epitaxial layer of a predetermined thickness is epitaxially grown on an N-type doped semiconductor substrate.
[0101] Step 2: Prepare the bottom region of the fourth floating island in a P-type locally heavily doped semiconductor: such as Figure 9 As shown, for the device prepared in step 1, a specific ion implantation mask layer is formed on the left side of its upper surface, and high-dose ion implantation is performed to form the bottom region of the fourth floating island of the P-type locally heavily doped semiconductor.
[0102] Step 3: Prepare the central region of the fourth floating island in a P-type locally heavily doped semiconductor: (e.g., ...) Figure 10 As shown, for the device prepared in step 2, ion implantation is performed according to the mask layer formed in step 2 to form the central region of the fourth floating island of the P-type locally heavily doped semiconductor.
[0103] Step 4: Prepare the top region of the fourth floating island in a P-type locally heavily doped semiconductor: as shown in the figure. Figure 11 As shown, for the device prepared in step 3, ion implantation is performed according to the mask layer formed in step 2 to form the top region of the fourth floating island of the P-type locally heavily doped semiconductor. The mask layer is then removed, and then high-temperature annealing is performed.
[0104] Step 5: Fabricate the first, second, and third floating islands of the P-type locally heavily doped semiconductor: as follows Figure 12 As shown, repeat steps 1 to 4 above to complete the fabrication of the first, second, and third floating islands of the P-type locally heavily doped semiconductor.
[0105] Step 6: Continue epitaxial growth of the N-type doped semiconductor epitaxial layer and etching to form the gate trench: (e.g.) Figure 13 As shown, for the device formed in step 5, SiC is epitaxially grown on its upper surface to a set thickness, and then a specific etching mask layer is formed on the right side of its upper surface. The gate trench is formed by etching using the etching mask layer.
[0106] Step 7: Prepare a P-type doped semiconductor shielding layer: such as Figure 14 As shown, for the device formed in step 6, ion implantation is performed at the bottom of the gate trench to form a P-type doped semiconductor shielding layer, followed by high-temperature annealing.
[0107] Step 8: Fabricate a P-type doped semiconductor well: such as Figure 15 As shown, a specific ion implantation mask layer is formed on the upper surface of the device formed in step 7, and then ion implantation is performed to form a P-type doped semiconductor well. After removing the mask layer, high-temperature annealing is performed.
[0108] Step 9: Prepare the p-type doped semiconductor ohmic contact region: such as Figure 16 As shown, for the device formed in step 8, a specific ion implantation mask layer is formed on the left side of its upper surface, high-dose ion implantation is performed to form a P-type doped semiconductor ohmic contact region, the mask layer is removed, and then high-temperature annealing is performed.
[0109] Step 10: Prepare the N-type doped semiconductor source contact region: such as Figure 17 As shown, for the device formed in step 9, a specific ion implantation mask layer is formed on its upper surface, high-dose ion implantation is performed to form an N-type doped semiconductor source contact region, the mask layer is removed, and then high-temperature annealing is performed.
[0110] Step 11, First deposition of gate insulating dielectric: such as Figure 18 As shown, the gate insulating dielectric is deposited once in the gate trench by chemical vapor deposition, and then the gate insulating dielectric is etched into an L-shaped form.
[0111] Step 12, Deposit metal gate: such as Figure 19 As shown, a metal gate is deposited on an L-shaped gate insulating dielectric, such that its upper surface is flush with the upper surface of the L-shaped gate insulating dielectric.
[0112] Step 13, Secondary deposition of gate insulating dielectric: such as Figure 20 As shown, a secondary deposition of the gate insulating dielectric is performed, causing the metal gate to suspend in the insulating dielectric.
[0113] Step 14, Deposit the metal source and metal drain: as follows Figure 21 As shown, for the device formed in step 13, a metal source electrode is deposited on its upper surface, and a metal drain electrode is deposited on the bottom surface of the N-type doped semiconductor substrate.
[0114] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.
Claims
1. A potential-clamped silicon carbide floating island device with zero dynamic resistance degradation, characterized in that: It includes an N-type doped semiconductor epitaxial layer, a P-type doped semiconductor well, and M locally heavily doped P-type semiconductor floating islands; where M ≥ 2. P-type doped semiconductor wells are arranged on top of N-type doped semiconductor epitaxial layers; M P-type locally heavily doped semiconductor floating islands are arranged at equal intervals from top to bottom within the N-type doped semiconductor epitaxial layer below the P-type doped semiconductor well; wherein, the upper surface of the top P-type locally heavily doped semiconductor floating island is in contact with the lower surface of the P-type doped semiconductor well. Each P-type locally heavily doped semiconductor island includes a bottom island region, a middle island region, and a top island region arranged from bottom to top; wherein the P-type doping concentration of the bottom island region and the top island region is greater than that of the middle island region.
2. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 1, characterized in that: M = 2~10. When the breakdown voltage of the device increases, the value of M increases accordingly.
3. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 1, characterized in that: Let the vertical depth of each P-type locally heavily doped semiconductor floating island be H, and the vertical depths of the bottom floating island region, the middle floating island region, and the top floating island region be H1, H2, and H3, respectively; then the settings of H1, H2, and H3 must simultaneously satisfy the following requirements: H1 < H2 and H1 < 0.4H H3 < H2 and H2 < 0.4H.
4. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 3, characterized in that: Assume the spacing between two adjacent P-type locally heavily doped semiconductor floating islands is 1. ,but: ； In the formula, The width of the depletion region formed by the bottom floating island region and the N-type doped semiconductor epitaxial layer; The width of the depletion region formed by the top floating island region and the N-type doped semiconductor epitaxial layer.
5. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 4, characterized in that: H1=H3, the P-type doping concentration is equal in the bottom floating island region and the top floating island region.
6. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 5, characterized in that: Let the difference between the P-type doping concentration in the bottom or top floating island region and the P-type doping concentration in the middle floating island region be _____. ,but The method for obtaining the optimal value includes the following steps: Step A: Design several values that gradually increase. and several more in succession value; Step B, Build each The degree of degradation of dynamic on-resistance varies with different The change curve A; Step C: Compare each variation curve A with the set zero dynamic resistance degradation line to obtain the variation curves A that do not exceed the zero dynamic resistance degradation line. Quantity A; will The curves corresponding to the largest number of variations A The value is recorded as better. ; will be better The maximum value located at the zero dynamic resistance degradation line , recorded as The optimal value.
7. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 6, characterized in that: By designing several N-type doped semiconductor epitaxial layers with gradually increasing concentrations, each optimal layer is constructed. The curve B representing the variation of device quality factor with different N-type doped semiconductor epitaxial layer concentrations is selected; the curve B corresponding to the highest device quality factor is chosen. Record as best and will be the best The N-type doped semiconductor epitaxial layer concentration corresponding to the highest point of device quality factor is denoted as the optimal N-type doped semiconductor epitaxial layer concentration.
8. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 6 or 7, characterized in that: In step A, several values gradually increase. They are respectively: 0cm -3 0.5 10 12 cm -3 1.5 10 13 cm -3 and 2.5 10 13 cm -3 Several increasing ones The values are 0µm, 0.1µm, 0.2µm, 0.3µm, 0.4µm, 0.5µm, 0.6µm, 0.7µm, 0.8µm, 0.9µm and 1µm, respectively.
9. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 8, characterized in that: In step C, the preferred method is... 0.5 respectively 10 12 cm -3 1.5 10 13 cm -3 and 2.5 10 13 cm -3 ; The optimal value is 0.5µm; the concentrations of several N-type doped semiconductor epitaxial layers range from 0.5 to 6 cm⁻¹. -3 Between 0.5 cm -3 The optimal value is obtained by taking 10 concentration values in ascending order. It is 0.5 10 12 cm -3 The optimal N-type doped semiconductor epitaxial layer concentration is 4.5 cm⁻¹. -3 .
10. The potential-clamped silicon carbide floating island device with zero dynamic resistance degradation according to claim 1, characterized in that: All bottom, middle, and top floating island regions have the same width, and none exceed the width of the P-type doped semiconductor well.