Lateral indium phosphide diode based on tunnel junction and preparation method thereof

Abstract

The invention discloses a lateral indium phosphide diode based on a tunnel junction and a preparation method of the lateral indium phosphide diode. The indium phosphide diode comprises a wafer and a diode structure, an n-type electrode and a p-type electrode are arranged above the diode structure; the wafer sequentially comprises a seed crystal layer, a buried oxide layer and a substrate from top to bottom; and the diode structure laterally extends above the buried oxide layer. The device has the characteristics of high performance and low preparation difficulty.

Description

Technical Field

[0001] This invention relates to the field of integrated optoelectronic devices and semiconductor materials technology, specifically to a lateral indium phosphide diode based on a tunnel junction and its fabrication method. Background Technology

[0002] Lateral selective epitaxy (LSE) technology allows for the tight integration of high-quality III-V material optoelectronic devices on silicon or III-V substrates, and has received widespread attention from academia and industry since its inception. Represented by IBM's Template-Assisted Selective Epitaxy (TASE) and the Lateral Aspect Ratio Trapping (LART) technology proposed by the Hong Kong University of Science and Technology (HKUST), these technologies utilize MOCVD processes to selectively grow III-V materials on Si or InP wafers, providing a feasible path for the monolithic integration of InP lasers (LDs) or photodetectors (PDs). Lateral selective epitaxy (DSE) technology can directly construct InP lateral pin structures on Si or InP wafers through a single epitaxy step. Compared with traditional vertical pin structures, lateral pin structures not only ensure sufficient distance between the optical mode field and the metal electrode in the lateral direction, effectively suppressing metal absorption losses, but also enable thin-film devices with a thickness of less than 350 nm. This allows the effective refractive index of III-V devices to be well matched with 220 nm silicon waveguides, thus ensuring compatibility with mainstream silicon optoelectronic platforms. Furthermore, compared to the bonding process widely used in the industry, lateral selective epitaxy technology offers a simpler process path and lower manufacturing costs. Bonding processes, such as the lateral indium phosphide buried heterojunction (BH) thin-film laser developed by NTT in Japan, involve a complex and cumbersome process, requiring multiple steps including two MOCVD epitaxial growths, bonding, etching, and doping. This not only results in high manufacturing costs, a narrow process window, and low yield, but also limits large-scale production due to the size of the indium phosphide wafer. In contrast, lateral selective epitaxy (LSE) technology can directly grow a complete InP lateral pin diode structure on a large-size silicon or InP wafer by constructing a lateral epitaxy template and then using a single-step MOCVD process. This greatly simplifies the process flow, reduces manufacturing costs, and enables monolithic integration of InP material devices that are highly compatible with silicon photonics platforms.

[0003] However, a key challenge in achieving the growth of lateral indium phosphide (IP) pin diodes lies in the difficulty of obtaining highly conductive p-type heavily doped InP using the MOCVD process. MOCVD systems typically use Zn as the p-type dopant source. While Zn doping offers good doping control, it is prone to doping saturation in InP materials, making it difficult to exceed 2 × 10⁻⁶ holes. 18 / cm3 This is far lower than the 5 × 10⁻⁶ required for a low-resistance ohmic contact between a metal electrode and p-type InP. 18 / cm 3 The high p-type contact resistance, due to insufficient p-type doping concentration in MOCVD, severely impacts the injection efficiency of indium phosphide (IP) side-mounted diode lasers and the responsivity of IPT photodiodes. While some studies using heavily doped p-type InGaAs as a contact layer to replace p-type InP in InP-based photodetectors via MOCVD have attempted this approach, the polycrystalline structure of InGaAs easily leads to compositional inhomogeneities, resulting in bandgap and affecting carrier transport efficiency. Furthermore, the high refractive index of InGaAs introduces additional light absorption losses, making this method less than ideal. In summary, the performance of devices based on lateral epitaxy is limited by insufficient p-type InP doping concentration in MOCVD processes, leading to excessively high contact resistance between p-metal and p-type InP. This severely affects carrier transport and significantly suppresses the photoelectric conversion efficiency of side-mounted diode devices such as lasers and photodetectors, becoming one of the core constraints for achieving high-performance IPT diode devices using current lateral epitaxy technology. Summary of the Invention

[0004] To address the technical problem of existing lateral indium phosphide diodes based on MOCVD epitaxy processes, which struggle to achieve an effective p-type heavily doped InP contact layer, resulting in difficulties in forming a low-resistance ohmic contact between the metal and p-type InP, severely limiting the carrier transport efficiency of lateral diode devices and thus affecting the photoelectric conversion performance of lateral indium phosphide diode lasers and photodetectors, this invention provides a lateral indium phosphide diode based on a tunnel junction and its fabrication method. The technical solution adopted by this invention is as follows: The first aspect of the present invention provides a lateral indium phosphide diode based on a tunnel junction, comprising a wafer and a diode structure; an n-type electrode and a p-type electrode are provided on the top of the diode structure; the wafer comprises a seed layer, a buried oxide layer and a substrate from top to bottom; the diode structure is laterally epitaxial on the buried oxide layer.

[0005] As a preferred embodiment, the wafer is an SOI wafer or an InPOI wafer.

[0006] As a preferred embodiment, the diode structure comprises, from left to right, an n-type contact layer, a device layer, and a tunnel junction.

[0007] As a preferred embodiment, the tunneling junction, from left to right, includes p + -InP layer, p ++ -InGaAs layer, p-region contact layer; wherein, the p +The InP layer uses diethylzinc as the doping source, with a doping concentration of 2 × 10⁻⁶. 18 cm -3 The p ++ The InGaAs layer uses diethylzinc as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 .

[0008] As a preferred embodiment, the n-type contact layer includes a first n ++ -InP layer, the first n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The p-region contact layer includes a second n ++ -InP layer, the second n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The n-type electrode forms an ohmic contact with the n-type contact layer, and the p-type electrode forms an ohmic contact with the p-region contact layer.

[0009] As a preferred embodiment, the device layer is a photodetector device layer containing intrinsic InGaAs or a laser device layer containing an InGaAs quantum well structure with multiple i-InP spacings.

[0010] As a preferred embodiment, the thickness of the photodetector device layer containing intrinsic InGaAs is 200 nm.

[0011] As a preferred embodiment, the laser device layer comprising an InGaAs quantum well structure with multiple i-InP spacings includes n - -InP layer, i-InP layer, i-InGaAs quantum well active region containing seven pairs of i-InP spacers, and p - -InP layer.

[0012] A second aspect of the present invention provides a method for fabricating a lateral indium phosphide diode based on a tunnel junction, applicable to the aforementioned lateral indium phosphide diode based on a tunnel junction, comprising the following steps: S1: A pattern template for the lateral epitaxy of a diode structure is prepared on a substrate using photolithography, dry etching, chemical vapor deposition, and wet etching. S2: Using an MOCVD system, an n-type contact layer, a device layer, and a p-type contact layer are sequentially epitaxially grown laterally on the pattern template. + -InP layer, p ++ -InGaAs layer, p-region contact layer; S3: Etch the cladding layer of the epitaxial template to expose the laterally epitaxial diode structure and planarize the wafer; S4: Electrode patterns are exposed above the diode structure by photolithography, and metal is deposited above the n-type contact layer and p-type contact layer to form n-type and p-type electrodes using electron beam evaporation and lift-off processes.

[0013] As a preferred embodiment, in step S3, the method of etching the cladding layer of the epitaxial template to expose the laterally epitaxial diode structure and planarizing the wafer includes: The coating layer of the epitaxial template is etched using a dry etching process to expose the lateral epitaxial diode structure, and the wafer is planarized using benzocyclobutene resin.

[0014] Compared with the prior art, the beneficial effects of this invention are: This invention employs a low-cost, all-epitaxy process to fabricate lateral indium phosphide (INP) diodes. It utilizes lateral epitaxy to achieve device performance comparable to lateral pin structures fabricated using bonding techniques, while significantly simplifying the process and reducing manufacturing costs. Traditional bonding processes are complex, requiring multiple steps including epitaxial growth, wafer bonding, etching, epitaxial re-growth, n-type doping via ion implantation, and p-type doping via diffusion. This process is cumbersome, and high-yield heterobonding demands stringent requirements for material interface cleanliness and process conditions, resulting in a narrow process window, high manufacturing costs, and difficulty in meeting the demands of large-scale integration. In contrast, this invention achieves the growth of all device material layers through a single MOCVD lateral epitaxy step, exhibiting excellent scalability and enabling the large-scale fabrication of high-performance lateral InP lasers and photodetectors on large-size Si-based or InP-based substrates.

[0015] The invention introduces p + -InP、p ++ -InGaAs and the second n ++ The tunneling junction formed by InP can significantly improve the hole transport efficiency of devices, thereby enhancing the performance of related side-biased diodes. In side-biased InP laser devices operating under forward bias, the tunneling junction can significantly improve both electrical injection efficiency and luminous efficiency. In photodetectors operating under reverse bias, this structure can also improve hole extraction efficiency and detector response performance. Furthermore, the design of this tunneling junction structure allows both electrodes to use n⁺⁺-InP as the contact layer, making it easier to achieve low ohmic resistance in the fabricated n-type metal contacts, significantly reducing heat dissipation. Simultaneously, both the n-type and p-type electrodes can use the same metal as the electrode material, enabling simultaneous fabrication of both electrodes through a single-step photolithography and metallization process, further simplifying the overall process flow. Attached Figure Description

[0016] Figure 1 A schematic diagram of a lateral indium phosphide diode based on a tunnel junction is provided for Example 1 (the device layer includes an intrinsic InGaAs layer). Figure 2 A schematic diagram of a lateral indium phosphide diode based on a tunnel junction is provided for Example 2 (the device layer includes an InGaAs quantum well structure with multiple i-InP spacings). Figure 3 This embodiment provides a flowchart of a method for fabricating a lateral indium phosphide diode based on a tunnel junction. Figure 4 This is a schematic diagram of a fabrication method for a lateral indium phosphide diode based on a tunnel junction provided in this embodiment; Figure 5 The linear coordinate IV characteristic curve of the indium phosphide diode provided in this embodiment; Figure 6 The indium phosphide diode provided in this embodiment has an IV characteristic curve on a logarithmic coordinate system. Explanation of reference numerals in the attached figures: 1. Substrate; 2. Buried oxide layer; 3. Seed layer; 4. n-type contact layer; 5. n - 6. i-InP layer; 7. i-InGaAs quantum well active region; 8. p - -InP layer; 9, p + -InP layer; 10, p ++ -InGaAs layer; 11. p-region contact layer; 12. benzocyclobutene resin; 13. n-type electrode; 14. p-type electrode; 15. silicon oxide coating layer. Detailed Implementation

[0017] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the invention. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of the embodiments of this application.

[0018] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0019] In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims. In the description of this application, it should be understood that the terms "first," "second," "third," etc., are used only to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. The invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] Example 1 Please refer to Figure 1 This embodiment provides a lateral indium phosphide diode based on a tunnel junction, including a wafer and a diode structure; an n-type electrode and a p-type electrode are provided on the top of the diode structure; the wafer consists of a seed layer, a buried oxide layer and a substrate from top to bottom; the diode structure is laterally epitaxial on the buried oxide layer.

[0023] Specifically, the buried oxide layer is silicon dioxide.

[0024] Specifically, the n-type electrode and the p-type electrode are made of gold.

[0025] In one specific embodiment, the wafer is an SOI wafer or an InPOI wafer.

[0026] In one specific embodiment, the diode structure includes, from left to right, an n-type contact layer, a device layer, and a tunnel junction.

[0027] In one specific embodiment, the tunnel junction includes p from left to right. + -InP layer, p ++ -InGaAs layer, p-region contact layer; wherein, the p + The InP layer uses diethylzinc as the doping source, with a doping concentration of 2 × 10⁻⁶. 18 cm-3 The p ++ The InGaAs layer uses diethylzinc as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 .

[0028] In one specific embodiment, the n-type contact layer includes a first n ++ -InP layer, the first n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The p-region contact layer includes a second n ++ -InP layer, the second n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The n-type electrode forms an ohmic contact with the n-type contact layer, and the p-type electrode forms an ohmic contact with the p-region contact layer.

[0029] In one specific embodiment, the device layer is a photodetector device layer containing intrinsic InGaAs.

[0030] In one specific embodiment, the thickness of the photodetector device layer containing intrinsic InGaAs is 200 nm.

[0031] Example 2 Please refer to Figure 2 This embodiment provides a lateral indium phosphide diode based on a tunnel junction, including a wafer and a diode structure; an n-type electrode 13 and a p-type electrode 14 are provided on the top of the diode structure; the wafer consists of a seed layer 3, a buried oxide layer 2 and a substrate 1 from top to bottom; the diode structure is laterally extended above the buried oxide layer 2.

[0032] Specifically, the n-type electrode 13 and the p-type electrode 14 are made of gold.

[0033] In one specific embodiment, the wafer is an SOI wafer or an InPOI wafer.

[0034] In one specific embodiment, the diode structure includes, from left to right, an n-type contact layer 4, a device layer, and a tunnel junction.

[0035] In one specific embodiment, the tunnel junction includes p from left to right. + -InP layer 9, p ++ -InGaAs layer 10, p-region contact layer 11; wherein, the p +-InP layer 9 uses diethylzinc as the doping source, with a doping concentration of 2×10⁻⁶. 18 cm -3 The p ++ -InGaAs layer 10 uses diethylzinc as the doping source, with a doping concentration of 2×10⁻⁶. 19 cm -3 .

[0036] In one specific embodiment, the n-type contact layer 4 includes a first n ++ -InP layer, the first n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The p-region contact layer 11 includes a second n ++ -InP layer, the second n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The n-type electrode 13 forms an ohmic contact with the n-type contact layer 4, and the p-type electrode 14 forms an ohmic contact with the p-region contact layer 11.

[0037] In one specific embodiment, the device layer is a laser device layer comprising an InGaAs quantum well structure with multiple i-InP spacings.

[0038] In one specific embodiment, the laser device layer comprising an InGaAs quantum well structure with multiple i-InP spacings includes n - -InP layer 5, i-InP layer 6, i-InGaAs quantum well active region 7 containing seven pairs of i-InP spaced apart, and p - -InP layer 8.

[0039] Example 3 Please refer to Figure 1 as well as Figure 3 This embodiment provides a method for fabricating a lateral indium phosphide diode based on a tunnel junction, applied to the lateral indium phosphide diode based on a tunnel junction described in Embodiment 1, including the following steps: S1: A pattern template for the lateral epitaxy of a diode structure is prepared on a substrate using photolithography, dry etching, chemical vapor deposition, and wet etching. S2: Using an MOCVD system, an n-type contact layer, a device layer, and a p-type contact layer are sequentially epitaxially grown laterally on the pattern template. + -InP layer 9, p ++ -InGaAs layer 10, p-region contact layer 11; Specifically, a MOCVD system is used to sequentially grow doped cells with a doping concentration of 2×10⁻⁶. 19 cm -3 The first n with a width of approximately 1~2 μm ++ -The InP layer serves as the n-type contact layer 4. The device layer is designed according to the device type, with a doping concentration of 2 × 10⁻⁶. 18 cm -3 p with a width of approximately 100 nm to 1 μm + -InP layer 9, doping concentration is 2×10⁻⁶ 19 cm -3 p with a width of approximately 10 nm ++ -InGaAs layer 10, doping concentration 2×10⁻⁶ 19 cm -3 The second n with a width of 1~2 μm ++ -InP layer, to obtain a lateral indium phosphide diode structure with tunnel junction. If it is to prepare a photodetector diode suitable for communication band, the device layer is an intrinsic InGaAs layer with a width of 200 nm. S3: Etch the cladding layer of the epitaxial template to expose the laterally epitaxial diode structure and planarize the wafer; S4: Electrode patterns are exposed above the diode structure by photolithography, and metal is deposited above the n-type contact layer 4 and the p-type contact layer 11 to form n-type electrode 13 and p-type electrode 14 using electron beam evaporation and lift-off processes.

[0040] Example 4 Please refer to Figure 2 , 3 4. This embodiment provides a method for fabricating a lateral indium phosphide diode based on a tunnel junction, applied to the lateral indium phosphide diode based on a tunnel junction described in Embodiment 2, including the following steps: S1: A pattern template for the lateral epitaxy of a diode structure is prepared on substrate 1 using photolithography, dry etching, chemical vapor deposition and wet etching. Specifically, using maskless photolithography and inductively coupled plasma etching (ICP etching) processes, the top silicon layer of the wafer is etched into a strip-shaped silicon block with a width of approximately 15 μm and a length of tens of micrometers. The thickness of the top silicon layer of the substrate is the industry standard of 220 nm. Then, a silicon oxide cladding layer with a thickness of approximately 800 nm is deposited using an inductively coupled plasma chemical vapor deposition (ICPCVD) system. After baking in a nitrogen environment at a temperature of approximately 1000℃ for 45 min in an annealing furnace, the silicon is made harder. Using maskless photolithography and reactive ion etching (RIE) processes, a window with a width of 5 μm and a length of tens of micrometers is obtained at one end of the silicon block. Then, tetramethylammonium hydroxide (TMAH) is used to anisotropically etch the silicon. Under constant temperature conditions of 70℃, the {111} crystal plane is etched through the window of the silicon block and drilled to a depth of 5-6 μm to obtain a pattern template for the lateral epitaxial growth of indium phosphide diodes.

[0041] S2: Using an MOCVD system, n-type contact layer 4, device layer, and p-type contact layer are sequentially epitaxially grown laterally on the pattern template. + -InP layer 9, p ++ -InGaAs layer 10, p-region contact layer 11; Specifically, an MOCVD system was used to sequentially grow fibers with a width of approximately 2500 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 The first n ++ -InP layer, approximately 300 nm wide, doping concentration 2 × 10⁻⁶ 17 ~5×10 17 cm -3 n - The structure consists of an i-InP layer 5, an i-InP layer 6 with a width of approximately 0–300 nm, and seven i-InGaAs quantum well active regions 7 with a width of 4–6 nm and spaced by 12 nm thick i-InP layers. Following this, another i-InP layer 6 with a width of approximately 300 nm and a doping concentration of 2 × 10⁻⁶ is grown. 17 ~5×10 17 cm -3 p - -InP layer 8, approximately 900 nm wide, with a doping concentration of 2 × 10⁸. 18 cm -3 p + -InP layer 9, approximately 8 nm wide, doping concentration 2 × 10⁻⁶ 19 cm -3 p ++ -InGaAs layer 10, approximately 1500 nm wide, doping concentration 2 × 10⁻⁶ 19 cm -3 n++ -InP layer, a side-oriented indium phosphide laser diode structure with tunnel junction is obtained. The n-type doping of indium phosphide uses silane (SiH4) precursor in the MOCVD system as the doping source, and the p-type doping of indium phosphide uses diethylzinc (DeZn) precursor as the doping source.

[0042] S3: Etch the cladding layer of the epitaxial template to expose the laterally epitaxial diode structure and planarize the wafer; In one specific embodiment, in step S3, the method of etching the cladding layer of the epitaxial template to expose the laterally epitaxial diode structure and planarizing the wafer includes: The coating layer of the epitaxial template is etched using a dry etching process to expose the laterally epitaxial diode structure, and the wafer is planarized using benzocyclobutene resin 12.

[0043] Specifically, the silicon oxide cladding layer on top of the epitaxial layer is etched using a reactive ion beam etching (RIE) system until all the epitaxial layers are exposed. Benzocyclobutene resin 12 is then spin-coated onto the surface of the epitaxial wafer and cured by baking at 250 °C for 2 hours. The surface layer of benzocyclobutene resin 12 is then thinned using RIE to obtain a planarized wafer containing the epitaxial layer. S4: Electrode patterns are exposed above the diode structure by photolithography, and metal is deposited above the n-type contact layer 4 and the p-type contact layer 11 to form n-type electrode 13 and p-type electrode 14 using electron beam evaporation and lift-off processes.

[0044] Using the fabrication method described in this embodiment, a lateral indium phosphide tunneling junction laser diode was fabricated on an SOI substrate with a top silicon thickness of 220 nm. The fabricated device has a thickness of 5 μm in the direction perpendicular to the paper plane. Figure 5 The current-voltage (IV) characteristic curves of the device in linear coordinates are shown, including a comparison between simulation results and actual device measurement data. As can be seen from the figure, at a forward bias of 3 V, the device output current can reach tens of microamps, verifying the effectiveness of carrier injection after introducing the tunneling structure. Figure 6 The IV characteristic curves of the same device in logarithmic coordinates are shown. It can be observed that the leakage current of the device under reverse bias is only about two orders of magnitude higher than the simulated value, which is still within the acceptable range for practical applications. This indicates that the structure has good leakage current control capability under reverse bias voltage.

[0045] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A lateral indium phosphide diode based on a tunnel junction, characterized in that, It includes a wafer and a diode structure; an n-type electrode (13) and a p-type electrode (14) are provided on the top of the diode structure; the wafer consists of a seed layer (3), a buried oxide layer (2) and a substrate (1) from top to bottom; the diode structure is laterally extended above the buried oxide layer (2).

2. The lateral indium phosphide diode based on a tunnel junction according to claim 1, characterized in that, The wafer is an SOI wafer or an InPOI wafer.

3. A lateral indium phosphide diode based on a tunnel junction according to claim 1, characterized in that, The diode structure, from left to right, includes an n-type contact layer (4), a device layer, and a tunnel junction.

4. A lateral indium phosphide diode based on a tunnel junction according to claim 3, characterized in that, The tunneling junction, from left to right, includes p + -InP layer (9), p ++ -InGaAs layer (10), p-region contact layer (11); wherein, the p + -InP layer (9) uses diethylzinc as the doping source, with a doping concentration of 2×10⁻⁶. 18 cm -3 The p ++ -The InGaAs layer (10) uses diethylzinc as the doping source with a doping concentration of 2×10⁻⁶. 19 cm -3 .

5. A lateral indium phosphide diode based on a tunnel junction according to claim 4, characterized in that, The n-type contact layer (4) includes a first n ++ -InP layer, the first n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The p-region contact layer (11) includes a second n ++ -InP layer, the second n ++ The InP layer uses silane from the MOCVD system as the doping source, with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The n-type electrode (13) forms an ohmic contact with the n-type contact layer (4), and the p-type electrode (14) forms an ohmic contact with the p-region contact layer (11).

6. A lateral indium phosphide diode based on a tunnel junction according to claim 3, characterized in that, The device layer is either a photodetector device layer containing intrinsic InGaAs or a laser device layer containing an InGaAs quantum well structure with multiple i-InP spacings.

7. A lateral indium phosphide diode based on a tunnel junction according to claim 6, characterized in that, The thickness of the photodetector device layer containing intrinsic InGaAs is 200 nm.

8. A lateral indium phosphide diode based on a tunnel junction according to claim 6, characterized in that, The laser device layer comprising an InGaAs quantum well structure with multiple i-InP spacings includes n - -InP layer (5), i-InP layer (6), i-InGaAs quantum well active region containing seven pairs of i-InP spaced by i-InP (7) and p - -InP layer (8).

9. A method for fabricating a lateral indium phosphide diode based on a tunnel junction, applicable to the lateral indium phosphide diode based on a tunnel junction as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1: A pattern template for the lateral epitaxy of a diode structure is prepared on a substrate using photolithography, dry etching, chemical vapor deposition, and wet etching. S2: Using an MOCVD system, an n-type contact layer, a device layer, and a p-type contact layer are sequentially epitaxially grown laterally on the pattern template. + -InP layer, p ++ -InGaAs layer, p-region contact layer; S3: Etch the cladding layer of the epitaxial template to expose the laterally epitaxial diode structure and planarize the wafer; S4: Electrode patterns are exposed above the diode structure by photolithography, and metal is deposited above the n-type contact layer and p-type contact layer to form n-type and p-type electrodes using electron beam evaporation and lift-off processes.

10. The method for fabricating a lateral indium phosphide diode based on a tunnel junction according to claim 9, characterized in that, In step S3, the method of etching the cladding layer of the epitaxial template to expose the laterally epitaxial diode structure and planarizing the wafer includes: The coating layer of the epitaxial template is etched using a dry etching process to expose the lateral epitaxial diode structure, and the wafer is planarized using benzocyclobutene resin.

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