Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of ensuring moisture resistance reliability by suppressing infiltration of moisture from the outside to the inside of the multilayer ceramic capacitor, and capable of achieving a low resistance of ESR. A laminated ceramic capacitor (10) is provided with: a laminated body (12) in which a ceramic layer (14) and an internal electrode layer (16) are laminated; a barrier film (28) disposed on the laminated body (12); and external electrodes (24) disposed on the barrier film (28) on both end surfaces (12e, 12f) of the laminated body (12). The ceramic layer (14) contains a perovskite compound represented by the general formula ABO3, wherein the A site is Ba. The barrier film (28) contains Ba and at least one of S and C. The barrier film (28) covers both main surfaces (12a, 12b) and both side surfaces (12c, 12d), and covers both end surfaces (12e, 12f) excluding an exposed surface (29) from which the internal electrode layer (16) is exposed, and the external electrode (24) is in contact with the internal electrode layer (16) at the exposed surface (29).

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors and methods for manufacturing multilayer ceramic capacitors. Background Technology

[0002] In recent years, multilayer ceramic electronic components, such as multilayer ceramic capacitors, have been used in harsher environments than ever before.

[0003] Such a typical multilayer ceramic capacitor comprises a capacitor element (main body) having multiple ceramic layers and multiple internal electrode layers stacked together, with external electrodes formed on the outer surface of the capacitor element. The internal electrode layers extend to the end faces and sides of the capacitor element and are connected to the external electrodes. The external electrodes, for example, consist of a base electrode formed by applying and firing a conductive paste, and a plating layer formed on the outer surface of the base electrode. Depending on the requirements, the plating layer may sometimes consist of multiple layers.

[0004] For example, Patent Document 1 discloses a multilayer ceramic capacitor comprising a first electrode layer and a second electrode layer disposed on the first electrode layer to ensure moisture resistance reliability. The first electrode layer, containing titanium nitride (TiN), is formed on the entire surface of the multilayer comprising the ceramic layer and the inner electrode layer using atomic layer deposition. Patent Document 1 discloses a multilayer ceramic capacitor that, by forming a thin and dense first electrode layer in its body, ensures sufficient moisture resistance reliability even with a thin outer electrode, thus preventing moisture from seeping into the inner electrode layer from the outside.

[0005] On the other hand, addressing the ESR issue, Patent Document 2 discloses a structure in which multiple grooves are formed in the ceramic layer at the end face where the external electrode is formed, exposing the end of the internal electrode layer. The external electrode includes a conductive resin layer containing metal particles and resin, and an electrode layer on the conductive resin layer. An intermetallic compound is formed in the grooves during the formation of the conductive resin layer. This intermetallic compound ensures electrical conductivity between the exposed end of the internal electrode layer and the external electrode.

[0006] Prior art literature

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2019-96862

[0009] Patent Document 2: Japanese Patent Application Publication No. 2019-117942 Summary of the Invention

[0010] The problem the invention aims to solve

[0011] In recent years, the miniaturization of multilayer ceramic capacitors has been developing rapidly, which has led to higher requirements for the characteristics of multilayer ceramic capacitors, requiring high reliability and low resistance.

[0012] However, in the multilayer ceramic capacitor disclosed in Patent Document 1, the increased ESR (Equivalent Series Resistance) arises in order to ensure moisture resistance reliability, creating a trade-off between them. Furthermore, while the structure in Patent Document 2 may suppress the ESR problem, it lacks a structure specifically designed to ensure moisture resistance reliability, thus presenting issues with moisture resistance reliability. Therefore, there is a need for a multilayer ceramic capacitor that can stably balance high reliability and low resistance, even in a smaller form factor.

[0013] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that can ensure moisture resistance reliability by inhibiting the infiltration of moisture from the outside to the inside of the multilayer ceramic capacitor, and to achieve low ESR, as well as a method for manufacturing the multilayer ceramic capacitor.

[0014] Technical solutions for solving the problem

[0015] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked ceramic layers and a plurality of internal electrode layers, and including a first main surface and a second main surface opposite to each other in the height direction, a first side surface and a second side surface opposite to each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite to each other in the length direction orthogonal to the height direction and the width direction; a barrier film disposed on the multilayer body; and an external electrode disposed on the barrier film on the first end surface and the second end surface.

[0016] The ceramic layer contains a perovskite compound represented by the general formula ABO3 with Ba at the A site.

[0017] The barrier membrane contains at least one of Ba, S, and C.

[0018] The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and covers the first end surface and the second end surface except for the exposed surface of the internal electrode layer in the laminate.

[0019] The external electrode contacts the internal electrode layer on the exposed surface.

[0020] The multilayer ceramic capacitor according to the present invention can achieve low ESR resistance while ensuring moisture resistance and reliability.

[0021] The present invention relates to a method for manufacturing a multilayer ceramic capacitor comprising: a preparation step of firing to prepare a multilayer body, the multilayer body including a plurality of ceramic layers comprising a perovskite compound represented by the general formula ABO3 and having Ba at the A site and a plurality of internal electrode layers, and including a first main surface and a second main surface opposite each other in the height direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height direction and the width direction; a film forming step of impregnating the multilayer body in a solution containing at least one of S ions and C ions to form a barrier film comprising Ba and at least one of S and C on the multilayer body; and an external electrode forming step of forming an external electrode on the barrier film on the first end surface and the second end surface.

[0022] The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and covers the first end surface and the second end surface except for the exposed surface of the internal electrode layer in the laminate.

[0023] The external electrode contacts the internal electrode layer on the exposed surface.

[0024] According to the manufacturing method of the multilayer ceramic capacitor of the present invention, it is possible to obtain a multilayer ceramic capacitor that can achieve low ESR while ensuring moisture resistance and reliability.

[0025] Invention Effects

[0026] According to the present invention, a multilayer ceramic capacitor that can ensure moisture resistance reliability by inhibiting the infiltration of moisture from the outside to the inside of the multilayer ceramic capacitor, and a method for manufacturing the multilayer ceramic capacitor can be provided.

[0027] The above-described objects, other objects, features, and advantages of the present invention will become clearer from the following detailed description of specific embodiments with reference to the accompanying drawings. Attached Figure Description

[0028] Figure 1 This is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention.

[0029] Figure 2 yes Figure 1 A sectional view at line II-II.

[0030] Figure 3 yes Figure 1 A cross-sectional view at line III-III.

[0031] Figure 4 yes Figure 2 An enlarged view of A.

[0032] Figure 5 It is shown as Figure 1 The flowchart illustrates the manufacturing method of a multilayer ceramic capacitor, including the method for forming a barrier film and external electrodes.

[0033] Figure 6 (a) to (c) are schematic cross-sectional views illustrating a method for forming a barrier film and an external electrode of a multilayer ceramic capacitor according to an embodiment of the present invention.

[0034] Figure 7 This is a schematic cross-sectional view of the multilayer ceramic capacitor involved in the comparative example.

[0035] Figure 8 This is a schematic diagram illustrating the experimental method used to confirm conductivity. Detailed Implementation

[0036] 1. Multilayer ceramic capacitor

[0037] The first embodiment of the present invention relates to a multilayer ceramic capacitor. Figure 1 This is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 yes Figure 1 A sectional view at line II-II. Figure 3 yes Figure 1 A cross-sectional view at line III-III. Figure 4 yes Figure 2 An enlarged view of A.

[0038] like Figures 1 to 3 As shown, the multilayer ceramic capacitor 10 includes a cuboid-shaped multilayer 12, a blocking film 28, and an external electrode 24.

[0039] The laminate 12 has multiple stacked ceramic layers 14 and multiple internal electrode layers 16. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b facing each other in the height direction x, a first side surface 12c and a second side surface 12d facing each other in the width direction y (orthogonal to the height direction x), and a first end surface 12e and a second end surface 12f facing each other in the length direction z (orthogonal to both the height direction x and the width direction y). In this laminate 12, it is preferable to have rounded corners and edges. A corner is the portion where three adjacent surfaces of the laminate intersect, and an edge is the portion where two adjacent surfaces of the laminate intersect. Additionally, some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may be formed with irregularities or protrusions. Furthermore, the dimension of the stacked body 12 in the length direction z is not necessarily longer than the dimension in the width direction y.

[0040] The number of ceramic layers 14, including the outer layer, is preferably 15 or more and 700 or less.

[0041] The laminate 12 has an effective layer portion 15a in the lamination direction that connects the first main surface 12a and the second main surface 12b, an effective layer portion 15a with internal electrode layers 16 facing each other, a first outer layer portion 15b located between the internal electrode layer 16 closest to the first main surface 12a and the first main surface 12a, and a second outer layer portion 15c located between the internal electrode layer 16 closest to the second main surface 12b and the second main surface 12b.

[0042] The first outer layer 15b is located on the first main surface 12a side of the laminate 12, and is an assembly of multiple ceramic layers 14 located between the first main surface 12a and the inner electrode layer 16 closest to the first main surface 12a.

[0043] The second outer layer 15c is located on the second main surface 12b side of the laminate 12, and is an assembly of multiple ceramic layers 14 located between the second main surface 12b and the inner electrode layer 16 closest to the second main surface 12b.

[0044] The area sandwiched between the first outer layer 15b and the second outer layer 15c is the effective layer 15a.

[0045] The dimensions of the laminate 12 are not particularly limited, but it is preferred that the length z dimension is 0.2 mm or more and 10.0 mm or less, the width y dimension is 0.1 mm or more and 10.0 mm or less, and the height x dimension is 0.1 mm or more and 5.0 mm or less.

[0046] The ceramic layer 14 can be formed from a dielectric material, for example, as a ceramic material. Such a dielectric material may include a perovskite compound represented by the general formula ABO3 with Ba at the A-site. For example, a dielectric ceramic containing components such as BaTiO3 can be used as the dielectric material. When the above-mentioned dielectric material is used as the main component, depending on the desired characteristics of the laminate 12, materials containing minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds, which are present in smaller amounts than the main component, may also be used.

[0047] The thickness of the fired ceramic layer 14 is preferably 0.4 μm or more and 10.0 μm or less.

[0048] like Figure 2 as well as Figure 3As shown, the laminate 12 has a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b, which are generally rectangular, serving as a plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded and arranged alternately at equal intervals along the lamination direction of the laminate 12. The first internal electrode layers 16a and the second internal electrode layers 16b can be arranged parallel or perpendicular to the mounting surface.

[0049] The first internal electrode layer 16a has a first opposing electrode portion 18a opposite to the second internal electrode layer 16b, and a first lead-out electrode portion 20a located at one end of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. The end of the first lead-out electrode portion 20a extends to the first end face 12e and is exposed.

[0050] The second inner electrode layer 16b has a second opposing electrode portion 18b opposite to the first inner electrode layer 16a, and a second lead-out electrode portion 20b located at one end of the second inner electrode layer 16b and extending from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. The end of the second lead-out electrode portion 20b extends to the second end face 12f and is exposed.

[0051] The shapes of the first opposing electrode portion 18a of the first inner electrode layer 16a and the second opposing electrode portion 18b of the second inner electrode layer 16b are not particularly limited, but are preferably rectangular. However, the corner portions may be rounded or formed as inclined (conical).

[0052] The shapes of the first lead-out electrode portion 20a of the first inner electrode layer 16a and the second lead-out electrode portion 20b of the second inner electrode layer 16b are not particularly limited, but are preferably rectangular. However, the corner portions may be rounded or formed as inclined (conical).

[0053] The width of the first opposing electrode portion 18a and the width of the first lead-out electrode portion 20a of the first internal electrode layer 16a can be formed to be the same width, or either one can be formed to be narrower. Similarly, the width of the second opposing electrode portion 18b and the width of the second lead-out electrode portion 20b of the second internal electrode layer 16b can be formed to be the same width, or either one can be formed to be narrower.

[0054] The laminate 12 includes a side portion (W gap) 22a formed between one end of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the first side surface 12c, and between the other end of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes an end portion (L gap) 22b formed between the end of the first inner electrode layer 16a opposite to the first lead-out electrode portion 20a and the second end surface 12f, and between the end of the second inner electrode layer 16b opposite to the second lead-out electrode portion 20b and the first end surface 12e.

[0055] The internal electrode layer 16 may contain, for example, suitable conductive materials such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals, such as Ag-Pd alloys. The internal electrode layer 16 may also contain dielectric particles with the same composition as the ceramic included in the ceramic layer 14.

[0056] The thickness of the internal electrode layer 16 is preferably 0.2 μm or more and 2.0 μm or less. Furthermore, the number of internal electrode layers 16 is preferably 15 or more and 200 or less.

[0057] A barrier film 28 is disposed on the laminate 12. Specifically, the barrier film 28 covers the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d, and covers the first end surface 12e and the second end surface 12f except for the exposed surface 29 of the internal electrode layer 16 exposed in the laminate 12. The end of the first lead electrode portion 20a extends to the first end surface 12e and is exposed, and the end of the second lead electrode portion 20b extends to the second end surface 12f and is exposed, thus creating the exposed surface 29. On the first end surface 12e and the second end surface 12f, the barrier film 28 does not cover the exposed surface 29, which is covered by the external electrode 24.

[0058] The barrier membrane 28 comprises at least one of Ba, S, and C. The barrier membrane 28 is, for example, BaSO4, BaCO3, etc. BaSO4 and BaCO3 are not readily soluble in water, so by forming the barrier membrane 28 from any of them, it is possible to further inhibit the intrusion of liquids such as water into the laminate 12 from the outside.

[0059] External electrodes 24 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12. The external electrodes 24 have a first external electrode 24a and a second external electrode 24b.

[0060] The external electrode 24 includes a base electrode layer 26 comprising metal and glass components, and a plating layer 30 formed on the surface of the base electrode layer 26.

[0061] The first external electrode 24a is disposed on the surface of the barrier film 28 at the first end face 12e side and is connected to the first internal electrode layer 16a at the exposed surface 29. Furthermore, the first external electrode 24a extends from the first end face 12e side and is also disposed on the surface of the barrier film 28 at a portion of the first main surface 12a side, a portion of the second main surface 12b side, a portion of the first side surface 12c side, and a portion of the second side surface 12d side. In this case, the first external electrode 24a is electrically connected to the first lead-out electrode portion 20a of the first internal electrode layer 16a.

[0062] The second external electrode 24b is disposed on the surface of the barrier film 28 at the second end face 12f side and is connected to the second internal electrode layer 16b at the exposed surface 29. Furthermore, the second external electrode 24b extends from the second end face 12f side and is also disposed on the surface of the barrier film 28 at a portion of the first main surface 12a side, a portion of the second main surface 12b side, a portion of the first side surface 12c side, and a portion of the second side surface 12d side. In this case, the second external electrode 24b is electrically connected to the second lead-out electrode portion 20b of the second internal electrode layer 16b.

[0063] Within the laminate 12, an electrostatic capacitor is formed by the first opposing electrode portion 18a of the first inner electrode layer 16a and the second opposing electrode portion 18b of the second inner electrode layer 16b being opposed to each other across the ceramic layer 14. Therefore, an electrostatic capacitor can be obtained between the first external electrode 24a connected to the first inner electrode layer 16a and the second external electrode 24b connected to the second inner electrode layer 16b, exhibiting the characteristics of a capacitor.

[0064] The substrate electrode layer 26 has a first substrate electrode layer 26a and a second substrate electrode layer 26b.

[0065] The first base electrode layer 26a is disposed on the surface of the barrier film 28 on the first end face 12e side of the laminate 12 and is connected to the first inner electrode layer 16a on the exposed surface 29. Figure 4 As shown, on exposed surface 29, an alloy layer 40 is formed by the interdiffusion of Cu in the first base electrode layer 26a and Ni in the first inner electrode layer 16a. This alloy layer 40 is formed more densely than the first inner electrode layer 16a and the first base electrode layer 26a itself, thereby improving the bonding strength between the first base electrode layer 26a and the first inner electrode layer 16a. Consequently, the ESR can be further reduced.

[0066] Furthermore, the first base electrode layer 26a extends from the first end face 12e side and is formed to cover part of the surface of the barrier film 28 on the first main face 12a side, the second main face 12b side, the first side face 12c side, and the second side face 12d side.

[0067] The second base electrode layer 26b is disposed on the surface of the barrier film 28 on the second end face 12f side of the laminate 12 and is connected to the second inner electrode layer 16b on the exposed surface 29. For example... Figure 4 As shown, on exposed surface 29, an alloy layer 40 is formed by the interdiffusion of Cu in the second base electrode layer 26b and Ni in the second inner electrode layer 16b. This alloy layer 40 is formed more densely than the second inner electrode layer 16b and the second base electrode layer 26b itself, thereby improving the bonding strength between the second base electrode layer 26b and the second inner electrode layer 16b. Consequently, the ESR can be further reduced.

[0068] Furthermore, the second base electrode layer 26b extends from the second end face 12f side and is formed to cover part of the surface of the barrier film 28 on the first main face 12a side, the second main face 12b side, the first side face 12c side, and the second side face 12d side.

[0069] Alternatively, the first base electrode layer 26a may be disposed only on the surface of the barrier film 28 on the first end face 12e side of the laminate 12, and the second base electrode layer 26b may be disposed only on the surface of the barrier film 28 on the second end face 12f side of the laminate 12.

[0070] Next, the structure when the base electrode layer 26 is set as the above-described sintered layer will be described.

[0071] The sintered layer comprises glass and metal components. The glass component of the sintered layer comprises at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the sintered layer comprises, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer may also consist of multiple layers. The sintered layer is formed by applying a conductive paste comprising glass and metal components to the laminate 12 and then sintering it. It can be formed by simultaneously sintering a chip having an internal electrode layer 16 and a ceramic layer 14 before sintering and applying the conductive paste to the chip, or by sintering the chip having an internal electrode layer 16 and a ceramic layer 14 before sintering to obtain the laminate 12 and then applying the conductive paste to the laminate 12 and sintering it. In addition, when the sintered layer is formed by simultaneously firing the stacked small pieces having an internal electrode layer 16 and a ceramic layer 14 and the conductive paste applied to the stacked small pieces, it is preferable to add ceramic materials instead of glass components to form the sintered layer.

[0072] The thickness of the first sintered layer and the second sintered layer located at the center of the height direction x of the first base electrode layer 26a and the second base electrode layer 26b located on the first end face 12e and the second end face 12f is preferably 10 μm or more and 160 μm or less.

[0073] Furthermore, when the base electrode layer 26 is provided on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the first sintered layer and the second sintered layer located at the central portion of the length direction z of the first base electrode layer 26a and the second base electrode layer 26b on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is preferably, for example, 5 μm or more and 40 μm or less.

[0074] The plating layer 30 has a first plating layer 30a and a second plating layer 30b.

[0075] Next, regarding the first plating layer 30a and the second plating layer 30b, which are plating layers 30 that can be disposed on the substrate electrode layer 26, refer to... Figure 2 as well as Figure 3 To illustrate.

[0076] The first plating layer 30a and the second plating layer 30b may include at least one material selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0077] The first plating layer 30a is configured to cover the first substrate electrode layer 26a.

[0078] The second plating layer 30b is configured to cover the second substrate electrode layer 26b.

[0079] The first plating layer 30a and the second plating layer 30b may also be formed from multiple layers. In this case, the plating layer 30 is preferably a two-layer structure consisting of a lower plating layer 32 based on Ni plating formed on the substrate electrode layer 26 and an upper plating layer 34 based on Sn plating formed on the lower plating layer 32.

[0080] That is, the first plating layer 30a has a first lower plating layer 32a and a first upper plating layer 34a located on the surface of the first lower plating layer 32a.

[0081] Furthermore, the second plating layer 30b has a second lower plating layer 32b and a second upper plating layer 34b located on the surface of the second lower plating layer 32b.

[0082] The lower plating layer 32 based on Ni plating is used to prevent the base electrode layer 26 from being eroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer 34 based on Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby making it easy to mount.

[0083] The thickness of each coating layer is preferably 2.0 μm or more and 15.0 μm or less.

[0084] The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 24a, and the second external electrode 24b, in the length direction z is set as dimension L. The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 24a, and the second external electrode 24b, in the height direction x is set as dimension T. The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 24a, and the second external electrode 24b, in the width direction y is set as dimension W.

[0085] The dimensions of the multilayer ceramic capacitor 10 are not particularly limited, but the length dimension L in the z-direction is 0.2 mm or more and 7.5 mm or less, the width dimension W in the y-direction is 0.1 mm or more and 3.5 mm or less, and the height dimension T in the x-direction is 0.2 mm or more and 3.5 mm or less. Furthermore, the length dimension L in the z-direction is not necessarily longer than the width dimension W in the y-direction. Moreover, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0086] exist Figure 1 In the multilayer ceramic capacitor 10 shown, the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d of the multilayer 12 are covered by a barrier film 28, and the first end surface 12e and the second end surface 12f of the multilayer 12 are also covered by the barrier film 28 except for the exposed surface 29 of the internal electrode layer 16. Furthermore, the exposed surface 29 is covered by the first external electrode 24a and the second external electrode 24b. In other words, the multilayer 12 is covered by the barrier film 28 and by the first external electrode 24a and the second external electrode 24b. Therefore, the intrusion of liquids such as moisture into the multilayer 12 from the outside is suppressed by the barrier film 28, the first external electrode 24a, and the second external electrode 24b, improving moisture resistance reliability. For example, if grain boundaries are formed within the ceramic layer 14, these become parts that cannot withstand the intrusion of moisture, and the ceramic layer 14 may break. Grain boundaries are the boundaries between the glass or other particles constituting the ceramic layer 14. However, according to the above structure, the intrusion of the isotropic layer 12 of water can be suppressed, thus suppressing the damage of the ceramic layer 14.

[0087] Furthermore, according to the above structure, by also providing a barrier film 28 between the external electrode 24 and the laminate 12, even if the external electrode 24 is damaged due to holes, the barrier film 28 can be used to suppress the intrusion of moisture and other substances that enter through the external electrode 24 into the laminate 12.

[0088] Furthermore, according to the above structure, no barrier film 28 is formed on the exposed surface 29, so the inner electrode layer 16 and the outer electrode 24 are directly connected on the exposed surface 29. Therefore, the conductivity between the inner electrode layer 16 and the outer electrode 24 can be ensured, resulting in a low ESR (Equivalent Series Resistance).

[0089] Based on the above structure, it is possible to achieve low ESR resistance while ensuring moisture resistance and reliability.

[0090] Furthermore, even if the base electrode layer 26 contains a glass component that cannot withstand moisture, the barrier film 28 is formed on the entire laminate 12 except for the exposed surface 29, thus preventing the intrusion of liquids such as moisture into the laminate 12 from the outside.

[0091] 2. Manufacturing method of multilayer ceramic capacitors

[0092] Next, the manufacturing method of multilayer ceramic capacitors will be explained.

[0093] First, ceramic raw sheets are produced by applying a ceramic paste containing ceramic powder into a sheet, for example by screen printing, and then drying it.

[0094] Next, a conductive paste for forming internal electrodes is prepared. The conductive paste for forming internal electrodes is applied to a ceramic green sheet in a given pattern, for example by screen printing or gravure printing, to prepare a ceramic green sheet with a conductive pattern for forming internal electrodes and a ceramic green sheet without a conductive pattern for forming internal electrodes.

[0095] In addition, known organic binders and solvents may be included in ceramic pastes and conductive pastes for forming internal electrodes.

[0096] Next, a given number of outer ceramic green sheets without conductive patterns for forming internal electrodes are stacked, and then a given number of ceramic green sheets with conductive patterns for forming internal electrodes are stacked on top of them, thereby creating a master laminate. At this point, multiple ceramic green sheets with printed conductive patterns for forming internal electrodes are stacked, making the leads of the conductive patterns for forming internal electrodes different from each other, thereby creating a laminate.

[0097] The laminated sheets are pressed together in the lamination direction by means of isostatic pressing, thereby producing a laminated block.

[0098] The laminated blocks are then cut into given shapes and sizes, producing unprocessed laminated pieces. At this point, the corners and edges of the laminated pieces can be rounded using methods such as tumble grinding.

[0099] Next, the cut, unprocessed laminated pieces are fired to form a laminate 12 in which a first internal electrode layer and a second internal electrode layer are disposed inside the laminate, with the first internal electrode layer extending to a first end face and the second internal electrode layer extending to a second end face. Furthermore, while the firing temperature of the unprocessed laminated pieces depends on the ceramic material and the material of the conductive paste used to form the internal electrodes, it is preferably 900°C or higher and 1300°C or lower.

[0100] Next, a barrier film 28 is formed on the generated laminate 12, but a process of processing the end faces 12e and 12f of the laminate 12 can also be added before forming the barrier film 28.

[0101] The conductive paste and ceramic paste used for forming the internal electrodes are fired at different temperatures, causing shrinkage at different times during firing. Consequently, in the fired laminate 12, at the first end face 12e and the second end face 12f along the length direction z, the ends of the ceramic layer 14 and the internal electrode layer 16 are not formed on the same surface; the end of the internal electrode layer 16 is located more inwardly than the end of the ceramic layer 14 (inner side along the length direction z of the laminate 12). In other words, a step is formed at the ends of the internal electrode layer 16 and the ceramic layer 14. If this step is maintained, the contact between the external electrode 24 and the internal electrode layer 16 may decrease when the external electrode 24 is formed at the ends of the internal electrode layer 16 and the ceramic layer 14 at the first end face 12e and the second end face 12f. Therefore, for the fired laminate 12, the ends of the ceramic layer 14 at the first end face 12e and the second end face 12f of the laminate 12 can be removed by sandblasting or other methods, thereby reducing the aforementioned steps, or processing can be performed so that the ends of the internal electrode layer 16 and the ends of the ceramic layer 14 become the same surface.

[0102] Next, a barrier membrane 28 is formed on the laminate 12.

[0103] Figure 5 Show as Figure 1 A flowchart illustrating the manufacturing method of a multilayer ceramic capacitor, including the method for forming a barrier film and external electrodes. Figure 6 In the diagram, (a) to (c) are schematic cross-sectional views illustrating a method for forming a barrier film and an external electrode of a multilayer ceramic capacitor according to an embodiment of the present invention.

[0104] First, after generating the laminate 12 (S11), the laminate 12 is immersed in a solution (S12). The solution contains at least one of S ions and C ions. For example, the entire laminate 12 is immersed in the solution at room temperature and left to stand for 15 minutes. The solution can also be stirred. The solution preferably does not dissolve the internal electrode layer and the laminate, and exists as a liquid. Examples of solutions containing S ions include Na2SO4, K2SO4, CuSO4, NiSO4, Al2(SO4)3, MnSO4, etc. Examples of solutions containing C ions include Na2CO3, K2CO3, CuCO3, NiCO3, Al2(CO3)3, MnCO3, etc. The concentration of the solution, although an example, is 50 g / L.

[0105] Therefore, as Figure 6 As shown in (a), a barrier film 28 is formed on the laminate 12. When the solution contains S ions, the Ba in the ceramic layer 14 of the laminate 12 reacts with the S ions, thereby forming a barrier film 28 containing BaSO4 on the laminate 12. Furthermore, when the solution contains C ions, the Ba in the ceramic layer 14 of the laminate 12 reacts with the C ions, thereby forming a barrier film 28 containing BaCO3 on the laminate 12. However, the solution does not react with the inner electrode layer 16, therefore, a barrier film 28 is not formed on the exposed surface 29 of the inner electrode layer 16.

[0106] The laminate 12, after being immersed in the solution, is removed from the solution and dried (S13). For example, the solution adhering to the laminate 12 is removed by DSC (distillation pressure suction). This removes droplets from the barrier membrane 28. As a drying method, heat treatment using a dryer at a temperature of up to 100°C can also be used.

[0107] Next, an external electrode 24 is formed on the laminate 12.

[0108] A conductive paste for external electrodes is applied to both ends of the laminate 12 on which the barrier film 28 is formed (S14). Then, the applied conductive paste for external electrodes is fired, as shown in the image. Figure 6 As shown in (b), a sintered layer is formed on the first base electrode layer 26a of the first external electrode 24a and the second base electrode layer 26b of the second external electrode 24b (S15). At this time, on the exposed surface 29, the first base electrode layer 26a and the second base electrode layer 26b are in direct contact with the first internal electrode layer 16a and the second internal electrode layer 16b, thereby electrically connecting them. Furthermore, as... Figure 4As shown, on the exposed surface 29, an alloy layer 40 is formed, for example, by Cu in the first base electrode layer 26a and the second base electrode layer 26b and Ni in the first internal electrode layer 16a and the second internal electrode layer 16b.

[0109] Alternatively, in the case of forming a sintered layer, a conductive paste containing glass and metal components is applied by means such as impregnation and then sintered to form a sintered layer as a base electrode layer 26. The sintering temperature is preferably 700°C or higher and 900°C or lower.

[0110] After that, as Figure 6 As shown in (c), a lower plating layer 32 is formed on the surface of the base electrode layer 26 (S16), and an upper plating layer 34 is formed on the surface of the lower plating layer 32 (S17). Through this process, the external electrode 24 is formed. Figure 1 In the multilayer ceramic capacitor 10 shown, a Ni plating layer is formed as the lower plating layer 32 on the substrate electrode layer 26, and a Sn plating layer is formed as the upper plating layer 34. The lower plating layer 32 and the upper plating layer 34 are formed by electrolytic plating or electroless plating, etc. Furthermore, it is preferable that the plating layers are formed in multiple layers.

[0111] As described above, manufacturing Figure 1 The stacked ceramic capacitor 10 shown.

[0112] 3. Experimental Example

[0113] Next, in order to confirm the effectiveness of the multilayer ceramic capacitor involved in the present invention, a multilayer ceramic capacitor was manufactured, and a moisture resistance reliability test and an ESR measurement test were conducted.

[0114] (1) Specifications of the test specimens in the examples

[0115] First, following the manufacturing method of the multilayer ceramic capacitor described above, a multilayer ceramic capacitor with the specifications described in the following embodiment was manufactured.

[0116] (Example)

[0117] • Construction of multilayer ceramic capacitor: 2 terminals (refer to...) Figures 1 to 3 )

[0118] • Dimensions of the multilayer ceramic capacitor: L×W×T (including design values): 1.0mm×0.5mm×0.5mm

[0119] • Ceramic layer material: BaTiO3

[0120] • Capacitance: 10μF

[0121] Rated voltage: 6.3V

[0122] • Structure of the internal electrode layer

[0123] Metallic composition: Cu

[0124] • Structure of the barrier membrane

[0125] Ingredients: BaSO4

[0126] Construction of external electrodes

[0127] Substrate electrode layer

[0128] Metallic composition: Ni

[0129] Plating layer: A two-layer structure consisting of a Ni plating layer and a Sn plating layer.

[0130] (2) Specifications of the test specimens in the comparative examples

[0131] Next, a comparative example of a multilayer ceramic capacitor with the following specifications was manufactured: a 10A capacitor.

[0132] Figure 7 This is a schematic cross-sectional view of the multilayer ceramic capacitor involved in the comparative example. The multilayer ceramic capacitor 10A involved in the comparative example has the same specifications as the multilayer ceramic capacitor 10 involved in the embodiment, except that the barrier film 28 is not formed.

[0133] (3) Methods of each experiment

[0134] (a) Moisture resistance reliability test

[0135] After mounting the samples from the examples and the comparative examples onto a substrate, the substrate was placed in a high-temperature and high-humidity bath, and a voltage of 4V was applied to each sample for 200 hours at 85°C and 85% RH. Next, the insulation resistance value of each sample after the humidity resistance reliability test was measured.

[0136] Then, for each sample, the insulation resistance values ​​before and after the moisture resistance reliability test were compared. Samples whose insulation resistance values ​​did not drop by more than one digit were classified as good. The number of samples for each test was set to 20. In Table 2, for each sample number, if more than 10% of the samples were defective, they were judged as NG and indicated by "×", and other cases were indicated by "〇".

[0137] (b) ESR measurement test

[0138] The cross-sections of each sample were machined. When the probe was placed against the internal electrode layer and the Sn plating layer, a value of ESR below 100Ω was considered good. Seven samples were used for each sample. In Table 2, if more than two out of seven samples were defective, they were judged as NG and marked with "×", while other cases were marked with "〇".

[0139] In addition, during the confirmation of conductivity, after grinding each sample to expose the LT profile, Figure 8 A measuring instrument, which functions as a voltmeter 41 and an ammeter 42, is installed at positions P1, P2, P3, and P4 as shown. The resistance value between P1 and P3 (2-3 cm) is measured using a four-terminal method. For example, a digital multimeter (PC7000, manufactured by Sanwa Electric Keiki Co., Ltd.) is used as the measuring instrument for the voltage measurement between P1 and P2 and the current measurement between P3 and P4.

[0140] When the measuring voltage is set to 100mV, and the internal electrode layer and external electrode are conductive, a current of several hundred mA can be measured according to Ohm's law, for example. On the other hand, when the conductivity between the internal electrode layer and the external electrode is poor, the current becomes less than several tens of mA.

[0141] The evaluation results are shown in Table 1.

[0142] [Table 1]

[0143]

[0144] (4) Experimental results

[0145] According to Table 1, the multilayer ceramic capacitor 10, which is the sample involved in the embodiment, has barrier films formed on its two end faces, two main faces, and two side faces to cover the surface of the multilayer, and the two end faces are covered by external electrodes. Therefore, it is able to suppress the infiltration of moisture from the outside, and thus it is judged to be good in the moisture resistance reliability test.

[0146] Furthermore, according to Table 1, the multilayer ceramic capacitor 10, as a sample according to the embodiment, ensures conductivity between the external electrode and the internal electrode layer through the exposed surface, and is deemed good in the ESR measurement test. The ESR measurement test of the multilayer ceramic capacitor 10, as a sample according to the embodiment, is also good, just like the ESR measurement test of the multilayer ceramic capacitor 10A, as a comparative example. Therefore, it can be seen that the presence of the blocking film 28 does not hinder the reduction of ESR resistance. Based on the above, it is clear that the multilayer ceramic capacitor 10, as a sample according to the embodiment, can maintain a low ESR resistance.

[0147] On the other hand, the multilayer ceramic capacitor 10A of the comparative example did not form a barrier film, and was therefore judged to be defective in the moisture resistance reliability test.

[0148] Furthermore, since the stacked ceramic capacitor 10A of the comparative example did not form a blocking film, the conductivity between the internal electrode layer and the plating layer was ensured, and it was judged to be good in the ESR measurement test.

[0149] Based on the above, the multilayer ceramic capacitor 10 of the present invention has barrier films formed on its two end faces, two main faces, and two side faces to cover the surfaces of the multilayer, and the two end faces are covered by external electrodes. Furthermore, the exposed surfaces ensure conductivity between the external electrodes and the internal electrode layers. Therefore, it is clear that moisture intrusion from the outside can be suppressed, moisture resistance reliability can be improved, and low ESR resistance can be maintained.

[0150] Furthermore, since a barrier film is formed between the external electrode and the laminate, moisture resistance and low ESR are achieved. Therefore, it can be assumed that the external electrode and the barrier film are adhered and that the external electrode will not peel off due to the presence of the barrier film.

[0151] Furthermore, as described above, embodiments of the present invention have been disclosed in the foregoing description, but the present invention is not limited thereto.

[0152] That is, without departing from the technical concept and scope of the present invention, various changes can be made to the above-described embodiments regarding the mechanism, shape, material, quantity, position or configuration, etc., and these are included in the present invention.

[0153] <1>

[0154] A multilayer ceramic capacitor, comprising:

[0155] A laminate comprising multiple stacked ceramic layers and multiple internal electrode layers, and including a first main surface and a second main surface opposite each other in the height direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height direction and the width direction.

[0156] A barrier membrane, disposed on the laminate; and

[0157] External electrodes are disposed on the barrier film on the first end face and the second end face.

[0158] The ceramic layer comprises a perovskite compound represented by the general formula ABO3 with Ba at the A site.

[0159] The barrier film comprises at least one of Ba, S, and C.

[0160] The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and covers the first end surface and the second end surface except for the exposed surface of the internal electrode layer in the laminate.

[0161] The external electrode is in contact with the internal electrode layer on the exposed surface.

[0162] <2>

[0163] according to <1> The described multilayer ceramic capacitors, among which,

[0164] The barrier membrane is at least one of barium sulfate and barium carbonate.

[0165] <3>

[0166] according to <1> or <2> The described multilayer ceramic capacitors, among which,

[0167] The internal electrode layer contains Ni as the main component.

[0168] The external electrode has a base electrode layer containing Cu as the main component and a plating layer on the base electrode layer.

[0169] The internal electrode layer and the base electrode layer are in contact at the exposed surface.

[0170] <4>

[0171] according to <3> The described multilayer ceramic capacitors, among which,

[0172] The substrate electrode layer contains glass and metal components.

[0173] <5>

[0174] A method for manufacturing a multilayer ceramic capacitor, comprising:

[0175] The preparation process involves firing to prepare a laminate, which includes multiple ceramic layers and multiple internal electrode layers comprising a perovskite compound represented by the general formula ABO3 and having Ba at the A site, and includes a first main surface and a second main surface opposite each other in the height direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height and width directions.

[0176] The membrane formation process involves forming a barrier membrane containing Ba and at least one of S and C on the laminate by impregnating the laminate in a solution containing at least one of S ions and C ions; and

[0177] In the external electrode forming process, external electrodes are formed on the barrier film on the first end face and the second end face.

[0178] The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and covers the first end surface and the second end surface except for the exposed surface of the internal electrode layer in the laminate.

[0179] The external electrode is in contact with the internal electrode layer on the exposed surface.

[0180] <6>

[0181] according to <5> The method for manufacturing multilayer ceramic capacitors described herein includes,

[0182] The barrier membrane is at least one of barium sulfate and barium carbonate.

[0183] <7>

[0184] according to <5> or <6> The method for manufacturing multilayer ceramic capacitors described herein includes,

[0185] The internal electrode layer contains Ni as the main component.

[0186] The external electrode has a base electrode layer containing Cu as the main component and a plating layer on the base electrode layer.

[0187] The internal electrode layer and the base electrode layer are in contact at the exposed surface.

[0188] <8>

[0189] according to <7> The method for manufacturing multilayer ceramic capacitors described herein includes,

[0190] The substrate electrode layer contains glass and metal components.

[0191] Explanation of reference numerals in the attached figures

[0192] 10-layer ceramic capacitor

[0193] 12-layer stack

[0194] 12a 1st main side

[0195] 12b 2nd main side

[0196] 12c First side

[0197] 12d Second side view

[0198] 12e First end face

[0199] 12f Second end face

[0200] 14 Ceramic Layer

[0201] 15a Effective layer

[0202] 15b First outer layer

[0203] 15c Second outer layer

[0204] 16 Internal electrode layer

[0205] 16a First inner electrode layer

[0206] 16b Second internal electrode layer

[0207] 18a First Opposite Electrode Section

[0208] 18b Second Opposite Electrode Section

[0209] 20a First lead electrode section

[0210] 20b Second lead-out electrode section

[0211] 22a Side (W gap)

[0212] 22b End (L-gap)

[0213] 24 External Electrodes

[0214] 24a First external electrode

[0215] 24b Second external electrode

[0216] 26. Substrate electrode layer

[0217] 26a First base electrode layer

[0218] 26b Second base electrode layer

[0219] 28. Barrier membrane

[0220] 29. Appearance

[0221] 30 coating layers

[0222] 30a First plating layer

[0223] 30b Second plating layer

[0224] 32 Lower plating layer

[0225] 32a First lower plating layer

[0226] 32b Second lower plating layer

[0227] 34 Upper plating layer

[0228] 34a First upper plating layer

[0229] 34b Second upper plating layer

[0230] x height direction

[0231] y-width direction

[0232] z represents the length direction.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising multiple stacked ceramic layers and multiple internal electrode layers, and including a first main surface and a second main surface opposite each other in the height direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height direction and the width direction. A barrier membrane is disposed on the laminate; and External electrodes are disposed on the barrier film on the first end face and the second end face. The ceramic layer comprises a perovskite compound represented by the general formula ABO3 with Ba at the A site. The barrier film comprises at least one of Ba, S, and C. The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and covers the first end surface and the second end surface except for the exposed surface of the internal electrode layer in the laminate. The external electrode is in contact with the internal electrode layer on the exposed surface.

2. The multilayer ceramic capacitor according to claim 1, wherein, The barrier membrane is at least one of barium sulfate and barium carbonate.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The internal electrode layer contains Ni as the main component. The external electrode has a base electrode layer containing Cu as the main component and a plating layer on the base electrode layer. The internal electrode layer and the base electrode layer are in contact at the exposed surface.

4. The multilayer ceramic capacitor according to claim 3, wherein, The substrate electrode layer contains glass and metal components.

5. A method for manufacturing a multilayer ceramic capacitor, comprising: The preparation process involves firing to prepare a laminate, which includes multiple ceramic layers and multiple internal electrode layers comprising a perovskite compound represented by the general formula ABO3 and having Ba at the A site, and includes a first main surface and a second main surface opposite each other in the height direction, a first side surface and a second side surface opposite each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite each other in the length direction orthogonal to the height and width directions. The membrane formation process involves forming a barrier membrane containing Ba and at least one of S and C on the laminate by impregnating the laminate in a solution containing at least one of S ions and C ions; and In the external electrode forming process, external electrodes are formed on the barrier film on the first end face and the second end face. The barrier film covers the first main surface, the second main surface, the first side surface, and the second side surface, and covers the first end surface and the second end surface except for the exposed surface of the internal electrode layer in the laminate. The external electrode is in contact with the internal electrode layer on the exposed surface.

6. The method for manufacturing a multilayer ceramic capacitor according to claim 5, wherein, The barrier membrane is at least one of barium sulfate and barium carbonate.

7. The method for manufacturing a multilayer ceramic capacitor according to claim 5 or 6, wherein, The internal electrode layer contains Ni as the main component. The external electrode has a base electrode layer containing Cu as the main component and a plating layer on the base electrode layer. The internal electrode layer and the base electrode layer are in contact at the exposed surface.

8. The method for manufacturing a multilayer ceramic capacitor according to claim 7, wherein, The substrate electrode layer contains glass and metal components.

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