Full-surrounding gate semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) disposed directly on the support (1a). At least one pFET structure is located directly on the dielectric layer (1b), each pFET structure comprising a first stack of channel nanosheets made of compressively strained silicon germanium and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure is located directly on the dielectric layer, each nFET structure comprising a second stack of channel nanosheets made of silicon and an nFET gate structure encapsulating each channel nanosheet of the second stack.

Description

Technical Field

[0001] This invention relates to a gate-all-around semiconductor structure and a method for fabricating such a structure. Background Technology

[0002] All-around gate semiconductor structures offer many improvements over planar transistors and non-planar (e.g., FinFET) transistors. Specifically, improved gate control for the channel provides greater immunity to short-channel effects and lower leakage current.

[0003] Figures 1A to 1K The diagram illustrates the main steps involved in fabricating a gate-all-around semiconductor structure according to existing techniques. For simplicity, a single structure is shown in the accompanying drawings; however, typically, an array of such structures is fabricated together during the execution of these steps.

[0004] like Figure 1A As shown, a pseudocrystalline superlattice SL, made of a silicon layer SL1 and a compressively strained silicon-germanium layer SL2, is initially grown on a silicon substrate 1 (e.g., a p-type bulk (100) silicon substrate). The silicon-germanium layer SL2 may contain about 30% germanium and have a thickness of about 8 nm to 20 nm. The silicon layer SL1 may have a thickness of about 4 nm to 10 nm.

[0005] Then, before defining the fins 2 in the pseudocrystalline superlattice SL using conventional photolithography and etching techniques, the superlattice SL is protected with a stack of low-temperature oxides and nitrides. The etching can be formed, for example, by reactive ion etching. Figure 1B This indicates the intermediate structure after the etching step.

[0006] In a subsequent step after forming the shallow trench isolation portion, silicon dioxide is deposited on the intermediate structure, and a chemical mechanical planarization (CMP) step is performed to planarize the surface. Low-temperature annealing of the shallow trench isolation portion prior to CMP application is possible. Then, the silicon dioxide is etched back to expose the fin 2, and the shallow trench isolation portion 3 is retained on each side of the fin. This... Figure 1C The Chinese side indicated that...

[0007] In a subsequent step, a dummy gate 4 is formed above the fin 2 by depositing a stack consisting of a relatively thin oxide protective film and a relatively thick amorphous or polycrystalline silicon layer. For example... Figure 1D As indicated, a dummy gate 4 is defined in the stacked body by photolithography and etching. Then, silicon nitride spacers 5 are formed on each side of the dummy gate 4 by deposition and etching.

[0008] In a subsequent step, a dual source / drain electrode 6 is formed by extending the electrode onto each side of the fin against the spacer 5.

[0009] Then, in Figure 1FA first interlayer dielectric layer 7 is formed above the intermediate structure. This first interlayer dielectric layer is planarized by CMP to expose the top of the dummy gate 4, as shown below. Figure 1G As shown, the dummy gate 4 can then be removed, for example, by wet etching. Figure 1H In the resulting intermediate structure, the pseudocrystalline superlattice SL is partially exposed by removing the pseudo-gate 4. Then, the suspended channel nanosheets 8 extending between the source / drain regions 6 of the semiconductor structure are defined by selectively removing the silicon-germanium layer SL2. Then, a gate structure 9 made of multiple layers of high-k materials (i.e., materials with a dielectric value greater than that of silicon dioxide) and metal is deposited, for example, by atomic layer deposition, to completely encapsulate each channel nanosheet 8, forming a fully enclosed gate structure, such as... Figure 1J As shown.

[0010] In the CMP planarization step used to remove excess metal deposits ( Figure 1K After that, another interlayer dielectric layer 7 can be formed on the intermediate structure. Figure 1L Gate vias, source vias, and drain vias (not shown) can be formed in the interlayer dielectric layer 7 to contact the corresponding electrodes, respectively.

[0011] As reported in Sun X et al.'s paper "A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation" Nanomaterials 2023, 13, 504, the main conductive surface orientation in channel nanosheets is typically (100), resulting in an imbalance in the mobility of holes and electrons entering these channels. To achieve current matching between the pFET and nFET structures of the device, compressive stress can be introduced into the channel nanosheets of the pFET structure to enhance hole mobility.

[0012] In document US2021 / 0151601, a strain material is formed along the sidewall surface of the gate. The strain material is configured to generate strain in the channel nanosheet.

[0013] In document US2023031490, a substrate comprising a surface-relaxed silicon-germanium region and a surface silicon region is fabricated. The pFET structure is formed from strained silicon-germanium material formed over the surface silicon region. The nFET structure is formed from strained silicon material formed over the surface-relaxed silicon-germanium region. The surface-relaxed silicon-germanium region and the surface silicon region are retained in the final structure, and neither the nFET nor the pFET structure directly relies on a dielectric layer.

[0014] In document US2023147499A1, channel nanosheets of silicon-germanium (SiGe) or germanium-tin (GeSn) are formed and subsequently annealed to drive germanium or tin inward along a portion of the channel nanosheets, thereby increasing the germanium or tin concentration and providing strain to the channel. The channel nanosheets constituting the nFET and pFET structures must be staggered and non-coplanar. In this case, the nFET and pFET structures do not rely directly on the dielectric layer.

[0015] Purpose of the invention

[0016] The object of the present invention is to provide a semiconductor structure that at least partially compensates for the unbalanced current matching between pFET and nFET full-around-gate structures.

[0017] Another object of the present invention is to provide a method for preparing such a semiconductor structure. Summary of the Invention

[0018] Therefore, the present invention relates to a semiconductor structure, the semiconductor structure comprising: a. Support structure; b. A dielectric layer, wherein the dielectric layer is directly disposed on the support; c. At least one pFET structure, said at least one pFET structure being directly located on the dielectric layer, each pFET structure comprising: i. A first stack of channel nanosheets made of compressively strained silicon-germanium; ii. A pFET gate structure encapsulating each channel nanosheet of the first stack; and d. At least one nFET structure, said at least one nFET structure being directly located on the dielectric layer, each nFET structure comprising: i. A second stack of channel nanosheets made of silicon; ii. An nFET gate structure that encapsulates each channel nanosheet of the second stack.

[0019] According to further non-limiting features of the invention, either alone or in any technically feasible combination: - The channel nanosheets in the first stack of channel nanosheets are coplanar with the channel nanosheets in the second stack of channel nanosheets; - The silicon in the channel nanosheets of the second stack is under tensile strain; - The semiconductor structure further includes: A source pFET region and a drain pFET region, the source pFET region and the drain pFET region being formed on the support and respectively associated with the channel nanosheets of the first stack; and A source nFET region and a drain nFET region are formed on the support and are respectively associated with the channel nanosheet of the second stack; - The semiconductor structure further includes a boundary trench that separates the pFET structure and the nFET structure; - The channel nanosheets of the first stack and the channel nanosheets of the second stack have a thickness between 4 nm and 20 nm.

[0020] According to another aspect, the present invention relates to a method for preparing a semiconductor structure, the method comprising the following steps: a. A substrate is provided, the substrate comprising a support, a dielectric layer disposed directly on the support, and a top silicon film disposed directly on the dielectric layer (1c). b. In the pFET region of the substrate, a portion of the top silicon film is transformed into a compressive strain silicon-germanium film, and the remaining portion of the top silicon film forms the nFET region of the substrate; c. Selectively growing a first pseudocrystalline superlattice made of a silicon layer and a compressively strained silicon-germanium layer on the pFET region; d. Define at least one pFET structure directly located on the dielectric layer by the following steps: i. Selectively remove the silicon layer of the first pseudocrystalline superlattice to define a first stack of channel nanosheets made of the compressively strained silicon-germanium layer; ii. A pFET gate structure is formed by deposition to encapsulate each channel nanosheet of the first stack. e. Selectively growing a second pseudocrystalline superlattice made of silicon and silicon-germanium layers on the nFET region; f. Define at least one nFET structure directly located on the dielectric layer by the following steps: i. Selectively remove the silicon-germanium layer of the second pseudocrystalline superlattice to define a second stack of channel nanosheets made of the silicon layer; ii. An nFET gate structure is formed by deposition to encapsulate each channel nanosheet of the second stack.

[0021] Further non-limiting features of this aspect of the invention, either alone or in any technically feasible combination: - The top silicon film of the substrate is under tensile strain; - Prior to the step of transforming a portion of the top silicon film, the method further includes the step of: at least partially relaxing the tensile strain of the top silicon film in the pFET region; - Relaxing the tensile strain includes: in the pFET region, amorphizing a portion of the top silicon film by ion implantation, and heat-treating the substrate to recrystallize the amorphous portion; - Transformation of a portion of the top silicon film includes: A germanium-rich layer is selectively formed on the top silicon film of the pFET region; and At least a portion of the germanium-rich layer is oxidized to allow germanium material to diffuse into the top silicon film in the pFET region, thereby forming the compressive strain silicon-germanium layer; - Wherein, the germanium-rich layer is a silicon-germanium layer, the silicon-germanium layer has a germanium concentration between 10% and 20%, and has a thickness between 5 nm and 10 nm; - The silicon layers of the first pseudocrystalline superlattice each have a thickness between 4 nm and 20 nm, and the silicon-germanium layers of the first pseudocrystalline superlattice each have a thickness between 4 nm and 20 nm. - The silicon-germanium layers of the second pseudocrystalline superlattice each have a thickness between 4 nm and 20 nm, and the silicon layers of the second pseudocrystalline superlattice each have a thickness between 4 nm and 20 nm. Attached Figure Description

[0022] Many other features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which... [ Figure 1A ][ Figure 1B ][ Figure 1C ][ Figure 1D ][ Figure 1F ][ Figure 1G ][ Figure 1H ][ Figure 1I ][ Figure 1J ][ Figure 1K ] Figures 1A to 1K This describes a method for fabricating a semiconductor all-around gate structure using existing technology; [ Figure 2A ][ Figure 2B ][ Figure 2C ][ Figure 2D ][ Figure 2E ][ Figure 2F][ Figure 2G ][ Figure 2H ][ Figure 2I ][ Figure 2J ][ Figure 2K ][ Figure 2L ][ Figure 2M ][ Figure 2N ][ Figure 2O ][ Figure 2P ][ Figure 2Q ] Figures 2A to 2Q This describes a method for preparing a semiconductor all-around gate structure according to the present invention; [ Figure 3A ][ Figure 3B ][ Figure 3C ][ Figure 3D ] Figure 3A , Figure 3B , Figure 2C and Figure 3D A specific application of the method for manufacturing a fork-type FET structure according to the present invention is illustrated. Detailed Implementation

[0023] The illustrations presented herein are not intended to be actual views of any particular semiconductor structure, device, system, or method, but are merely idealized representations used to describe embodiments of this disclosure.

[0024] The following is a reference to the appendix. Figures 2A to 2Q Describe a method that can be used to manufacture semiconductor structures.

[0025] exist Figure 2A The first step of the method according to the present invention is to provide a substrate 1. The substrate 1 includes a support 1a, a dielectric layer 1b directly disposed on the support 1a, and a top silicon film 1c directly disposed on the dielectric layer 1b. The substrate 1 can be in the form of a circular wafer with a diameter of 100 mm, 150 mm, 200 mm, 300 mm, or even 450 mm.

[0026] The support 1a is typically several hundred micrometers thick, sufficient to self-support and accommodate other layers forming the substrate 1. For usability and cost reasons, the support 1a is preferably made of monocrystalline silicon. It may include a surface charge trapping layer (such as a surface polycrystalline silicon layer) disposed below and in contact with the dielectric layer 1b.

[0027] The dielectric layer 1b can have a thickness between 10 nm and 1 micrometer. In some embodiments, a thin dielectric layer 1b of less than 20 nm may be preferred to allow for better thermal diffusion to the underlying support. Furthermore, if the dielectric layer 1b is intended to also replace the shallow trench isolation portion, as will be presented in more detail below, a greater thickness can be selected, for example, 90 nm or greater. The dielectric layer 1b can be formed of any dielectric material, but preferably, it consists of a silicon dioxide layer.

[0028] The top silicon film 1c is made of single-crystal silicon. It can have a thickness between 4 nm and 20 nm. In some embodiments, the top silicon film 1c is non-strained. In other embodiments, the top silicon film 1c has tensile strain, typically between 0.5 GPa and 2 GPa. Methods for preparing such strained top silicon layers are well known, for example, as described in US6953736B2.

[0029] The second step of the method according to the invention includes patterning a top silicon film 1c to define two distinct regions of a substrate 1 extending above the surface of the film. A first region, designated a "pFET region," is configured to receive at least one pFET structure, and a second region, designated an "nFET region," is configured to receive at least one nFET structure. As is well known to those skilled in the art, a pFET structure is a semiconductor device (such as a transistor) that includes a low-p-doped channel disposed between a heavily p-doped drain region and a heavily p-doped source region. In a pFET structure, the current carriers are holes. Similarly, an nFET structure is a semiconductor device (such as a transistor) that includes a low-n-doped channel disposed between a heavily n-doped drain region and a heavily n-doped source region. In an nFET structure, the current carriers are electrons.

[0030] The pFET and nFET regions do not need to be continuous regions. Each of these regions can be formed by unconnected sub-regions arranged above the surface of the top silicon film 1c to lay out that surface.

[0031] The pFET region of substrate 1 is defined by transforming a portion of the top silicon film 1c into a compressive strain silicon-germanium film 1c'. The remaining portion of the top silicon film 1c forms the nFET region of substrate 1. This can be determined according to... Figures 2B to 2F The steps shown are transformed.

[0032] exist Figure 2BIn this embodiment, the top silicon film 1c of substrate 1 is completely covered by a protective layer 1d. The protective layer may comprise a single layer or multiple layers of protective material. Typically, the protective layer 1d may comprise a relatively thin pad silicon oxide film that contacts the top silicon film 1c and is covered by a relatively thick silicon nitride film. The pad silicon oxide film may have a thickness between 2 nm and 5 nm, and the silicon nitride film may have a thickness between 20 nm and 100 nm.

[0033] exist Figure 2C The subsequent steps shown involve using conventional photolithography techniques, employing a photoresist mask layer 1e disposed on the protective layer 1d, and etching to open the protective layer 1d, selectively exposing the top silicon film 1c. This opening (which can be discontinuous and formed by unconnected sub-regions, as mentioned above) corresponds to the pFET region of the substrate. The unexposed portion of the top silicon film 1c forms the nFET region of the substrate 1.

[0034] If the top silicon film 1c is under tensile strain, the implementation may include: selectively releasing the tensile strain of the top silicon film 1c in the pFET region of the substrate during opening formation, such as in Figure 2D This can be performed by selectively etching the silicon nitride of the protective layer 1d film while retaining the pad silicon oxide film on the pFET region during aperture formation. The nFET region is protected by a photoresist mask layer 1e, ensuring that the region remains unaffected by strain release operations. Atomic materials such as argon, germanium, or silicon can then be selectively injected through the pad silicon oxide film into the bottom of the top silicon film 1c of the pFET region (i.e., the portion of the film in contact with the dielectric layer 1b). This injection can amorphize the bottom of the top silicon film 1c in the pFET region and release tensile strain. Then, after removing the photoresist mask layer 1e, a low-temperature annealing applied to the substrate 1 can be applied to recrystallize the amorphous portion of the top silicon film 1c. The pad silicon oxide film above the pFET region is then removed to obtain... Figure 2C The structure shown.

[0035] Regardless of whether the strain release step has been performed, substrate 1 has a top silicon film 1c made of monocrystalline silicon. The portion of the top silicon film 1c corresponding to the pFET region is unstrained and exposed, while the portion of the top silicon film 1c corresponding to the nFET region is disposed below the protective layer 1d. If the initially supplied substrate 1 includes such a strained top silicon layer 1c, this portion may be under tensile strain.

[0036] Then, as Figure 2E and Figure 2FAs shown, a germanium-rich layer 1f (such as a silicon-germanium film 1f) is epitaxially and selectively formed on the exposed pFET region of the top silicon film 1c. The epitaxial silicon-germanium film 1f can typically contain a germanium content between 10% and 20% and can have a thickness between 4 nm and 20 nm. The substrate 1 is then exposed to an oxygen-rich atmosphere and the epitaxial silicon-germanium film 1f is oxidized. During this oxidation step, oxygen from the oxygen-rich atmosphere bonds with the silicon of the silicon-germanium film to form a surface silicon oxide layer 1g. The germanium material is not oxidized and is implanted into the underlying top silicon film 1c, as explained in US9219150B1, to form a compressive strain silicon-germanium film 1c'.

[0037] Following this oxidation step, the portion of the top silicon film 1c located in the pFET region is transformed into a compressive strained silicon-germanium film 1c'. The portion of the top silicon film 1c located in the nFET region remains unaffected by this step, and its crystalline silicon properties are preserved. After removing the surface silicon oxide layer 1g, the following is obtained: Figure 2G The structure shown forms a platform for providing at least one pFET structure on the pFET region of the substrate (i.e., on the compressively strained silicon-germanium layer 1c'), the pFET structure benefiting from the exposed strained germanium layer 1c'. Furthermore, at least one nFET structure is formed on the nFET region of the substrate (i.e., on the strained or unstrained top silicon film 1c).

[0038] More precisely, in Figure 2H The next step, as shown, involves growing a first pseudocrystalline superlattice SL' on the exposed compressive strain silicon-germanium film 1c', consisting of a silicon layer SL1' and a compressive strain silicon-germanium layer SL2'. The compressive strain silicon-germanium layer SL2' of the first pseudocrystalline superlattice SL' may contain approximately 30% germanium and have a thickness between 4 nm and 20 nm, while the silicon layer SL1' of the superlattice SL' may have a thickness between 4 nm and 20 nm. The layers of the first pseudocrystalline superlattice SL' may be grown undoped or slightly p-doped.

[0039] Then, as Figure 2I As shown, an additional protective layer 1d' is disposed above the substrate 1. This additional protective layer 1d' may also include a thin CVD or ALD silicon oxide pad layer covered by a silicon nitride layer. The protective layers 1d and 1d' can then be selectively removed by photolithography and wet or dry etching to expose the top silicon film 1c in the nFET region of the substrate 1. Advantageously, the protective layers 1d and 1d' are not completely removed above the nFET region, and a residual portion 1d'' is retained to encapsulate the side of the first pseudocrystalline superlattice SL', as shown in Figure 2J As can be seen in the image. Then, a second pseudocrystalline superlattice SL, made of silicon layer SL1 and silicon-germanium layer SL2, is grown on the exposed top silicon layer 1c of the nFET region. Figure 2KThe silicon-germanium layer SL2 of the second pseudocrystalline superlattice SL can contain approximately 30% germanium and have a thickness between 4 nm and 20 nm, while the silicon layer SL1 of the second pseudocrystalline superlattice SL can have a thickness between 4 nm and 20 nm. The layers of the second pseudocrystalline superlattice SL can be grown undoped or slightly n-doped.

[0040] Then, remove the additional protective layer 1d' and the remaining portion 1d'' of the protective layer 1d', as follows: Figure 2L As shown. On the obtained substrate 1, by using... Figures 1A to 1K The main steps in fabricating the fully all-around gate semiconductor structure shown can be to directly define at least one pFET structure in the pFET region and at least one nFET structure in the nFET region. The pFET structure and the nFET structure are directly located on the dielectric layer 1b.

[0041] More specifically, the first pseudocrystalline superlattice SL and the second pseudocrystalline superlattice SL' can be patterned and etched to define at least one nFET fin 2 in the first pseudocrystalline superlattice SL and a pFET fin 2' in the second pseudocrystalline superlattice SL'. The etched openings can extend down into the dielectric layer 1b (and in this case, the dielectric layer preferably has a thickness equal to or greater than 90 nm, as previously described). If shallow trench isolation is required, the openings can be defined to penetrate into the support 1a, through the dielectric layer 1b, and can then be filled with recessed silicon oxide. The substrate can be polished to remove any excess recessed silicon oxide.

[0042] Advantageously, at least one of the openings is formed at the boundary between the pFET region and the nFET region to electrically isolate the two regions from each other. This opening is filled with oxide to form a boundary trench 10, which will be retained during the remaining process steps to maintain the electrical isolation by protecting it with a protective layer. Figure 2M ).

[0043] In the next step, the pFET region and nFET region are processed to form a dummy gate 4, thereby defining silicon nitride spacers on each side of the dummy gate, epitaxially depositing dual source / drain electrodes on each side of the fins 2, 2' (e.g., in-situ doped epitaxial formation of source and drain electrodes), and depositing an interlayer dielectric layer 7. Figure 2N ).

[0044] like Figure 2OAs shown, a protective layer 1d is then selectively formed over the nFET region, and the pFET fin 2' is partially exposed by selectively removing the dummy gate 4. A suspended channel nanosheet extending between the source and drain regions defines the pFET semiconductor structure by selectively removing the silicon layer SL1' (e.g., by wet etching). Etching reveals a first stack of channel nanosheets 8' made of compressively strained silicon germanium SL2'. Then, a pFET gate structure 9' made of multiple layers of high-k materials (such as hafnium oxide) and p-work function metals is deposited, for example, by atomic layer deposition, to completely encapsulate each channel nanosheet 8', forming a fully all-around gate pFET structure. Figure 2P ).

[0045] The same process is repeated on the nFET region, while the pFET region is protected by a selectively formed protective layer. The suspended channel nanosheets 8 extending between the source and drain regions define the nFET semiconductor structure by selectively removing the silicon-germanium layer SL2 of the nFET fins (e.g., by wet etching). The etching reveals a first stack of channel nanosheets 8 made of silicon SL1. If the initial top silicon layer 1c is initially strained, the channel nanosheets 8 may also be strained. An nFET gate structure 9 made of multiple layers of high-k materials (such as hafnium oxide) and an n work function metal is then deposited, for example, by atomic layer deposition, to completely encapsulate each channel nanosheet 8, forming a full-around-gate nFET structure.

[0046] After removing the protective layer 1d, and as Figure 2Q As shown, the method according to the present invention produces a semiconductor structure SC including a support 1a and a dielectric layer 1b directly disposed on the support 1a. At least one pFET structure is directly disposed on the dielectric layer 1b. Each pFET structure includes a first stack of channel nanosheets 8' made of compressively strained silicon germanium and a pFET gate structure 9' encapsulating each channel nanosheet 8 of the first stack. The semiconductor structure SC also includes at least one nFET structure directly disposed on the dielectric layer 1b. Each nFET structure includes a second stack of channel nanosheets 8 made of silicon and an nFET gate structure 9' encapsulating each channel nanosheet 8 of the second stack. The pFET structure and the nFET structure are separated by a boundary trench 10.

[0047] Regarding "directly located on the dielectric layer," it refers to the channel nanosheets (the first channel nanosheet in each stack) of the pFET and nFET structures being in contact with the dielectric layer 1b. Therefore, the channel nanosheets 8' of the pFET structure and 8' of the nFET structure according to the present invention are coplanar.

[0048] Although not visible in the figure, the semiconductor structure SC also includes source and drain pFET regions (n-doped) formed on the support and associated with the channel nanosheets of the first stack, and source and drain nFET regions (p-doped) formed on the support and associated with the channel nanosheets of the second stack.

[0049] The method according to the invention can be used to form a so-called fork-type FET structure. The fork-type FET structure includes both an nFET structure and a pFET structure, wherein a thin dielectric wall separates the two structures.

[0050] like Figure 3A As shown, the method according to the invention is applied to substrate 1 to define a plurality of pFET sub-regions and nFET sub-regions that are adjacent to each other and are deposited on the front side of the substrate. Figures 2A to 2L The steps shown can be applied to substrate 1 accordingly.

[0051] The pFET subregion and nFET subregion are separated from each other by a boundary trench 1t. A portion of the top silicon layer 1c forms the bottom of the boundary trench. According to one embodiment, this portion can be removed by etching, and the trench is filled with a dielectric such as silicon nitride to form multiple boundary trenches, thereby completely electrically isolating the pFET subregion and nFET subregion. Figure 3B ).

[0052] This method can then be applied to the resulting structure to define two pFET fins 2' in the pFET subregion and two nFET fins 2 in the nFET subregion, as follows. Figure 3C As shown. After completing the pFET and nFET structures, multiple fork-type semiconductor structures FS1 to FS5 can be defined by grouping adjacent pFET and nFET structures together, such as... Figure 3D As shown.

[0053] By studying the accompanying drawings, the disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention.

[0054] Specifically, the thickness of the channel nanosheets can be selected based on the end application of the structure. Digital applications typically require or benefit from thinner channels, so the channel nanosheet thickness can be selected between 4 nm and 10 nm. Simulation applications may require or benefit from thicker channels, so the channel nanosheet thickness can be selected between 10 nm and 20 nm for that application.

[0055] Multiple semiconductor structures according to the present invention can be stacked together in a 3D structure, or fabricated individually and connected in a system using 2.5D or 3D integration or packaging methods.

Claims

1. A semiconductor structure (SC), said SC comprising: a. Support structure (1a); b. A dielectric layer (1b), which is disposed directly on the support (1a); c. At least one pFET structure, said at least one pFET structure being directly located on the dielectric layer (1b), each pFET structure comprising: i. A first stack of channel nanosheets made of compressively strained silicon-germanium; ii. A pFET gate structure encapsulating each channel nanosheet of the first stack; and d. At least one nFET structure, said at least one nFET structure being directly located on the dielectric layer, each nFET structure comprising: i. A second stack of channel nanosheets made of silicon; ii. An nFET gate structure that encapsulates each channel nanosheet of the second stack.

2. The semiconductor structure according to claim 1, wherein, The channel nanosheets in the first stack of channel nanosheets are coplanar with the channel nanosheets in the second stack of channel nanosheets.

3. The semiconductor structure according to claim 1 or 2, wherein, The silicon in the channel nanosheets of the second stack is under tensile strain.

4. The semiconductor structure according to any one of the preceding claims, wherein the semiconductor structure further comprises: a. A source pFET region and a drain pFET region, wherein the source pFET region and the drain pFET region are formed on the support and are respectively associated with the channel nanosheet of the first stack; as well as b. A source nFET region and a drain nFET region, the source nFET region and the drain nFET region being formed on the support and respectively associated with the channel nanosheet of the second stack.

5. The semiconductor structure according to any one of the preceding claims, the semiconductor structure further comprising a boundary trench (10) separating the pFET structure and the nFET structure.

6. The semiconductor structure according to any one of the preceding claims, wherein, The channel nanosheets of the first stack and the channel nanosheets of the second stack have a thickness between 4 nm and 20 nm.

7. A method for fabricating a semiconductor structure (SC), the method comprising the following steps: a. Provide a substrate (1), the substrate (1) including a support (1a), a dielectric layer (1b) directly disposed on the support (1a) and a top silicon film (1c) directly disposed on the dielectric layer (1b). b. In the pFET region of the substrate (1), a portion of the top silicon film (1c) is transformed into a compressive strain silicon-germanium film (1c'), and the remaining portion of the top silicon film (1c) forms the nFET region of the substrate (1); c. Selectively grow a first pseudomorphic superlattice (SL') made of a silicon layer (SL1') and a compressively strained silicon-germanium layer (SL2') on the pFET region; d. Define at least one pFET structure directly located on the dielectric layer (1b) by the following steps: i. Selectively remove the silicon layer of the first pseudocrystalline superlattice (SL') to define a first stack of channel nanosheets (8') made of the compressively strained silicon-germanium layer; ii. Forming a pFET gate structure (9') by deposition to encapsulate each channel nanosheet of the first stack. e. Selectively grow a second pseudocrystalline superlattice (SL) made of a silicon layer (SL1) and a silicon-germanium layer (SL2) on the nFET region; f. Define at least one nFET structure directly located on the dielectric layer (1b) by the following steps: i. Selectively remove the silicon-germanium layer (SL2) of the second pseudocrystalline superlattice (SL) to define a second stack of channel nanosheets (8) made of the silicon layer (SL1); ii. An nFET gate structure (9) is formed by deposition to encapsulate each channel nanosheet (8) of the second stack.

8. The method according to claim 7, wherein, The top silicon film (1c) of the substrate (1) is under tensile strain.

9. The method of claim 8, further comprising the step of transforming a portion of the top silicon film (1c) prior to the step of: The tensile strain of the top silicon film (1c) is at least partially relaxed in the pFET region.

10. The method according to claim 9, wherein, Relaxing the tensile strain includes: in the pFET region, amorphizing a portion of the top silicon film (1b) by ion implantation, and heat-treating the substrate (1) to recrystallize the amorphous portion.

11. The method according to claims 7 to 10, wherein, Transformation of a portion of the top silicon film (1c) includes: a. Selectively forming a germanium-rich layer (1f) on the top silicon film (1c) of the pFET region; and b. Oxidize at least a portion of the germanium-rich layer (1f) to allow germanium material to diffuse into the top silicon film (1) in the pFET region, thereby forming the compressive strain silicon-germanium layer.

12. The method according to claim 11, wherein, The germanium-rich layer (1f) is a silicon-germanium layer having a germanium concentration between 10% and 20% and a thickness between 5 nm and 10 nm.

13. The method according to any one of claims 7 to 12, wherein, The silicon layer (SL1') of the first pseudocrystalline superlattice (SL') each has a thickness between 4 nm and 20 nm, and the silicon-germanium layer (SL2') of the first pseudocrystalline superlattice (SL) each has a thickness between 4 nm and 20 nm.

14. The method according to any one of claims 7 to 13, wherein, The silicon-germanium layer (SL2) of the second pseudocrystalline superlattice (SL) each has a thickness between 4 nm and 20 nm, and the silicon layer (SL1) of the second pseudocrystalline superlattice (SL) each has a thickness between 4 nm and 20 nm.

Images