Pickcake-shaped radio frequency (RF) switch

Abstract

A radio frequency (RF) switch is described herein. The RF switch includes a two-dimensional (2D) gate array surrounding a source / drain region and a drain / source region. The RF switch also includes a backside source / drain contact coupled to the source / drain region at a backside of the 2D gate array. The RF switch further includes a backside metallization layer coupled to the backside source / drain contact. The RF switch also includes a front side drain / source contact coupled to the drain / source region at a front side of the 2D gate array opposite the backside. The RF switch further includes a front side metallization layer coupled to the front side drain / source contact.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 362,831, filed July 31, 2023, entitled “WAFFLE-SHAPED RADIO FREQUENCY (RF) SWITCH”, the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0002] This disclosure relates to integrated circuits (ICs). More specifically, this disclosure relates to a muffin-shaped radio frequency (RF) switch. Background Technology

[0003] The design complexity of mobile radio frequency (RF) chips (e.g., mobile RF transceivers) is compounded by the added circuitry to support enhanced communications. Designing mobile RF transceivers may involve the use of semiconductor-on-insulator (SOI) technology. SOI technology replaces conventional semiconductor (e.g., silicon) substrates with layered semiconductor-insulator (e.g., buried oxide (BOX) layers) semiconductor substrates to reduce parasitic device capacitance and improve performance. For example, high-performance complementary metal-oxide-semiconductor (CMOS) radio frequency (RF) switches are currently fabricated using SOI substrates.

[0004] In fact, reducing the switching area is a major factor in RF switch design. The industry desires to reduce the size of the RF chip package without compromising RF switch performance. Traditional RF switch structures haven't changed from linear finger-type transistors with multiple fingers. This structure is a one-dimensional gate array. Conventional solutions for reducing RF switch size involve reducing the gate-to-gate pitch, thereby reducing the overall area. A solution that reduces the size of the RF chip package without compromising RF switch performance is desired. Summary of the Invention

[0005] This document describes a radio frequency (RF) switch. The RF switch includes a two-dimensional (2D) gate array surrounding a source / drain region and a drain / source region. The RF switch also includes a back-side source / drain contact coupled to the source / drain region at the back side of the 2D gate array. The RF switch further includes a back-side metallization layer coupled to the back-side source / drain contact. The RF switch also includes a front-side drain / source contact coupled to the drain / source region at the front side of the 2D gate array opposite to the back side. The RF switch further includes a front-side metallization layer coupled to the front-side drain / source contact.

[0006] This document describes a method for constructing a radio frequency (RF) switch. The method includes: forming a two-dimensional (2D) gate array surrounding a plurality of source / drain regions and a plurality of drain / source regions. The method further includes: forming a back-side source / drain contact coupled to the plurality of source / drain regions at the back side of the 2D gate array. The method further includes: forming a back-side metallization layer coupled to the back-side source / drain contact. The method further includes: forming a front-side drain / source contact coupled to the plurality of drain / source regions at the front side of the 2D gate array opposite to the back side. The method further includes: forming a front-side metallization layer coupled to the front-side drain / source contact.

[0007] This has broadly outlined the features and technical advantages of this disclosure in order to provide a better understanding of the following detailed description. Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for performing the same purposes of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0008] To gain a more complete understanding of this disclosure, reference is now made to the following description in conjunction with the accompanying drawings.

[0009] Figure 1 This is a schematic diagram of a wireless device having a wireless local area network module and a radio frequency (RF) front-end module for a chipset, according to various aspects of this disclosure, wherein the wireless device includes a muffin-shaped RF switch.

[0010] Figure 2 A cross-sectional view of a radio frequency integrated circuit (RFIC) according to various aspects of the present disclosure is shown, wherein the RFIC includes an RF insulator-on-silicon (SOI) device that can be used to implement a muffin-shaped radio frequency (RF) switch.

[0011] Figure 3 This is a block diagram illustrating a top view of a conventional radio frequency (RF) switch structure having a linear finger-type transistor with multiple fingers.

[0012] Figure 4This is a block diagram illustrating a top view of a muffin-shaped radio frequency (RF) switching field-effect transistor (FET) according to various aspects of this disclosure.

[0013] Figures 5A to 5C This illustrates various aspects of this disclosure. Figure 4 Block diagram of perspective and cross-sectional view of a muffin-shaped radio frequency (RF) switching field-effect transistor (FET).

[0014] Figure 6A and Figure 6B These are schematic diagrams illustrating top views and enlarged top views of a muffin-shaped radio frequency (RF) switching field-effect transistor (FET) according to various aspects of this disclosure.

[0015] Figure 7 This is a flowchart illustrating various aspects of the present disclosure of a method for constructing a radio frequency (RF) switch having a muffin shape.

[0016] Figure 8 This is a block diagram illustrating an exemplary wireless communication system in which the configurations of this disclosure may be advantageously employed.

[0017] Figure 9 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration. Detailed Implementation

[0018] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0019] As described herein, the term “and / or” is used to indicate “inclusive or”, and the term “or” is used to indicate “exclusive or”. As described herein, the term “exemplary” as used throughout the description means “serving as an example, instance, or illustration” and is not necessarily to be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” as used throughout the description means “direct or indirectly connected via an intermediate connection (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Furthermore, a connection can permanently or releasably connect objects. Connections can be made via switches. As described herein, the term “proximity” as used throughout the description means “adjacent, very close, adjacent, or near.” As described herein, the term “on” as used throughout the description means “directly on” in some configurations and “indirectly on” in others.

[0020] Due to cost and power consumption considerations, mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to deep submicron process nodes. Designing mobile RF transceivers may include the use of semiconductor-on-insulator (SOI) technology. SOI technology replaces conventional silicon substrates with layered semiconductor-insulator (e.g., buried oxide (BOX) layers) semiconductor substrates to reduce parasitic device capacitance and improve performance. Active devices on the SOI layer may include high-performance complementary metal-oxide-semiconductor (CMOS) transistors. For example, high-performance CMOS RF switching technology is currently fabricated using SOI substrates.

[0021] RF front-ends (RFFEs) rely on such high-performance CMOS RF switching technologies to successfully operate high-performance CMOS RF switching technology. Therefore, a process for manufacturing RFFEs involves expensive SOI wafer integration to support such high-performance CMOS RF switching technologies. In fact, reducing the switch area is a major factor in RF switch design. Indeed, the industry desires to reduce the size of the RF chip package without compromising RF switch performance.

[0022] Traditional RF switch structures have not changed from linear finger-type transistors with multiple fingers. This RF switch structure consists of a one-dimensional gate array. Conventional solutions for reducing RF switch size involve reducing the gate-to-gate pitch, thereby reducing the overall area. Furthermore, traditional RF switch structures rely on the left and right sides of the gate metal contacts to provide the front metal contacts. The front metal contacts in traditional RF switch structures fundamentally limit the interconnects and current paths of the RF switch. A solution that reduces the size of the RF chip package without compromising RF switch performance is desired.

[0023] Various aspects of this disclosure provide techniques for muffin-shaped radio frequency (RF) switches. The semiconductor manufacturing process flow for muffin-shaped RF switches may include front-end process (FEOL), mid-end process (MOL), and back-end process (BEOL). It should be understood that the term "layer" includes films and will not be construed as indicating vertical or horizontal thickness unless otherwise stated. As described herein, the term "substrate" may refer to the substrate of a diced wafer or the substrate of an undicated wafer. Similarly, the terms "chip" and "die" are used interchangeably.

[0024] Various aspects of this disclosure relate to a muffin-shaped radio frequency (RF) switch. Specifically, various aspects of this disclosure employ a muffin-shaped RF switch comprising a two-dimensional (2D) gate array surrounding a source / drain region and a drain / source region. In this configuration, the 2D gate array includes a front side and a back side opposite the front side. The muffin-shaped RF switch includes a back-side source / drain contact coupled to the source / drain region at the back side of the 2D gate array. The RF switch further includes a back-side metallization layer coupled to the back-side source / drain contact. Additionally, the RF switch includes a front-side drain / drain contact coupled to the drain / source region at the front side of the 2D gate array. The RF switch further includes a front metallization layer coupled to the front drain / source contact.

[0025] According to various aspects of this disclosure, a waffle-shaped RF switch provides a novel structure that utilizes four or more contact corners, maximizing the efficiency of the total channel width per unit area. According to the waffle-shaped switch structure, a 2D gate array is surrounded by contacts in the source and drain regions. Because the front and back contacts are separate, the back contacts and metallization process work together to realize this waffle-shaped switch structure. It is proposed that the waffle-shaped switch structure enhances the use of metal contacts, thereby reducing the area while maintaining the same total width. Furthermore, using proprietary processing techniques, the area of ​​the RF switch can be significantly reduced (e.g., by 28%) compared to a reference linear switch structure with the same total channel width. Further area reduction can be achieved by optimizing the back-side process.

[0026] Figure 1This is a schematic diagram of a wireless device 100 (e.g., a mobile phone or smartphone) according to various aspects of this disclosure, which includes a muffin-shaped radio frequency (RF) switching device. The wireless device 100 has a wireless local area network (WLAN) (e.g., Wi-Fi) module 150 for a chipset 110 and an RF front-end module 170. The Wi-Fi module 150 includes a first duplexer 160 that communicatively couples an antenna 162 to the WLAN module (e.g., WLAN module 152). The RF front-end module 170 includes a second duplexer 190 that communicatively couples the antenna 192 to a wireless transceiver 120 (WTR) via a duplexer 180 (DUP). The RF switch 172 (e.g., a muffin-shaped RF switching device) communicatively couples the second duplexer 190 to the duplexer 180. The wireless transceiver 120 and the WLAN module 152 of the WIFI module 150 are coupled to a modem (MSM, such as a baseband modem) 130, which is powered by a power supply 102 via a power management integrated circuit (PMIC) 140. Chipset 110 also includes capacitors 112 and 114, and an inductor 116 to provide signal integrity. The PMIC 140, modem 130, wireless transceiver 120, and WLAN module 152 each include capacitors (e.g., 142, 132, 122, and 154) and operate according to a clock 118. The geometry and arrangement of the various inductor and capacitor assemblies in chipset 110 reduce electromagnetic coupling between components.

[0027] The wireless transceiver 120 of the wireless device includes a mobile RF transceiver for transmitting and receiving data for bidirectional communication. The mobile RF transceiver may include a transmitting section for data transmission and a receiving section for data reception. For data transmission, the transmitting section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal with an appropriate output power level, and transmit the amplified RF signal to a base station via antenna 192. For data reception, the receiving section may obtain the received RF signal via an antenna, amplify the received RF signal using a low-noise amplifier (LNA), and process the received RF signal to recover the data transmitted by the base station in the communication signal.

[0028] The wireless transceiver 120 may include one or more circuits for amplifying such communication signals. The amplifier circuitry (e.g., an LNA / PA) may include one or more amplifier stages, which may have one or more driver stages and one or more amplifier output stages. Each of these amplifier stages includes one or more transistors configured in various ways to amplify the communication signals. Various options exist for manufacturing transistors configured to amplify communication signals transmitted and received by the wireless transceiver 120.

[0029] The wireless transceiver 120 and RF front-end module 170 can be implemented using semiconductor-on-insulator (SOI) technology, which helps reduce high-order harmonics in the RF front-end module 170. SOI technology replaces conventional semiconductor substrates with layered semiconductor-insulator (e.g., buried oxide (BOX) layers) semiconductor substrates to reduce parasitic device capacitance and improve performance. For example, high-performance complementary metal-oxide-semiconductor (CMOS) radio frequency (RF) switching technology is currently manufactured using SOI substrates. For example, as... Figure 2 As shown, active devices, such as muffin-shaped RF switches, are manufactured using SOI technology.

[0030] Figure 2 A cross-sectional view of a radio frequency (RF) integrated circuit (RFIC) 200 is shown. (See diagram.) Figure 2 As shown, an RF SOI device includes an active device 210 on a buried oxide (BOX) layer 220 supported by an SOI substrate 202 (e.g., a silicon wafer). The RF SOI device can be fabricated as a complementary metal-oxide-semiconductor (CMOS) transistor using CMOS processes. The RF SOI device also includes an interconnect 250 coupled to the active device 210 within a first dielectric layer 206. In this configuration, the parasitic capacitance of the RF SOI device is proportional to the thickness of the BOX layer 220, which determines the distance between the active device 210 and the SOI substrate 202.

[0031] The active device 210 on the BOX layer 220 can be a CMOS transistor. For example, high-performance CMOS RF switching technology is currently manufactured using SOI substrates. RFFE 170 ( Figure 1Successful operation can rely on such high-performance CMOS RF technology. Therefore, the process of manufacturing the RFFE 170 involves SOI wafer integration to support such high-performance CMOS RF switching technology. Furthermore, support for future RF performance enhancements involves increasing device isolation while reducing RF losses. The RF integrated circuit 200 can be used to implement the RFFE 170. For example, according to various aspects of this disclosure, the active device 210 can be a switching field-effect transistor (FET) of the RF switch 172 of the RFFE 170, such as a muffin-shaped RF switching device.

[0032] Figure 3 This is a block diagram illustrating a top view of a conventional radio frequency (RF) switch structure having a linear finger-type transistor with multiple fingers. In this example, the RF switch structure 300 is formed by a linear source (S) region and drain (D) region with fingers forked between the gate (G) region to provide a finger-type transistor structure. Additionally, the RF switch structure 300 relies on the metal contacts (C) on both sides of the left and right sides of the gate (G) region to provide front-side metal contacts. The front-side metal contacts C of the conventional RF switch structure 300 fundamentally restrict the interconnection and current (i) paths of the RF switch structure 300.

[0033] In fact, reducing the switching area is a major factor in RF switch design. The industry's goal is to reduce the size of the RF chip package without compromising RF switch performance. Figure 3 As shown, the conventional RF switch structure 300 does not change from a linear finger-type transistor with multiple fingers. This structure is a one-dimensional gate G array. Conventional solutions for reducing the size of RF switch structures involve reducing the gate-to-gate pitch, thereby reducing the overall area. For example, as... Figure 4 As shown, the muffin-shaped RF switch provides a solution for reducing the size of the RF chip package without compromising RF switch performance.

[0034] Figure 4 This is a block diagram illustrating a top view of a muffin-shaped radio frequency (RF) switching field-effect transistor (FET) according to various aspects of this disclosure. Figure 4 As shown, the muffin-shaped RF switch 400 includes a 2D gate array 420 surrounding a source (S) region and a drain (D) region. In this configuration, the 2D gate array 420 includes a front side (shown) and a back side (not shown) opposite the front side. Based on this arrangement of the 2D gate array 420 surrounding the source (S) and drain (D) regions, current (i) flows from front to back or vice versa, depending on whether the source (S) or drain (D) region is contacted on the front or back side of the 2D gate array 420, as... Figures 5A to 5C As further shown in the text.

[0035] exist Figure 4 In the example, the waffle-shaped RF switch 400 includes a back-side source contact 430 coupled to a source (S) region on the back side of the 2D gate array 420. Additionally, the waffle-shaped RF switch 400 includes a front-side drain contact 410 coupled to a drain (D) region on the front side of the 2D gate array 420. Figure 4 As shown, each of the front drain contact 410 and the back source contact 430 is surrounded by a 2D gate array 420. In this example, the front drain contact 410 contacts the front metallization layer 440, and the back source contact 430 contacts the back metallization layer 450 (e.g., a mid-stage (MOL) metallization layer), as... Figures 5A to 5C Further examples are provided.

[0036] Figures 5A to 5C This illustrates various aspects of this disclosure. Figure 4 Block diagram of perspective and cross-sectional view of a muffin-shaped radio frequency (RF) switching field-effect transistor (FET).

[0037] Figure 5A Examples of various aspects according to this disclosure Figure 4 A perspective view of the front side 500 of a muffin-shaped RF switch 400. In this example, a 2D gate array 420 is shown surrounding the back-side source contact 430 and coupled to the back-side gate 422 and the back-side metallization layer 450. Additionally, Figure 5A The connection between the front metallization layer 440 and the front drain contact 410 is further illustrated. In this example, the front metallization layer 440 is composed of a mid-stage process (MOL) zero interconnect layer (which includes metal zero (M0) interconnects connected to the front drain contact 410), followed by a zero via (V0) to the back-end process (BEOL). The BEOL layer includes a first metal (M1) interconnect coupled to a first metal via (V1) and a second metal (M2) interconnect, followed by a second metal via (V2) connected to a third metal (M3) interconnect, which extends to an external bus line. In this example, the interconnects to the drain (D) region or the source (S) region are separated by the front metallization layer 440 or the back metallization layer 450.

[0038] Figure 5B Examples of various aspects according to this disclosure Figure 4A perspective view of the back side 550 of a muffin-shaped RF switch 400. In this example, a 2D gate array 420 is shown coupled to a back-side gate 422 and a back-side metallization layer 450. Furthermore, the connection between the back-side metallization layer 450 and the back-side source contact 430 is further illustrated. In this example, the back-side metallization layer 450 is composed of a mid-stage (MOL) metallization layer, which includes metal zero (MO) interconnects connected to the back-side gate 422 via zero via (VO) interconnects. The MO interconnects may extend to external bus lines, such as... Figure 5C Further examples are provided.

[0039] Figure 5C Examples of various aspects according to this disclosure Figure 4 A cross-sectional view 570 of a muffin-shaped RF switch 400 is shown. In this example, a 2D gate array 420 is further illustrated, including a connection between a back-side metallization layer 450 and a back-side source contact 430. Additionally, the connection between the back-side metallization layer 450 and the back-side source contact 430 is further illustrated. Figure 5C As shown, the muffin-shaped RF switch 400 is constructed using a novel structure that utilizes four or more contact corners (see...). Figure 4 This new structure maximizes the efficiency of the total channel width per unit area. Based on the structure of the muffin-shaped RF switch 400, a 2D gate array 420 surrounds a front drain contact 410 to the drain (D) region and a back source contact 430 to the source (S) region. Because the front drain contact 410 and the back source contact 430 are separate, the back contact and metallization process are involved in implementation. Figure 5C The structure of the muffin-shaped RF switch 400 is shown in cross-sectional view 570.

[0040] Figure 6A and Figure 6B These are schematic diagrams illustrating top views and enlarged top views of muffin-shaped radio frequency (RF) switching field-effect transistors (FETs) according to various aspects of this disclosure. Figure 6A As shown, the muffin-shaped radio frequency (RF) switching field-effect transistor (FET) 600 includes a protruding portion 602, which protrudes in... Figure 6B Further examples are provided below.

[0041] Figure 6B This illustrates various aspects of this disclosure. Figure 6A A schematic diagram of an enlarged view 650 of the muffin-shaped RF switch FET 600 shown. The portion of the muffin-shaped RF switch FET 600 in the enlarged view 650 resembles... Figure 4 The muffin-shaped RF switch 400 shown is described using similar reference numerals. Figure 6BAs shown, the muffin-shaped RF switch FET 600 includes a 2D gate array 420 surrounding a source (S) region and a drain (D) region. In this example, the muffin-shaped RF switch FET 600 includes a back-side source contact 430 coupled to the source (S) region at the back side of the 2D gate array 420.

[0042] Additionally, the waffle-shaped RF switch FET 600 includes a front-side drain contact 410 coupled to the drain (D) region at the front side of the 2D gate array 420. In this example, the front-side drain contact 410 contacts the front-side metallization layer 440, and the back-side source contact 430 contacts the back-side metallization layer 450, as shown below. Figures 5A to 5C Further examples are provided. Figure 6A and Figure 6B The proposed structure of the muffin-shaped RF switch FET 600 shown enhances the use of the front-side drain contact 410 and the back-side source contact 430, thereby resulting in a reduced area with the same total width. Additionally, proprietary processing techniques, such as... Figure 5C As shown, with the same total channel width Figure 3 Compared to the reference linear RF switch structure 300 shown, the area of ​​the muffin-shaped RF switch FET 600 is significantly reduced (e.g., by 28%). Area reduction can be further improved by optimizing the back-side process. Figure 7 A method for constructing a muffin-shaped RF switch according to various aspects of this disclosure is shown.

[0043] Figure 7 This is a flowchart illustrating various aspects of a method for constructing a radio frequency (RF) switch according to the present disclosure. Method 700 begins at block 702, wherein a two-dimensional (2D) gate array is formed surrounding a plurality of source / drain regions and a plurality of drain / source regions. For example, as... Figure 4 As shown, the muffin-shaped RF switch 400 includes a 2D gate array 420 surrounding a source (S) region and a drain (D) region. In this configuration, the 2D gate array 420 includes a front side (shown) and a back side (not shown) opposite the front side.

[0044] At frame 704, a back-side source / drain contact is formed to couple the plurality of source / drain regions on the back side of the 2D gate array. For example, as Figure 4As shown, the waffle-shaped RF switch 400 includes a back-side source contact 430 coupled to the source (S) region at the back side of the 2D gate array 420. Additionally, the waffle-shaped RF switch 400 includes a front-side drain contact 410 coupled to the drain (D) region at the front side of the 2D gate array 420.

[0045] At frame 706, a back-side metallization layer is formed to couple to the back-side source / drain contacts. Additionally, at frame 708, a front-side drain / source contact is formed to couple the plurality of drain / source regions to the front side of the 2D gate array opposite the back side. For example, as... Figure 4 As shown, the muffin-shaped RF switch FET 400 includes a front-side drain contact 410 coupled to the drain (D) region at the front side of the 2D gate array 420. In this example, the front-side drain contact 410 contacts the front-side metallization layer 440, and the back-side source contact 430 contacts the back-side metallization layer 450, as shown. Figures 5A to 5C Further examples are provided.

[0046] At frame 710, a front-side metallization layer is formed, which is coupled to the front-side drain / source contact. For example, Figure 5A The connection between the front metallization layer 440 and the front drain contact 410 is further illustrated. In this example, the front metallization layer 440 is composed of a mid-stage process (MOL) zero interconnect layer (which includes metal zero (M0) interconnects connected to the front drain contact 410), followed by a zero via (V0) to the back-end process (BEOL). The BEOL layer includes a first metal (M1) interconnect coupled to a first metal via (V1) and a second metal (M2) interconnect, followed by a second metal via (V2) connected to a third metal (M3) interconnect, which extends to an external bus line. In this example, the interconnects to the drain (D) region or the source (S) region are separated by the front metallization layer 440 or the back metallization layer 450.

[0047] Figure 8 This is a block diagram illustrating an exemplary wireless communication system 800 in which aspects of this disclosure may be advantageously employed. For illustrative purposes, Figure 8 Three remote units 820, 830, and 850 and two base stations 840 are shown. It should be understood that wireless communication systems may have more remote units and base stations. Remote units 820, 830, and 850 include IC devices 825A, 825C, and 825B, which include the disclosed muffin-shaped switching field-effect transistor (FET). It should be recognized that other devices may also include the disclosed muffin-shaped switching field-effect transistor (FET), such as base stations, switching devices, and network devices. Figure 8 The diagram shows a forward link signal 880 from base station 840 to remote units 820, 830 and 850, and a reverse link signal 890 from remote units 820, 830 and 850 to base station 840.

[0048] exist Figure 8 In the diagram, remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a fixed-location remote unit in a wireless local loop system. For example, a remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal digital assistant (PDA)), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed-location data unit (such as a meter reading device), or other communication devices that store or capture data or computer instructions, or combinations thereof. Figure 8 Remote units according to various aspects of this disclosure are illustrated, but this disclosure is not limited to such exemplary illustrated units. Various aspects of this disclosure can be suitably applied to a variety of devices, including the disclosed muffin-shaped switching field-effect transistor (FET).

[0049] Figure 9 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components, such as the muffin-shaped switching field-effect transistors (FETs) disclosed above. Design workstation 900 includes a hard disk 901 containing operating system software, support files, and design software (such as Cadence or OrCAD). Design workstation 900 also includes a display 902 to facilitate circuit design 910 or RFIC 912. Storage medium 904 is provided for tangibly storing circuit design 910 or RFIC 912. Circuit design 910 or RFIC 912 can be stored on storage medium 904 in file formats such as GDSII or GERBER. Storage medium 904 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Furthermore, design workstation 900 includes a drive device 903 for accepting input from storage medium 904 or writing output to storage medium 904.

[0050] Data recorded on storage medium 904 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial writing tools such as electron beam lithography. The data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 904 facilitates the design of circuit design 910 or RFIC 912 by reducing the number of processes used to design semiconductor wafers.

[0051] Specific implementation examples are described in the following numbered clauses: 1. A radio frequency (RF) switch, the radio frequency (RF) switch comprising: A two-dimensional (2D) gate array surrounding multiple source / drain regions and multiple drain / source regions; A back-side source / drain contact, wherein the back-side source / drain contact is coupled to the plurality of source / drain regions at the back side of the 2D gate array; A back-side metallization layer coupled to the back-side source / drain contacts; A front drain / source contact, the front drain / source contact being coupled to the plurality of drain / source regions at the front side of the 2D gate array opposite to the back side; and A front metallization layer coupled to the front drain / source contact.

[0052] 2. The RF switch according to Clause 1, wherein the front-side metallization layer comprises: A mid-process (MOL) metallization layer, said mid-process (MOL) metallization layer being coupled to the front drain / source contacts; and Back-end process (BEOL) metallization layer, which is coupled to the MOL metallization layer.

[0053] 3. The RF switch according to Clause 2, wherein the MOL metallization layer includes a plurality of zero vias (V0) coupled to the front drain / source contacts.

[0054] 4. The RF switch according to any one of Clauses 1 to 3, wherein the back-side metallization layer includes a mid-stage (MOL) metallization layer coupled to the back-side source / drain contacts.

[0055] 5. The RF switch according to any one of Clauses 1 to 4, wherein the RF switch further includes a back-side gate coupled to the 2D gate array.

[0056] 6. The RF switch according to any one of Clauses 1 to 5, the RF switch further comprising a back-side gate coupled to the back-side source / drain contact.

[0057] 7. The RF switch according to any one of Clauses 1 to 6, wherein the RF switch is integrated into the RF front-end module.

[0058] 8. The RF switch according to Clause 7, wherein the RF front-end module is incorporated into at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

[0059] 9. A method for constructing a radio frequency (RF) switch, the method comprising: A two-dimensional (2D) gate array is formed, the (2D) gate array surrounding multiple source / drain regions and multiple drain / source regions; A back-side source / drain contact is formed, which is coupled to the plurality of source / drain regions at the back side of the 2D gate array; A back-side metallization layer is formed, and the back-side metallization layer is coupled to the back-side source / drain contact; A front-side drain / source contact is formed, the front-side drain / source contact being coupled to the plurality of drain / source regions at the front side of the 2D gate array opposite to the back side; and A front metallization layer is formed, which is coupled to the front drain / source contact.

[0060] 10. The method according to Clause 9, wherein forming the front metallization layer comprises: A mid-process (MOL) metallization layer is formed, the (MOL) metallization layer being coupled to the front drain / source contacts; and A back-end process (BEOL) metallization layer is formed, and the (BEOL) metallization layer is coupled to the MOL metallization layer.

[0061] 11. The method according to Clause 10, wherein the MOL metallization layer includes a plurality of zero vias (V0) coupled to the front drain / source contacts.

[0062] 12. The method according to any one of Clauses 9 to 11, wherein forming the back-side metallization layer includes forming a mid-process (MOL) metallization layer coupled to the back-side source / drain contacts.

[0063] 13. The method according to any one of Clauses 9 to 12, the method further comprising forming a back-side gate coupled to the 2D gate array.

[0064] 14. The method according to any one of Clauses 9 to 13, the method further comprising forming a back-side gate coupled to the back-side source / drain contact.

[0065] 15. The method according to any one of Clauses 9 to 14, the method further comprising integrating the RF switch into an RF front-end module.

[0066] 16. The method of claim 15, further comprising incorporating the RF front-end module into at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

[0067] For firmware and / or software implementations, these methods can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described herein. Machine-readable media that tangibly embody instructions can be used to implement the methods described herein. For example, software code can be stored in memory and executed by a processor unit. Memory can be implemented within or outside the processor unit. As used herein, the term "memory" refers to any type of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a particular type of memory or a particular number of memories, or the type of medium for storing memories.

[0068] If implemented in firmware and / or software, functionality may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoding data structures and computer-readable media encoding computer programs. Computer-readable media include physical computer storage media. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disks and optical discs include compact optical discs (CDs), laser optical discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically copy data, while optical discs use lasers to optically copy data. Combinations of the above should also be included within the scope of computer-readable media.

[0069] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals included on a transmission medium in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicating instructions and data. These instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0070] Although this disclosure and its advantages have been described in detail, various changes, substitutions, and alterations may be made herein without departing from the technology of this disclosure as defined by the appended claims. For example, relational terms such as "above" and "below" are used for substrates or electronic devices. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if it is laterally oriented, above and below may refer to the sides of the substrate or electronic device. Furthermore, the scope of this patent application is not intended to be limited to the configuration of the procedures, machines, manufacturing processes, and compositions of matter, components, methods, and steps described herein. As will be readily understood by one of ordinary skill in the art from this disclosure, processes, machines, manufacturing processes, compositions of matter, components, methods, or steps that currently exist or will be developed later can be utilized to perform the same function or achieve the same result as the corresponding configuration described herein. Therefore, the appended claims are intended to include such processes, machines, manufacturing processes, compositions of matter, components, methods, or steps within their scope.

Claims

1. A radio frequency (RF) switch, the radio frequency (RF) switch comprising: A two-dimensional (2D) gate array surrounding multiple source / drain regions and multiple drain / source regions; A back-side source / drain contact, wherein the back-side source / drain contact is coupled to the plurality of source / drain regions at the back side of the 2D gate array; A back-side metallization layer coupled to the back-side source / drain contacts; A front drain / source contact is coupled to the plurality of drain / source regions at the front side of the 2D gate array opposite to the back side; as well as A front metallization layer coupled to the front drain / source contact.

2. The RF switch of claim 1, wherein the front metallization layer comprises: A mid-process (MOL) metallization layer coupled to the front drain / source contacts; as well as Back-end process (BEOL) metallization layer, which is coupled to the MOL metallization layer.

3. The RF switch of claim 2, wherein the MOL metallization layer includes a plurality of zero vias (VOs) coupled to the front drain / source contacts.

4. The RF switch of claim 1, wherein the back-side metallization layer includes a mid-stage (MOL) metallization layer, the MOL metallization layer being coupled to the back-side source / drain contacts.

5. The RF switch according to claim 1, wherein the RF switch further includes a back gate coupled to the 2D gate array.

6. The RF switch of claim 1, further comprising a back gate coupled to the back source / drain contact.

7. The RF switch according to claim 1, wherein the RF switch is integrated into the RF front-end module.

8. The RF switch of claim 7, wherein the RF front-end module incorporates at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

9. A method for constructing a radio frequency (RF) switch, the method comprising: A two-dimensional (2D) gate array is formed, the (2D) gate array surrounding multiple source / drain regions and multiple drain / source regions; A back-side source / drain contact is formed, which is coupled to the plurality of source / drain regions at the back side of the 2D gate array; A back-side metallization layer is formed, and the back-side metallization layer is coupled to the back-side source / drain contact; A front drain / source contact is formed, which is coupled to the plurality of drain / source regions at the front side of the 2D gate array opposite to the back side; as well as A front metallization layer is formed, which is coupled to the front drain / source contact.

10. The method of claim 9, wherein forming the front metallization layer comprises: A mid-stage (MOL) metallization layer is formed, the (MOL) metallization layer being coupled to the front drain / source contacts; as well as A back-end process (BEOL) metallization layer is formed, and the (BEOL) metallization layer is coupled to the MOL metallization layer.

11. The method of claim 10, wherein the MOL metallization layer includes a plurality of zero vias (V0) coupled to the front drain / source contact.

12. The method of claim 9, wherein forming the back-side metallization layer includes forming a mid-process (MOL) metallization layer, the (MOL) metallization layer being coupled to the back-side source / drain contacts.

13. The method of claim 9, the method further comprising forming a back-side gate coupled to the 2D gate array.

14. The method of claim 9, the method further comprising forming a back-side gate coupled to the back-side source / drain contact.

15. The method of claim 9, further comprising integrating the RF switch into an RF front-end module.

16. The method of claim 15, further comprising incorporating the RF front-end module into at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

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