Data scheduling method, controller, transmission system, equipment and storage medium

Abstract

The invention provides a data scheduling method, a controller, a transmission system, equipment and a storage medium, and relates to the technical field of communication. The method is applied to a data scheduling controller, and comprises the following steps: acquiring first temporary storage time of first to-be-scheduled data in a data cache unit; determining whether the first to-be-scheduled data is overtime scheduling data according to the first temporary storage time; and when it is determined that the first to-be-scheduled data is the overtime scheduling data, scheduling the overtime scheduling data to a data receiving unit. The data scheduling process is completed by the data scheduling controller, and the processor does not need to execute a software scheduling algorithm, so that the problem that software scheduling consumes computing resources of the processor is solved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, and in particular, to a data scheduling method, a controller, a transmission system, a device, and a storage medium. BACKGROUND

[0002] There is a buffer unit between a data sending unit and a data receiving unit in a terminal, the buffer unit is used to temporarily store data transmitted by the data sending unit to the data receiving unit, and the data sent by the data sending unit is scheduled to the data receiving unit through the buffer unit.

[0003] In related technologies of data scheduling, a software scheduling algorithm is used to control data scheduling of the buffer unit, but the software scheduling algorithm needs to be executed by a processor in the terminal, which causes the software scheduling algorithm to consume computing resources of the processor. SUMMARY

[0004] The present disclosure provides a data scheduling method, a controller, a transmission system, a device, and a storage medium to solve the problems in related technologies.

[0005] A second aspect of the present disclosure provides a data scheduling method, which comprises: obtaining a first temporary storage time of first to-be-scheduled data in a data buffer unit; determining whether the first to-be-scheduled data is timeout scheduling data according to the first temporary storage time; scheduling the timeout scheduling data to a data receiving unit in a case where it is determined that the first to-be-scheduled data is the timeout scheduling data.

[0006] In some embodiments of the present disclosure, the determination of whether the first to-be-scheduled data is timeout scheduling data according to the first temporary storage time comprises: obtaining a second temporary storage time of second to-be-scheduled data in a data buffer module; the data buffer unit comprises at least two data buffer modules; determining whether the second to-be-scheduled data is timeout scheduling data according to the second temporary storage time; the first to-be-scheduled data comprises at least two second to-be-scheduled data, and the first temporary storage time comprises at least two second temporary storage times.

[0007] In some embodiments of the present disclosure, the obtaining of the second temporary storage time of the second to-be-scheduled data in the data buffer module comprises: obtaining a first time at which the data buffer module receives the second to-be-scheduled data, and obtaining a temporary storage time threshold of the data buffer module; calculating the second temporary storage time according to the first time and the temporary storage time threshold.

[0008] In some embodiments of the present disclosure, the determining whether the second to-be-scheduled data is the timeout-scheduled data according to the second temporary storage time comprises: obtaining a second time at which the second to-be-scheduled data is temporarily stored in the data cache module; the second time is greater than the first time; determining whether the second to-be-scheduled data is the timeout-scheduled data according to the second time and the second temporary storage time.

[0009] In some embodiments of the present disclosure, the scheduling the timeout-scheduled data to the data receiving unit comprises: obtaining an initial scheduling priority of a data cache module in which the timeout-scheduled data is located; updating the initial scheduling priority to a highest scheduling priority, so as to schedule the timeout-scheduled data to the data receiving unit based on the highest scheduling priority.

[0010] In some embodiments of the present disclosure, the method further comprises: determining whether the timeout-scheduled data exists in the data cache module; when it is determined that the timeout-scheduled data does not exist in the data cache module, obtaining a current scheduling priority of the data cache module, and determining whether the current scheduling priority of the data cache module is the initial scheduling priority; when it is determined that the current scheduling priority of the data cache module is not the initial scheduling priority, updating the current scheduling priority to the initial scheduling priority.

[0011] In some embodiments of the present disclosure, the scheduling the timeout-scheduled data to the data receiving unit based on the highest scheduling priority comprises: calling the data cache module of the highest scheduling priority, and scheduling the timeout-scheduled data in the data cache module of the highest scheduling priority to the data receiving unit.

[0012] In some embodiments of the present disclosure, the method further comprises: obtaining current scheduling priorities of at least two data cache modules; calling the at least two data cache modules respectively according to descending order of the current scheduling priorities of the at least two data cache modules, and scheduling second to-be-scheduled data in the at least two data cache modules to the data receiving unit.

[0013] A second aspect embodiment of the present disclosure provides a data scheduling controller, comprising: a detection unit and a scheduling unit, wherein, The detection unit is configured to acquire a first temporary storage time of first to-be-scheduled data in the data buffer unit, and determine whether the first to-be-scheduled data is timeout scheduling data according to the first temporary storage time; the first to-be-scheduled data is data sent by the data sending unit to the data buffer unit. The scheduling unit is configured to, in a case where it is determined that the first to-be-scheduled data is the timeout scheduling data, call the data buffer unit to schedule the timeout scheduling data to the data receiving unit.

[0014] In some embodiments of the present disclosure, the detection unit comprises at least two detection modules. The at least two detection modules are respectively connected with corresponding data buffer modules in the data buffer unit; the data buffer unit comprises at least two data buffer modules, and each data buffer module has a corresponding detection module. The detection module is configured to acquire a second temporary storage time of second to-be-scheduled data in the data buffer module, and determine whether the second to-be-scheduled data is timeout scheduling data according to the second temporary storage time; the first to-be-scheduled data comprises at least two second to-be-scheduled data, and the first temporary storage time comprises at least two second temporary storage times.

[0015] In some embodiments of the present disclosure, the detection module is configured to: acquire a first time at which the data buffer module receives the second to-be-scheduled data, and acquire a temporary storage time threshold of the data buffer module; calculate the second temporary storage time according to the first time and the temporary storage time threshold.

[0016] In some embodiments of the present disclosure, the detection module is configured to: acquire a second time at which the second to-be-scheduled data is temporarily stored in the data buffer module; the second time is greater than the first time; determine whether the second to-be-scheduled data is timeout scheduling data according to the second time and the second temporary storage time.

[0017] In some embodiments of the present disclosure, the detection module is configured to: acquire an initial scheduling priority of a data buffer module in which the timeout scheduling data is located; update the initial scheduling priority to a highest scheduling priority, so as to schedule the timeout scheduling data to the data receiving unit based on the highest scheduling priority.

[0018] In some embodiments of the present disclosure, the detection module is configured to: determine whether the timeout scheduling data exists in the data buffer module. When it is determined that there is no timeout scheduling data in the data caching module, the current scheduling priority of the data caching module is obtained, and it is determined whether the current scheduling priority of the data caching module is the initial scheduling priority. When it is determined that the current scheduling priority of the data caching module is not the initial scheduling priority, the current scheduling priority is updated to the initial scheduling priority.

[0019] In some embodiments of this disclosure, the scheduling unit is configured as follows: The highest priority data caching module is invoked to schedule the timeout scheduling data in the highest priority data caching module to the data receiving unit.

[0020] In some embodiments of this disclosure, the scheduling unit is configured as follows: Obtain the current scheduling priority of at least two data caching modules; According to the descending order of the current scheduling priorities of the at least two data cache modules, the at least two data cache modules are called respectively, and the second data to be scheduled in the at least two data cache modules is scheduled to the data receiving unit.

[0021] A third aspect of this disclosure provides a data transmission system comprising: Data transmission unit; Data receiving unit; A data buffer unit is connected to the data sending unit and the data receiving unit; The system described in any of the first aspects of the present disclosure is connected to the data cache unit.

[0022] A fourth aspect of this disclosure provides a data scheduling apparatus, which is applied to the method described in any one of the first aspects, comprising: The acquisition unit is used to acquire the first temporary storage time of the first data to be scheduled in the data cache unit; A determining unit is configured to determine whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time. The scheduling unit is used to schedule the timed-out scheduling data to the data receiving unit when it is determined that the first data to be scheduled is the timed-out scheduling data.

[0023] In some embodiments of this disclosure, the determining unit includes: The first acquisition module is used to acquire the second temporary storage time of the second data to be scheduled in the data cache module; the data cache unit includes at least two data cache modules. The determining module is used to determine whether the second data to be scheduled is timed out based on the second temporary storage time; the first data to be scheduled includes at least two second data to be scheduled, and the first temporary storage time includes at least two second temporary storage times.

[0024] In some embodiments of this disclosure, the first acquisition module is further configured to: The first time when the data caching module receives the second data to be scheduled is obtained, and the temporary storage time threshold of the data caching module is obtained; The second temporary storage time is calculated based on the first time and the temporary storage time threshold.

[0025] In some embodiments of this disclosure, the determining module is further configured to: The second time at which the second data to be scheduled is temporarily stored in the data cache module is obtained; the second time is greater than the first time. Based on the second time and the second temporary storage time, determine whether the second data to be scheduled is timed-out scheduling data.

[0026] In some embodiments of this disclosure, the scheduling unit includes: The second acquisition module is used to acquire the initial scheduling priority of the data cache module where the timeout scheduling data is located; The update module is used to update the initial scheduling priority to the highest scheduling priority. The scheduling module is used to schedule the timed-out scheduling data to the data receiving unit based on the highest scheduling priority.

[0027] In some embodiments of this disclosure, the apparatus further includes: The determining unit is further configured to determine whether the timeout scheduling data exists in the data caching module; The acquisition unit is further configured to, when it is determined that there is no timeout scheduling data in the data cache module, acquire the current scheduling priority of the data cache module, and determine whether the current scheduling priority of the data cache module is the initial scheduling priority; The update unit is used to update the current scheduling priority to the initial scheduling priority when it is determined that the current scheduling priority of the data cache module is not the initial scheduling priority.

[0028] In some embodiments of this disclosure, the scheduling module is further configured to: The highest priority data caching module is invoked to schedule the timeout scheduling data in the highest priority data caching module to the data receiving unit.

[0029] In some embodiments of this disclosure, the apparatus further includes: The acquisition unit is also used to acquire the current scheduling priority of at least two data caching modules; The scheduling unit is further configured to call the at least two data cache modules respectively in descending order of their current scheduling priorities, and schedule the second data to be scheduled in the at least two data cache modules to the data receiving unit.

[0030] A fifth aspect of this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the second aspect of this disclosure.

[0031] A sixth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the second aspect of this disclosure.

[0032] A seventh aspect of this disclosure provides a chip including one or more interfaces and one or more processors; the interfaces are configured to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processors, cause the electronic device to perform the methods described in the second aspect of this disclosure.

[0033] In summary, the data scheduling method proposed in this disclosure is applied to a data scheduling controller. The method includes obtaining a first temporary storage time for a first data to be scheduled in a data cache unit; determining whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; and scheduling the timed-out scheduling data to a data receiving unit if it is determined that the first data to be scheduled is timed-out scheduling data. The data scheduling process is completed by the data scheduling controller, eliminating the need for the processor to execute a software scheduling algorithm, thereby solving the problem of software scheduling consuming processor computing resources.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0036] Figure 1A flowchart of a data scheduling method provided in an embodiment of this disclosure; Figure 2 A diagram illustrating the deployment location of a data scheduling controller provided in an embodiment of this disclosure; Figure 3 A block diagram of another data scheduling controller provided in an embodiment of this disclosure; Figure 4 A schematic diagram of the scheduling process of a data scheduling controller provided in an embodiment of this disclosure; Figure 5 A comparative diagram illustrating a data scheduling process provided in an embodiment of this disclosure; Figure 6 A block diagram of a data scheduling controller provided in an embodiment of this disclosure; Figure 7 A block diagram of a data transmission system provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure of a data scheduling device provided in an embodiment of the present disclosure; Figure 9 A schematic diagram of another data scheduling device provided in this disclosure embodiment; Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure; Figure 11 This is a schematic diagram of the structure of a chip provided in an embodiment of the present disclosure; Figure 12 This is a schematic diagram of another chip structure provided in an embodiment of this disclosure. Detailed Implementation

[0037] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0038] There is a buffer unit between the data sending unit and the data receiving unit in the terminal. The buffer unit is used to temporarily store the data transmitted by the data sending unit to the data receiving unit, and to schedule the data sent by the data sending unit to the data receiving unit through the buffer unit.

[0039] In data scheduling technologies, data scheduling of cache units is controlled by software scheduling algorithms. However, software scheduling algorithms require the processor in the terminal to execute, which causes the software scheduling algorithms to consume the processor's computing resources.

[0040] Therefore, to address the problems existing in related technologies, this disclosure proposes a data scheduling controller. The method, applied to the data scheduling controller, includes obtaining a first temporary storage time for a first data to be scheduled in a data cache unit; determining whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; and scheduling the timed-out scheduling data to a data receiving unit if it is determined that the first data to be scheduled is timed-out scheduling data. The data scheduling process is completed by the data scheduling controller, eliminating the need for the processor to execute software scheduling algorithms, thereby solving the problem of software scheduling consuming processor computing resources.

[0041] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments. In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships. The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. In this disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular or a plural expression. In some embodiments, the terms “in response to…”, “in response to determining…”, “in the case of…”, “when…”, “if…”, “if…”, etc., can be used interchangeably. In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”. The prefixes such as "first" and "second" in the embodiments of this disclosure are only for distinguishing different descriptive objects and do not constitute restrictions on the position, order, priority, number or content of the descriptive objects. For the description of the descriptive objects, please refer to the description in the claims or the context of the embodiments. The use of prefixes should not constitute unnecessary restrictions.

[0042] In the embodiments disclosed herein, "multiple" refers to two or more. In the embodiments disclosed herein, terms such as “import”, “input”, and “read in” can be used interchangeably.

[0043] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0044] In some embodiments, the terms "terminal", "terminal device", "user equipment (UE)", "user terminal", "mobile station (MS)", "mobile terminal (MT)", "subscriber station", "mobile unit", "subscriber unit", "wireless unit", "remote unit", "mobile device", "wireless device", "wireless communication device", "remote device", "mobile subscriber station", "access terminal", "mobile terminal", "wireless terminal", "remote terminal", "handset", "useragent", "mobile client", and "client" can be used interchangeably. Figure 1 This is a flowchart illustrating a data scheduling method provided in an embodiment of this disclosure. This method can be applied to application scenarios such as smart terminals, and can be executed by a data scheduling controller integrated with data scheduling functions, or by other devices suitable for performing data scheduling and outputting data scheduling results. This disclosure does not limit its application. Figure 1 As shown, the data display method includes steps S101-S103.

[0045] Step S101: Obtain the first temporary storage time of the first data to be scheduled in the data cache unit.

[0046] In the embodiments of this disclosure, the data caching unit refers to a hardware storage module (such as a cache, buffer, etc.) in the terminal used for temporary data storage. One end of the module is connected to the data sending unit (such as a sensor, external device interface, etc.), and the other end is connected to the data receiving unit (such as a processor, display module, etc.), used to balance the difference in data sending and receiving rates. The first data to be scheduled refers to all data that has been transmitted by the data sending unit to the data caching unit but has not yet been scheduled to the data receiving unit. For example, real-time environmental data collected by sensors, file fragments transmitted by external devices, etc., may all be temporarily stored in the data caching unit as the first data to be scheduled. The first storage time refers to the length of time the first data to be scheduled stays in the data caching unit, starting from the time the first data to be scheduled enters the data caching unit. The first data to be scheduled can be data sent by the data sending unit to the data caching unit. Step S102: Determine whether the first data to be scheduled is timed out based on the first temporary storage time.

[0047] In embodiments of this disclosure, timeout scheduling data refers to data that has been stored in the data cache unit for a period exceeding a predetermined time threshold.

[0048] In the embodiments of this disclosure, when the data sending unit transmits the first data to be scheduled to the data buffer unit, the detection unit in the data scheduling controller synchronously records the initial time when the data enters the buffer unit (e.g., by generating a timestamp through a hardware clock module). Subsequently, the detection unit calculates the difference between the current time and the initial time in real time using a built-in timer, which is the first temporary storage time of the first data to be scheduled. For example, if data A enters the buffer unit at time t0, the detection unit calculates t1-t0 at time t1 (t1>t0) to obtain the first temporary storage time of data A as Δt=t1-t0. The detection unit has a preset temporary storage time threshold T (this threshold can be dynamically configured according to the data type, such as 50ms for real-time control data and 10s for ordinary file data). The detection unit compares the first temporary storage time Δt with the threshold T: if Δt>T, the first data to be scheduled is determined to be timed-out scheduling data; if Δt≤T, the first data to be scheduled is determined to be normal temporary storage data and does not require immediate scheduling. The detection unit employs a dual-mode triggering approach: real-time monitoring and periodic inspection. Real-time monitoring: When new data enters the cache unit, the detection unit immediately starts timing the temporary storage time of that data. Periodic inspection: Every preset interval (e.g., 1ms), the detection unit performs batch checks on the temporary storage time of all first-time-to-be-scheduled data in the cache unit to ensure no timeout data is missed. However, it should be clarified that this statement does not imply that the determination of timeout-scheduled data can only be achieved through the above method; other methods can also be used.

[0049] The detection unit independently completes the temporary storage time calculation and timeout judgment through hardware circuitry, without requiring the processor to execute software scheduling algorithms. This solves the problem of traditional software scheduling consuming processor computing resources and improves the overall operating efficiency of the terminal.

[0050] Step S103: If it is determined that the first data to be scheduled is the timed-out scheduling data, the timed-out scheduling data is scheduled to the data receiving unit.

[0051] In the embodiments of this disclosure, during system operation, the scheduling unit in the data scheduling controller is in a standby state, maintaining close communication with the detection unit. When the detection unit determines that the first data to be scheduled is timed-out scheduling data, it immediately sends a signal containing information related to the timed-out data (such as the storage location of the data in the cache unit, data identifier, etc.) to the scheduling unit. Upon receiving the signal, the scheduling unit first parses the signal content to determine the specific location of the timed-out scheduling data. Then, through a predefined interface and communication protocol, it sends a call request to the data cache unit. This request acts like a precise location command, directly targeting the area in the data cache unit where the timed-out scheduling data is stored. After receiving the call request, the data cache unit performs a series of verification and preparation tasks to ensure that the data to be scheduled is accurate. After successful verification, the data cache unit encapsulates the timed-out scheduling data according to a certain data transmission format, awaiting further instructions from the scheduling unit. After confirming that the data cache unit has prepared the data, the scheduling unit initiates the data transmission process. The scheduling unit will select an appropriate time and method to retrieve the encapsulated timeout scheduling data from the data buffer unit based on the current status of the data receiving unit and the availability of the data transmission channel, and send it to the data receiving unit through the data bus or other data transmission channels.

[0052] By sending timeout scheduling data to the data receiving unit in a timely manner through the scheduling unit, the problem of delayed processing caused by data staying in the buffer unit for a long time is avoided.

[0053] In summary, in the embodiments of this disclosure, the data scheduling method proposed herein is applied to a data scheduling controller. The method includes obtaining a first temporary storage time for a first data to be scheduled in a data cache unit; determining whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; and scheduling the timed-out scheduling data to a data receiving unit if it is determined that the first data to be scheduled is timed-out scheduling data. The data scheduling process is completed by the data scheduling controller, eliminating the need for the processor to execute a software scheduling algorithm, thereby solving the problem of software scheduling consuming processor computing resources.

[0054] As a refinement of step S102, when performing the step of determining whether the first data to be scheduled is timed out based on the first temporary storage time, the following methods can be used, but are not limited to: obtaining the second temporary storage time of the second data to be scheduled in the data cache module; the data cache unit includes at least two data cache modules; determining whether the second data to be scheduled is timed out based on the second temporary storage time; the first data to be scheduled includes at least two second data to be scheduled, and the first temporary storage time includes at least two second temporary storage times.

[0055] In the embodiments of this disclosure, the detection module refers to a sub-module of the detection unit, which is a hardware logic circuit (such as a dedicated timer circuit, comparator component, etc.). It corresponds one-to-one with a single data cache module in the data cache unit and is responsible for independently monitoring the temporary storage status of data within that data cache module, without relying on software scheduling by the terminal processor. The data cache module refers to a partitioned sub-module of the data cache unit (such as an independent cache partition divided by data type, priority, or source). Each module has independent storage space and read / write interfaces, such as a "sensor data cache module," a "file transfer cache module," and a "control instruction cache module," which temporarily store different types of data to be scheduled. The second data to be scheduled refers to data temporarily stored in a single data cache module that has not yet been scheduled to the data receiving unit; it is a subset of the "first data to be scheduled." For example, the temperature and humidity data temporarily stored in the "sensor data cache module" are the second data to be scheduled for that module. The second storage time refers to the duration of the second data to be scheduled within a single cache module and is a component of the "first storage time."

[0056] In the embodiments of this disclosure, the detection module first obtains the second temporary storage time of all second data to be scheduled in the data cache module. The second temporary storage time is calculated using the system clock and represents the duration for which the second data to be scheduled is stored in the cache unit. The detection module compares the second temporary storage time of each second data to be scheduled with a preset temporary storage time threshold. If the second temporary storage time of a certain data exceeds the threshold, the data is determined to be timed out. Once the second temporary storage time of a second data to be scheduled is detected to exceed the predetermined time threshold, the detection module marks the data as timed out and processes it first. This processing can be triggered by the scheduling unit. The first data to be scheduled contains at least two second data to be scheduled, so when scheduling, the detection module also needs to consider the temporary storage time of multiple second data to be scheduled. Based on the timeout judgment result of each second temporary storage time, the scheduling priority of the entire first data to be scheduled is determined. For data determined to have timed out, the detection module sends a signal to prompt the scheduling unit to schedule these timed out data first. In this way, the system can ensure that timed out data can be effectively processed when processing a large amount of data, avoiding affecting the overall scheduling efficiency. However, it should be clarified that this statement is not intended to limit the determination of timeout scheduling data to the methods described above; it can also be achieved through other methods.

[0057] Each detection module independently monitors its corresponding data cache module. Multiple detection modules can process the temporary storage time detection of different cache modules in parallel, avoiding the performance bottleneck of a single detection unit and improving the overall detection efficiency.

[0058] As a refinement of the above embodiments, when executing the second temporary storage time of the second data to be scheduled in the data cache module, it can be implemented in the following ways, but not limited to: obtaining the first time when the data cache module receives the second data to be scheduled, and obtaining the temporary storage time threshold of the data cache module; calculating the second temporary storage time based on the first time and the temporary storage time threshold.

[0059] In the embodiments of this disclosure, the first time refers to the moment when the data caching module successfully receives and stores the second data to be scheduled, as recorded by a timestamp generated by the terminal's hardware clock module (such as a real-time clock, system clock counter, etc.). The temporary storage time threshold refers to the maximum duration for which the second data to be scheduled is allowed to be temporarily stored, preset by the data caching module. This threshold is pre-configured according to the data type or business requirements and stored in the configuration register of the data caching module.

[0060] In the embodiments of this disclosure, when the data sending unit transmits second data to be scheduled to a data buffer module, the data buffer module sends a "data storage complete signal" to the corresponding detection module after completing the data writing. Upon receiving this signal, the detection module records the timestamp (denoted as T_start) as the first time using a time counter synchronized with the system clock. For example, if the system clock frequency is 100MHz and the timestamp is in clock cycles, assuming the counter value is 10000 when data storage is complete, then T_start = 10000 clock cycles (i.e., 100μs). The detection module obtains the current temporary storage time threshold (denoted as T_threshold) of the data buffer module in the following ways: Method 1: Reading a preset register value. During system initialization, the threshold is written to a dedicated register (e.g., T_threshold = 20ms, corresponding to 2000000 clock cycles) according to the type of the data buffer module (e.g., audio buffer module), and the detection module directly reads this register value. Method 2: Receiving a dynamic configuration command. When system requirements change (e.g., increased real-time requirements), the main controller sends a new threshold instruction to the detection module (e.g., adjusting T_threshold to 10ms). The detection module then updates the locally stored threshold parameters. The detection module uses a hardware adder to sum the first time and the temporary storage time threshold to obtain the second temporary storage time (denoted as T_deadline). The calculation formula is: T_deadline = T_start + T_threshold. For example, if T_start = 10,000 clock cycles and T_threshold = 2,000,000 clock cycles, then T_deadline = 2,010,000 clock cycles (i.e., 20.1ms), indicating that the second data to be scheduled must be scheduled before 20.1ms; otherwise, it is considered a timeout.

[0061] By implementing the calculation of the first time and threshold through hardware logic, the instruction delay of software calculation is avoided, and the time accuracy can be improved to the microsecond or even nanosecond level, meeting the scheduling requirements of high real-time data.

[0062] As a refinement of the above embodiments, when performing the step of determining whether the second data to be scheduled is timed out based on the second temporary storage time, the following methods can be used, but are not limited to: obtaining the second time when the second data to be scheduled is temporarily stored in the data cache module; the second time is greater than the first time; and determining whether the second data to be scheduled is timed out based on the second time and the second temporary storage time.

[0063] Among the embodiments of the present disclosure, the first time (T1) refers to the initial timestamp when the data cache module receives and stores the second data to be scheduled (for example: the nanosecond-level time recorded by the hardware timer). The second time (T2) refers to the current system time when the timeout detection is performed (T2 > T1, representing the duration for which the data has been temporarily stored). The second temporary storage time (T_timeout) refers to the maximum time threshold for which the data is allowed to stay in the cache (i.e., T1 + the fixed temporary storage time threshold ΔT). The timeout-scheduled data is the data that has stayed in the cache for more than T_timeout and needs to be scheduled preferentially.

[0064] Among the embodiments of the present disclosure, the detection module has a built-in hardware timer (such as a high-precision clock circuit), which automatically captures the current moment as T2 when the timeout detection logic is triggered. Example scenario: Detect once every 10 μs periodically, or trigger the detection when new data is written into the cache. The hardware comparator circuit in the detection module directly compares T2 with the pre-computed T_timeout (T1 + ΔT). If T2 ≥ T_timeout, it is determined that the second data to be scheduled is timeout-scheduled data. If T2 < T_timeout, it is determined that the second data to be scheduled is not timeout-scheduled data. The temporary storage time threshold ΔT can be dynamically adjusted through the configuration register to adapt to different service scenarios (for example, set ΔT = 5 ms for real-time video streams and ΔT = 50 ms for ordinary file transfers). When it is determined that the second data to be scheduled is timeout-scheduled data, the detection module sends unit sends a hardware interrupt signal to the scheduling unit and marks the timeout status bit of the cache module where the data is located.

[0065] By obtaining the second time and calculating the second temporary storage time, the temporary storage situation of each data in the cache module can be monitored dynamically and in real time, enabling the system to more flexibly and accurately determine whether the data has timed out, avoiding the errors that may be caused by relying solely on fixed time nodes for judgment, and improving the accuracy of data scheduling decisions.

[0066] As a refinement of the above embodiments, when performing the scheduling of the timeout-scheduled data to the data receiving unit, it can be implemented by, but not limited to, the following methods, including: obtaining the initial scheduling priority of the data cache module where the timeout-scheduled data is located; updating the initial scheduling priority to the highest scheduling priority, so as to schedule the timeout-scheduled data to the data receiving unit based on the highest scheduling priority.

[0067] In the embodiments of this disclosure, the initial scheduling priority refers to the priority preset in the data scheduling controller for each data caching module, used to determine the scheduling order of data in each caching module when scheduling data. The initial scheduling priority can be set according to various factors such as data type, data importance, and data urgency. The highest scheduling priority refers to the highest preset scheduling priority in the system, which is higher than the initial scheduling priority of all data caching modules. For example, if the system sets the highest scheduling priority to 5, the initial scheduling priority of all data caching modules is less than 5. When the priority of a data caching module is updated to the highest scheduling priority, the data in that module will be scheduled to the data receiving unit with priority over data from other modules.

[0068] In the embodiments of this disclosure, during system initialization, an initial scheduling priority is configured for each data caching module according to the characteristics of the data service, and this priority is stored in the hardware register (such as a priority configuration register) of the corresponding detection module. For example, the initial scheduling priority 4 is stored in the register of the detection module corresponding to the "real-time video caching module"; the initial scheduling priority 3 is stored in the register of the detection module corresponding to the "sensor data caching module"; and the initial scheduling priority 2 is stored in the register of the detection module corresponding to the "log data caching module". Simultaneously, the system presets a maximum scheduling priority of 6 at the hardware level, which is stored in the global configuration register of the detection module. When the detection module compares the second time with the second temporary storage time, it accesses its own priority configuration register through a hardware interface (such as an internal bus) to read the initial scheduling priority of the data caching module. For example, if timeout data appears in the "sensor data caching module", the detection module reads its initial scheduling priority 3 from the register. The detection module compares the initial scheduling priority it reads with the highest scheduling priority (6) in the global configuration register. If the initial scheduling priority is lower than the highest scheduling priority, the module updates the current scheduling priority of the data cache module to the highest scheduling priority (6) through hardware logic and stores the updated priority in the detection module's temporary priority register. Simultaneously, the detection module generates a "priority update signal," which includes the identifier of the data cache module containing the timed-out scheduling data and the updated highest scheduling priority. The detection module sends the "priority update signal" to the scheduling unit via a hardware link. Upon receiving the signal, the scheduling unit records the highest scheduling priority status of the corresponding data cache module, providing a basis for subsequent data scheduling.

[0069] By updating the priority of the module containing the timeout scheduling data to the highest scheduling priority, it can be ensured that the timeout data is processed first in the scheduling queue, avoiding the continuous retention of timeout data due to low priority. This solves the problem of "important timeout data being blocked by low-priority data" that may occur in traditional fixed-priority scheduling.

[0070] In practical applications, it is necessary to adjust the scheduling priority of the data caching module. This can be achieved in ways that are not limited to the following: determining whether the timeout scheduling data exists in the data caching module; when it is determined that the timeout scheduling data does not exist in the data caching module, obtaining the current scheduling priority of the data caching module and determining whether the current scheduling priority of the data caching module is the initial scheduling priority; when it is determined that the current scheduling priority of the data caching module is not the initial scheduling priority, updating the current scheduling priority to the initial scheduling priority.

[0071] In the embodiments of this disclosure, the current scheduling priority refers to the actual scheduling priority of the data caching module at the current moment, which may be the initial scheduling priority (when there is no timeout data) or the highest scheduling priority (when timeout data exists and it is temporarily boosted). For example, if a module's initial priority is 2, and it is boosted to the highest priority of 5 due to timeout data, then the "current scheduling priority" is 5.

[0072] In the embodiments of this disclosure, the detection module reads the initial value from the "initial priority configuration register" (which stores the initial scheduling priority preset by the module) and compares it with the current value in the temporary register using hardware logic. If the two values ​​are equal (e.g., both are 2), the current scheduling priority is determined to be in the initial state, and no operation is performed. If the two values ​​are not equal (e.g., the current value is 5, and the initial value is 2), the current scheduling priority is determined to be in a temporary boost state, and a recovery operation needs to be performed. When the current scheduling priority is detected to be inconsistent with the initial scheduling priority, the detection module rewrites the current value in the temporary priority register to the value in the initial priority configuration register (e.g., updating 5 to 2) through hardware logic, completing the priority reset. At the same time, the detection module sends a "priority recovery signal" to the scheduling unit, notifying it that the module's priority has been restored to the initial state.

[0073] By automatically restoring the priority to the initial value after the timeout scheduling data processing is completed, the data caching module can be prevented from occupying high priority for a long time due to the occurrence of timeout data, thus avoiding the continuous blocking of normal data of other modules (such as the "file transfer data caching module" restoring the initial priority after timeout data processing to prevent long-term preemption of the scheduling resources of "real-time communication data").

[0074] As a refinement of the above embodiments, when executing the step of scheduling the timed-out scheduling data to the data receiving unit based on the highest scheduling priority, it can be implemented in the following ways, but is not limited to: calling the data cache module of the highest scheduling priority and scheduling the timed-out scheduling data in the data cache module of the highest scheduling priority to the data receiving unit.

[0075] In the embodiments of this disclosure, the scheduling unit receives "current scheduling priority" information sent by each detection module in real time through a hardware interface (such as a priority signal bus). This information is periodically updated and synchronized to the scheduling unit by the detection modules. The priority arbitrator inside the scheduling unit compares the current priorities of all data cache modules and selects the module with the highest priority value (i.e., the "data cache module with the highest scheduling priority"). For example, if there are three modules in the system with current priorities of 5 (highest), 3, and 2, the arbitrator will lock the module with priority 5 as the target. The scheduling unit sends a "scheduling start signal" (a hardware pulse signal) to the identified highest priority data cache module. This signal includes a module identifier (such as module number "001") and a data transmission instruction (such as "output timeout data"). After receiving the signal, the data cache module activates its data output port through internal hardware logic, preparing to transmit timeout scheduling data. The scheduling unit controls the hardware path (such as a high-speed data bus) between the data cache module and the data receiving unit to switch to the active state. The specific process is as follows: the data cache module reads the timeout scheduling data from the storage address (quickly located through the "timeout data address table" pre-marked by the detection module); it sends the data to the data receiving unit (such as the processor's receiving interface) through the hardware path at a preset maximum transmission rate (such as 1Gbps); during transmission, the scheduling unit monitors the transmission integrity in real time through a "data verification signal" (such as verifying the data frame header / tail) to ensure no data loss. After all the timeout data has been transmitted to the data receiving unit, the data receiving unit returns a "reception completion signal" to the scheduling unit. After receiving the signal, the scheduling unit performs the following operations: it sends a "clear signal" to the corresponding data cache module, causing it to delete the transmitted timeout data and release the storage space; it notifies the detection module to update the "timeout flag register" of the module (set from "1" to "0"), triggering the subsequent priority recovery process (as described in the previous embodiment).

[0076] By calling the highest priority module, timeout scheduling data is ensured to be transmitted first among all data to be scheduled, avoiding delays caused by insufficient priority (e.g., timeout frames of real-time monitoring video can be transmitted before ordinary file data, reducing screen stuttering).

[0077] In practical applications, the scheduling of the second data to be scheduled in the data caching module can be implemented in, but is not limited to, the following ways: obtaining the current scheduling priority of at least two data caching modules; calling the at least two data caching modules respectively in descending order of the current scheduling priority of the at least two data caching modules, and scheduling the second data to be scheduled in the at least two data caching modules to the data receiving unit.

[0078] In the embodiments of this disclosure, descending order refers to arranging the current scheduling priorities of multiple data cache modules in descending order (e.g., priority 5→3→2). The scheduling unit schedules the data in the modules in this order to ensure that the data of high-priority modules is transmitted before the data of low-priority modules.

[0079] In the embodiments of this disclosure, the priority sorter inside the scheduling unit performs hardware-level sorting on all acquired priorities: first, it sorts them in descending order of numerical value to generate a priority sequence (e.g., 5→3→3→2 after sorting in the example above); if there are modules with the same priority (e.g., both module B and module C are 3), the order is determined according to a preset "secondary sorting rule" (e.g., module numbers from smallest to largest) (e.g., if module B is numbered 02 and module C is numbered 03, the order is B→C); the sorting result is stored in the "sorting result register" of the scheduling unit to form a sequential list of modules to be scheduled. According to the order list in the sorting result register, the scheduling unit sends "scheduling trigger signals" to each data buffer module in sequence: First, it sends a signal to the module with the highest priority (such as module A, priority 5), which contains the module identifier and data transmission instructions (such as "transmit all second data to be scheduled"); After receiving the signal, module A activates data output through its internal hardware path and transmits its stored second data to be scheduled (including data that has not timed out and data that has timed out) to the data receiving unit; When the data transmission of module A is completed (the data receiving unit returns a "transmission complete signal"), the scheduling unit immediately sends a scheduling signal to the next priority module (such as module B, priority 3), and repeats the above transmission process until the second data to be scheduled of all modules has been scheduled. If, during the sequential scheduling process, a module (e.g., module D, originally priority 2) experiences new timeout data, and its priority is updated to the highest (e.g., 5) by the detection module, the detection module will send a "priority change interrupt signal" to the scheduling unit. The scheduling unit will then suspend the scheduling of the currently running low-priority modules (e.g., module C), save their transmission progress, re-execute the priority acquisition and sorting process, generate a new sequence list (e.g., updated to 5→5→3→2), prioritize the newly promoted highest-priority module (module D), and resume the scheduling of the originally suspended modules after completion, ensuring that dynamic priority changes do not affect the timely processing of high-priority data.

[0080] By scheduling in descending order of priority, we ensure that data from high-priority modules (such as real-time interactive data) is processed first, preventing low-priority data (such as non-real-time logs) from preempting resources. At the same time, we sort modules with the same priority according to secondary rules to avoid scheduling chaos caused by the same priority and improve the scheduling fairness in multi-module scenarios.

[0081] To facilitate a better understanding of the deployment location of the data scheduling controller, such as Figure 2 As shown,Figure 2 This diagram illustrates the deployment location of a data scheduling controller provided in an embodiment of this disclosure. APP1, APP2, and APP3 are data sending units; APP1, APP2, and APP3 are data sources; HW queue is a data caching module; HW IOscheduler Agent is the data scheduling controller; file system is a file system; and Universal Flash Storage (UFS) controller is a universal flash storage controller. An input / output (IO) scheduling engine unit (i.e., the data scheduling controller) is added to the UFS controller to replace the original software IO scheduling (i.e., the software scheduling algorithm).

[0082] To facilitate a better understanding of the structure of the data scheduling controller, such as Figure 3 As shown, Figure 3This is a block diagram of a data scheduling controller provided in an embodiment of this disclosure. Sys timer is a system timer used to provide a global time base for timing (such as command timeouts and periodic updates). SW update SCTs / point is a software update counter / time point used to trigger update operations and synchronize software-side timing or status. URTD is the data to be scheduled. Hostmemory is the host memory used to store configuration data such as URTD, for shared access by the host and hardware modules. Queue0 / Queue1 / QueueX are registers; each data cache module corresponds to a 4-byte register. The register space required for n hardware queues is 4*n. The timeout configuration unit is ms, used to classify and manage IO commands (grouped by priority and type) for easy scheduling and timeout detection. Queue timeout period is the queue timeout period, setting a timeout time base for each queue to calculate the command's expire time. CMD0 req time is the command 0 request time, used to record the time the command was initiated (for calculating the expire time). CMD0 exp time is the expiration time of command 0, used to determine when a command times out. Timeout detect UNIT0 / UNIT1 / UNITX are timeout detection units (i.e., detection units 0 / 1 / X), controlling the commands in the corresponding queues, comparing the current time with the exp time to detect if the command (i.e., the data to be scheduled) has timed out. HW scheduler agent is the data scheduling controller. Priority arbitration unit is the priority arbitration unit, arbitrating the command issuance authority of multiple queues according to the priority configuration in URTD (higher priority queues are executed first). cmd buffer is the command buffer, temporarily storing IO commands to be issued (i.e., the data to be scheduled), buffering the command stream after scheduling, and adapting to the link layer transmission rhythm. link layer is the link layer (protocol layer), responsible for the physical transmission of commands (serialization, error control) and link management (handshake, synchronization). UFS host controller is the UFS host controller, the interface between the host and the UFS host, integrating scheduling, arbitration, and link management to coordinate and complete scheduling operations.A new timeout configuration register list has been added, with one 4-byte register corresponding to each hardware queue. The register space required for n hardware queues is 4*n, and the timeout configuration unit is ms. A new timeout register list has also been added for each slot of each hardware. If there are n hardware queues and each hardware queue has m slots (i.e., data to be scheduled), the total register space required is n*m*4. A new hardware scheduling engine unit has been added, mainly including a timeout detection unit corresponding to each hardware queue. The timeout detection unit is used to calculate the timeout time of each IO request, detect whether there are timeout requests in the queue, and temporarily increase the queue priority. The system's timer signal needs to be introduced into the UFS controller to obtain the timestamp.

[0083] To facilitate a better understanding of the scheduling process of the data scheduling controller, such as Figure 4 As shown, Figure 4This is a schematic diagram of the scheduling process of a data scheduling controller provided in an embodiment of this disclosure. During the initialization of the UFS controller (i.e., the data scheduling controller), the software configures the timeout period (i.e., temporary storage time threshold) for each hardware queue (data cache module) and fills it into the corresponding register. Simultaneously, the priority (i.e., scheduling priority) of each hardware queue is configured. When the software submits an IO request (i.e., data to be scheduled) to a hardware queue, the timeout detection unit (i.e., the detection unit) first reads the value of the sys timer to obtain the IO submission timestamp (submit time, i.e., the first time), and adds it to the timeoutperiod of this queue to obtain the timeout time (second temporary storage time): IO expired time = submit time + timeout period; the expired time is filled into the register corresponding to this slot. If the IO request in a certain hardware queue is not empty, the timeout detection unit of this hardware queue starts working: it reads the value of the sys timer to obtain the current timestamp now (i.e., the second time), and uses now to compare the expired time of each IO request in the queue; if now <= expired time, If now indicates that an IO request has timed out in this queue, the priority of this queue is increased to max (i.e., the highest scheduling priority) (max is 0). If now > expired time, it means that no IO requests have timed out in this queue, and the software-configured priority is restored. If the IO requests in this queue have been cleared, timeout detection is stopped. The UFS controller retrieves the IO requests from the highest priority queue according to the hardware queue priority and puts them into the cmd buffer. After the cmd buffers in the high-priority queues are exhausted, the lower-priority queues are retrieved. If there are queues with the same priority, a round-robin method is used, retrieving one request from each queue and polling each queue in turn.

[0084] To facilitate a better understanding of the data scheduling process in the embodiments of this disclosure and the data scheduling process in related technologies, such as Figure 5 As shown, Figure 5This is a comparative diagram of a data scheduling process provided in an embodiment of this disclosure. The process before optimization is the data scheduling process of related technologies, and the process after optimization is the data scheduling process of this embodiment. Submit_bio is the submission of data to be scheduled, Insert to sw queue is the insertion of data to be scheduled into the software queue, IO scheduler is the data scheduler to be processed, and the IO scheduler is used to schedule the data to be scheduled in the software queue, Dispatch to hw queue is the transfer of data to be scheduled to the hardware queue, and UFS handle request is the processing of data to be scheduled by general flash storage. By adding a hardware timeout mechanism in the UFS controller IP, the software deadline scheduling algorithm can be replaced, reducing the software overhead of the IO stack.

[0085] Figure 6 This is a block diagram of a data scheduling controller provided in an embodiment of this disclosure. This data scheduling controller can be applied to application scenarios such as smart terminals, for example, executed by a terminal integrated with data scheduling functions, or by other devices suitable for performing data scheduling and outputting data scheduling results; this disclosure does not limit its scope. Figure 1 As shown, the data scheduling controller includes: a detection unit 11 and a scheduling unit 12, wherein: The detection unit 21 is configured to obtain the first temporary storage time of the first data to be scheduled in the data cache unit, and determine whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; the first data to be scheduled is data sent by the data sending unit to the data cache unit; The detection unit 22 is configured to, when it is determined that the first data to be scheduled is the timed-out scheduling data, call the data caching unit to schedule the timed-out scheduling data to the data receiving unit.

[0086] In summary, in the embodiments of this disclosure, the data scheduling controller proposed in this disclosure includes: obtaining a first temporary storage time for a first data to be scheduled in a data cache unit; determining whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; and scheduling the timed-out scheduling data to a data receiving unit if it is determined that the first data to be scheduled is timed-out scheduling data. The data scheduling process is completed by the data scheduling controller, eliminating the need for the processor to execute a software scheduling algorithm, thereby solving the problem of software scheduling consuming processor computing resources.

[0087] In some embodiments, please continue reading Figure 6 The detection unit 21 includes at least two detection modules; The at least two detection modules are respectively connected to the corresponding data cache modules in the data cache unit; the data cache unit includes at least two data cache modules, and each data cache module has a corresponding detection module. The detection module is configured to obtain the second temporary storage time of the second data to be scheduled in the data caching module, and determine whether the second data to be scheduled is timed out based on the second temporary storage time; the first data to be scheduled includes at least two second data to be scheduled, and the first temporary storage time includes at least two second temporary storage times.

[0088] In some embodiments, please continue reading Figure 6 The detection module is configured as follows: The first time when the data caching module receives the second data to be scheduled is obtained, and the temporary storage time threshold of the data caching module is obtained; The second temporary storage time is calculated based on the first time and the temporary storage time threshold.

[0089] In some embodiments, please continue reading Figure 6 The detection module is configured as follows: The second time at which the second data to be scheduled is temporarily stored in the data cache module is obtained; the second time is greater than the first time. Based on the second time and the second temporary storage time, determine whether the second data to be scheduled is timed-out scheduling data.

[0090] In some embodiments, please continue reading Figure 6 The detection module is configured as follows: Obtain the initial scheduling priority of the data cache module where the timeout scheduling data is located; The initial scheduling priority is updated to the highest scheduling priority so that the timed-out scheduling data is scheduled to the data receiving unit based on the highest scheduling priority.

[0091] In some embodiments, please continue reading Figure 6 The detection module is configured as follows: Determine whether the timeout scheduling data exists in the data caching module; When it is determined that there is no timeout scheduling data in the data caching module, the current scheduling priority of the data caching module is obtained, and it is determined whether the current scheduling priority of the data caching module is the initial scheduling priority. When it is determined that the current scheduling priority of the data caching module is not the initial scheduling priority, the current scheduling priority is updated to the initial scheduling priority.

[0092] In some embodiments, please continue reading Figure 6 The detection unit 22 is configured as follows: The highest priority data caching module is invoked to schedule the timeout scheduling data in the highest priority data caching module to the data receiving unit.

[0093] In some embodiments, please continue reading Figure 6 The detection unit 22 is configured as follows: Obtain the current scheduling priority of at least two data caching modules; According to the descending order of the current scheduling priorities of the at least two data cache modules, the at least two data cache modules are called respectively, and the second data to be scheduled in the at least two data cache modules is scheduled to the data receiving unit.

[0094] For more detailed information on the working process of the above embodiments, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0095] To better understand the connection relationships between the data sending unit, data receiving unit, data buffering unit, and data scheduling controller, such as Figure 7 As shown, Figure 7 This is a block diagram of a data transmission system provided in an embodiment of the present disclosure. The system includes: Data transmission unit 41; Data receiving unit 42; Data buffer unit 43 is connected to the data sending unit 41 and the data receiving unit 42; The data scheduling controller 44 is connected to the data cache unit 43.

[0096] Corresponding to the data scheduling controller described above, this invention also proposes a data scheduling device. Since the device embodiments of this invention correspond to the method embodiments described above, details not disclosed in the device embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0097] Figure 8 This is a schematic diagram of a data scheduling device provided in an embodiment of the present disclosure. The data scheduling device includes: Acquisition unit 51 is used to acquire the first temporary storage time of the first data to be scheduled in the data cache unit; Determining unit 52 is used to determine whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; The scheduling unit 53 is used to schedule the timed-out scheduling data to the data receiving unit when it is determined that the first data to be scheduled is the timed-out scheduling data.

[0098] In summary, in the embodiments of this disclosure, the data scheduling apparatus proposed in this disclosure includes: obtaining a first temporary storage time for a first data to be scheduled in a data cache unit; determining whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; and scheduling the timed-out scheduling data to a data receiving unit if it is determined that the first data to be scheduled is timed-out scheduling data. The data scheduling process is completed by a data scheduling controller, eliminating the need for the processor to execute a software scheduling algorithm, thereby solving the problem of software scheduling consuming processor computing resources.

[0099] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 9 As shown, the determining unit 52 includes: The first acquisition module 521 is used to acquire the second temporary storage time of the second data to be scheduled in the data cache module; the data cache unit includes at least two data cache modules. The determining module 522 is used to determine whether the second data to be scheduled is timed out based on the second temporary storage time; the first data to be scheduled includes at least two second data to be scheduled, and the first temporary storage time includes at least two second temporary storage times.

[0100] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 9 As shown, the first acquisition module 521 is further configured to: The first time when the data caching module receives the second data to be scheduled is obtained, and the temporary storage time threshold of the data caching module is obtained; The second temporary storage time is calculated based on the first time and the temporary storage time threshold.

[0101] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 9 As shown, the determining module 522 is further configured to: The second time at which the second data to be scheduled is temporarily stored in the data cache module is obtained; the second time is greater than the first time. Based on the second time and the second temporary storage time, determine whether the second data to be scheduled is timed-out scheduling data.

[0102] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 9 As shown, the scheduling unit 53 includes: The second acquisition module 531 is used to acquire the initial scheduling priority of the data cache module where the timeout scheduling data is located; Update module 532 is used to update the initial scheduling priority to the highest scheduling priority. The scheduling module 533 is used to schedule the timed-out scheduling data to the data receiving unit based on the highest scheduling priority.

[0103] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 9 As shown, the device further includes: The determining unit 52 is further configured to determine whether the timeout scheduling data exists in the data caching module; The acquisition unit 51 is further configured to, when it is determined that there is no timeout scheduling data in the data cache module, acquire the current scheduling priority of the data cache module, and determine whether the current scheduling priority of the data cache module is the initial scheduling priority; The update unit 54 is used to update the current scheduling priority to the initial scheduling priority when it is determined that the current scheduling priority of the data cache module is not the initial scheduling priority.

[0104] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 9 As shown, the scheduling module 533 is further configured to: The highest priority data caching module is invoked to schedule the timeout scheduling data in the highest priority data caching module to the data receiving unit.

[0105] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 9 As shown, the device further includes: The acquisition unit 51 is further configured to acquire the current scheduling priority of at least two data caching modules; The scheduling unit 53 is further configured to call the at least two data cache modules respectively in descending order of their current scheduling priorities, and schedule the second data to be scheduled in the at least two data cache modules to the data receiving unit.

[0106] Since the apparatus provided in this embodiment corresponds to the methods provided in the above embodiments, the implementation of the methods is also applicable to the apparatus provided in this embodiment, and will not be described in detail in this embodiment.

[0107] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0108] Figure 10 This is a block diagram illustrating an electronic device 600 for implementing the above-described data scheduling method, according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0109] Reference Figure 10 The electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0110] Processing component 602 typically controls the overall operation of electronic device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.

[0111] Memory 604 is configured to store various types of data to support the operation of electronic device 600. Examples of such data include instructions for any application or method operating on electronic device 600, contact data, phonebook data, messages, pictures, videos, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0112] Power supply component 606 provides power to various components of electronic device 600. Power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 600.

[0113] Multimedia component 608 includes a screen that provides an output interface between electronic device 600 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When electronic device 600 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0114] Audio component 610 is configured to output and / or input audio signals. For example, audio component 610 includes a microphone (MIC) configured to receive external audio signals when electronic device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.

[0115] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0116] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of electronic device 600. For example, sensor assembly 614 may detect the on / off state of electronic device 600, the relative positioning of components such as the display and keypad of electronic device 600, changes in position of electronic device 600 or a component of electronic device 600, the presence or absence of user contact with electronic device 600, orientation or acceleration / deceleration of electronic device 600, and temperature changes of electronic device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0117] Communication component 616 is configured to facilitate wired or wireless communication between electronic device 600 and other devices. Electronic device 600 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 616 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0118] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0119] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, which can be executed by a processor 620 of an electronic device 600 to complete the above-described method through data scheduling. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0120] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the above embodiments of this disclosure.

[0121] To implement the above embodiments, this disclosure also proposes a chip, including: the chip includes processing circuitry configured to perform the methods provided in the foregoing embodiments.

[0122] Figure 11 This is a schematic diagram of the structure of a chip according to an embodiment of this disclosure. See also... Figure 11 The diagram shown is a schematic representation of the structure of chip 700, but is not limited thereto.

[0123] Chip 700 includes processing circuit 701 and interface circuit 702. Interface circuit 702 is used to read instructions and send instructions to processing circuit 701 so that processing circuit 701 executes the above-described method.

[0124] Optionally, such as Figure 12 As shown,Figure 12 This is a schematic diagram of another chip structure proposed in an embodiment of this disclosure. Chip 700 may further include: a memory 703 for storing instructions, and an interface circuit 702 for reading the instructions stored in the memory 703.

[0125] Optionally, the interface circuit 702 is connected to the memory 703. The interface circuit 702 can be used to receive signals from the memory 703 or other devices, and can also be used to send signals to the memory 703 or other devices. For example, the interface circuit 702 can read instructions stored in the memory 703 and send those instructions to the processing circuit 701.

[0126] Optionally, the number of memories 703 can be one or more. The number of interface circuits 702 can also be one or more.

[0127] In some embodiments, the interface circuit 702 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 701 performs other steps.

[0128] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0129] Alternatively, all or part of the memory 703 may be located outside of the chip 700.

[0130] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0131] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0132] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0133] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0134] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0135] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0136] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0137] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0138] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A data scheduling method, characterized in that, The method is applied to a data scheduling controller, and the method includes: Get the first temporary storage time of the first data to be scheduled in the data cache unit; Determine whether the first data to be scheduled is timed out based on the first temporary storage time; If it is determined that the first data to be scheduled is the timed-out scheduling data, the timed-out scheduling data is scheduled to the data receiving unit.

2. The method according to claim 1, characterized in that, The step of determining whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time includes: The second temporary storage time of the second data to be scheduled in the data caching module is obtained; the data caching unit includes at least two data caching modules. The second data to be scheduled is determined based on the second temporary storage time. The first data to be scheduled includes at least two second data to be scheduled, and the first temporary storage time includes at least two second temporary storage times.

3. The method according to claim 2, characterized in that, The second temporary storage time of the second data to be scheduled in the data acquisition cache module includes: The first time when the data caching module receives the second data to be scheduled is obtained, and the temporary storage time threshold of the data caching module is obtained; The second temporary storage time is calculated based on the first time and the temporary storage time threshold.

4. The method according to claim 3, characterized in that, The step of determining whether the second data to be scheduled is timed-out scheduling data based on the second temporary storage time includes: The second time at which the second data to be scheduled is temporarily stored in the data cache module is obtained; the second time is greater than the first time. Based on the second time and the second temporary storage time, determine whether the second data to be scheduled is timed-out scheduling data.

5. The method according to claim 2, characterized in that, The step of scheduling the timed-out scheduling data to the data receiving unit includes: Obtain the initial scheduling priority of the data cache module where the timeout scheduling data is located; The initial scheduling priority is updated to the highest scheduling priority so that the timed-out scheduling data is scheduled to the data receiving unit based on the highest scheduling priority.

6. The method according to claim 5, characterized in that, The method further includes: Determine whether the timeout scheduling data exists in the data caching module; When it is determined that there is no timeout scheduling data in the data caching module, the current scheduling priority of the data caching module is obtained, and it is determined whether the current scheduling priority of the data caching module is the initial scheduling priority. When it is determined that the current scheduling priority of the data caching module is not the initial scheduling priority, the current scheduling priority is updated to the initial scheduling priority.

7. The method according to claim 5, characterized in that, The step of scheduling the timed-out scheduling data to the data receiving unit based on the highest scheduling priority includes: The highest priority data caching module is invoked to schedule the timeout scheduling data in the highest priority data caching module to the data receiving unit.

8. The method according to claim 2, characterized in that, The method further includes: Obtain the current scheduling priority of at least two data caching modules; According to the descending order of the current scheduling priorities of the at least two data cache modules, the at least two data cache modules are called respectively, and the second data to be scheduled in the at least two data cache modules is scheduled to the data receiving unit.

9. A data scheduling controller, characterized in that, The controller includes: a detection unit and a scheduling unit, wherein... The detection unit is configured to obtain the first temporary storage time of the first data to be scheduled in the data cache unit, and determine whether the first data to be scheduled is timed-out scheduling data based on the first temporary storage time; the first data to be scheduled is data sent by the data sending unit to the data cache unit; The scheduling unit is configured to, when it is determined that the first data to be scheduled is the timed-out scheduling data, invoke the data caching unit to schedule the timed-out scheduling data to the data receiving unit.

10. The controller according to claim 9, characterized in that, The detection unit includes at least two detection modules; The at least two detection modules are respectively connected to the corresponding data cache modules in the data cache unit; the data cache unit includes at least two data cache modules, and each data cache module has a corresponding detection module. The detection module is configured to obtain the second temporary storage time of the second data to be scheduled in the data caching module, and determine whether the second data to be scheduled is timed out based on the second temporary storage time; the first data to be scheduled includes at least two second data to be scheduled, and the first temporary storage time includes at least two second temporary storage times.

11. The controller according to claim 10, characterized in that, The detection module is configured as follows: The first time when the data caching module receives the second data to be scheduled is obtained, and the temporary storage time threshold of the data caching module is obtained; The second temporary storage time is calculated based on the first time and the temporary storage time threshold.

12. The controller according to claim 11, characterized in that, The detection module is configured as follows: The second time at which the second data to be scheduled is temporarily stored in the data cache module is obtained; the second time is greater than the first time. Based on the second time and the second temporary storage time, determine whether the second data to be scheduled is timed-out scheduling data.

13. The controller according to claim 10, characterized in that, The detection module is configured as follows: Obtain the initial scheduling priority of the data cache module where the timeout scheduling data is located; The initial scheduling priority is updated to the highest scheduling priority so that the timed-out scheduling data is scheduled to the data receiving unit based on the highest scheduling priority.

14. The controller according to claim 13, characterized in that, The detection module is configured as follows: Determine whether the timeout scheduling data exists in the data caching module; When it is determined that there is no timeout scheduling data in the data caching module, the current scheduling priority of the data caching module is obtained, and it is determined whether the current scheduling priority of the data caching module is the initial scheduling priority. When it is determined that the current scheduling priority of the data caching module is not the initial scheduling priority, the current scheduling priority is updated to the initial scheduling priority.

15. The controller according to claim 13, characterized in that, The scheduling unit is configured as follows: The highest priority data caching module is invoked to schedule the timeout scheduling data in the highest priority data caching module to the data receiving unit.

16. The controller according to claim 10, characterized in that, The scheduling unit is configured as follows: Obtain the current scheduling priority of at least two data caching modules; According to the descending order of the current scheduling priorities of the at least two data cache modules, the at least two data cache modules are called respectively, and the second data to be scheduled in the at least two data cache modules is scheduled to the data receiving unit.

17. A data transmission system, characterized in that, The system includes: Data transmission unit; Data receiving unit; A data buffer unit is connected to the data sending unit and the data receiving unit; The data scheduling controller as described in any one of claims 9-16 is connected to the data cache unit.

18. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

19. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-8.

20. A chip, characterized in that, The chip includes a processing circuit and an interface circuit; wherein the interface circuit is used to read instructions and send the instructions to the processing circuit so that the processing circuit executes the method as described in any one of claims 1-8.

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