Server signal false pull-up prevention system and server

Abstract

The invention provides a server signal false pull-up prevention system and a server, and relates to the technical field of computers. Comprising a power management module, a first controller, a logic judgment module and a pull-up module, the output end of the power management module is electrically connected with the first controller; the first output end of the first controller is connected with the first signal input end of the logic judgment module, and the second output end of the first controller is connected with the second signal input end of the logic judgment module; the output end of the logic judgment module is electrically connected with one end of the pull-up module; the other end of the pull-up module is electrically connected with the output end of the power management module, and the pull-up module is used for conducting a circuit when a high level is input, and pulling down an enabling pin of the target voltage regulator to complete mistaken pull-up operation. When the logic judgment module detects that the initialization of the first controller is not completed, the logic judgment module pulls down the enabling pin of the target voltage regulator, so that wrong startup or state misjudgment caused by the fact that the controller is not ready is eliminated, and the timing sequence specification is strictly ensured.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a server anti-false signal pull-up system and server. Background Technology

[0002] With the development of server technology, their performance is becoming increasingly higher, and the requirements for reliability are also becoming more stringent. To ensure the normal operation of the server, the power supply design must not only meet stability requirements but also ensure that when power supplies are used as pull-up signals, there will be no accidental high pull-ups. This ensures stable operation under various special working conditions.

[0003] Currently, the enable pin (EN pin) of the voltage regulator (VR) is directly provided by the controller. If the EN pin is mistakenly pulled up by a pull-up signal before the controller initialization is complete, the controller will not perform any monitoring actions, and the system will not misjudge the situation. However, if the EN pin is mistakenly pulled up after the controller initialization is complete, the controller will monitor it. When the voltage of the mistakenly pulled-up EN pin exceeds the threshold for VR operation, the system will mistakenly assume that the EN pin is high, and the VR will output normally. Since the power supplies of the server have strict timing requirements, if the EN pin is mistakenly pulled high before the controller initialization is complete, the VR will not operate in accordance with the server's timing requirements. Summary of the Invention

[0004] This application provides a server anti-signal pull-up system and server to at least solve the problem in related technologies where the EN pin is mistakenly pulled to a high level before the controller initialization is completed, causing the VR operation to fail to meet the server timing requirements.

[0005] In a first aspect, this application provides a server anti-signal pull-up system, comprising: a power management module, a first controller, a logic judgment module, and a pull-up module;

[0006] The output of the power management module is electrically connected to the first controller, and the power management module is used to convert standard power into power for controller initialization.

[0007] The first output terminal of the first controller is connected to the first signal input terminal of the logic judgment module, and the second output terminal of the first controller is connected to the second signal input terminal of the logic judgment module. The first controller is used to receive the controller initialization power output by the power management module, and outputs a low level and an enable signal when it is detected that the initialization of the first controller is not completed.

[0008] The output of the logic judgment module is electrically connected to one end of the pull-up module. The logic judgment module is used to compare the low level with the threshold level to obtain the first condition judgment result, and compare the enable signal with the fixed signal to obtain the second condition judgment result. When the first condition judgment result or the second condition judgment result is not satisfied, the output is high level.

[0009] The other end of the pull-up module is electrically connected to the output of the power management module. The pull-up module is used to turn on the circuit when the input is high and pull the enable pin of the target voltage regulator low to complete the pull-up operation.

[0010] Secondly, this application provides a server, including a server body and a server anti-signal erroneous pull-up system provided in the first aspect of this application.

[0011] This application provides a server anti-false pull-up system and server, including: a power management module, a first controller, a logic judgment module, and a pull-up module; wherein, the output terminal of the power management module is electrically connected to the first controller, and the power management module is used to convert standard power into controller initialization power; the first output terminal of the first controller is connected to the first signal input terminal of the logic judgment module, and the second output terminal of the first controller is connected to the second signal input terminal of the logic judgment module, and the first controller is used to receive the controller initialization power output by the power management module, and output a low level and an enable signal when it is detected that the first controller initialization is not completed; the output terminal of the logic judgment module is electrically connected to one end of the pull-up module, and the logic judgment module is used to compare the low level with a threshold level to obtain a first condition judgment result, and compare the enable signal with a fixed signal to obtain a second condition judgment result, and output a high level when it is detected that the first condition judgment result or the second condition judgment result is not satisfied; the other end of the pull-up module is electrically connected to the output terminal of the power management module, and the pull-up module is used to turn on the circuit when the input is high level, and pull down the enable pin of the target voltage regulator to complete the false pull-up operation. Through the above structural design, the following technical effects are achieved: When the initialization of the first controller is incomplete, the first output terminal of the first controller outputs a low-level signal to the logic judgment module. Since the low level is less than the threshold level, the first condition judgment result is not met, and the logic judgment module outputs a high level. The pull-up module receives the high level and turns on the circuit, pulling the enable pin of the target voltage regulator low, thus completing the erroneous pull-up operation. By detecting that the initialization of the first controller is incomplete, the logic judgment module pulls the enable pin of the target voltage regulator low, eliminating erroneous power-on or status misjudgment caused by the first controller not being ready. This ensures that the power-on of relevant components strictly follows the server's power sequence specifications, thereby avoiding power-on surges or short-circuit currents that may be caused by disordered power sequences, and mitigating potential device damage. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic diagram of the server anti-false signal pull-up system provided in this application embodiment. Figure 1 ;

[0014] Figure 2 A schematic diagram of the server anti-false signal pull-up system provided in this application embodiment. Figure 2 . Detailed Implementation

[0015] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0016] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply difference. It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner. In the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more.

[0017] It should be noted that the server anti-false signal pull-up system and server provided in this application embodiment are only examples, and the server anti-false signal pull-up system and server may include more or less content.

[0018] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with relevant laws, regulations and standards, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0019] First, some terms used in the embodiments of this application will be explained.

[0020] STBY power and core power: Current server power supplies are divided into STBY power and core power. STBY power means that the motherboard has power when the power supply unit (PSU) is in place and working. Core power means that the controller on the controlled board has power, which means that it will only start after the controller is initialized.

[0021] VR: EN pin is its enable pin, and PG pin is its power good pin. VR starts working and outputs voltage only when the EN pin receives a high-level signal; once the VR's output voltage is stable and normal, the PG pin sends a high-level signal.

[0022] In order to clearly understand the technical solution of this application, the solutions of related technologies are described in detail.

[0023] Currently, the VR enable pin (EN pin) is directly provided by the controller. If the EN pin is mistakenly pulled up by a pull-up signal before the controller initialization is complete, the controller will not perform any monitoring actions, and the system will not misjudge the situation. However, if the EN pin is still mistakenly pulled up after the controller initialization is complete, the controller will monitor it. When the voltage of the mistakenly pulled-up EN pin exceeds the threshold for VR operation, the system will mistakenly assume that the EN pin is high, and the VR will output normally. Because the server's power supplies have strict timing requirements, if the EN pin is mistakenly pulled high before the controller initialization is complete, the VR will not operate within the server's timing requirements.

[0024] In summary, the problem that VR operation does not meet the server timing requirements is that the relevant technology mistakenly pulls the EN pin to a high level before the controller initialization is completed. This is the problem that this application urgently needs to solve.

[0025] Therefore, in view of the above-mentioned technical problems existing in the related technologies, the embodiments of this application provide a server anti-signal erroneous pull-up system and server, which aims to effectively ensure the strict timing requirements of the server.

[0026] The following describes a server anti-false signal pull-up system and its application scenarios provided by embodiments of this application. The application scenarios described below are merely examples, intended to help those skilled in the art understand the technical content of this application, but do not imply that the embodiments of this application cannot be used in other devices, systems, environments, or scenarios.

[0027] Data center server cluster: The server anti-signal pull-up system and server provided in this application embodiment strictly ensure power supply timing issues, ensuring that only after the core hardware such as CPU and memory completes self-test and initialization and reaches a stable working state, the subsequent power supplies and peripheral components are woken up in an orderly manner, thus providing a safer and more reliable startup environment.

[0028] Figure 1 A schematic diagram of the server anti-false signal pull-up system provided in this application embodiment. Figure 1 .like Figure 1 As shown, the server anti-signal pull-up system provided in this embodiment includes: a power management module, a first controller, a logic judgment module, and a pull-up module.

[0029] The output of the power management module is electrically connected to the first controller, and the power management module is used to convert standard electricity into power for controller initialization.

[0030] In this embodiment, the power management module includes a PSU, an electronic fuse module, and a power management integrated circuit (PMIC) module.

[0031] After the server is plugged in, the PSU outputs a 12V DC voltage, which is the standard voltage and is marked as P12V_PSU. After passing through the electronic fuse module, it becomes P12V_STBY, which is the standby 12V, and is sent to the PMIC module. The PMIC module's input is the standby voltage output from the electronic fuse module, and its output is multiple low-voltage standby voltages, which are used for controller initialization.

[0032] The first output terminal of the first controller is connected to the first signal input terminal of the logic judgment module, and the second output terminal of the first controller is connected to the second signal input terminal of the logic judgment module. The first controller is used to receive the controller initialization power output by the power management module, and outputs a low level and an enable signal when it is detected that the initialization of the first controller is not completed.

[0033] In this embodiment, the signals output by the first output terminal of the first controller include, but are not limited to, the CPLD_Done signal or the MCU_Ready signal, and the signals output by the second output terminal of the first controller include, but are not limited to, the CPLD_ENn signal or the MCU_Enable signal. The first controller receives the controller initialization power from the power management module. When the initialization of the first controller is not complete, the signal output by the first output terminal of the first controller is a low-level signal, and the signal output by the second output terminal of the first controller is an enable signal.

[0034] The first controller sends the En signal to each Core, which is the enable signal output by the second output terminal of the first controller. This signal determines whether EN is provided by using 0 or 1.

[0035] The output of the logic judgment module is electrically connected to one end of the pull-up module. The logic judgment module is used to compare the low level with the threshold level to obtain the first condition judgment result, and compare the enable signal with the fixed signal to obtain the second condition judgment result. When the first condition judgment result or the second condition judgment result is not satisfied, a high level is output.

[0036] In this embodiment, the logic judgment module can optionally be a digital comparator or other components that can achieve the same function; no specific restrictions are imposed here.

[0037] The threshold level is a fixed reference threshold that is pre-set in the logic judgment module. If the input signal at the first signal input terminal of the logic judgment module is less than the threshold level, the first condition judgment result is not met. Specifically, in this embodiment, if the low level is less than the threshold level, the first condition judgment result is not met. Regardless of whether the second condition judgment result is met, the logic judgment module outputs a high level at this time.

[0038] The other end of the pull-up module is electrically connected to the output of the power management module. The pull-up module is used to turn on the circuit when the input is high and pull the enable pin of the target voltage regulator low to complete the pull-up operation.

[0039] In this embodiment, if the logic judgment module outputs a high level, the high-level signal is input to the pull-up module, and the pull-up module turns on Q1, pulling the enable pin EN of the target VR low, thus preventing the target device from starting. An NMOS pull-down is used, where the NMOS is jointly controlled by the first base voltage and the output of the logic judgment module.

[0040] Optionally, the first controller can be a Complex Programmable Logic Device (CPLD) or a Microcontroller Unit (MCU). When the first controller is a CPLD, the signal output from its first output terminal is the CPLD_Done signal, electrically connected to the first signal input terminal of the logic judgment module, and the signal output from its second output terminal is the CPLD_ENn signal, electrically connected to the second signal input terminal of the logic judgment module. When the first controller is an MCU, the signal output from its first output terminal is the MCU_Ready signal, electrically connected to the first signal input terminal of the logic judgment module, and the signal output from its second output terminal is the MCU_Enable signal, electrically connected to the second signal input terminal of the logic judgment module. No specific restrictions are placed on the first controller here.

[0041] When the first controller initialization is incomplete, the first output terminal of the first controller outputs a low-level signal to the logic judgment module. Since the low level is less than the threshold level, the first condition judgment result is not met, and the logic judgment module outputs a high level. The pull-up module receives the high level and turns on the circuit, pulling the enable pin of the target voltage regulator low, thus completing the erroneous pull-up operation. By detecting that the first controller initialization is incomplete, the logic judgment module pulls the enable pin of the target voltage regulator low, eliminating erroneous power-on or status misjudgment caused by the first controller not being ready. This ensures that the power-on of relevant components strictly follows the server's power sequence specifications, thereby avoiding potential power-on surges or short-circuit currents caused by disordered power sequences and mitigating potential device damage.

[0042] This application provides a server anti-false pull-up system, comprising: a power management module, a first controller, a logic judgment module, and a pull-up module; wherein, the output terminal of the power management module is electrically connected to the first controller, and the power management module is used to convert standard power into controller initialization power; the first output terminal of the first controller is connected to the first signal input terminal of the logic judgment module, and the second output terminal of the first controller is connected to the second signal input terminal of the logic judgment module, and the first controller is used to receive the controller initialization power output by the power management module, and output a low level and an enable signal when it is detected that the first controller initialization is not completed; the output terminal of the logic judgment module is electrically connected to one end of the pull-up module, and the logic judgment module is used to compare the low level with a threshold level to obtain a first condition judgment result, and compare the enable signal with a fixed signal to obtain a second condition judgment result, and output a high level when it is detected that the first condition judgment result or the second condition judgment result is not met; the other end of the pull-up module is electrically connected to the output terminal of the power management module, and the pull-up module is used to turn on the circuit when the input is high level, and pull down the enable pin of the target voltage regulator to complete the false pull-up operation. Through the above structural design, the following technical effects are achieved: When the initialization of the first controller is incomplete, the first output terminal of the first controller outputs a low-level signal to the logic judgment module. Since the low level is less than the threshold level, the first condition judgment result is not met, and the logic judgment module outputs a high level. The pull-up module receives the high level and turns on the circuit, pulling the enable pin of the target voltage regulator low, thus completing the erroneous pull-up operation. By detecting that the initialization of the first controller is incomplete, the logic judgment module pulls the enable pin of the target voltage regulator low, eliminating erroneous power-on or status misjudgment caused by the first controller not being ready. This ensures that the power-on of relevant components strictly follows the server's power sequence specifications, thereby avoiding power-on surges or short-circuit currents that may be caused by disordered power sequences, and mitigating potential device damage.

[0043] Based on the above embodiments, this application provides a server anti-false signal pull-up system. In this embodiment, the controller initialization power output from the power management module in the server anti-false signal pull-up system includes a first base voltage, a second base voltage, and a third base voltage; wherein, the first base voltage is greater than the second base voltage, the second base voltage is greater than the third base voltage, and the other end of the pull-up module is electrically connected to the output of the power management module to receive the first base voltage. The first base voltage, the second base voltage, and the third base voltage are all input to the first controller to complete the initialization of the first controller.

[0044] In this embodiment, the first base voltage is P3V3_STBY, the second base voltage is P1V8_STBY, and the third base voltage is P1V2_STBY. The PMIC module converts P12V_STBY into P3V3_STBY, P1V8_STBY, and P1V2_STBY. The first controller uses P3V3_STBY, P1V8_STBY, and P1V2_STBY for power supply and begins initialization. Optionally, in addition to outputting the three standby voltages P3V3_STBY, P1V8_STBY, and P1V2_STBY, the PMIC module can also output other standby voltages. The PMIC module can achieve multi-channel power conversion, has a small board area, and is compact, meeting design requirements for board-constrained applications.

[0045] The power management module outputs a first base voltage, a second base voltage, and a third base voltage, which are then used by the first controller for initialization, achieving an efficient, stable, and integrated power management solution. By providing multiple precise voltage levels, it not only optimizes energy utilization and reduces heat generation, but also ensures the reliable startup and operation sequence of each system component, thereby improving the system's response speed and reliability. At the same time, it simplifies hardware design and supports flexible power consumption control strategies.

[0046] The output of the logic judgment module is electrically connected to one end of the pull-up module, and the other end of the pull-up module is connected to the first base voltage. Optionally, the other end of the pull-up module can be connected to the first base voltage or to another suitable STBY, such as P5V_STBY; no specific limitation is made here. The electronic fuse module, power management integrated circuit module, first controller, logic judgment module, and pull-up module are connected to each other via electrical signals. The logic judgment module detects the operating status of the first controller, i.e., monitors the initialization completion status of the first controller.

[0047] Based on the above embodiments, this application provides a server anti-false signal pull-up system. In this embodiment, the pull-up module in the server anti-false signal pull-up system includes a switching resistor, a negatively charged metal-oxide-semiconductor field-effect transistor, and a pull-up resistor.

[0048] The switching resistor is connected to the first base voltage and the gate of the negative charge metal oxide semiconductor field-effect transistor, respectively. The source of the negative charge metal oxide semiconductor field-effect transistor is grounded. The drain of the negative charge metal oxide semiconductor field-effect transistor is connected to the enable pin of the target voltage regulator and the pull-up resistor, respectively. The pull-up resistor is connected to the first base voltage.

[0049] In this embodiment, as Figure 1As shown, the switching resistor is R1, the negative charge type metal-oxide-semiconductor field-effect transistor is an N-channel depletion-mode metal-oxide-semiconductor field-effect transistor (NMOS), and the NMOS transistor is Q1. The pull-up resistor is R2. The gate (G) of Q1 is connected to R1, the source (S) of Q1 is grounded, and the drain (D) of Q1 is connected to the enable pin (EN) of the target voltage regulator and the pull-up resistor R2, respectively.

[0050] By using a pull-up module composed of a switching resistor, a negative charge metal oxide semiconductor field-effect transistor, and a pull-up resistor, the voltage regulator can be pulled to a low level when the first controller has not completed initialization, i.e., has not entered the normal working state. This eliminates the possibility of false power-on or misjudgment of status caused by the first controller not being ready, and strictly ensures the strict timing of the server.

[0051] Based on the above embodiments, this application provides a server anti-false signal pull-up system. In this embodiment, the first controller in the server anti-false signal pull-up system is further configured to: receive controller initialization power output from the power management module, and output a high-level signal and an enable signal when the initialization of the first controller is detected to be complete.

[0052] In this embodiment, the first controller is also used to receive the controller initialization power output by the power management module. When the first controller completes initialization, the signal output by the first output terminal of the first controller is a high-level signal, and the signal output by the second output terminal of the first controller is an enable signal.

[0053] The logic judgment module is also used to: compare the high level with the threshold level to obtain the first condition judgment result, and compare the enable signal with the fixed signal to obtain the second condition judgment result. When the first condition judgment result and the second condition judgment result are both satisfied, a low level is output.

[0054] In this embodiment, the fixed signal is the digital number 1, and the threshold level is a fixed reference threshold pre-set in the logic judgment module. If the input signal at the first signal input terminal of the logic judgment module is greater than or equal to the threshold level, the first condition judgment result is satisfied. Specifically, in this embodiment, the high level is greater than the threshold level, and the first condition judgment result is satisfied. If the enable signal is 1, the second condition judgment result is satisfied; otherwise, the second condition judgment result is not satisfied. The enable signal is controlled by internal logic to be either 0 or 1.

[0055] When both the first and second condition determination results are satisfied, the output terminal of the logic judgment module outputs a low-level signal.

[0056] The pull-up module is also used to: cut off the circuit when the input is low and pull up the enable pin of the target voltage regulator to complete the pull-up operation.

[0057] In this embodiment, when both the first condition determination result and the second condition determination result are satisfied, the output terminal of the logic judgment module outputs a low-level signal, inputs the low-level signal to the pull-up module, and cuts off Q1 through the pull-up module, so that the enable pin EN pin of the target VR is pulled high, and the target device is started.

[0058] This method achieves strict timing control and fault safety protection. The system only allows the target voltage regulator to be powered on when both the first and second condition judgment results are met. This ensures that each functional module starts up in the predetermined order, avoiding system instability caused by power competition or logic confusion. At the same time, it also serves as an interlocking mechanism to effectively prevent accidental startup when the necessary conditions are not met, thereby avoiding potential surge current, power conflicts or signal latching errors, and significantly improving the robustness and reliability of the hardware.

[0059] The following is the control logic of the server's anti-false signal pull-up system:

[0060] First, the electronic fuse module converts P12V_PSU to P12V_STBY and sends P12V_STBY to the PMIC module. The PMIC module then converts P12V_STBY into P3V3_STBY, P1V8_STBY, and P1V2_STBY, which power the first controller and are used as pull-up resistors. The initialization status signal of the first controller is then acquired, indicating whether the first controller has completed initialization.

[0061] Secondly, based on the initialization status signal, the level signal output by the first output terminal of the first controller is determined. Specifically, if the initialization of the first controller is complete, the level signal output by the first output terminal of the first controller is high; if the initialization of the first controller is not complete, the level signal output by the first output terminal of the first controller is low.

[0062] Then, the level signal output from the first output terminal of the first controller, the enable signal output from the second output terminal of the first controller, and the threshold level are input to the logic judgment module to obtain the level signal output by the logic judgment module. The level signal output from the first output terminal is compared with the threshold level to obtain the first condition judgment result, and the enable signal output from the second output terminal of the first controller is compared with the fixed signal to obtain the second condition judgment result. The level signal output by the logic judgment module is obtained based on the comparison result of the first condition and the comparison result of the second condition. Specifically, when the level signal output from the first output terminal is greater than or equal to the threshold level, the first condition judgment result is satisfied; otherwise, it is not satisfied. When the enable signal output from the second output terminal of the first controller is equal to the fixed signal, the second condition judgment result is satisfied; otherwise, it is not satisfied. The control logic that uses an AND operation between the first and second condition judgment results outputs a low-level signal only when both the first and second condition judgment results are satisfied; otherwise, the logic judgment module outputs a high-level signal.

[0063] Finally, the level signal output by the logic judgment module is input to the pull-up module, which dynamically adjusts the pull-up state of the enable pin of the target voltage regulator based on the level signal output by the logic judgment module. Specifically, if the level signal output by the logic judgment module is high, the high-level signal is input to the pull-up module, which turns on the negative charge metal-oxide-semiconductor field-effect transistor (MOSFET), pulling the enable pin of the target voltage regulator low and preventing the target device from starting. If the level signal output by the logic judgment module is low, the low-level signal is input to the pull-up module, which turns off the MOSFET, setting the enable pin of the target voltage regulator high and starting the target device.

[0064] During power-on, since the STBY power supply precedes the CPLD, and the CPLD precedes the core power supply, if the input to the core power supply VR is the STBY power supply, and the EN signal is mistakenly pulled up by the STBY power supply, the VR will output prematurely, causing timing and CPLD logic confusion, resulting in abnormal server startup. The server anti-signal pull-up system and server provided in this application embodiment can strictly guarantee timing issues.

[0065] When the EN signal of the electronic fuse module that supplies power to components such as hard drives and fans is repeatedly and mistakenly pulled up, the electronic fuse module repeatedly turns on, and the large current caused by the untimely switching of the back-end load can burn out the back-end components. The server anti-signal pull-up system and server provided in this application embodiment can effectively solve the problem of mistaken pull-up.

[0066] Because the EN signal is mistakenly pulled up, it is impossible to accurately locate the problem when the motherboard malfunctions. The server anti-mistaken signal pull-up system and server provided in this application embodiment can effectively solve the mistaken pull-up problem.

[0067] In related technologies, pull-up signals are suppressed by adding a pull-down capacitor to the EN signal. However, if this capacitor is too large during the design process, it will cause slow power-up, leading to controller recognition timeouts and preventing the device from booting up. Furthermore, as the capacitor ages, its capacitance decreases, reducing its suppression effectiveness and potentially causing suppression failure. The server anti-false pull-up signal system and server provided in this application effectively solve the problem of suppression failure.

[0068] For the subsequent VR stage, if the VR's EN pin is pulled high, and the input is not yet reached, the EN pin is easily damaged, leading to device failure. The server anti-signal pull-up system and server provided in this application embodiment can strictly guarantee timing issues and avoid device damage caused by timing violations.

[0069] Figure 2 A schematic diagram of the server anti-false signal pull-up system provided in this application embodiment. Figure 2 .like Figure 2 As shown, the pull-up module in the server anti-signal pull-up system provided in this embodiment further includes: an AND gate section with its first input terminal grounded and connected to the enable pin of the target voltage regulator, a second controller with its input terminal connected to the output terminal of the AND gate section, and the second input terminal of the AND gate section connected to the second output terminal of the first controller.

[0070] In this embodiment, the second controller M1 can be an MCU, and the pull-up module also includes an AND gate section A1 and the second controller M1. The first input terminal of the AND gate section A1 is interface 1, the second input terminal of the AND gate section A1 is interface 2, and the output terminal of the AND gate section is interface 3.

[0071] The first input terminal of A1 is grounded and connected to the VR EN pin. The second input terminal of A1 is connected to the second output terminal of the first controller. The output terminal of A1 is connected to the second controller M1.

[0072] The second output of the first controller is connected to the enable pin of the target voltage regulator.

[0073] In this embodiment, the second output terminal of the first controller is connected to the VR EN pin. The VR EN pin is used to turn the VR module on or off. When the VR module is turned on, it outputs the working voltage of the target component to start the target component.

[0074] The second controller is used to: detect the target enable signal output by the target voltage regulator when it is working normally, and send a reset signal to the AND gate section according to the detection results within a preset time period.

[0075] In this embodiment, the target enable signal output by the target voltage regulator when it is working normally is the level signal emitted by the PG Pin, i.e., the PG signal. The second controller M1 is used to detect the PG signal and send a reset signal to A1 according to the detection results within a preset time period. Optionally, the preset time period is 20 minutes. No specific limitation is made to the preset time period here.

[0076] The AND gate section is used to receive a reset signal and output a reset signal to the second output terminal of the first controller. The reset signal is used to control the target voltage regulator to reset and restart.

[0077] In this embodiment, A1 is used to receive a reset signal and output a reset signal to the second output terminal of the first controller. After receiving the reset signal, the second output terminal of the first controller controls the target voltage regulator to reset and restart according to the reset signal.

[0078] The second controller and AND gates are used to detect and reset the PG signal output by the VR module. This allows for real-time monitoring of the PG signal through the second controller, ensuring no transient anomalies are missed, while the combination of the second controller and AND gates enables the VR module to be reset and restarted. This solution combines the determinism of hardware circuitry with the programmability of the controller, offering both extremely high response speed and flexible fault handling strategies. It can not only capture and respond to transient power anomalies in a timely manner to prevent system crashes, but also intelligently determine and execute targeted reset actions. Furthermore, it reports precise fault information when autonomous recovery fails, thereby fundamentally improving the system's reliability and maintainability.

[0079] Based on the above embodiments, this application provides a server signal false pull-up prevention system. In the server signal false pull-up prevention system provided in this embodiment, the second controller is specifically used for:

[0080] The falling edge of the target enable signal output by the target voltage regulator during normal operation is detected. If the target enable signal has a first target number of falling edges and is continuously output at a low level within a preset time period, it is determined to be a latching fault.

[0081] In this embodiment, the first target count is 1 or 2. When the enable pin (EN pin) of the target VR is set high, the VR module operates normally and outputs the PG signal.

[0082] If a PG signal is detected to have one falling edge and continuously output a low level within a preset time period, it is determined to be a latch fault, and the VR module is considered to be a latch module. Similarly, if a PG signal is detected to have two falling edges and continuously output a low level within a preset time period, it is determined to be a latch fault, and the VR module is considered to be a latch module.

[0083] After determining that a latching fault has occurred, the second controller M1 sends a reset signal to A1. A1 receives the reset signal and outputs a reset signal to the second output terminal of the first controller. After receiving the reset signal, the second output terminal of the first controller controls the VR module to reset and restart according to the reset signal.

[0084] When the target voltage regulator reset and restart count reaches the preset target number and the target enable signal is low, the output target voltage regulator latch power supply is abnormal.

[0085] In this embodiment, the preset target number of resets is 3. Specifically, if the PG signal returns to normal after the VR module performs the first reset and restart, it indicates that the VR module has also returned to normal. If the PG signal remains low after the VR module performs the first reset and restart, the second controller M1 sends a reset signal to A1 again, and the VR module performs a second reset and restart.

[0086] If the PG signal returns to normal after the VR module performs a second reset and restart, it indicates that the VR module has also returned to normal. If the PG signal remains low after the VR module performs a second reset and restart, the second controller M1 sends a reset signal to A1 again, and the VR module performs a third reset and restart.

[0087] If the PG signal returns to normal after the VR module undergoes a third reset and restart, it indicates that the VR module has also returned to normal. If the PG signal remains low after the VR module undergoes a third reset and restart, it indicates that the output target voltage regulator latch power supply is abnormal. This is considered a power supply abnormality in the VR module, generating an alarm signal and feeding it back to the Baseboard Management Controller (BMC) for fault handling.

[0088] When a falling edge of the PG signal is detected for the first target number and the output remains low, a latching fault is identified, and the VR module is reset and restarted. This approach can accurately distinguish between transient interference and real permanent latching faults, effectively avoiding misjudgments and system malfunctions caused by signal glitches or brief jitters. It ensures the accuracy of fault identification, and triggers subsequent reset or alarm procedures only when necessary, greatly improving the stability of system operation and the reliability of decision-making.

[0089] Based on the above embodiments, this application provides a server signal false pull-up prevention system. In the server signal false pull-up prevention system provided in this embodiment, the second controller is further used for:

[0090] If the target enable signal is detected to have a second falling edge and continuously output a low level within a preset time period, the output target voltage regulator latch power supply is abnormal.

[0091] In this embodiment, the second target count is 3 times or more. If the PG signal is detected to have 3 or more falling edges and continuously output a low level within a preset time period, the output target voltage regulator latch power supply is abnormal, the VR module is considered to be a retry module, the VR module power supply is considered abnormal, and feedback is given to the BMC for fault handling.

[0092] By accurately identifying specific fault modes, the essential differences between intermittent faults and permanent hardware faults can be effectively identified and located. This not only avoids transient interference that may lead to misjudgment by single falling edge detection, but more importantly, it can accurately mark and report truly abnormal modules, thereby enabling rapid diagnosis and precise isolation of system power supply problems and significantly improving system reliability and maintenance efficiency.

[0093] Based on the above embodiments, this application provides a server signal erroneous pull-up system. The pull-up module in this server signal erroneous pull-up system further includes a capacitor, one end of which is connected to a second controller, and the other end of which is grounded. The capacitor is used to filter high-frequency noise in the target enable signal before inputting the noise-reduced target enable signal to the second controller.

[0094] In this embodiment, one end of capacitor C1 is connected to the second controller M1, and the other end of the capacitor is grounded. Capacitor C1 can suppress instantaneous fluctuations in the PG signal, such as glitches when the PG signal transitions, making the PG signal received by the second controller M1 more stable and accurate, and preventing the second controller M1 from misjudging the state of the PG signal, such as misidentifying noise as the falling edge of the PG signal.

[0095] Based on the above embodiments, this application provides a server anti-false signal pull-up system. The logic judgment module in this server anti-false signal pull-up system is any one of a digital comparator, an AND gate circuit, and a logic processor.

[0096] In this embodiment, the logic judgment module can be any one of a digital comparator, an AND gate circuit, and a logic processor.

[0097] This architecture offers great flexibility and scalability, allowing for the free selection of implementation schemes based on performance requirements, cost constraints, and functional complexity in different scenarios. This enables precise optimization of resource allocation and performance while ensuring core decision-making functions are maintained.

[0098] This embodiment provides a server, including a server body and the server anti-signal erroneous pull-up system provided in the above embodiment.

[0099] In this embodiment, the server consists of the server body and the server anti-false signal pull-up system provided in the above embodiment.

[0100] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0101] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0102] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A server anti-signal false pull-up system, characterized in that, The application relates to a power management module, a first controller, a logic judgment module and a pull-up module. The output end of the power management module is electrically connected with the first controller, and the power management module is used for converting standard electricity into controller initialization electricity. The first output end of the first controller is connected with the first signal input end of the logic judgment module, the second output end of the first controller is connected with the second signal input end of the logic judgment module, and the first controller is used for receiving the controller initialization electricity output by the power management module and outputting a low level and an enable signal when it is detected that the first controller initialization is not completed. The output end of the logic judgment module is electrically connected with one end of the pull-up module, the logic judgment module is used for comparing the low level with a threshold level to obtain a first condition judgment result and comparing the enable signal with a fixed signal to obtain a second condition judgment result, and a high level is output when it is detected that the first condition judgment result or the second condition judgment result is not satisfied. The other end of the pull-up module is electrically connected with the output end of the power management module, and the pull-up module is used for turning on a circuit and pulling down an enable pin of a target voltage regulator when a high level is input, so that the false pull-up operation is completed. The controller initialization electricity output by the output end of the power management module comprises a first basic voltage, a second basic voltage and a third basic voltage, the first basic voltage is greater than the second basic voltage, the second basic voltage is greater than the third basic voltage, the other end of the pull-up module is electrically connected with the output end of the power management module and is used for receiving the first basic voltage, and the first basic voltage, the second basic voltage and the third basic voltage are all input into the first controller and are used for completing the initialization of the first controller.

2. The system of claim 1, wherein, The pull-up module comprises a switch resistor, a negative charge type metal oxide semiconductor field effect transistor and a pull-up resistor.

3. The system of claim 2, wherein, The switch resistor is connected with the first basic voltage and the gate level of the negative charge type metal oxide semiconductor field effect transistor respectively, the source level of the negative charge type metal oxide semiconductor field effect transistor is grounded, the drain of the negative charge type metal oxide semiconductor field effect transistor is connected with the enable pin of the target voltage regulator and the pull-up resistor respectively, and the pull-up resistor is connected with the first basic voltage. The first controller is also used for receiving the controller initialization electricity output by the power management module and outputting a high level and an enable signal when it is detected that the first controller initialization is completed.

4. The system of claim 1, wherein, The logic judgment module is also used for comparing the high level with the threshold level to obtain a first condition judgment result, comparing the enable signal with the fixed signal to obtain a second condition judgment result, and outputting a low level when it is detected that the first condition judgment result is satisfied and the second condition judgment result is satisfied. The pull-up module is also used for turning off a circuit and pulling up the enable pin of the target voltage regulator when a low level is input, so that the pull-up operation is completed. ​ ​ 5. The system of claim 3, wherein, The pull-up module further comprises an AND gate part having a first input terminal grounded and connected with an enable pin of the target voltage regulator, and a second controller having an input terminal connected with an output terminal of the AND gate part, and a second input terminal of the AND gate part connected with a second output terminal of the first controller; the second output terminal of the first controller is connected with the enable pin of the target voltage regulator; the second controller is configured to detect a target enable signal output by the target voltage regulator when the target voltage regulator is working normally, and send a reset signal to the AND gate part according to a detection result in a preset time period; the AND gate part is configured to receive the reset signal and output the reset signal to the second output terminal of the first controller, and the reset signal is used to control the target voltage regulator to reset and restart.

6. The system of claim 5, wherein, The second controller is specifically configured to: detect a falling edge of the target enable signal output by the target voltage regulator when the target voltage regulator is working normally, and determine that a latch fault occurs when a first target number of falling edges of the target enable signal are detected in a preset time period and the target enable signal continuously outputs a low level; output a target voltage regulator latch power supply abnormality when the target enable signal is a low level after a number of times of resetting and restarting of the target voltage regulator reaches a preset target number.

7. The system of claim 6, wherein, The second controller is further configured to: output a target voltage regulator latch power supply abnormality when a second target number of falling edges of the target enable signal are detected in a preset time period and the target enable signal continuously outputs a low level.

8. The system of claim 6, wherein, The pull-up module further comprises a capacitor, one end of the capacitor is connected with the second controller, and the other end of the capacitor is grounded, and the capacitor is used to filter high-frequency noise in the target enable signal and input the target enable signal after noise elimination to the second controller.

9. The system of any one of claims 1 to 8, wherein, The logic judgment module is any one of a digital comparator, an AND gate circuit and a logic processor.

10. A server, characterized by The server body and the server false signal pull-up prevention system according to any one of claims 1 to 9 are included.

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