Defective chip screening method, electronic equipment and program product
By fusing wafer spatial information and parameter information through a neural network model and dynamically adjusting the weights, the problems of incomplete information utilization and low screening efficiency in integrated circuit testing are solved, and high-precision chip screening is achieved.
Patent Information
- Application Number
- CN202511729639.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-02-27
AI Technical Summary
In existing integrated circuit testing technologies, the RS algorithm suffers from problems such as incomplete utilization of single-dimensional information, rigid information fusion mechanism, and low screening efficiency during chip screening, making it impossible to achieve high-precision identification of failed chips.
By constructing a neural network model, integrating spatial information on the wafer with chip parameter test information, and dynamically adjusting information weights, adaptive coupling is achieved, thereby improving screening accuracy and efficiency.
It significantly reduces the false negative rate, improves screening accuracy, adapts to different failure modes, supports large-scale real-time screening, and reduces engineering application costs.
Smart Images
Figure CN121580110A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of integrated circuit testing technology, specifically relating to defect chip screening methods for reliability screening (RS) and yield optimization, electronic devices, and program products. Background Technology
[0002] To meet the stringent reliability requirements of integrated circuit manufacturing processes, Reliability Screening (RS) algorithms have become a crucial part of screening potentially failing chips and controlling yield losses before they leave the factory. Currently, the industry primarily utilizes RS algorithm information in two main ways:
[0003] (1) RS algorithm based on spatial information: Represented by traditional clustering algorithms (such as K-Means, DBSCAN) and ZPAT algorithm, this method analyzes the spatial distribution characteristics of chips on the wafer (such as the area where failed chips are clustered) to capture clusters of failures caused by particles in the process. This type of method can determine the probability of potential failed chips being generated around the area, and thus screen out high-risk chips;
[0004] (2) RS method based on parameter information: represented by Cpk (process capability index) and DPAT (dynamic device average test), it achieves screening by calculating the parameter fluctuations of test items (such as the deviation thresholds of voltage and current). It has high interpretability and can capture the numerical correlation between test items. For example, parameter screening based on DPAT can identify failed chips with single test items exceeding the standard, but it cannot capture potential failed chips with "normal parameters but around spatial clusters". Summary of the Invention
[0005] One embodiment of this disclosure discloses a reliability screening method that fuses spatial information and parameter test information, applicable to reliability screening scenarios for consumer-grade chips at advanced process nodes and below. This method couples the spatial location information and electrical parameter information of the chip through a neural network to achieve highly accurate identification of potentially failed chips. It can be directly applied to the chip wafer probe testing stage (CP stage), the final testing stage (FT stage), or multi-stage joint screening. Attached Figure Description
[0006] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:
[0007] Figure 1 A schematic diagram comparing the effects of different defect chip screening methods according to one of the embodiments of this disclosure.
[0008] Figure 2 A schematic diagram of a defect chip screening model structure according to one embodiment of this disclosure. Detailed Implementation
[0009] By analyzing existing defective chip screening algorithms, the following problems can be identified:
[0010] (1) Incomplete use of information
[0011] Existing RS algorithms only use spatial or parametric information in a single dimension, failing to achieve deep coupling between the two types of information, and thus cannot meet the requirements for accurate screening of failed chips.
[0012] (2) Inflexible information fusion mechanism
[0013] Simple OR / AND logic or linear combinations cannot dynamically adjust information weights and have poor adaptability to different failure modes;
[0014] (3) Low screening efficiency
[0015] Traditional combined methods require running a space filtering algorithm first, followed by a parameter filtering algorithm. These two steps take longer than a single method, making it difficult to support large-scale real-time filtering of chips.
[0016] Therefore, this disclosure proposes to construct an RS algorithm based on an adaptive mechanism that couples spatial-parameter information through a neural network, dynamically adjusting the influence of the two types of information on the screening results to solve the problem of real-time screening for high chip reliability. The purpose of this disclosure is to address the shortcomings of existing RS algorithms, such as single-information utilization, rigid fusion, and low efficiency, by solving the following core problems:
[0017] (1) Achieve deep coupling between spatial information on the wafer and parameter test information (including but not limited to: test item Vds / Id, module connectivity, operating frequency) to avoid missed detections caused by single information;
[0018] (2) Design an adaptive fusion mechanism to dynamically adjust based on actual failure modes;
[0019] (3) Improve computational efficiency while ensuring screening accuracy;
[0020] (4) Enables modular reuse of models, eliminating the need for repeated calibration for different chip types and reducing engineering application costs.
[0021] Ultimately, through information fusion driven by neural networks, the RS algorithm can simultaneously meet the requirements of high accuracy and low yield loss in chip screening.
[0022] According to one or more embodiments, a defect chip screening method is provided. This method integrates the spatial information of the chip on the wafer with the test information from chip parameter testing, thereby achieving adaptive coupling. The specific steps are as follows:
[0023] Step 1: Preprocessing and feature alignment of the acquired data. Two types of raw data from the wafer are acquired, including...
[0024] ① Spatial data, namely the coordinates (x, y) of the die on the wafer map and the label of the die (good die / bad die);
[0025] ② Parameter data, including various test parameters of the die (drain voltage Vds, drain current Id, values of other test items, etc.);
[0026] Step 2: Feature extraction is performed using a neural network.
[0027] A neural network model is constructed to extract high-dimensional features of the chip's space and parameters. It should be clarified that while there may be approaches in the industry that first train separate models for spatial information and parameter information, and then perform a posteriori fusion of the judgment results (such as 'good / bad' labels or failure probability values) from the two models, the design logic of this disclosure is completely different. This disclosure does not simply combine the final judgment results of the independent models, but rather, during the feature extraction stage, it directly mines the high-dimensional features of the two types of information through a dual-branch parallel architecture and achieves pre-coupling.
[0028] The spatial feature extraction branch and the parameter feature extraction branch can each independently select machine learning or neural network architectures such as CNN, FCN, and Transformer, depending on the data dimension (e.g., spatial coordinates are two-dimensional features, parameters are multi-dimensional vectors).
[0029] Spatial feature branches (such as using CNN) can capture fine-grained features such as chip local clustering patterns and cross-regional failure correlations layer by layer from the two-dimensional coordinate matrix of the wafer map;
[0030] The parameter feature branch (such as FCN) can map multi-dimensional parameters such as voltage and current into a high-dimensional vector that includes parameter co-fluctuations and the sensitivity of key test items.
[0031] The core of this step is to extract high-dimensional features of both spatial and parametric information through parallel dual-branch extraction. This process preserves the more fundamental and finer-grained correlation details between the two types of information (such as the implicit correlation between chip parameter drift and spatial location in a certain region), avoiding the loss of details caused by the information being compressed into "judgment results" when fusing results from independent models. This lays a more accurate feature foundation for subsequent dynamic fusion of multimodal information (such as adjusting feature weights based on abnormal patterns).
[0032] Step 3: Adaptively adjust the weights of the dynamic fusion layer.
[0033] Machine learning methods (including but not limited to attention mechanisms, meta-learners, etc.) are used as the fusion layer. The core principle is to drive weight allocation based on the confidence of the actual abnormal patterns of the chip. First, the matching degree between the space, parameter features and failure modes (i.e., the anomaly confidence) is quantified, and then higher weights are assigned to features with high confidence to ensure that the screening decision fits the actual anomaly type.
[0034] Specific implementation examples: If an attention mechanism is used, weights are generated by calculating the similarity between spatial / parameter features and failure mode templates (e.g., spatial features match cluster failure templates, and weights are prioritized); if a meta-learner is used, cross-scenario adjustment rules are pre-learned, and weights are directly adapted based on the initial features of the chip to be screened (e.g., whether there are spatial cluster failures).
[0035] The weight adjustment strictly corresponds to the abnormal mode: when spatial cluster failure (such as failure in the lithographic deviation region), the spatial feature confidence is high and the weight ratio is higher; when parameter out-of-tolerance failure (such as discrete electrical performance), the parameter feature confidence is high and the weight ratio is higher; when mixed failure (cluster + parameter anomaly), the weight is allocated according to the confidence ratio of the two.
[0036] The adjustment follows three main strategic principles: First, confidence is prioritized, with no fixed proportions preset, and the weights are strongly correlated with abnormal features; second, dynamic threshold constraints (the upper and lower limits of the weights are learned by the model, not manually set) are used to avoid ignoring key information by giving too high a weight to a single feature; and third, closed-loop iteration is used to optimize the weights in real time based on the feedback from the screening accuracy to ensure adaptability.
[0037] Step 4: Select and train the model.
[0038] With the goal of minimizing the false negative rate while controlling the false positive rate (i.e. reducing yield loss), a labeled dataset (including but not limited to wafer spatial parameter-test parameter data, actual screening results (good / bad chips)) is used for training.
[0039] Step 5: RS algorithm screening application.
[0040] Deploying the trained model to the chip testing process specifically includes:
[0041] (1) Input the spatial data and parameter data to be filtered in real time;
[0042] (2) The model outputs the probability of each chip being faulty through “preprocessing → feature extraction → dynamic fusion”;
[0043] (3) For chips with an automatic screening probability ≥ the set threshold, generate a screening report (including the location of the failed chip, the type of abnormality (determined by the weight ratio of the dynamic fusion layer), and the yield loss rate).
[0044] In this disclosure, several improvements are proposed to the existing defect chip screening scheme, specifically including:
[0045] (1) The spatial-parameter data of the chip wafer was integrated and applied. The features of the two types of data, spatial data and test parameter data of the chip, were extracted through various machine learning methods to achieve coupling of the two types of data and solve the problem of missed detection in traditional single data information methods;
[0046] (2) Dynamically adjust the weights of various data to be integrated. Based on the actual abnormal mode of the chip (spatial cluster or parameter abnormality), calculate the weights through the abnormal confidence level instead of fixed weights to improve the screening adaptability in different scenarios.
[0047] (3) A modular feature extraction architecture is adopted, that is, the spatial and parameter branches are independent and reusable, which supports rapid adaptation to different chip types and different test scenarios, reducing engineering application costs.
[0048] The beneficial effects achieved by the embodiments disclosed herein include:
[0049] 1. By fusing wafer space-parameter information, the false negative rate is significantly reduced compared to traditional single-information methods. Although the specific reduction in false negative rate varies depending on the test scenario, the actual screening accuracy is significantly improved.
[0050] 2. This disclosure adopts a dynamic fusion layer, which adjusts information weights according to specific circumstances without manual intervention, and has strong dynamic adaptability:
[0051] 3. The chip screening algorithm disclosed herein has high computational efficiency, enabling large-scale real-time screening of chips;
[0052] 4. The solution implemented in this disclosure has good robustness and reusability, and is adaptable to different chip types.
[0053] According to one or more embodiments, a defect chip screening method based on the fusion of wafer chip spatial information and parameter test information includes the following steps:
[0054] Step 1: Data Acquisition and Preprocessing.
[0055] Select several batches of wafers according to the screening requirements (batch size and number of wafers will be adjusted according to the mass production plan or testing objectives).
[0056] By using various wafer testing equipment, obtain the spatial location information and initial status labels (good die / bad die) of the chips (dies) on the wafer; the labels may come from preliminary functional tests, appearance inspection results, etc.
[0057] Test data for each die is collected using the corresponding testing equipment (CP probe tester, FT finished product tester, special reliability test equipment, etc.) for the corresponding testing stage.
[0058] Spatial data undergoes format conversion, parameter data is noise-processed and standardized, and time-series data (such as parameter variation trends of multiple batches of wafers) and environmental data (such as test temperature and humidity) are collected and standardized. The specific preprocessing strategy is adjusted according to the data type and model input requirements.
[0059] Step 2: Construct a neural network model. Build a modular neural network that includes a "spatial feature extraction branch + parameter feature extraction branch + dynamic fusion layer" and flexibly select the architecture of each branch.
[0060] A sample annotation dataset covering multiple scenarios is used. Data sources include: historical wafer data of different chip types / process nodes, manually annotated failed chip data, real failure data after reliability testing and verification, and simulated extreme failure scenario data. The ratio of training set to validation set is adjusted according to the amount of data and scenario coverage.
[0061] After training, the model meets the preset indicators for specific application scenarios, such as false negative rate, false positive rate, and computation time (the indicator thresholds are set according to the reliability level of the application scenario, such as false negative rate ≤5%, false positive rate ≤3%, and single wafer processing time ≤ the preset time for scenario adaptation).
[0062] Step 3: Calibrate and select the trained model for application.
[0063] Based on the characteristics of the current screening scenario, select calibration data, and adapt the model to the current scenario by fine-tuning the model parameters or model transfer learning.
[0064] Dies with a failure probability greater than or equal to a preset threshold are marked as "potentially failed dies to be removed";
[0065] Generate a screening report, including: spatial distribution of failed chips, anomaly type, single / multi-batch yield loss statistics, model screening accuracy feedback, etc.
[0066] The effectiveness of the screening is verified by sampling and actual testing (such as functional retesting and reliability aging tests), ensuring that the screening accuracy meets the preset standards and that the yield loss is controlled within the acceptable range for mass production.
[0067] The core of this disclosure lies in achieving dynamic coupling between wafer space information and chip parameter information through a neural network, making it applicable to reliability screening scenarios across all chip types, process nodes, and testing phases. Therefore, this disclosure covers the following typical scenarios, and these scenarios can be combined in various ways, including:
[0068] The chip types include consumer-grade / industrial-grade / automotive-grade logic chips, memory chips (NAND Flash / DRAM / eMMC), RF chips, analog chips (power management / signal chain), sensor chips, etc.
[0069] The process nodes are mature process nodes (such as 90nm, 55nm, 40nm) and advanced process nodes (such as 28nm, 12nm, 7nm, 5nm and below).
[0070] The testing phases of the application include: early reliability screening through wafer probe testing (CP phase), final product screening through final testing (FT phase), or multi-stage joint screening;
[0071] The target chip failure modes include: spatial cluster failure (such as regional failure caused by process particles), parameter abnormality failure (such as abnormal electrical / timing parameters), timing-environment related failure (such as batch process drift, test temperature fluctuation, etc.), and mixed failure (multiple failure modes superimposed).
[0072] Figure 1 shows a comparison of the screening performance of the existing RS algorithm and the method disclosed in this paper on a wafer map. The chips (die) with red boundaries represent RMAs (Return Material Authorizations, referring to chips returned by customers after actual failure). Specifically, (a) the method involving only spatial information has a high false positive rate and misses dies with abnormal parameters (spatial dispersion); (b) the method involving only parameter information completely ignores cluster information, missing RMA dies near the cluster; (c) the method disclosed in this paper has relatively low false positive and false negative rates, and finds the most RMAs. The abbreviations in the figure include:
[0073] Safe die — security chip
[0074] Uncertain die — an uncertain chip
[0075] Risky die — a chip prone to risk.
[0076] Fail die — a defective chip.
[0077] Found RMA – RMAs that can be detected early
[0078] Missed RMA
[0079] RMA (Return Merchandise Authorization) usually refers to the authorization of returns, and in the semiconductor industry, it often refers to returned defective or defective chips.
[0080] like Figure 2 As shown, the model calculation flowchart includes the following steps: 1. Collect wafer space / parameter data → 2. Data standardization and feature alignment → 3. Extract features through two branches → 4. Dynamically fuse and calculate weights → 5. Output bad die probability and screening results → 6. Calibrate the model based on specific application data (such as RMA data).
[0081] First, a spatial distribution map of the chips (dies) and corresponding test parameter data are acquired from the wafer under test. Two key sets of information are extracted from the obtained data: spatial information and parameter information. Spatial information includes the chip's position coordinates (x, y) on the wafer map, while parameter information involves the chip's electrical parameter test results, such as drain voltage Vds and drain current Id. The screening model includes spatial branches and parameter branches, as well as a dynamic fusion layer. The spatial branch uses methods such as convolutional neural networks (CNNs) to extract spatial features from the spatial information, while the parameter branch uses fully connected networks (FCNs) or other models suitable for processing multidimensional data to extract parameter features from the parameter information. The features extracted from both branches are fed into the dynamic fusion layer. The dynamic fusion layer uses advanced machine learning methods (such as attention mechanisms or meta-learners) to dynamically adjust the weights of the spatial and parameter information based on the chip's actual anomaly patterns. The information processed by the dynamic fusion layer is used to generate the failure probability of each chip. Based on a set threshold, it can be determined whether a chip is a potential failure chip, and a screening report is generated.
[0082] The screening report in the output is not only used for direct screening decisions, but also provides feedback for continuous model calibration and optimization. By comparing the actual screening results with subsequent reliability test results, model parameters can be further adjusted to improve the accuracy of the next screening.
[0083] Furthermore, this disclosure provides several different solutions for the dynamic fusion of spatial-parameter information driven by neural networks for different application scenarios, specifically including:
[0084] (1) Simple combination and fusion scheme
[0085] The core of this scheme is to use logical AND / OR or linear combinations to simply fuse spatial and parameter information, which can be used in situations with relatively little information and simple coupling. Specifically:
[0086] ① OR logic: For the same chip, first use the RS algorithm based on spatial information (such as using K-Means to identify whether it is in the failure cluster region) and the RS algorithm based on parameter information (such as using Cpk to determine whether its electrical parameters exceed the standard) to make a judgment. If either algorithm determines that the chip is "bad", the chip is directly screened out.
[0087] ② AND logic: Similarly, the chip is first determined by the two algorithms in ① above. Only when both algorithms determine that the chip is "bad" is it filtered out.
[0088] ③ Linear combination: Pre-set fixed weights for spatial information algorithm and parameter information algorithm (e.g., spatial weight 0.5, parameter weight 0.5), add the "probability value of chip being bad" output by the two algorithms according to the weights, and then determine whether to screen out based on the comparison between the total probability after addition and the preset threshold (e.g., 0.8).
[0089] (2) Multi-dimensional fusion scheme of time-series and environmental information
[0090] The core of this solution is to overcome the limitations of static, two-dimensional information from a single wafer by incorporating the time-dimensional process evolution patterns and environmental-dimensional testing interference factors into a fusion framework. This multi-dimensional information complementarity eliminates screening bias.
[0091] Timing information refers to the spatial-parameter variation trend of multiple batches of wafers (such as the drift amplitude of a certain test parameter in 5 consecutive batches of wafers, the migration pattern of the location of failure clusters). Its essence is to reflect the process stability. In chip manufacturing, process parameters such as photolithography precision and ion implantation dose will drift slightly with production time. Single-batch spatial-parameter information cannot capture such dynamic changes, while timing information can quantify the degree of process drift between batches, avoiding the outdated screening criteria caused by process drift (such as the qualification threshold of a certain parameter needs to be lowered due to process drift, but it is not reflected in the single-batch data, resulting in missed detection).
[0092] Environmental information refers to external conditions such as temperature, humidity, and voltage fluctuations of the test equipment during chip testing. Its essence is to isolate environmental interference from inherent chip defects. The parameter test results of the same chip may differ under different environments (e.g., leakage current parameters are prone to exceed the standard at high temperatures). If only parameter values are relied upon for judgment, false anomalies caused by environmental interference may be misjudged as inherent chip defects. Environmental information can be used to establish an environment-parameter correlation model (e.g., for every 5°C increase in temperature, the leakage current threshold needs to be increased by 10%) to calibrate parameter test results and eliminate the interference of environmental fluctuations on screening.
[0093] The application value refers to solving the screening deviation problem of traditional two-dimensional solutions under "multi-batch process drift and complex testing environment" through the multi-dimensional integration of "space + parameters + time sequence + environment", and adapting to the scenario of long-term continuous screening and multiple testing environment switching (such as laboratory and mass production workshop) in the mass production stage.
[0094] (3) Failure physical model-driven fusion scheme
[0095] The core of this solution is to break away from the reliance of data-driven models on large-scale labeled data. It constructs fusion rules based on the physical mechanisms of chip failure (such as electromigration, hot carrier injection, and oxide layer breakdown) to achieve accurate screening in unlabeled data scenarios. The principle behind this solution is...
[0096] Chip failures do not occur randomly, but follow specific physical laws (such as "electromigration failure," which is atomic migration caused by electron flow impacts in metal interconnects, and its failure probability is exponentially related to current density and temperature). This approach first establishes a correlation between spatial information, parameter information, and physical failure mechanisms through a failure physics model. For example, for hot carrier injection failure, the physical model clearly identifies excessively high drain voltage (Vds) and excessively large channel current (Id) as the core causes, and such failed chips are often spatially concentrated at the wafer edge (where heat dissipation is poor and the temperature is higher). Based on this, the fusion rule can be set to determine a high-risk failed chip when the chip's Vds / Id parameter exceeds the physical threshold and is located in the wafer edge spatial region, without relying on historical failure data to train the model.
[0097] Application value: Solving the "cold start" problem of data-driven solutions - For newly developed chips (without historical failure data), small-batch trial production chips (with limited labeled data), or special failure modes (extreme failures that have not appeared in historical data), there is no need to wait for labeled data to accumulate. Fusion rules can be directly built based on known physical mechanisms to quickly implement and screen applications.
[0098] It should be understood that in the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0099] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this disclosure, and these modifications or substitutions should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for screening defective chips, characterized in that, By constructing a defect chip screening model, high-risk defect chips are identified.
2. The method according to claim 1, characterized in that, The model selection method includes: First, spatial distribution data of the chips and electrical test parameter data of the corresponding chips are collected from the wafer to be tested and input into the screening model. The spatial branch and parameter branch of the screening model extract the spatial features and parameter features of the chip from the obtained data, respectively. Chip space features and parameter features are fed into the dynamic fusion layer of the screening model, whereby the dynamic fusion layer fuses the chip space features and parameter features. The failure probability of the chip is calculated based on the features processed by the dynamic fusion layer. Based on the set threshold, determine whether a chip is a potential failure chip and generate a screening report.
3. The method according to claim 2, characterized in that, The dynamic fusion layer performs fusion processing on chip space features and parameter features through logical OR / AND.
4. The method according to claim 2, characterized in that, The dynamic fusion layer performs fusion processing on chip space features and parameter features through linear combination.
5. The method according to claim 2, characterized in that, When fusing chip spatial features and parametric features, the dynamic fusion layer dynamically adjusts the weights of spatial features and parametric features based on the confidence level of the chip's abnormal patterns.
6. The method according to claim 2, characterized in that, The dynamic fusion layer of the screening model is based on machine learning.
7. The method according to claim 2, characterized in that, A spatial feature extraction model based on neural networks and a parametric feature extraction model based on neural networks are constructed. High-dimensional spatial features and parametric features of the chip are extracted through spatial branches and parametric branches.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method as described in any one of claims 1 to 7.
9. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.
10. A computer program product, comprising a computer program, characterized in that, The computer program is executed by a processor to implement the method according to any one of claims 1 to 7.