Large-area AI embedded computing system and glass panel level integrated packaging method

Abstract

The invention discloses a large-area AI embedded computing system, and relates to the technical field of semiconductor packaging, the system comprises a sensing layer, a computing layer and a facility function layer which are sequentially stacked from top to bottom, and the sensing layer is used for receiving incident light to be detected and generating a sensing signal; the calculation layer is used for carrying out data processing on the sensing signal and outputting data, and the facility layer is used for providing energy and communication support for the system; each functional layer is independently arranged on the glass panel, an optical waveguide path and / or a vertical conductive path are / is arranged in the glass panel, and optical I / O chips are integrated among the layers and are packaged through three-dimensional stacking to form an interlayer optical interconnection network and realize electrical and optical collaborative interconnection, so that high-speed and low-power photoelectric data transmission is realized; the computing system can remarkably reduce stray capacitance and signal loss, improve heat dissipation efficiency and packaging reliability, simplify the manufacturing process and reduce cost, and is suitable for high-computing-power and large-area AI embedded computing application scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a large-area AI embedded computing system and a glass panel level integrated packaging method. BACKGROUND

[0002] With the rapid development of emerging technologies such as artificial intelligence (AI), Internet of Things (IoT), and augmented / virtual reality (AR / VR), computing systems are evolving towards large area, high pixel density, low power consumption, and embedded AI function integration, requiring the implementation of multi-chip, multi-functional collaborative optimization on the same packaging platform.

[0003] However, traditional silicon-based semiconductor packaging has gradually encountered the slowdown of Moore's Law and system-level performance bottlenecks: continuous increase in chip size, improvement in computing frequency, simultaneous growth in high-speed signal transmission and thermal management requirements, making it difficult for traditional packaging structures to balance high computing power, low power consumption, and reliability.

[0004] In recent years, the industry has proposed new technologies such as glass panel level packaging (PLP) and three-dimensional stacked packaging, attempting to utilize the insulating properties, low parasitic capacitance, and large area characteristics of glass substrates to achieve high-density integration of multi-chip modules; as a vertical interconnection structure that penetrates the glass substrate, the Through Glass Via (TGV) can effectively reduce parasitic capacitance and improve high-frequency signal transmission capability compared to the Through Silicon Via (TSV); panel level packaging, inspired by display panel manufacturing, achieves efficient packaging of multiple chips and multiple passive devices through fan-out wiring, promising a balance between cost and integration.

[0005] Despite the progress made by the above technologies, existing advanced packaging solutions still have obvious shortcomings. With the existing silicon interposer packaging structure, while improving the wiring density, there is still a problem of high parasitic capacitance (about 50 fF or more) of the silicon interposer, resulting in significant signal loss during high-frequency operation, limiting AI computing power output; the existing combination of silicon-based and optical glass substrates, while achieving logic chip stacking, has a large difference in thermal expansion coefficient between the silicon substrate (CTE≈2.6 ppm / ℃) and the optical glass substrate (CTE≈7 ppm / ℃), and the bonding interface is prone to failure after thermal cycling; in addition, OLED display modules combine high thermal conductivity metal plates with low thermal conductivity polymer layers to achieve heat dissipation and shock absorption, but in high power density scenarios (>3W), the surface or junction temperature may still exceed 150℃, and device performance may degrade; obviously, the difference in material thermophysical properties and insufficient heat dissipation have become a core obstacle to the improvement of three-dimensional integration reliability.

[0006] In addition, the current through-silicon via (TSV) packaging structure is still limited by signal transmission performance at high integration: high parasitic capacitance of silicon interposer causes high-frequency signal distortion, bandwidth reduction, directly affecting AI inference response; thermal reliability aspect of the coefficient of thermal expansion mismatch between silicon, glass and organic materials (such as Cu vs SiLK) causes interface cracks, bond peeling; and the low thermal conductivity of the organic layer causes rapid temperature rise under high power, inducing frequency reduction or device failure. At the same time, the complex multi-layer process and material combination also push up the manufacturing cost, and the process cost per square centimeter is too high, which restricts its popularization in large-area, low-cost commercial scenarios.

[0007] The prior art at least has the following technical problems: first, high-frequency signal transmission is still limited by parasitic capacitance and transmission loss, which is difficult to meet the demand of large computing power AI system; second, the reliability problem caused by low heat dissipation efficiency and multi-material thermal expansion mismatch has not been effectively solved; third, the complex manufacturing process and high cost per unit area limit the popularization of glass panel level packaging in large-scale commercialization.

[0008] In summary, it is found that the prior art at least has the following technical problems: In the existing packaging technology, there are technical problems of high-frequency signal transmission still being limited by parasitic capacitance and transmission loss, low heat dissipation efficiency, low reliability caused by multi-material thermal expansion mismatch, and high packaging cost caused by complex manufacturing process. SUMMARY

[0009] The purpose of the present application is to provide a large-area AI embedded computing system and a glass panel level integrated packaging method to solve the technical problems of high-frequency signal transmission still being limited by parasitic capacitance and transmission loss, low heat dissipation efficiency, low reliability caused by multi-material thermal expansion mismatch, and high packaging cost caused by complex manufacturing process in the existing packaging technology.

[0010] The technical effects of the preferred technical solutions among the many technical solutions provided by the present application are described in detail below.

[0011] In order to solve the above technical problems, the present application provides the following technical solutions: The application provides a large-area AI embedded computing system, which comprises a perception layer, a computing layer and a facility layer arranged in a top-down manner, the perception layer is used for receiving incident light to be detected and generating a perception signal, the perception signal enters the computing layer for data processing and outputs data, the facility layer supports the working of the perception layer and the computing layer through photoelectric interconnection, accepts the data output by the computing layer and transmits the data to external equipment; the perception layer, the computing layer and the facility layer are independently provided with glass panels, light wave guide channels and / or vertical conductive channels are arranged in the glass panels, light I / O chips are integrated between the layers, and the layers are packaged through three-dimensional stacking to form an interlayer optical interconnection network for electrical and optical interconnection, so that high-speed and low-power photoelectric collaborative data transmission is realized.

[0012] In one embodiment, the perception layer comprises an absorber and a detector; the absorber is laid on the matrix detection unit to receive light to be detected; a plurality of detectors are laid on the glass panel of the perception layer in a matrix manner to form a matrix detection unit, the matrix detection unit is interconnected with the absorber to amplify and convert the incident light signal into the perception signal in the form of an electrical signal, the perception signal is transmitted in the form of optical conduction to the light I / O chip between the computing layer and the perception layer through the interlayer optical interconnection network, and the light I / O chip performs photoelectric conversion and module communication of the computing layer.

[0013] In one embodiment, the computing layer comprises a computing chip set composed of an AI-FPGA module, a CPU module and a GPU module; the computing chip set is connected with the light I / O chip between the computing layer and the perception layer and the computing layer and the facility layer, and is used for optical and electrical communication connection of the computing layer, the perception layer and the facility layer; the computing chip set of the computing layer receives instructions of the facility layer and perception signals of the perception layer through the light I / O chip between the layers, is used for real-time data processing, machine learning inference and algorithm acceleration, and completes high-speed optical signal communication and photoelectric conversion between the layers through the light I / O chip.

[0014] In one embodiment, the facility layer comprises a power management module, a micro battery, a storage chip and a high-speed interface module; the micro battery is arranged in a battery cavity of the glass panel of the facility layer and is electrically connected with the power management module, the storage chip and the high-speed interface module, the high-speed interface module is connected and communicated with the storage chip, the light I / O chip between the computing layer and the facility layer and external equipment to be accessed; the battery cavity is formed by dry etching, the micro battery is embedded in the battery cavity, and the micro battery is packaged in the facility layer by covering a nickel sealing sheet on the top of the battery cavity.

[0015] In one embodiment, the battery cavity depth is 250-350 μm; the micro battery is a solid-state thin film lithium battery with a thickness of 180-280 μm and an energy density of 350 Wh / L; a nickel sealing sheet is covered on the top of the battery cavity, and the nickel sealing sheet is fused with the glass panel around the battery cavity through nickel-glass laser ring welding, so as to achieve a very short power supply path for auxiliary reduction of the resistance of the power supply path.

[0016] In one embodiment, a PMIC chip is embedded on the glass panel of the facility layer, and the PMIC chip is electrically connected with the micro battery and the power management module, so as to achieve dynamic voltage regulation of 0.8 V to -1.2 V for the power management module to perform module-level dynamic power scheduling.

[0017] In one embodiment, a glass via hole with an aperture of ≤10 μm is formed on the glass panel, a Ti / Cu composite seed layer is deposited in the hole wall, and copper is filled in the glass via hole in an electroplating manner to form the vertical conductive path; the optical waveguide path is arranged in a region within 15 μm of the structural periphery of the glass via hole, and the optical waveguide path is a silicon nitride optical waveguide, which is used to reduce electromagnetic crosstalk and reduce optical loss; a TGV pad is arranged at the glass via hole, and the optical I / O chip is flip-chip bonded to the TGV pad, the optical I / O chip senses the optical communication information of the silicon nitride optical waveguide and converts it into an electrical signal, and forms an electrical communication through the vertical conductive path, which is used to realize high-speed optical-electrical signal conversion.

[0018] In one embodiment, a flexible film layer is bonded to the surface of the glass panel through thermal compression bonding, and the flexible film layer is a polyimide flexible interlayer; a Cu / Ni / Au multilayer wiring is constructed on the flexible film layer between the glass panel of the computing layer and the computing chip set, and the electrical signals of the computing chip set and the optical I / O chip are transmitted through the Cu / Ni / Au multilayer wiring.

[0019] A glass panel level integrated packaging method is also provided, which includes a large-area AI embedded computing system and comprises the following steps: (1) preparing optical waveguide paths and vertical conductive paths on a multilayer glass panel; (2) preparing functional panels of a sensing layer, a computing layer and a facility layer; including preparing absorbers and detectors for the sensing layer, preparing computing chip sets and optical I / O chips for the computing layer, preparing a power management module, a battery cavity, a storage chip and a high-speed interface module for the facility layer; (3) using high-precision alignment and 3D hybrid bonding process to stack the sensing layer, the computing layer and the facility layer in sequence to realize optical-electrical integrated interconnection; (4) after glass-glass thermal compression bonding, embedding a micro battery in the battery cavity of the facility layer and welding a nickel sealing sheet to the battery cavity through nickel-glass laser ring welding to form a packaging structure.

[0020] In one embodiment, the 3D hybrid bonding process includes two stages of low-temperature bonding and high-temperature annealing: a low-temperature bonding stage, at a temperature of ≤ 250℃, the respective glass panels of the perception layer, the calculation layer and the facility layer are first subjected to hot-press bonding of the glass panel and the flexible film, then the optical I / O chip is welded, and finally the packaged optical waveguide channel and the optical I / O chip are cured using a low-temperature curing epoxy resin; a high-temperature annealing stage, at a temperature of ≥ 300℃, the glass via is annealed in an H2 atmosphere to repair the electroplating defects and reduce the resistivity, and the calculation chip set is selectively annealed by infrared laser to avoid thermal damage to the packaged optoelectronic devices.

[0021] The large-area AI embedded computing system provided by the application has the following remarkable beneficial effects compared with the existing silicon-based or organic packaging structure: (1) Significantly reduce signal transmission loss and parasitic capacitance, improve high-speed interconnection performance The optical waveguide and the vertical conductive channel (Through Glass Via, TGV) are integrated in the glass panel to construct an interlayer optical interconnection network, replacing the traditional metal wiring method. The glass material has low dielectric constant and excellent electrical insulation properties, which can effectively reduce parasitic capacitance and electromagnetic crosstalk; at the same time, the high-speed conversion of optical signals and electrical signals between layers is realized through the optical I / O chip, so that the high-frequency data transmission loss is significantly reduced, the system bandwidth is significantly improved, and the application requirements of AI high computing power and high response are met.

[0022] (2) Improve heat dissipation efficiency and packaging reliability The functional layers of the perception layer, the calculation layer and the facility layer are distributed on independent glass panels, and the space is layered by three-dimensional stacking; the thermal conductivity of the glass panel is better than that of the traditional organic carrier, and the thermal expansion coefficient is close to that of the optoelectronic chip material, which can effectively alleviate the problem of thermal stress concentration and interface peeling; The layered packaging structure also facilitates the integration of micro-channel cooling, thermal diffusion layer or metal film heat sink, reduces the overall packaging thermal resistance and maintains temperature balance, thereby improving the long-term reliability of the system.

[0023] (3) Realize the three-dimensional packaging structure of optical and electrical cooperation, improve the system integration The structure design of the optical I / O chip combined with the three-dimensional stacked packaging realizes the optical and electrical dual-channel interconnection between layers, forming a collaborative operation network of perception, calculation and output. This architecture enables the perception layer, the calculation layer and the facility layer to work efficiently in a single system, supports the integrated operation of large-area array sensing and AI inference calculation, and improves the system modularity and functional expansion capability.

[0024] (4) Reducing manufacturing complexity and cost, improving process compatibility The glass panel adopts a panel-level processing technology, and multiple functional modules can be simultaneously manufactured on a large-size substrate; compared with a silicon interposer or an organic multilayer board, the glass material has low process temperature, low cost and high dimensional stability, and is suitable for large-area production; in the three-dimensional stacked packaging process, the interposer and the complex wiring structure are reduced, and the packaging process steps are reduced by about 30%, thereby significantly reducing the manufacturing cost and improving the yield.

[0025] In summary, the AI embedded computing system with high bandwidth, low power consumption, high heat dissipation efficiency and low cost compatibility is realized through the glass panel-level optoelectronic interconnection and three-dimensional stacked structure, which can meet the application requirements of future high computing power, large-area integration and high-frequency working scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0027] Fig. 1 is the integrated structure schematic diagram of the large-area AI embedded computing system of the present application; Fig. 2 is the top view structure schematic diagram of the computing layer of the present application; Fig. 3 is the top view structure schematic diagram of the facility layer of the present application.

[0028] Among them, the reference signs are as follows: 1, perception layer; 11, absorber; 12, detector; 2, computing layer; 21, computing chip set; 211, AI-FPGA module; 212, CPU module; 213, GPU module; 3, facility layer; 31, power management module; 32, micro battery; 33, storage chip; 34, high-speed interface module; 35, battery cavity; 4, optical interconnection network; 41, optical waveguide channel; 5, vertical conductive channel; 51, glass via hole; 52, TGV pad; 6, optical I / O chip; 7, glass panel; 8, PMIC chip. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0030] The specific embodiment provides a large-area AI embedded computing system and a glass panel level packaging method. The system comprises functional layers of perception, calculation and facilities arranged in a stack from top to bottom. The perception layer is used for accepting light rays to be detected and generating a perception signal. The calculation layer is used for data processing of the perception signal and outputting data. The facility layer is used for providing energy and communication support for the system. Each functional layer is independently arranged on a glass panel. The glass panel is provided with an optical waveguide channel and / or a vertical conductive channel. An optical I / O chip is integrated between each layer and packaged through three-dimensional stacking to form an interlayer optical interconnection network, realize collaborative interconnection of electrical properties and optics, and realize high-speed and low-power optical and electrical data transmission. The computing system can significantly reduce parasitic capacitance and signal loss, improve heat dissipation efficiency and packaging reliability, simplify manufacturing process and reduce cost, and is suitable for high-bandwidth, high-computing-power and large-area AI embedded computing application scenarios. The technical problems of existing packaging technology, such as high-frequency signal transmission still being limited by parasitic capacitance and transmission loss, low heat dissipation efficiency, low reliability caused by thermal expansion mismatch of multiple materials, and high packaging cost caused by complex manufacturing process, are effectively solved.

[0031] The first embodiment of the large-area AI embedded computing system is shown in Figs. 1-3 The first embodiment of the large-area AI embedded computing system is shown in

[0032] Specifically, the large-area AI embedded computing system realizes the optical and electrical collaborative interconnection and communication between the perception layer 1, the computing layer 2 and the facility layer 3 by independently arranging the glass panel 7 structure in the three layers and forming the optical waveguide channel 41 and the vertical conductive channel 5 in the glass panel 7. Compared with the existing silicon-based or organic packaging structure, the system has multiple technical advantages: significantly reducing signal transmission loss and parasitic capacitance, and improving high-speed interconnection performance; integrating the optical waveguide and the vertical conductive channel 5 (Through Glass Via, TGV) in the glass panel 7 to build an interlayer optical interconnection network 4, replacing the traditional metal wiring method. The glass material has low dielectric constant and excellent electrical insulation properties, which can effectively reduce parasitic capacitance and electromagnetic crosstalk; at the same time, the high-speed conversion of optical signals and electrical signals between layers is realized through the optical I / O chip 6, which significantly reduces the high-frequency data transmission loss and significantly improves the system bandwidth, meeting the application requirements of AI high computing power and high response.

[0033] Improving heat dissipation efficiency and packaging reliability; the functional layers of the perception layer 1, the computing layer 2 and the facility layer 3 are distributed on independent glass panels 7, and space layering heat dissipation is realized through three-dimensional stacking; the thermal conductivity of the glass panel 7 is better than that of the traditional organic carrier, and the thermal expansion coefficient is close to that of the optoelectronic chip material, which can effectively alleviate the problem of thermal stress concentration and interface peeling; and the layered packaging structure also facilitates the integration of micro-channel cooling, thermal diffusion layer or metal film heat sink, reducing the overall packaging thermal resistance and maintaining temperature balance, thereby improving the long-term reliability of the system.

[0034] Realizing the three-dimensional packaging structure of optical and electrical collaboration, improving the system integration; the structure design of combining the optical I / O chip 6 with three-dimensional stacked packaging realizes optical and electrical dual-channel interconnection between layers, forming a collaborative operation network of perception, calculation and output. This architecture enables the perception layer 1, the computing layer 2 and the facility layer 3 to work efficiently in a single system, supports the integrated operation of large-area arrayed sensing and AI inference calculation, and improves the system modularity and functional expansion capability.

[0035] Reducing manufacturing complexity and cost, improving process compatibility; the glass panel 7 adopts panel-level processing technology, which can manufacture multiple functional modules on a large-size substrate at the same time; compared with the silicon interlayer or organic multilayer board, the glass material has low processing temperature, low cost and high dimensional stability, which is suitable for large-area production; in the three-dimensional stacked packaging process, the interlayer and complex wiring structure are reduced, and the packaging process steps are reduced by about 30%, significantly reducing the manufacturing cost and improving the yield.

[0036] In summary, through the glass panel 7 level optical and electrical interconnection and three-dimensional stacking structure, an AI embedded computing system with high bandwidth, low power consumption, high heat dissipation efficiency and low cost compatibility is realized, which can meet the application requirements of future high computing power, large-area integration and high-frequency working scenarios.

[0037] As one of the optional embodiments: The specific structure of the sensing layer 1 is shown in the following embodiment: Figs. 1-3 As shown in the figure, the sensing layer 1 includes an absorber 11 and a detector 12; the absorber 11 is laid on the matrix detection unit to receive the light to be detected; a plurality of detectors 12 are laid on the glass panel 7 of the sensing layer 1 in a matrix manner to form a matrix detection unit, the matrix detection unit is interconnected with the absorber 11 to amplify the incident light signal and convert it into an electrical signal form of sensing signal, the sensing signal is transmitted in the form of optical conduction to the optical I / O chip 6 between the sensing layer 1 and the computing layer 2 through the interlayer optical interconnection network 4, and the optical I / O chip 6 performs photoelectric conversion and module communication with the computing layer 2.

[0038] Among them, the matrix detection unit is a TFT photoelectric array manufactured on the glass panel 7 by using a back-illuminated etching process, and the absorber 11 is a grating enhancement unit constructed by using a microlens lithography process, which amplifies the incident light signal to improve the collection efficiency.

[0039] In application, the absorber 11 in the sensing layer 1 efficiently absorbs and amplifies the light signal of different wavelengths under the irradiation of incident light, and the matrix detector 12 array below responds to the change of light intensity in real time to generate corresponding electrical signals; the absorber 11 and the matrix detection unit are optically interconnected to amplify the light signal and convert it into an electrical signal form of sensing signal, and the sensing signal is transmitted in the form of optical signal to the optical I / O chip 6 through the interlayer optical interconnection network 4; after the photoelectric conversion of the optical I / O chip 6, the sensing data is transmitted to the corresponding module of the computing layer 2 to realize high-speed and low-delay data reading.

[0040] This structure can realize large-area and high-pixel-density light signal collection and real-time sensing, solve the problem of limited collection range and high response delay of traditional silicon-based sensing units; at the same time, the transmission noise and power consumption are reduced through optical signal transmission, and the signal-to-noise ratio and overall computing response speed of the system are improved.

[0041] In addition, the detection matrix can also adopt a stacked photodetector array structure to realize multi-spectral imaging or depth imaging function.

[0042] The specific structure of the computing layer 2 is shown in the following embodiment: Figs. 1-3As shown, the computing layer 2 includes a computing chip set 21 composed of an AI-FPGA module 211, a CPU module 212, and a GPU module 213; the computing chip set 21 is connected with the optical I / O chip 6 between the computing layer 2, the perception layer 1, and the facility layer 3, for optical and electrical communication connection between the computing layer 2, the perception layer 1, and the facility layer 3; the computing chip set 21 of the computing layer 2 receives the instructions of the facility layer 3 and the perception signals of the perception layer 1 through the optical I / O chip 6 between the layers, for performing real-time data processing, machine learning inference, and algorithm acceleration, and completing high-speed optical signal communication and photoelectric conversion between the layers through the optical I / O chip 6.

[0043] In the application, the AI-FPGA module 211, the CPU module 212, and the GPU module 213 in the computing layer 2 are cooperatively operated, optical communication and electrical signal synchronous control are realized with the upper and lower layers through the optical I / O chip 6; the computing layer 2 receives the perception signals from the perception layer 1 and the system instructions from the facility layer 3, performs neural network calculation, machine learning inference, and algorithm optimization through the on-chip parallel acceleration structure, and returns the processed results to the facility layer 3 for output through the optical I / O chip 6.

[0044] The layer structure realizes an optical-electric integrated on-chip computing architecture, solves the signal time delay and power consumption bottleneck problem of the traditional electrical interconnection AI system under high-frequency operation; multi-channel data interaction with Tb / s level bandwidth is realized through the optical interconnection link, and the AI inference efficiency and energy consumption ratio are significantly improved.

[0045] In addition, an on-chip quantum dot acceleration unit or an AI-NPU sub-module is introduced in the AI computing layer 2, for realizing reconfigurable computing in different task scenarios; meanwhile, the optical waveguide path 41 can be coupled with the microlens array of the perception layer 1 through the optical interconnection path, and the multi-mode optical communication structure is realized between the perception layer 1 and the facility layer 3, to further improve the data throughput capacity.

[0046] The specific structure of the facility layer 3 is as follows: Figs. 1-3 As shown, the facility layer 3 includes a power management module 31, a micro battery 32, a storage chip 33, and a high-speed interface module 34; the micro battery 32 is arranged in a battery cavity 35 of the glass panel 7 of the facility layer 3 and is electrically connected with the power management module 31, the storage chip 33, and the high-speed interface module 34; the high-speed interface module 34 is connected in communication with the storage chip 33, the optical I / O chip 6 between the computing layer 2 and the facility layer 3, and an external device to be connected; the battery cavity 35 is formed by dry etching, the micro battery 32 is embedded in the battery cavity 35, and the micro battery 32 is packaged in the facility layer 3 by covering a nickel sealing sheet on the top of the battery cavity 35.

[0047] Specifically, the structure of the micro battery 32 and the packaging structure of the battery cavity 35 are as follows: Figs. 1-3As shown, the battery cavity 35 has a depth of 250-350 μm; the micro battery 32 is a solid-state thin film lithium battery with a thickness of 180-280 μm and an energy density of 350 Wh / L; a nickel sealing sheet is covered on the top of the battery cavity 35, and the nickel sealing sheet is fused with the glass panel 7 around the periphery of the battery cavity 35 through nickel-glass laser ring welding, so as to achieve a very short power supply path for auxiliary reduction of the resistance of the power supply path.

[0048] In the application, the depth of the battery cavity 35 is increased to at least 250-350 μm, so as to ensure that the micro battery 32 still has sufficient space (at least 70 μm) for placement and packaging of the battery under the thinnest battery thickness (180 μm), and avoid the influence of mechanical stress on the battery.

[0049] The power management module 31 of the facility layer 3 performs power detection and dynamic allocation on the embedded micro battery 32; at the system startup, the power management module 31 adjusts the output voltage according to the power consumption demand of the calculation layer 2, so as to ensure the stable power supply of the perception layer 1 and the calculation layer 2. The micro battery 32 is directly connected with the power supply network through the vertical conductive path 5 (TGV), and the power loss is extremely low; the high-speed interface module 34 is responsible for data communication with external devices, and transmits the output results processed by the calculation layer 2.

[0050] The structure significantly improves the continuity of on-chip power supply and the system integration, avoids the delay and energy consumption problems caused by the traditional external power supply wiring, encapsulates the micro battery 32 through the nickel sealing sheet, improves the cavity airtightness and structural reliability, and effectively reduces the resistance and heat accumulation under the very short power supply path.

[0051] In addition, the high-speed interface module 34 supports PCIe or optical fiber communication standards to realize multi-module cascading and external system expansion; the material of the micro battery 32 is selected from solid-state lithium, lithium-sulfur or thin film sodium ion system according to application requirements, so as to adapt to high-temperature or high-frequency use environment.

[0052] The specific structure and setting mode of the vertical conductive path 5 and the optical waveguide path 41 are as follows: Figs. 1-3 As shown, the glass through hole 51 with an aperture of ≤10 μm is formed on the glass panel 7, a Ti / Cu composite seed layer is deposited in the hole wall, and copper is filled in the glass through hole 51 in an electroplating manner to form the vertical conductive path 5; the optical waveguide path 41 is arranged within 15 μm of the structure periphery of the glass through hole 51, and the optical waveguide path 41 is a silicon nitride optical waveguide, which is used to reduce electromagnetic crosstalk and reduce optical loss; the TGV pad 52 is arranged at the glass through hole 51, and the optical I / O chip 6 is flip-chip bonded to the TGV pad 52; the optical I / O chip 6 senses the optical communication information of the silicon nitride optical waveguide and converts it into an electrical signal, and forms an electrical communication through the vertical conductive path 5, which is used to realize high-speed optical-electric signal conversion.

[0053] In the application, the vertical conductive path 5 formed in the glass panel 7 undertakes the function of interlayer vertical interconnection of electrical signals, and the silicon nitride optical waveguide path 41 undertakes the function of interlayer optical signal transmission; wherein the optical I / O chip 6 is flip-chip bonded on the TGV pad 52, which can synchronously perceive the optical signal from the optical waveguide and convert it into an electrical signal, or convert an electrical signal into an optical signal and transmit it to the adjacent layer; through this dual-channel optical and electrical interconnection structure, the system realizes cross-layer optical and electrical collaborative communication, so that different functional layers can complete multi-task parallel processing under low delay. And this structure significantly reduces parasitic capacitance and signal crosstalk, realizes physical isolation of electrical and optical paths, solves the problems of loss and heat accumulation in high-frequency signal transmission in the traditional TSV interconnection mode, and improves signal integrity and system stability.

[0054] Since the integration of the optical waveguide path 41 and the vertical conductive path 5 (TGV) in the glass panel 7 may have electromagnetic crosstalk problems; although the silicon nitride optical waveguide can reduce optical loss, but in high-frequency signal transmission, electromagnetic crosstalk may still affect signal integrity; therefore, the optical waveguide path 41 must be arranged in the region within at least 15 μm of the periphery of the glass via 51, so as to reduce electromagnetic crosstalk and optical loss as much as possible.

[0055] Further, an insulating material, which can be silicon dioxide, is added between the optical waveguide path 41 and the vertical conductive path 5 to further reduce the electromagnetic crosstalk between the optical waveguide path 41 and the vertical conductive path 5. Or by optimizing the wiring design, the layout of the optical waveguide path and the vertical conductive path is fully adjusted, the distance between the two is increased, and the electromagnetic coupling is reduced, so as to reduce the influence degree of the electromagnetic crosstalk between the optical waveguide path 41 and the vertical conductive path 5 on the high-frequency signal integrity.

[0056] In addition, the material of the optical waveguide can be selected as silicon nitride, silicon dioxide or a multi-layer composite system of oxynitride according to the wavelength of the optical signal to realize optical signal transmission of different bandwidths; and the metal filling material of the vertical conductive path 5 can also use Cu-Al or Cu-Mo alloy to optimize the electrical conductivity and heat dissipation performance.

[0057] Among them, the micro-channel cooling structure is additionally arranged at the periphery of the vertical conductive path 5 (TGV) of the calculation layer 2, which facilitates the dynamic thermal management of the large-area AI embedded computing system during high-power density operation.

[0058] The second embodiment of the large-area AI embedded computing system is as follows Fig. 3As shown, the difference between this embodiment and the first embodiment is that the PMIC chip 8 is embedded on the glass panel 7 of the facility layer 3, and the PMIC chip 8 is electrically connected with the micro battery 32 and the power management module 31, to realize dynamic voltage regulation of 0.8 V to -1.2 V for power management module 31 for module-level dynamic power scheduling.

[0059] In application, the PMIC chip 8 embedded in the facility layer 3 cooperates with the micro battery 32 and the power management module 31 to realize dynamic voltage regulation of 0.8 V to -1.2 V through the bidirectional power scheduling logic integrated on the PMIC chip 8; during the running of the large-area AI embedded computing system, the PMIC chip 8 dynamically adjusts the output voltage according to the load power change of the computing layer 2, so that each functional module is at the best energy efficiency point.

[0060] When the AI computing chip enters the high computing power mode, the PMIC chip 8 quickly increases the supply voltage to ensure the stability of the computing; in standby or low power mode, the output voltage is automatically reduced to reduce energy waste; this design can effectively solve the problems of large power consumption, slow response and unbalanced power supply in the traditional fixed power supply mode, and significantly improve the energy efficiency ratio and power supply reliability of the system.

[0061] The second embodiment of the large-area AI embedded computing system, the difference between this embodiment and the first embodiment is that the electrical communication of the glass panel 7 is realized by arranging a flexible film and wiring, reducing or not setting the vertical conductive path 5; the surface of the glass panel 7 is hot-pressed with a flexible film layer, and the flexible film layer is a polyimide flexible interlayer; Cu / Ni / Au multilayer wiring is constructed on the flexible film layer between the glass panel 7 of the computing layer 2 and the computing chip set 21, and the electrical signals of the computing chip set 21 and the optical I / O chip 6 are transmitted through the Cu / Ni / Au multilayer wiring.

[0062] In application, the electrical communication structure in the large-area AI embedded computing system can also be realized by the way of hot-pressing a polyimide (PI) flexible film layer on the surface of the glass panel 7; the Cu / Ni / Au multilayer wiring is pre-prepared in the flexible film layer, which is used to transmit high-speed electrical signals between the computing chip set 21 and the optical I / O chip 6. This structure effectively replaces the wiring mode of the traditional vertical conductive path 5 (TGV), which can also reduce the inductance and parasitic capacitance of the signal path, and reduce the high-frequency signal loss.

[0063] During the system operation, the flexible film layer bears the horizontal electrical connection and stress buffering effect, and can produce micro deformation with temperature change to absorb the difference in thermal expansion between layers, preventing cracks in the glass panel 7 due to thermal stress concentration; this structure scheme also simplifies the filling process of the glass via hole 51 in the glass panel 7, and significantly improves the yield and maintainability.

[0064] Based on the above embodiment of the large-area AI embedded computing system, a glass panel level integrated packaging method is provided, which contains the structure of the large-area AI embedded computing system and includes the following steps: (1) Preparing optical waveguide channels and vertical conductive channels on the multilayer glass panel, respectively; (2) Preparing functional panels of the sensing layer, the computing layer and the facility layer, respectively; including preparing absorbers and detectors for the sensing layer, preparing computing chip sets and optical I / O chips for the computing layer, preparing power management modules, battery cavities, storage chips and high-speed interface modules for the facility layer; (3) Stacking the sensing layer, the computing layer and the facility layer in turn by using high-precision alignment and 3D hybrid bonding process to realize photoelectric integrated interconnection; (4) After glass-glass thermal pressure bonding, a micro battery is embedded in the battery cavity of the facility layer, and a nickel sealing sheet is welded to the battery cavity by nickel-glass laser ring welding to form a packaging structure.

[0065] Specifically, in step (3), the 3D hybrid bonding process includes two stages of low-temperature bonding and high-temperature annealing: in the low-temperature bonding stage, at a temperature of ≤250℃, the respective glass panels of the sensing layer, the computing layer and the facility layer are first subjected to thermal pressure bonding of the glass panel and the flexible film, then the optical I / O chip is welded, and finally the low-temperature curing epoxy resin is used to cure and package the optical waveguide channel and the optical I / O chip; in the high-temperature annealing stage, at a temperature of ≥300℃, the glass via is annealed in an H2 atmosphere to repair the electroplating defects and reduce the resistivity, and the computing chip set is selectively annealed by infrared laser to avoid thermal damage to the packaged photoelectric devices.

[0066] In application, the entire packaging process includes the steps of photoelectric channel preparation, functional layer preparation, 3D hybrid bonding, micro battery packaging, etc.

[0067] Before the large-area AI embedded computing system is stacked, the preparation of the optical waveguide channel and the vertical conductive channel is completed on each glass panel, and the device modules are embedded on the corresponding functional layer. Then, through high-precision alignment technology, the sensing layer, the computing layer and the facility layer are stacked layer by layer to realize photoelectric interconnection.

[0068] In the low-temperature bonding stage (≤250℃), the thermal pressure bonding of the glass substrate and the flexible film and the welding of the optical I / O chip are completed, and the low-temperature curing epoxy resin is used to seal the optical waveguide and the chip to ensure the structural integrity and the stability of the optical signal; in the high-temperature annealing stage (≥300℃), the vertical conductive channel (TGV) is annealed in an H2 atmosphere to reduce the resistivity of the metal via, and the computing chip set is selectively annealed by infrared laser to ensure performance recovery without damaging the photoelectric devices.

[0069] The process path realizes multi-layer optoelectronic heterojunction integration, takes into account low thermal stress and high connection strength, and solves the problems of interface peeling and optical waveguide mismatch caused by the mismatch of thermal expansion of multiple materials in traditional packaging.

[0070] In addition, the 3D hybrid bonding process can introduce vacuum-assisted pressing and local laser reflow control technology to further improve the interlayer alignment accuracy; after annealing, plasma cleaning and SiO2 surface activation process can be used to enhance the bonding strength; micro-channel cooling structure can be embedded between the packaging layers for local thermal management of high-power modules.

[0071] The technical features of the above embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described.

Claims

1. A large-area AI embedded computing system, characterized in that, It includes a sensing layer, a computing layer and a facility layer arranged in a stacked manner from top to bottom. The sensing layer is used to receive the incident light to be detected and generate a sensing signal. The sensing signal enters the computing layer for data processing and outputs data. The facility layer supports the operation of the sensing layer and the computing layer through optoelectronic interconnection, receives the data output by the computing layer and transmits data to external devices. The sensing layer, the computing layer, and the facility layer are each independently mounted on a glass panel. Optical waveguide paths and / or vertical conductive paths are provided in each of the glass panels. Optical I / O chips are integrated between each layer and packaged through three-dimensional stacking to form an interlayer optical interconnect network for electrical and optical interconnection, thereby realizing high-speed, low-power optoelectronic collaborative data transmission.

2. The large-area AI embedded computing system according to claim 1, characterized in that, The sensing layer includes an absorber and a detector; The absorber is laid on the matrix detection unit to receive the light to be detected; Multiple detectors are arranged in a matrix on the glass panel of the sensing layer to form a matrix detection unit. The matrix detection unit is interconnected with the absorber to amplify the incident light signal and convert it into a sensing signal in the form of an electrical signal. The sensing signal is transmitted to the optical I / O chip between the computing layer and the sensing layer in the form of optical conduction through the interlayer optical interconnect network. The optical I / O chip performs photoelectric conversion and communicates with the module of the computing layer.

3. The large-area AI embedded computing system according to claim 1, characterized in that, The computing layer includes a computing chipset consisting of an AI-FPGA module, a CPU module, and a GPU module; The computing chipset is connected to the optical I / O chip between the computing layer and the sensing layer, and between the computing layer and the facility layer, for optical and electrical communication connections between the computing layer and the sensing layer and the facility layer; The computing chipset of the computing layer receives instructions from the facility layer and sensing signals from the sensing layer through the optical I / O chip between layers, and is used to perform real-time data processing, machine learning inference and algorithm acceleration, and completes high-speed optical signal communication and photoelectric conversion between layers through the optical I / O chip.

4. The large-area AI embedded computing system according to claim 1, characterized in that, The facility layer includes a power management module, a micro battery, a memory chip, and a high-speed interface module. The micro battery is disposed in the battery cavity of the glass panel of the facility layer and is electrically connected to the power management module, the memory chip, and the high-speed interface module. The high-speed interface module is connected and communicates with the memory chip, the optical I / O chip between the computing layer and the facility layer, and the external device to be connected. The battery cavity is formed by dry etching, the microcell is embedded in the battery cavity, and a nickel sealing sheet is placed on top of the battery cavity to encapsulate the microcell in the facility layer.

5. The large-area AI embedded computing system according to claim 4, characterized in that, The depth of the battery cavity is 250-350μm; The micro battery is a solid-state thin-film lithium battery with a thickness of 180-280μm and an energy density of 350Wh / L; The nickel sealing sheet covering the top of the battery cavity is fused to the glass panel surrounding the battery cavity by nickel-glass laser ring welding, thereby using an extremely short power supply path to help reduce the resistance of the power supply path.

6. The large-area AI embedded computing system according to claim 5, characterized in that, A PMIC chip is embedded in the glass panel of the facility layer. The PMIC chip is electrically connected to the micro battery and the power management module to realize dynamic voltage regulation from positive 0.8V to negative 1.2V for the power management module to perform module-level dynamic power scheduling.

7. The large-area AI embedded computing system according to claim 1, characterized in that, Glass vias with a diameter ≤10μm are formed on the glass panel, a Ti / Cu composite seed layer is deposited inside the via wall, and copper is filled into the glass vias by electroplating to form the vertical conductive path. The optical waveguide path is located within 15 μm of the outer periphery of the glass through-hole structure, and the optical waveguide path is a silicon nitride optical waveguide, which is used to reduce electromagnetic crosstalk and reduce optical loss. A TGV pad is provided at the glass through-hole, and the optical I / O chip is flip-chip soldered to the TGV pad. The optical I / O chip senses the optical communication information of the silicon nitride optical waveguide and converts it into an electrical signal. Electrical communication is formed through the vertical conductive path to realize high-speed photoelectric signal conversion.

8. The large-area AI embedded computing system according to claim 3, characterized in that, A flexible film layer is hot-pressed onto the surface of the glass panel, and the flexible film layer is a polyimide flexible interlayer. A Cu / Ni / Au multilayer wiring is constructed on the flexible thin film layer between the glass panel of the computing layer and the computing chipset, and the electrical signals of the computing chipset and the optical I / O chip are transmitted through the Cu / Ni / Au multilayer wiring.

9. A glass panel-level integrated packaging method, comprising the large-area AI embedded computing system as described in any one of claims 1 to 8, characterized in that, Includes the following steps: (1) Optical waveguide paths and vertical conductive paths are fabricated on multilayer glass panels respectively; (2) Prepare functional panels for the sensing layer, computing layer and facility layer respectively; including the fabrication of absorbers and detectors in the sensing layer, the fabrication of computing chipsets and optical I / O chips in the computing layer, and the fabrication of power management modules, battery cavities, memory chips and high-speed interface modules in the facility layer; (3) The sensing layer, the computing layer and the facility layer are stacked sequentially using a high-precision alignment and 3D hybrid bonding process to achieve optoelectronic integrated interconnection; (4) After glass-to-glass thermo-press bonding, a package structure is formed by embedding a micro battery in the battery cavity of the facility layer and by welding a nickel sealing sheet to the battery cavity by nickel-glass laser ring welding.

10. The glass panel-level integrated packaging method according to claim 9, characterized in that, The 3D hybrid bonding process includes two stages: low-temperature bonding and high-temperature annealing. In the low-temperature bonding stage, at a temperature of ≤250℃, the glass panels of the sensing layer, computing layer and facility layer are first thermo-press bonded to the flexible film, then the optical I / O chip is welded, and finally the optical waveguide path and optical I / O chip are encapsulated using low-temperature curing epoxy resin. During the high-temperature annealing stage, the glass vias are annealed in an H2 atmosphere at a temperature of ≥300℃ to repair electroplating defects and reduce resistivity. The computing chipset is selectively annealed using infrared laser to avoid thermal damage to the packaged optoelectronic devices.

Images