Configurable RRAM amplifier structure and memory

Abstract

According to the configurable RRAM amplifier structure and the memory provided by the invention, according to the resistance reference provided by the reference resistor, the sensing circuit can accurately judge the load difference between the resistance state of the resistance change subunit in the RRAM storage array and the reference resistor, and a reliable basis is provided for subsequent normal data reading and data verification reading. The latch circuit has two working modes, namely a verification reading access mode and a normal reading access mode, and different working modes can be switched according to use requirements, so that the circuit can adapt to different working scenes and requirements due to the flexible mode switching function, and the reliability of the circuit is improved in a verification stage after data is written. Carrying out accurate verification by adopting a verification reading path mode; when data is read normally, the mode is switched to a normal access reading mode, so that the reading speed is improved, and the optimal balance of performance is realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design and application technology, and in particular to a configurable RRAM amplifier structure and memory. Background Technology

[0002] When writing data, the resistance state transition of existing RRAMs cannot always be precisely controlled in a completely repeatable manner. To ensure the accuracy of data writing, sensitive amplifiers usually achieve the verification reading function by increasing the number of amplification stages, reducing noise, or extending the comparison time, which sacrifices processing speed. After the RRAM completes the data writing and enters the normal data reading operation, the amplifier is required to have a high data processing speed, which makes it impossible for sensitive amplifiers to simultaneously meet the requirements of data accuracy and speed.

[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0004] The purpose of this application is to at least partially solve one of the technical problems in the related art.

[0005] Therefore, the first objective of this application is to propose a configurable RRAM amplifier structure.

[0006] The second objective of this application is to propose a memory.

[0007] To achieve the above objectives, a first aspect of this application provides a configurable RRAM amplifier structure, comprising: An RRAM memory array and a reference resistor are provided. The RRAM memory array includes multiple RRAM memory cells, each RRAM memory cell including a resistive switching sub-cell and a select transistor. The resistive switching sub-cell is connected to the word line, bit line and source line respectively. The select transistor is used to control whether the RRAM memory cell is selected. The reference resistor is used to provide a resistance reference. The sensing circuit has a first branch connected to the bit line and a second branch connected to the reference resistor. By sensing the change in electrical parameters flowing through the resistive sub-unit, a load difference is formed between the first branch and the second branch. a latch circuit, a first end branch of the latch circuit is connected with the first end branch of the sensing circuit, a second end branch of the latch circuit is connected with the second end branch of the sensing circuit, for latch in a verify read pass mode when the load difference reaches a first preset state, and for latch in a normal read pass mode when the load difference reaches a second preset state; a pre-charge circuit, the pre-charge circuit is used to provide a steady voltage for the sensing circuit and the latch circuit.

[0008] To achieve the above object, the second aspect of the present application provides a memory, which comprises the configurable RRAM amplifier structure as provided in the first aspect of the present application.

[0009] In the embodiments of the present application, according to the resistance reference provided by the reference resistance, the sensing circuit can accurately determine the load difference between the resistance state of the resistance change subunit in the RRAM storage array and the reference resistance, and provide a reliable basis for subsequent data normal reading and data verification reading. The latch circuit has two working modes of verify read pass mode and normal read pass mode, and can switch different working modes according to the use requirement. This flexible mode switching function makes the circuit adapt to different working scenes and requirements. In the verification stage after writing data, the verify read pass mode is used for accurate verification; when reading data normally, the normal read pass mode is switched to, the reading speed is improved, and the performance optimization balance is realized.

[0010] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be known by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which: Figure 1 A structural schematic diagram of the configurable RRAM amplifier structure provided by the embodiments of the present application. DETAILED DESCRIPTION

[0012] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments are not meant to represent all implementations consistent with the embodiments of the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0013] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a” and “the” as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0014] It should be understood that although the terms first, second, third, etc., may be used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words "if" and "suppose" as used herein can be interpreted as "when," "when," or "in response to a determination."

[0015] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0016] In the current semiconductor memory technology field, resistive random access memory (RRAM) shows broad application prospects due to its unique advantages such as non-volatility, high-density storage, and low power consumption. However, in its actual data writing and reading operations (including normal reading and verification reading), the key circuit module of RRAM—the sense amplifier (SA)—has many shortcomings in balancing data accuracy and processing speed. It should be noted that normal reading refers to determining the stored data (0 or 1) by applying an appropriate voltage and detecting the resistance state of the RRAM cell (high resistance state HRS or low resistance state LRS). Verification reading, on the other hand, builds upon normal reading by adding a verification mechanism to ensure data accuracy.

[0017] In some scenarios, existing RRAMs face the problem of difficulty in achieving complete and repeatable precise control of resistance state transition when writing data. The core principle of RRAM is to store data based on the reversible change of the resistance state of the material. Typically, by applying a specific voltage pulse, the material is switched between the low resistance state (LRS, Low Resistance State) and the high resistance state (HRS, High Resistance State). However, in actual operation, due to the non-uniformity of the material's microscopic junctions, the subtle differences in manufacturing processes, and external environmental factors (such as temperature, electric field distribution, etc.), the transition of resistance state often has uncertainty.

[0018] This uncertainty causes the write operation to sometimes fail to accurately reach the expected set resistance value. For example, when the material needs to be switched to a specific low resistance state to represent data "0", the actual measured resistance value may be slightly higher than the target value; or when switching to a high resistance state to represent data "1", the resistance value may be slightly lower than the ideal value. If this deviation is not corrected, it will affect the accuracy and reliability of the data.

[0019] To ensure the accuracy of data writing, the verify function of SA during the write phase is crucial. Currently, SA usually uses methods such as increasing the number of amplification stages, reducing noise, or extending comparison time to achieve verification. Increasing the number of amplification stages can improve the amplification of the signal, allowing weak resistance change signals to be more clearly detected and processed, but it also increases the complexity of the circuit and the delay of signal transmission. Reducing noise helps improve signal quality and reduce the impact of external interference on verification results, but this often requires more complex noise suppression techniques and higher quality components, increasing cost and power consumption. Extending the comparison time allows the amplifier to have more time to accurately compare and judge the resistance value, but it significantly reduces processing speed, leading to a decrease in write operation efficiency.

[0020] When RRAM completes data writing and enters normal data reading operation (read), SA is required to have high data processing speed to meet the demand for fast and normal reading of large amounts of data. In many practical application scenarios, such as real-time data processing and cache, fast reading of data is crucial to the overall performance of the entire system. If the normal reading speed is too slow, it will cause system response delay, affecting user experience and system real-time performance.

[0021] However, there is a conflict between improving the normal read speed of data and ensuring the accuracy of data verification reading. In order to achieve high-speed reading, the amplifier may need to simplify the verification process, reduce the number of comparisons, or use a faster signal processing algorithm, but these measures may sacrifice the accuracy of verification to some extent. For example, simplifying the verification process may ignore some small resistance changes, leading to reading errors; reducing the number of comparisons may increase the probability of misjudgment; and using a fast signal processing algorithm may introduce more noise and errors.

[0022] Because of the obvious difference in the performance requirements of the amplifier in the verification read stage and the normal read stage, the existing amplifier design is difficult to simultaneously consider the requirements of data accuracy and speed, and this dilemma seriously limits the performance improvement and application expansion of RRAM memory.

[0023] The configurable RRAM amplifier structure and memory of the embodiments of the present application are described below with reference to the accompanying drawings.

[0024] Figure 1 A structural schematic diagram of a configurable RRAM amplifier structure provided by the embodiments of the present application.

[0025] As Figure 1 shown, the configurable RRAM amplifier structure includes an RRAM storage array and a reference resistance RREF. The RRAM storage array is the main body of data storage and includes a plurality of RRAM storage units, each of which includes a resistance change subunit and a selection tube that work together. The resistance change subunit and the selection tube are not shown in the Figure 1 The reference resistance is used to provide a resistance reference, which is an important basis for judging the resistance state of the resistance change subunit in subsequent data reading and verification processes and is set based on specific use scenarios.

[0026] It should be noted that the resistance change subunit is the core functional component of the RRAM storage unit and has a variable resistance characteristic. The resistance change subunit is electrically connected to the word line, the bit line, and the source line. The word line (WL) usually undertakes the task of transmitting the row selection signal and can locate a specific row in the RRAM storage array. The bit line (BL) is responsible for data input and output operations and realizes the transmission of data between the RRAM storage unit and the external circuit. The source line (SL) provides the necessary bias voltage for the resistance change subunit to ensure that it can work in a suitable electrical environment. Through the coordinated control of the word line, the bit line, and the source line, the resistance state of the resistance change subunit can be accurately regulated to switch between the high resistance state (HRS) and the low resistance state (LRS), thereby completing the storage of "0" and "1" data.

[0027] It should be noted that the selection tube is used to control whether the RRAM memory unit is selected, and the corresponding RRAM memory unit can be accurately selected or turned off according to the external control signal. When the RRAM memory array performs a storage operation, only the selected RRAM memory unit participates in data interaction, and other unselected RRAM memory units are in an isolated state, thereby avoiding signal crosstalk problems and improving the accuracy and reliability of data storage.

[0028] As shown in Figure 1 The configurable RRAM amplifier structure includes a sensing circuit, a first end branch of the sensing circuit is connected with a bit line, and a second end branch of the sensing circuit is connected with a reference resistance, thereby forming a comparison detection circuit structure. The sensing circuit senses the change of the electrical parameter (including voltage, current, etc.) flowing through the resistive switching sub-unit, and forms a load difference closely related to the resistive state of the resistive switching sub-unit between the first end branch and the second end branch.

[0029] As shown in Figure 1 The configurable RRAM amplifier structure includes a latch circuit, a first end branch of the latch circuit is connected with a first end branch of the sensing circuit, and a second end branch of the latch circuit is connected with a second end branch of the sensing circuit, which together constitute a complete data processing link. When the load difference generated by the sensing circuit reaches a first preset state, it indicates that it is in a verification reading stage after data writing, and the latch circuit enters a verification reading path mode and performs a latch operation based on pre-configuration. When the load difference generated by the sensing circuit reaches a second preset state, it indicates that it is in a normal reading stage, and the latch circuit enters a normal reading path mode and performs a latch operation based on pre-configuration. The verification reading path and the normal reading path use independent signal paths, timing control and latch modes, thereby avoiding signal interference between the two paths.

[0030] As shown in Figure 1 The configurable RRAM amplifier structure includes a pre-charge circuit, which is used to provide a steady-state voltage for the sensing circuit and the latch circuit, so as to ensure that the sensing circuit can accurately sense the change of the electrical parameter flowing through the resistive switching sub-unit under the steady-state voltage condition, and the latch circuit can reliably switch modes and lock data under the steady-state voltage condition.

[0031] In a feasible implementation, the resistive switching sub-unit of each RRAM memory unit is connected with a word line through a first connection node, connected with a bit line through a second connection node, and connected with a source line through a third connection node; the gate of the selection tube of each RRAM memory unit is connected with the word line, the source of the selection tube is connected with the third connection node, and the drain of the selection tube is connected with a reference ground.

[0032] In some embodiments, the resistive switching sub-unit has a variable resistance characteristic and can be switched between a high resistance state (HRS) and a low resistance state (LRS). When a voltage pulse of a certain direction and amplitude is applied across the resistive switching sub-unit, a process of forming or breaking of a conductive filament inside the resistive switching sub-unit occurs, resulting in a change of resistance state. Illustratively, a forward voltage pulse (a forward voltage pulse can be characterized as a charging process) can cause a conductive filament to form inside the resistive switching sub-unit, causing it to switch from a high resistance state to a low resistance state, which is defined as storing data "1"; while a reverse voltage pulse (a reverse voltage pulse can be characterized as a discharging process) can cause the conductive filament to break, causing the resistive switching sub-unit to return to a high resistance state, representing storing data "0".

[0033] In some embodiments, the select transistor in the RRAM memory cell functions as a switch control, with its gate connected to a word line. By controlling the voltage on the word line, the corresponding RRAM memory cell can be precisely turned on or turned off. Illustratively, when a sufficiently high forward voltage pulse is applied to the word line, the select transistor is turned on, allowing the resistive switching sub-unit to establish electrical connection with the bit line and the source line, and participate in data read / write operations; when the voltage on the word line is low or zero, the select transistor is turned off, isolating the resistive switching sub-unit from the external circuit, avoiding interference with unselected RRAM memory cells. The source of the select transistor is connected to the third connection node (connecting the source line) of the resistive switching sub-unit, and the drain is connected to the reference ground. This connection allows a stable current loop to be provided for the resistive switching sub-unit when the select transistor is turned on, ensuring the normal operation of data read / write operations.

[0034] In a feasible implementation, the RRAM memory cells in the RRAM memory array are arranged in a matrix, with the word lines extending in the row direction of the matrix and the bit lines extending in the column direction of the matrix, and the source lines being arranged based on a separate wiring manner.

[0035] In some embodiments, the RRAM memory cells are arranged in a matrix, with each intersection on the matrix corresponding to an RRAM memory cell. Illustratively, in an m x n matrix, there are m rows and n columns, and a total of m x n RRAM memory cells. This arrangement allows the RRAM memory cells to be highly ordered in space, facilitating large-scale integration and accommodating more RRAM memory cells in a limited chip area, thereby achieving high-density data storage.

[0036] In some embodiments, the word lines extend along the row direction of the matrix, and each row corresponds to an independent word line. By controlling the voltage signal on the word line, all RRAM memory cells in the row can be selected at the same time (in actual operation, a selection tube and other elements are used to accurately select a specific RRAM memory cell), thereby preparing for subsequent data read / write operations. The bit lines extend along the column direction of the matrix, and each column has an independent bit line. The bit line is mainly responsible for data input and output. When a row of RRAM memory cells is selected, data writing or reading (including normal reading and check reading) of a specific RRAM memory cell in the row can be achieved by applying a specific voltage to the bit line or detecting the current on the bit line.

[0037] In some embodiments, the source line is arranged in a separate wiring manner and is not shared with the word line and the bit line. Each RRAM memory cell or a group of RRAM memory cells is connected to an independent source line. This design provides more stable and flexible bias voltage supply for the RRAM memory cell. Separate wiring can avoid signal interference between the source line and other lines, ensure that the source line can provide accurate voltage reference for the RRAM memory cell during data read / write, and improve the accuracy and reliability of data operation.

[0038] In a feasible implementation, when the gate voltage of the selection tube is greater than the preset threshold voltage, the selection tube is turned on, the resistance change sub-unit of the RRAM memory cell forms a conduction loop with the bit line and the source line, and the RRAM memory cell is in the selected state; when the gate voltage of the selection tube is less than or equal to the preset threshold voltage, the selection tube is turned off, and the RRAM memory cell is in the unselected state.

[0039] In some embodiments, the selection tube usually adopts a field effect transistor structure, and its on and off states are mainly controlled by the gate voltage. When the gate voltage is greater than the preset threshold voltage (Vth), a conductive channel is formed in the semiconductor material below the gate. This conductive channel sharply reduces the resistance between the source and the drain, and the current can flow smoothly. The selection tube is in the on state. Conversely, when the gate voltage is less than or equal to the preset threshold voltage (Vth), an effective conductive channel cannot be formed, and the source and the drain are equivalent to an open circuit. The current is almost impossible to pass, and the selection tube is in the off state. This voltage-controlled switching characteristic provides a basis for accurately selecting the RRAM memory cell.

[0040] In some embodiments, when the select transistor is turned on, the resistive switching sub-cell of the RRAM memory cell establishes an electrical connection with the bit line and the source line through the select transistor, forming a complete conduction loop. In this loop, the bit line is used to input or output data signals, and the source line provides a stable bias voltage. For example, during data writing, a specific voltage pulse applied to the bit line and the bias voltage of the source line work together to create a suitable electric field across the resistive switching sub-cell, causing a change in the resistance state of the sub-cell, thereby achieving data storage. During data reading, the conduction loop enables the bit line to detect the current change corresponding to the resistance state of the resistive switching sub-cell, and thus read the stored data.

[0041] In one feasible implementation, such as Figure 1 As shown, the latching circuit includes a first transmission gate, a second transmission gate, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. The gate of the first NMOS transistor N1 is connected to the first branch of the pre-charge circuit; the first terminal of the first transmission gate is connected to the gate of the first NMOS transistor N1, and the second terminal of the first transmission gate is connected to the drain of the first NMOS transistor N1; the second NMOS transistor N2 is connected to the second branch of the pre-charge circuit, and the source of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1; the first terminal of the second transmission gate is connected to the gate of the second NMOS transistor N2, and the second terminal of the second transmission gate is connected to the drain of the second NMOS transistor N2; the drain of the third NMOS transistor N3 is connected to the source of the second NMOS transistor N2, and the third NMOS transistor... The source of N3 is connected to the reference ground; the drain of the first PMOS transistor P1 is connected to the second terminal of the second transmission gate; the drain of the fourth NMOS transistor N4 is connected to the drain of the first PMOS transistor P1, and the gate of the fourth NMOS transistor N4 is connected to the gate of the first PMOS transistor P1; the drain of the second PMOS transistor P2 is connected to the second terminal of the first transmission gate, and the source of the second PMOS transistor P2 is connected to the source of the first PMOS transistor P1; the drain of the fifth NMOS transistor N5 is connected to the drain of the second PMOS transistor P2, the gate of the fifth NMOS transistor N5 is connected to the gate of the second PMOS transistor P2, and the source of the fifth NMOS transistor N5 is connected to the source of the fourth NMOS transistor N4; the source of the third PMOS transistor P3 is connected to the operating voltage VDD, and the drain of the third PMOS transistor P3 is connected to the source of the second PMOS transistor P2; the drain of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5, and the source of the sixth NMOS transistor N6 is connected to the reference ground.

[0042] In some embodiments, the transmission gate is typically composed of a pair of complementary transistors (such as NMOS and PMOS), and the on or off state of the transmission gate is adjusted by an external control signal. Figure 1 As shown, when the first and second transmission gates are open, an external control signal controls the third NMOS transistor N3 to be in the off state. The pre-charge circuit performs pre-charge operations on each branch of the sensing circuit and the latch circuit. Due to the load difference between the first and second branches of the sensing circuit, a voltage difference is formed. This voltage difference is applied to the first and second branches of the latch circuit, establishing a voltage difference between the first terminals of the first and second transmission gates. The voltage difference is transmitted through the first and second transmission gates to nodes NQ and Q of the latch, which is composed of the first PMOS transistor P1, the second PMOS transistor P2, the fourth NMOS transistor N4, and the fifth NMOS transistor N5.

[0043] In some embodiments, such as Figure 1 As shown, when a data write operation is performed, the first and second transmission gates open, the sensing circuit detects the electrical parameters flowing through the resistive switching unit, and compares them with the resistance reference of the reference resistor. This comparison creates a load difference between the first and second branches of the sensing circuit. The first preset state is a specific range or threshold reached by the load difference. When the load difference is within the first preset state, further verification of the correctness of the written data is required, and the latch circuit enters the verification read path mode.

[0044] In some embodiments, it is assumed that during a data write operation, the resistive switching unit is expected to be in a low-resistance state (LRS) to represent the data "1". However, during the write process, due to various factors (such as inaccurate voltage pulse amplitude and width), the resistive switching unit may not fully reach the expected low-resistance state, and its actual resistance value may deviate from the ideal low-resistance state resistance value. When the sensing circuit detects this deviation, the resulting load difference will fall within a first preset state range. After the latching circuit detects this state, it enters the verification path mode, and further analyzes the resistive switching unit and the reference resistor to determine whether the written data meets the requirements. If the data is incorrect, appropriate measures are taken to correct it, such as re-performing the data write operation.

[0045] In some embodiments, such as Figure 1As shown, when a data read operation is performed, the first transfer gate and the second transfer gate are closed, and the sensing circuit also detects the electrical parameter of the RRAM sub-unit and compares it with the reference resistance to form a load difference. The load difference at this time is represented by detecting the gate voltages of the first NMOS transistor N1 and the second NMOS transistor N2. When the difference between the gate voltages of the first NMOS transistor N1 and the second NMOS transistor N2 reaches the second preset state, it indicates that the data read operation is ready to be performed, and the latch circuit enters the normal read path mode.

[0046] In some embodiments, when reading the data stored in the RRAM sub-unit, if the RRAM sub-unit is in a low resistance state (LRS) representing data "1" and in a high resistance state (HRS) representing data "0". After the sensing circuit detects the resistance state of the RRAM sub-unit, the load difference formed is matched with the second preset state. If the load difference indicates that the RRAM sub-unit is in a low resistance state and meets the range of the second preset state, the latch circuit enters the normal read path mode and converts the low resistance state information into a digital signal "1" output; similarly, if the load difference indicates that the RRAM sub-unit is in a high resistance state, the latch circuit converts it into a digital signal "0" output, thereby realizing the accuracy of normal data reading.

[0047] In a feasible implementation, as shown in Figure 1 The sensing circuit includes a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a first switch SENB1. The drain of the seventh NMOS transistor N7 is connected to the first end branch of the pre-charge circuit, and the source of the seventh NMOS transistor N7 is connected to the bit line. The gate of the eighth NMOS transistor N8 is connected to the gate of the seventh NMOS transistor N7, the drain of the eighth NMOS transistor N8 is connected to the second end branch of the pre-charge circuit, and the source of the eighth NMOS transistor N8 is connected to the reference resistance RREF. The first switch SENB1 is connected between the source of the seventh NMOS transistor N7 and the source of the eighth NMOS transistor N8.

[0048] In some embodiments, as shown in Figure 1 When the pre-charge circuit starts to work, it charges the relevant nodes through the first end branch and the second end branch. For example, according to the external control signal, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are in the on state, and the pre-charge circuit can charge the nodes related to the bit line and the reference resistance RREF through the seventh NMOS transistor N7 and the eighth NMOS transistor N8, respectively, so that these nodes reach a certain pre-charge voltage level.

[0049] In some embodiments, as shown in Figure 1As shown, the state of the first switch SENB1 affects the pre-charging process. If SENB1 is on, the nodes related to the bit line and the reference resistor RREF will form a certain electrical connection during pre-charging, affecting the voltage distribution during pre-charging. If SENB1 is off, the nodes related to the bit line and the reference resistor RREF will be independent of each other during pre-charging. The state of the first switch SENB1 should be set according to the specific scenario.

[0050] In some embodiments, such as Figure 1 As shown, when the sensing circuit starts working, the signal on the bit line changes according to the state of the RRAM memory cell (e.g., whether the stored data is "0" or "1"). The seventh NMOS transistor N7 transmits the signal on the bit line to the relevant node of the first branch of the precharge circuit. Simultaneously, the reference resistor RREF generates a stable reference signal, which is transmitted to the relevant node of the second branch of the precharge circuit by the eighth NMOS transistor N8. By comparing the bit line signal and the reference signal, the state of the RRAM memory cell can be determined. The state of the first switch SENB1 plays a crucial role in the operation of the sensing circuit. If the first switch SENB1 is on, the bit line signal and the reference signal may influence each other to some extent. This mutual influence can be used for correlation analysis, which can distinguish noise interference from the true data signal. If the first switch SENB1 is off, the bit line signal and the reference signal can be compared more independently, improving the accuracy of the sensing.

[0051] In one feasible implementation, such as Figure 1 As shown, the pre-charge circuit includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a second switch SENB2. The source of the fourth PMOS transistor P4 is connected to the operating voltage VDD, and its drain is connected to the first branch of the sensing circuit and latching circuit. The source of the fifth PMOS transistor P5 is connected to the source of the fourth PMOS transistor P4, and both its gate and drain are connected to the drain of the fourth PMOS transistor P4. The sixth PMOS transistor P6... The source of PMOS transistor P6 is connected to the source of PMOS transistor P5, the gate of PMOS transistor P6 is connected to the gate of PMOS transistor P5, and the drain of PMOS transistor P6 is connected to the second branch of the sensing circuit and latching circuit; the source of PMOS transistor P7 is connected to the source of PMOS transistor P6, and the drain of PMOS transistor P7 is connected to the drain of PMOS transistor P6; the second switch SENB2 is connected between the drain of PMOS transistor P7 and the drain of PMOS transistor P5.

[0052] In some embodiments, such as Figure 1As shown, when pre-charging, the external control signal makes the fourth PMOS P4, the fifth PMOS P5, the sixth PMOS P6 and the seventh PMOS P7 conduct. Due to the fourth PMOS P4 conducting, the working voltage VDD charges the first end branch of the sensing circuit and the latch circuit through the drain of the fourth PMOS P4. The working voltage VDD charges the second end branch of the sensing circuit and the latch circuit through the sixth PMOS P6 and the seventh PMOS P7. If the second switch SENB2 is on, the drain of the seventh PMOS P7 is connected to the drain of the fifth PMOS P5, at this time, the sixth PMOS P6 and the seventh PMOS P7 jointly charge the second end branch, the charging current may increase, and the charging speed is accelerated; if SENB2 is off, the sixth PMOS P6 and the seventh PMOS P7 independently charge the second end branch, and the charging process is relatively independent.

[0053] In a possible implementation, the configurable RRAM amplifier structure of the embodiment of the present application further comprises a control circuit connected with the latch circuit, the sensing circuit and the pre-charging circuit, for generating a control signal for controlling the working timing of the latch circuit, the sensing circuit and the pre-charging circuit, and the working timing is used for configuring the first preset state and the second preset state.

[0054] In some embodiments, the control signal can determine when the latch circuit starts to latch data, when to keep the latch state, and when to release the latched data. For example, when the sensing circuit completes the sensing of the data of the storage unit, the control circuit sends a specific control signal to make the latch circuit latch the sensed data for subsequent reading and processing.

[0055] In some embodiments, the control signal can control the start and stop of the sensing circuit, and adjust the sensitivity and accuracy of the sensing. For example, in different working modes, different sensing sensitivities may be required, and the control circuit can adjust the parameters of the sensing circuit by sending corresponding control signals to adapt to different working requirements.

[0056] In some embodiments, the control signal can control the charging time and charging voltage of the pre-charging circuit. Before the RRAM storage unit performs reading (including normal reading and verification reading) or writing operation, the pre-charging circuit needs to pre-charge the relevant circuit nodes to ensure accurate transmission of signals. The control circuit will send control signals to start and stop the working of the pre-charging circuit according to the specific working timing requirements, and adjust the charging parameters.

[0057] In some embodiments, when performing a data verify read, the control circuit sends a control signal to activate the pre-charge circuit to pre-charge the relevant nodes of the sensing circuit and the latch circuit to an initial voltage level of a first preset state; when performing a data read, the control circuit sends a control signal to control the relevant nodes of the sensing circuit and the latch circuit to an initial voltage level of a second preset state.

[0058] In particular, according to the embodiments of the present application, the configurable RRAM amplifier structure described above with reference to the structural schematic diagram can be implemented as a memory for verify read pass mode latching when the load difference reaches a first preset state, and normal read pass mode latching when the load difference reaches a second preset state, thereby realizing the separation of verify read and normal read.

[0059] In summary, the configurable RRAM amplifier structure and the memory of the embodiments of the present application can accurately determine the load difference between the resistance state of the resistive change subunit in the RRAM storage array and the reference resistance according to the resistance reference provided by the reference resistance, and provide a reliable basis for subsequent data normal read and data verify read. The latch circuit has two working modes of verify read pass mode and normal read pass mode, and can switch between different working modes according to the use requirements. This flexible mode switching function enables the circuit to adapt to different working scenarios and requirements. In the verify phase after writing data, the verify read pass mode is used for accurate verification; when reading data normally, the normal read pass mode is switched to, the reading speed is improved, and the performance optimization balance is realized.

[0060] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0061] It should be understood that the application is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should only be limited by the appended claims.

Claims

1. A configurable RRAM amplifier structure, characterized in that, include: An RRAM memory array and a reference resistor, wherein the RRAM memory array includes multiple RRAM memory cells, each RRAM memory cell includes a resistive switching sub-cell and a selection transistor, the resistive switching sub-cell is connected to the word line, bit line and source line respectively, and the selection transistor is used to control whether the RRAM memory cell is selected; The reference resistor is used to provide a resistance reference; The sensing circuit has a first branch connected to the bit line and a second branch connected to the reference resistor. By sensing the change in electrical parameters flowing through the resistive sub-unit, a load difference is formed between the first branch and the second branch. A latching circuit, wherein a first branch of the latching circuit is connected to a first branch of the sensing circuit, and a second branch of the latching circuit is connected to a second branch of the sensing circuit, is used to perform a verification read path mode latch when the load difference reaches a first preset state, and to perform a normal read path mode latch when the load difference reaches a second preset state. A pre-charging circuit is provided to provide a steady-state voltage to the sensing circuit and the latching circuit.

2. The configurable RRAM amplifier structure according to claim 1, characterized in that, The resistive switching sub-unit is connected to the word line through a first connection node, to the bit line through a second connection node, and to the source line through a third connection node; the gate of the select transistor is connected to the word line, the source of the select transistor is connected to the third connection node, and the drain of the select transistor is connected to the reference ground.

3. The configurable RRAM amplifier structure according to claim 1, characterized in that, The RRAM memory cells in the RRAM memory array are arranged in a matrix, with word lines extending along the row direction of the matrix, bit lines extending along the column direction of the matrix, and source lines set up based on a separate wiring method.

4. The configurable RRAM amplifier structure according to claim 1, characterized in that, When the gate voltage of the select transistor is greater than a preset threshold voltage, the select transistor is turned on, and the resistive switching sub-cell of the RRAM memory cell forms a conduction loop with the bit line and the source line, and the RRAM memory cell is in the selected state; when the gate voltage of the select transistor is less than or equal to the preset threshold voltage, the select transistor is turned off, and the RRAM memory cell is in the unselected state.

5. The configurable RRAM amplifier structure according to claim 1, characterized in that, The latching circuit includes a first transmission gate, a second transmission gate, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The gate of the first NMOS transistor is connected to the first branch of the pre-charge circuit; the first terminal of the first transmission gate is connected to the gate of the first NMOS transistor, and the second terminal of the first transmission gate is connected to the drain of the first NMOS transistor; the gate of the second NMOS transistor is connected to the second branch of the pre-charge circuit, and the source of the second NMOS transistor is connected to the source of the first NMOS transistor; the first terminal of the second transmission gate is connected to the gate of the second NMOS transistor, and the second terminal of the second transmission gate is connected to the drain of the second NMOS transistor; the drain of the third NMOS transistor is connected to the source of the second NMOS transistor, and the third NMOS transistor... The source of the first PMOS transistor is connected to the reference ground; the drain of the first PMOS transistor is connected to the second terminal of the second transmission gate; the drain of the fourth NMOS transistor is connected to the drain of the first PMOS transistor, and the gate of the fourth NMOS transistor is connected to the gate of the first PMOS transistor; the drain of the second PMOS transistor is connected to the second terminal of the first transmission gate, and the source of the second PMOS transistor is connected to the source of the first PMOS transistor; the drain of the fifth NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fifth NMOS transistor is connected to the gate of the second PMOS transistor, and the source of the fifth NMOS transistor is connected to the source of the fourth NMOS transistor; the source of the third PMOS transistor is connected to the operating voltage, and the drain of the third PMOS transistor is connected to the source of the second PMOS transistor; the drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is connected to the reference ground.

6. The configurable RRAM amplifier structure according to claim 5, characterized in that, When the first transmission gate and the second transmission gate are open, the latching circuit performs a verification read path mode latch when the load difference reaches a first preset state; when the first transmission gate and the second transmission gate are closed, the latching circuit performs a normal read path mode latch when the load difference reaches a second preset state.

7. The configurable RRAM amplifier structure according to claim 1, characterized in that, The sensing circuit includes a seventh NMOS transistor, an eighth NMOS transistor, and a first switch. The drain of the seventh NMOS transistor is connected to the first branch of the pre-charge circuit, and the source of the seventh NMOS transistor is connected to the bit line. The gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor, the drain of the eighth NMOS transistor is connected to the second branch of the pre-charge circuit, and the source of the eighth NMOS transistor is connected to the reference resistor. The first switch is connected between the sources of the seventh and eighth NMOS transistors.

8. The configurable RRAM amplifier structure according to claim 1, characterized in that, The pre-charge circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and a second switch. The source of the fourth PMOS transistor is connected to the operating voltage, and its drain is connected to the first branch of the sensing circuit and the latch circuit. The source of the fifth PMOS transistor is connected to the source of the fourth PMOS transistor, and both its gate and drain are connected to the drain of the fourth PMOS transistor. The source of the sixth PMOS transistor is connected to the source of the fifth PMOS transistor, its gate is connected to the gate of the fifth PMOS transistor, and its drain is connected to the second branch of the sensing circuit and the latch circuit. The source of the seventh PMOS transistor is connected to the source of the sixth PMOS transistor, and its drain is connected to the drain of the sixth PMOS transistor. The second switch is connected between the drain of the seventh PMOS transistor and the drain of the fifth PMOS transistor.

9. The configurable RRAM amplifier structure according to claim 1, characterized in that, Also includes: A control circuit, connected to the latch circuit, the sensing circuit and the pre-charge circuit, is used to generate a control signal. The control signal is used to control the operating timing of the latch circuit, the sensing circuit and the pre-charge circuit. The operating timing is used to configure a first preset state and a second preset state.

10. A memory, characterized in that, Includes a configurable RRAM amplifier structure as described in any one of claims 1 to 9.

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