Readout circuit of memory cell and control method thereof
By controlling the voltage of the read circuit of the 2T0C memory cell through the pre-charge and selection control unit, the problems of slow read speed and crosstalk are solved, and stable read current and high robustness are achieved.
Patent Information
- Application Number
- CN202511661826.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-02-27
AI Technical Summary
In the existing technology, the read operation of 2T0C memory cells suffers from the problem that the read speed is greatly affected by parasitic capacitance and resistance, the crosstalk between adjacent cells is serious, and the robustness is poor.
A pre-charge control unit is used to control the voltage of the energy storage sub-unit, read bit line, and read word line during the pre-charge stage. By selecting the control unit to obtain the voltage change of the energy storage sub-unit based on the voltage change of the read word line during the sensing stage, the reading result is judged in combination with the signal sensing unit, and the current interference of adjacent units is suppressed.
It improves readout speed, reduces the impact of parasitic capacitance and resistance on readout results, enhances the stability and robustness of readout current, and reduces the impact of crosstalk between adjacent cells.
Smart Images
Figure CN121583306A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the field of integrated circuit technology, and more particularly, to a readout circuit of a memory cell and a control method thereof. BACKGROUND
[0002] Dynamic Random Access Memory (DRAM) has high storage density and fast read-write speed, and is widely used in various electronic devices. DRAM usually includes a plurality of memory cells. Compared with the traditional memory cell, such as 1T1C (including one transistor and one capacitor), the volatile 2T0C (including two transistors) memory cell has the advantages of high retention characteristics, low operating power consumption, and high area efficiency. However, there are still deficiencies in the readout operation of the 2T0C memory cell in the related art. SUMMARY
[0003] Therefore, the present disclosure provides a readout circuit of a memory cell and a control method thereof.
[0004] One aspect of the present disclosure provides a readout circuit of a memory cell, wherein the memory cell includes a write transistor, a read transistor, a read bit line, and a read word line, a first end of the write transistor is electrically connected to a control end of the read transistor, a first end of the read transistor is electrically connected to the read bit line, a second end of the read transistor is electrically connected to the read word line, one end of the read word line is grounded, and the readout circuit includes:
[0005] a pre-charge control unit electrically connected to the selection control unit, including an energy storage subunit, configured to control a voltage of the energy storage subunit to be a first voltage by a first control voltage in a pre-charge phase, and stop the control of the first control voltage in a sensing phase;
[0006] a selection control unit, configured to control a read bit line voltage of the read bit line to be a second voltage and control a read word line voltage of the read word line to be the second voltage by a second control voltage in the pre-charge phase, and obtain a third voltage of the energy storage subunit according to a change of the read word line voltage in the sensing phase, wherein a voltage value of an effective level stored in the memory cell is the same as a voltage value of the second voltage;
[0007] a signal sensing unit, configured to obtain a readout result of the memory cell according to the third voltage and a reference voltage.
[0008] According to an embodiment of the present disclosure, the pre-charge control unit comprises a first transistor, the energy storage subunit comprises an energy storage capacitor, a first end of the first transistor is electrically connected with a first power supply voltage, a second end of the first transistor and a first end of the energy storage capacitor are electrically connected with the signal sensing unit, a control end of the first transistor is electrically connected with the first control voltage, and a second end of the energy storage capacitor is grounded.
[0009] According to an embodiment of the present disclosure, the selection control unit comprises a second transistor, a bit line selection transistor and a word line selection transistor.
[0010] A first end of the second transistor is electrically connected with a second end of the first transistor and a first end of the energy storage capacitor, a second end of the second transistor is electrically connected with a first end of the bit line selection transistor, a second end of the bit line selection transistor is electrically connected with the read bit line, a first end of the word line selection transistor is electrically connected with a second power supply voltage, a second end of the word line selection transistor is electrically connected with the read word line, and a voltage value of the second power supply voltage is the same as a voltage value of the second voltage.
[0011] According to an embodiment of the present disclosure, in a case where the storage content of the storage unit is the valid level, in the sensing stage, the read word line voltage is lowered to 0, the energy storage subunit discharges to the read word line, a first voltage of the energy storage subunit is lowered to obtain a first sub-voltage of the energy storage subunit, and in a case where the first sub-voltage is less than the reference voltage, the read result of the storage unit is output.
[0012] According to an embodiment of the present disclosure, in a case where the storage content of the storage unit is the invalid level, in the sensing stage, the read word line voltage is unchanged to obtain a second sub-voltage of the energy storage subunit, and according to the second sub-voltage and the reference voltage, the read result of the storage unit is output.
[0013] According to an embodiment of the present disclosure, the signal sensing unit comprises:
[0014] An amplifier configured to output the read result of the storage unit according to the third voltage and the reference voltage.
[0015] A latch configured to save the read result of the storage unit.
[0016] According to an embodiment of the present disclosure, the readout circuit further comprises:
[0017] A word line connection transistor comprising a first end electrically connected with the read word line and a second end grounded, and configured to be turned on in the pre-charge stage and the sensing stage.
[0018] Another aspect of the present disclosure provides a control method of a readout circuit of a memory cell, wherein the memory cell comprises a write transistor, a read transistor, a read bit line and a read word line, a first end of the write transistor is electrically connected to a control end of the read transistor, a first end of the read transistor is electrically connected to the read bit line, a second end of the read transistor is electrically connected to the read word line, one end of the read word line is grounded, and the method comprises:
[0019] The pre-charge control unit is used to control the voltage of the energy storage subunit to be a first voltage by a first control voltage in a pre-charge phase, and stop the control of the first control voltage in a sensing phase.
[0020] The selection control unit is used to control the read bit line voltage of the read bit line to be a second voltage and control the read word line voltage of the read word line to be the second voltage by a second control voltage in the pre-charge phase, and obtain a third voltage of the energy storage subunit according to the change of the read word line voltage in the sensing phase, the voltage value of the valid level stored in the memory cell is the same as the voltage value of the second voltage.
[0021] The signal sensing unit is used to obtain the readout result of the memory cell according to the third voltage and a reference voltage.
[0022] According to an embodiment of the present disclosure, the method further comprises: in the case that the storage content of the memory cell is the valid level, the read word line voltage is reduced to 0 in the sensing phase, the memory cell discharges to the read word line, the first voltage of the energy storage subunit is reduced to obtain a first sub-voltage of the energy storage subunit, and in the case that the first sub-voltage is less than the reference voltage, the readout result of the memory cell is output.
[0023] According to an embodiment of the present disclosure, the method further comprises: in the case that the storage content of the memory cell is an invalid level, the read word line voltage is unchanged in the sensing phase to obtain a second sub-voltage of the energy storage subunit, and the readout result of the memory cell is output according to the second sub-voltage and the reference voltage.
[0024] According to an embodiment of the present disclosure, the read word line and the read bit line of the storage unit are pre-charged by the second power supply voltage in the pre-charging stage, so that the read word line voltage of the read word line and the read bit line voltage of the read bit line are the second voltage, avoiding the current interference of the adjacent unit of the storage unit. And the pre-charging stage charges the energy storage sub-unit to the first voltage by the first power supply voltage, in the sensing stage, the read word line voltage will change according to the storage state of the storage unit, so as to cause the voltage of the energy storage sub-unit to change, and obtain the readout result of the storage unit, and improve the readout speed. And pre-charging the read word line and the read bit line to the second voltage and pre-charging the energy storage sub-unit to the first voltage in the pre-charging stage can reduce the influence of the parasitic capacitance of the storage unit on the readout result. BRIEF DESCRIPTION OF DRAWINGS
[0025] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:
[0026] Figure 1 A block diagram of a readout circuit of a storage unit according to an embodiment of the present disclosure is schematically shown;
[0027] Figure 2 A circuit schematic diagram of a readout circuit of a storage unit according to an embodiment of the present disclosure is schematically shown;
[0028] Figure 3 A control timing diagram of a readout circuit of a storage unit according to an embodiment of the present disclosure is schematically shown;
[0029] Figure 4 A flowchart of a control method of a readout circuit of a storage unit according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION
[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent, however, that one or more embodiments can be practiced without these specific details. In other instances, well-known structures and functions have been omitted to avoid obscuring the concept of the present disclosure in unnecessary detail.
[0031] The terms used herein are merely used to describe specific embodiments and are not intended to limit the present disclosure. The terms "include", "comprise" and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0032] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be further noted that the use of terms such as "first", "second" and the like can be used in this disclosure to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Terms in the singular sense can include the plural sense unless otherwise specified. Terms in the plural sense can include the singular sense unless otherwise specified. It will be understood that the terms so used are interchangeable and not limiting.
[0033] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should be generally interpreted that the meaning of the expression is at least one of A, B, and C, etc. (for example, "a system having at least one of A, B, and C" should include but not be limited to a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc.).
[0034] As the manufacturing process node of Complementary Metal-Oxide-Semiconductor (CMOS) shrinks, the DRAM based on the volatile 2T0C storage unit is beneficial to the shrink of the CMOS process node due to the reduction of the number of capacitors. However, the readout circuit of the volatile 2T0C storage unit of the DRAM still has problems such as storage current crosstalk and the like.
[0035] Some readout circuits in the related art do not have a pre-charge stage in the control timing in the readout circuit, so the readout speed is greatly affected by the parasitic capacitance of the storage unit; there are also some readout circuits in which the readout current is not constant, so the readout speed is more sensitive to the parasitic resistance of the storage array; and some readout circuits do not consider the crosstalk problem of adjacent units, and have poor robustness.
[0036] In view of this, the present disclosure provides a readout circuit of a storage unit, wherein the storage unit comprises a write transistor, a read transistor, a read bit line and a read word line, the first end of the write transistor is electrically connected with the control end of the read transistor, the first end of the read transistor is electrically connected with the read bit line, the second end of the read transistor is electrically connected with the read word line, one end of the read word line is grounded, and the readout circuit comprises: a pre-charge control unit electrically connected with a selection control unit, comprising an energy storage sub-unit, configured to control the voltage of the energy storage sub-unit to be a first voltage through a first control voltage in a pre-charge stage, and stop the control of the first control voltage in a sensing stage; a selection control unit, configured to control the read bit line voltage of the read bit line to be a second voltage and control the read word line voltage of the read word line to be the second voltage through a second control voltage in the pre-charge stage, and obtain a third voltage of the energy storage sub-unit according to the change of the read word line voltage in the sensing stage, the voltage value of the effective level stored by the storage unit being the same as the voltage value of the second voltage; and a signal sensing unit, configured to obtain the readout result of the storage unit according to the third voltage and a reference voltage.
[0037] Figure 1 A block diagram of a readout circuit of a storage unit according to an embodiment of the present disclosure is shown schematically.
[0038] As shown in Figure 1 , the readout circuit 100 of the storage unit can include a pre-charge control unit 110, a selection control unit 120, and a signal sensing unit 130.
[0039] The storage unit can include a write transistor, a read transistor, a read bit line, and a read word line, the first end of the write transistor is electrically connected to the control end of the read transistor, the first end of the read transistor is electrically connected to the read bit line, the second end of the read transistor is electrically connected to the read word line, and one end of the read word line is grounded.
[0040] The pre-charge control unit 110 is electrically connected to the selection control unit 120 and includes an energy storage subunit, which can be configured to control the voltage of the energy storage subunit to be a first voltage through a first control voltage in a pre-charge phase, and stop the control of the first control voltage in a sensing phase.
[0041] The selection control unit 120 can be configured to control the read bit line voltage of the read bit line to be a second voltage and control the read word line voltage of the read word line to be the second voltage through a second control voltage in the pre-charge phase, and in the sensing phase, according to the change of the read word line voltage, obtain a third voltage of the energy storage subunit, and the voltage value of the effective level stored by the storage unit is the same as the voltage value of the second voltage.
[0042] The signal sensing unit 130 can be configured to obtain the readout result of the storage unit according to the third voltage and a reference voltage.
[0043] The storage unit can be a DRAM unit of a 2T0C structure. The storage unit can be multiple and arranged in an array form. The storage units in each row can share a read bit line, and the storage units in each column can share a read word line. The storage unit can also include a write bit line and a write word line. The write bit line can be electrically connected to the second end of the write transistor, and the write word line can be electrically connected to the control end of the write transistor. In the case of multiple storage units, the specific arrangement of the write bit line and the write word line can be set as needed, which is not the focus of the description of the embodiment of the present disclosure.
[0044] The voltage value of the second power supply voltage can be less than the voltage value of the first power supply voltage. For example, the second power supply voltage can be one of two-thirds, half, or one-fourth of the first power supply voltage.
[0045] In the pre-charge stage, the energy storage sub-unit can be charged under the control of the first control voltage, and the voltage of the energy storage sub-unit is the first voltage. The read bit line voltage of the read bit line and the read word line voltage of the control read word line are the second voltage under the control of the second control voltage, which can avoid the crosstalk of the readout current of the selected storage unit caused by the adjacent units of the storage unit.
[0046] In the sensing stage, the storage unit can store an effective level or an invalid level. The effective level can be a high level, and the invalid level can be a low level. When the storage unit stores the effective level, the read transistor can be in a conductive state. Since one end of the read word line is grounded, the voltage of the read word line changes. Due to the voltage difference between the read word line and the read bit line, the energy storage sub-unit can discharge to the read word line, and the voltage of the energy storage sub-unit changes to obtain a third voltage. When the storage unit stores the invalid level, the read transistor can be in a non-conductive state. Therefore, the voltage of the read word line does not change, and the voltage of the energy storage sub-unit also does not change, so that the third voltage of the energy storage sub-unit is obtained. At this time, the third voltage can be equal to the first voltage.
[0047] The third voltage can be compared with a reference voltage. When the third voltage is greater than the reference voltage, it can be represented that the readout result of the obtained storage unit is the invalid level. When the third voltage is less than or equal to the reference voltage, it can be represented that the readout result of the obtained storage unit is the effective level.
[0048] According to the embodiment of the present disclosure, the read word line and the read bit line of the storage unit are pre-charged by the second power supply voltage in the pre-charge stage, so that the read word line voltage of the read word line and the read bit line voltage of the read bit line are the second voltage, avoiding the current interference of the adjacent units of the storage unit. In the pre-charge stage, the energy storage sub-unit is charged to the first voltage by the first power supply voltage. In the sensing stage, the read word line voltage changes according to the storage state of the storage unit, so that the voltage of the energy storage sub-unit changes, the readout result of the storage unit is obtained, and the readout speed is improved. Pre-charging the read word line and the read bit line to the second voltage and pre-charging the energy storage sub-unit to the first voltage in the pre-charge stage can reduce the influence of the parasitic capacitance of the storage unit on the readout result.
[0049] Figure 2 The circuit schematic diagram of the readout circuit of the storage unit according to the embodiment of the present disclosure is schematically shown.
[0050] As shown in Figure 2 , the storage unit can include a first storage unit and a second storage unit. The first storage unit includes a first write transistor M W0 and a first read transistor M R0 , and the second storage unit includes a second write transistor M W1and a second read transistor M R1 , read bit lines (a first read bit line RBL0 and a second read bit line RBL1), read word lines (a first read word line RWL0 and a second read word line RWL1), a write bit line WBL, and a write word line WWL. The pre-charge control unit can include a first transistor M PCH , the energy storage subunit includes an energy storage capacitor C SO , the selection control unit includes a second transistor M SEL , a bit line selection transistor M TRS , and a word line selection transistor (a first word line selection transistor M RW_PRE0 and a second word line selection transistor M RW_PRE1 ). The signal sensing unit includes an amplifier AMP and a latch. One input terminal of the amplifier is connected with a reference voltage V THSA , the other input terminal is connected with the energy storage capacitor, and the output terminal can be directly output or connected with the latch to store the read result to the latch. The read circuit can further include a word line communication transistor (a first word line communication transistor M RW_DIS0 and a second word line communication transistor M RW_DIS1 ). Figure 2 The capacitor shown by the dashed line in the figure is a parasitic capacitor C BL .
[0051] In Figure 2 , a first terminal of the first transistor is connected with a first power supply voltage V DD , a second terminal of the first transistor and a first terminal of the energy storage capacitor are connected with the signal sensing unit, a control terminal of the first transistor is connected with a first control voltage, and a second terminal of the energy storage capacitor is grounded.
[0052] A first terminal of the second transistor is connected with the second terminal of the first transistor and the first terminal of the energy storage capacitor, a second terminal of the second transistor is connected with a first terminal of the bit line selection transistor, a second terminal of the bit line selection transistor is connected with the read bit line, a first terminal of the word line selection transistor is connected with a second power supply voltage V DD / 2, a second terminal of the word line selection transistor is connected with the read word line, and the second power supply voltage has the same voltage value as the second voltage. The word line communication transistor includes a first terminal connected with the read word line and a second terminal grounded.
[0053] The amplifier can be configured to output the read result of the storage unit according to a third voltage and the reference voltage; and the latch can be configured to save the read result of the storage unit. The word line communication transistor can be configured to be turned on in the pre-charge stage and the sensing stage.
[0054] Figure 3 A control timing diagram of the read circuit of the storage unit according to the embodiment of the present disclosure is schematically shown.
[0055] As shown in Figure 3 , the pre-charge phase can be before T3, and the sensing phase can be after T3.
[0056] Under the action of the enable signal ENA_A, the reading of the storage unit is started. In the pre-charge phase, the potentials of the control electrodes of the first transistor M PCH and the second transistor M SEL are respectively the first control voltage V DD + V th and the second control voltage V DD / 2 + V th , and the second transistor M SEL is in the saturation region. The SO node is charged to V DD , that is, the first voltage of the energy storage capacitor C SO is V DD . The bit line selection transistor and the word line selection transistor corresponding to the storage unit to be selected are opened, for example, the storage unit to be read out is the first storage unit, the bit line selection transistor M TRS and the first word line selection transistor M RW_PRE0 are opened, the read bit line voltage of the first read bit line RBL0 and the read word line voltage of the first read word line RWL0 are the second voltage V DD / 2. The voltage of the energy storage capacitor C SO is the first voltage. The first transistor M PCH is closed, and the bias voltage of the first transistor M PCH is reduced by V safe , entering the sensing phase.
[0057] According to embodiments of the present disclosure, in the case that the storage content of the storage unit is a valid level, in the sensing phase, the read word line voltage is reduced to 0, the energy storage sub-unit discharges to the read word line, the first voltage of the energy storage sub-unit is reduced, the first sub-voltage of the energy storage sub-unit is obtained, and in the case that the first sub-voltage is less than the reference voltage, the readout result of the storage unit is output.
[0058] As shown in Figure 2 and 3 , in the case that the storage content of the storage unit to be read out is a valid level, for example, the storage content of the first storage unit to be read out is a valid level, that is, the control electrode voltage of the first read transistor is V DD / 2, the first read transistor is in the on state, in the pre-charge phase, the first word line connection transistor is grounded, and the voltage of the first read word line is reduced to 0. In the sensing phase, since the first transistor is closed and the first read transistor is turned on, the energy storage capacitor discharges to the first read word line, the voltage of the node SO is reduced (dashed line), and in the case that the third voltage of the SO node is less than the reference voltage, the voltage of the output OUT changes.
[0059] According to an embodiment of the present disclosure, in the case that the storage content of the storage unit is the invalid level, in the sensing stage, the read word line voltage is unchanged, the second sub-voltage of the energy storage sub-unit is obtained, and according to the second sub-voltage and the reference voltage, the read result of the storage unit is output.
[0060] For example, the storage unit to be read is a second storage unit, the storage content of the second storage unit is the invalid level, that is, the control electrode voltage of the second read transistor is 0, and the second read transistor is in a non-conductive state. In the pre-charging stage, the voltages of the first read bit line and the second read word line are both unchanged. In the sensing stage, since the second read transistor is not conductive, the voltage of the node SO is unchanged, and the voltage of the output OUT is also unchanged.
[0061] In the sensing stage, the read bit line voltage of the read bit line has small fluctuation and can be regarded as unchanged. Therefore, the read current I cell is fixed. Therefore, the read circuit of the storage unit provided by the present disclosure has relatively stable read current when reading the storage unit, is not sensitive to the size of the parasitic resistance of the storage array, and is suitable for application in occasions with more storage units and high read speed requirements. Moreover, the influence of the fluctuation of the size of the parasitic resistance of the storage unit on the read current is suppressed, and the reliability of the read result is increased.
[0062] Moreover, since the read word line and the read bit line are pre-charged, the influence of the leakage current of the adjacent storage unit on the storage unit to be read is suppressed, the read margin of the storage unit to be read is improved, and the read result has high robustness.
[0063] Figure 4 A flowchart of a control method of a read circuit of a storage unit according to an embodiment of the present disclosure is schematically shown.
[0064] As shown in Figure 4 , the storage unit includes a write transistor, a read transistor, a read bit line and a read word line, the first end of the write transistor is electrically connected to the control end of the read transistor, the first end of the read transistor is electrically connected to the read bit line, the second end of the read transistor is electrically connected to the read word line, one end of the read word line is grounded, and the method includes operation S410~operation S430.
[0065] In operation S410, the pre-charging control unit is used to control, in the pre-charging stage, the voltage of the energy storage sub-unit to be the first voltage by the first control voltage, and in the sensing stage, the control of the first control voltage is stopped.
[0066] In operation S420, the read bit line voltage of the read bit line is controlled to the second voltage and the read word line voltage of the read word line is controlled to the second voltage in the pre-charge phase by the second control voltage, and the third voltage of the energy storage sub-unit is obtained according to the change of the read word line voltage in the sensing phase by the selection control unit, and the voltage value of the valid level stored by the storage unit is the same as the voltage value of the second voltage.
[0067] In operation S430, the readout result of the storage unit is obtained according to the third voltage and the reference voltage by the signal sensing unit.
[0068] According to embodiments of the present disclosure, operations S410-S430 can refer to the description of other embodiments of the present disclosure, which will not be repeated here.
[0069] According to embodiments of the present disclosure, the method can further include, in the case that the storage content of the storage unit is a valid level, in the sensing phase, the read word line voltage is lowered to 0, the storage unit discharges to the read word line, the first voltage of the energy storage sub-unit is lowered, and in the case that the first sub-voltage of the energy storage sub-unit is less than the reference voltage, the readout result of the storage unit is output.
[0070] In the case that the storage content of the storage unit is a valid level, the read transistor is in a conductive state, in the pre-charge phase, the word line communication transistor is grounded, and the voltage of the read word line is lowered to 0. In the sensing phase, since the first transistor is closed and the first read transistor is turned on, the energy storage sub-unit discharges to the read word line, the voltage of the energy storage sub-unit is lowered, the first sub-voltage of the energy storage sub-unit can be obtained, the first sub-voltage can be less than the reference voltage, and the readout result of the storage unit is output.
[0071] According to embodiments of the present disclosure, the method can further include, in the case that the storage content of the storage unit is an invalid level, in the sensing phase, the read word line voltage is unchanged, the second sub-voltage of the energy storage sub-unit is obtained, and the readout result of the storage unit is output according to the second sub-voltage and the reference voltage.
[0072] In the case that the storage content of the storage unit is an invalid level, the read transistor is in a non-conductive state, and in the sensing phase, since the read transistor is not conductive, the voltage of the energy storage sub-unit does not change, the second sub-voltage of the energy storage sub-unit can be obtained, the second sub-voltage can be the same as the first voltage, and thus the readout result of the storage unit is output according to the second sub-voltage and the reference voltage.
[0073] According to embodiments of the present disclosure, the read word line and the read bit line are pre-charged in the pre-charge phase, the influence of the leakage current of the adjacent storage unit on the storage unit to be read out is suppressed, and the readout result of the storage unit is output according to the voltage change of the energy storage sub-unit, thereby improving the readout speed.
[0074] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of this disclosure may be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.
[0075] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A readout circuit for a memory cell, wherein, The storage unit includes a write transistor, a read transistor, a read bit line, and a read word line. A first terminal of the write transistor is electrically connected to the control terminal of the read transistor. A first terminal of the read transistor is electrically connected to the read bit line. A second terminal of the read transistor is electrically connected to the read word line. One end of the read word line is grounded. The readout circuit includes: A precharge control unit, electrically connected to a selection control unit, includes an energy storage subunit and is configured to control the voltage of the energy storage subunit to a first voltage via a first control voltage during the precharge phase, and to stop controlling the first control voltage during the sensing phase. The control unit is selected and configured to, during the pre-charging phase, control the read bit line voltage of the read bit line to the second voltage and control the read word line voltage of the read word line to the second voltage via the second control voltage, and during the sensing phase, obtain the third voltage of the energy storage sub-unit based on the change of the read word line voltage, wherein the voltage value of the effective level stored in the storage unit is the same as the voltage value of the second voltage; The signal sensing unit is configured to obtain the readout result of the storage unit based on the third voltage and the reference voltage.
2. The readout circuit according to claim 1, wherein, The precharge control unit includes a first transistor, the energy storage subunit includes an energy storage capacitor, the first terminal of the first transistor is electrically connected to a first power supply voltage, the second terminal of the first transistor and the first terminal of the energy storage capacitor are electrically connected to the signal sensing unit, the control terminal of the first transistor is electrically connected to the first control voltage, and the second terminal of the energy storage capacitor is grounded.
3. The readout circuit according to claim 2, wherein, The selection control unit includes a second transistor, a bit line selection transistor, and a word line selection transistor; The first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the first terminal of the energy storage capacitor. The second terminal of the second transistor is electrically connected to the first terminal of the bit line select transistor. The second terminal of the bit line select transistor is electrically connected to the read bit line. The first terminal of the word line select transistor is electrically connected to the second power supply voltage. The second terminal of the word line select transistor is electrically connected to the read word line. The voltage value of the second power supply voltage is the same as the voltage value of the second voltage.
4. The readout circuit according to any one of claims 1 to 3, wherein, When the stored content of the storage unit is at the effective level, during the sensing phase, the read word line voltage drops to 0, the energy storage sub-unit discharges to the read word line, the first voltage of the energy storage sub-unit drops, the first sub-voltage of the energy storage sub-unit is obtained, and when the first sub-voltage is less than the reference voltage, the read result of the storage unit is output.
5. The readout circuit according to any one of claims 1 to 3, wherein, When the stored content of the storage unit is invalid, during the sensing phase, the read word line voltage remains unchanged, the second sub-voltage of the energy storage sub-unit is obtained, and the read result of the storage unit is output based on the second sub-voltage and the reference voltage.
6. The readout circuit according to any one of claims 1 to 3, wherein, The signal sensing unit includes: An amplifier configured to output the readout result of the memory cell based on the third voltage and the reference voltage; A latch is configured to store the read results of the storage unit.
7. The readout circuit according to any one of claims 1 to 3, further comprising: A word line connecting transistor, the word line connecting transistor including a first terminal electrically connected to the read word line and a second terminal grounded, configured to be turned on during the precharge phase and the sensing phase.
8. A control method for the readout circuit of a memory cell, wherein, The storage cell includes a write transistor, a read transistor, a read bit line, and a read word line. A first terminal of the write transistor is electrically connected to a control terminal of the read transistor. A first terminal of the read transistor is electrically connected to the read bit line. A second terminal of the read transistor is electrically connected to the read word line. One end of the read word line is grounded. The method includes: Using a pre-charge control unit, during the pre-charge phase, the voltage of the energy storage sub-unit is controlled to a first voltage by a first control voltage, and during the sensing phase, the control of the first control voltage is stopped; Using a selection control unit, during the pre-charging phase, the voltage of the read bit line is controlled to be the second voltage by a second control voltage, and the voltage of the read word line is controlled to be the second voltage. During the sensing phase, the third voltage of the energy storage sub-unit is obtained based on the change of the read word line voltage. The voltage value of the effective level stored in the storage unit is the same as the voltage value of the second voltage. Using a signal sensing unit, the readout result of the storage unit is obtained based on the third voltage and the reference voltage.
9. The method according to claim 8, further comprising: When the stored content of the storage unit is at the effective level, during the sensing phase, the read word line voltage drops to 0, the storage unit discharges to the read word line, the first voltage of the energy storage sub-unit drops, the first sub-voltage of the energy storage sub-unit is obtained, and when the first sub-voltage is less than the reference voltage, the read result of the storage unit is output.
10. The method according to claim 8 or 9, further comprising: When the stored content of the storage unit is invalid, during the sensing phase, the read word line voltage remains unchanged, the second sub-voltage of the energy storage sub-unit is obtained, and the read result of the storage unit is output based on the second sub-voltage and the reference voltage.