Memory full-dynamic fault detection algorithm based on March algorithm

Abstract

The invention discloses a detection algorithm for dynamic faults of a memory, and aims to realize 100% coverage of all non-associated static faults (including single-unit faults and coupling faults), non-associated dynamic single-unit faults (SCF) and Saa / Svv type double-unit dynamic faults (DCF). Based on the analysis of a system fault model, the designed March YZ algorithm is integrated with an optimized operation sequence, on the premise of reserving the fault activation, sensitization and detection capabilities, detection sequences of dTF, dWDF, dCFtr and dCFwd type dynamic faults are emphatically adjusted, and redundant read-write cycles are eliminated. The complexity of the March YZ algorithm is only 62n, is reduced by 8n compared with the existing March MD2 (70n), and is reduced by 4n compared with the March WY (66n); the test time is reduced by 11.4% and 6.1% respectively while full fault coverage is realized, the operation energy consumption of a memory is reduced by 5-15%, the area overhead of an MBIST circuit is reduced, and the method is adaptive to advanced process SoC (System on Chip) of 5nm and below, and can be applied to high-reliability scenes such as automotive electronics, aeronautics and astronautics, industrial control and the like.

Description

Technical Field

[0001] This invention belongs to the field of on-chip memory testing technology, specifically involving a highly reliable built-in memory self-test (MBIST) core algorithm, which is suitable for dynamic fault detection of embedded memory in advanced nanoscale system-on-chip (SoC). Background Technology

[0002] As semiconductor manufacturing nodes continue to shrink to 3nm and below, embedded memory accounts for over 70% of SoCs, and its reliability directly determines system yield and lifespan. The probability of manufacturing defects and operational failures has increased significantly, requiring rigorous testing to maintain a low defect count (DPM) level.

[0003] Built-in Memory Test-Installation (MBIST) has become a mainstream testing solution due to its low area overhead and suitability for mass production, and the March algorithm is the core of MBIST. Mature algorithms already exist for static faults (single-cell fault SAF, transition fault TF, etc., and coupled faults CFid, CFst, etc.), such as March SS (22n) and March MSS (18n), which can achieve full coverage of static faults. Dynamic faults (activated by operation sequences, such as dynamic coupled fault dCF and two-operation single-cell faults) are becoming increasingly prominent, and existing algorithms have limitations: March MD2 (70n) achieves full coverage of dynamic faults, but its complexity is high; March WY (66n) reduces complexity but still has redundant read / write cycles, making it unsuitable for the low-power and small-area requirements of advanced processes. Therefore, there is an urgent need for a March algorithm that balances 100% dynamic fault coverage with low complexity and low power consumption. Summary of the Invention

[0004] This invention aims to solve the problems of incomplete dynamic fault coverage and excessive complexity in the existing March algorithm, and provides a memory full dynamic fault detection algorithm with low complexity (62n), full fault coverage, and adaptability to advanced manufacturing processes.

[0005] Based on dynamic fault sensitivity and detection logic, five types of FP merging and simplification rules are designed to eliminate redundant reads and writes. Rule 1: Utilize the final state of FP1 to reuse the initial state of FP2, reducing initial write operations; Rule 2: FPs with the same initial state share the operation sequence, reducing duplicate sequences; Rule 3: Utilize the detection sequence of FP1 (D... FP1 ) as the initial state of FP2 (S1) FP2 Rule 4: Reuse the sensitization and detection sequences of FP1 as the initial sequence of FP2 to eliminate redundant sequences; Rule 5: Reuse the D sequence from the previous detection. FP This serves as the initial read for the next detection, avoiding the need for additional read operations.

[0006] Furthermore, the designed algorithm is for the detection of dRDF type dynamic faults. The corresponding fault primitives are <xWyRy / ~y / ~y> and <xRxRx / ~x / ~x>. After performing read / write operations on the faulty unit and then immediately performing a read operation, the value of the storage unit will be flipped. In the algorithm, the detection is achieved by adding a read operation after the write / read sequence (such as M2(11), M2(12); M2(12)).

[0007] Furthermore, the designed algorithm is for the detection of dIRF type dynamic faults. The corresponding fault primitives are <xWyRy / y / ~y> and <xRxRx / x / ~x>. After performing read / write operations on the faulty unit and then performing a read operation, the read value of the storage unit will be incorrect, while the actual unit value remains unchanged. The algorithm is detected by adding a read operation after the write / read sequence (such as M2(3), M2(4); M2(4)).

[0008] Furthermore, the designed algorithm is for the detection of dDRDF type dynamic faults. The corresponding fault primitives are <xWyRy / ~y / y> and <xRxRx / ~x / x>. Based on the write / read operation on the faulty unit and then immediately performing a read operation, the value of the storage unit will be flipped, but the read value of the storage unit is not the faulty value, and an additional read operation is required to achieve detection. In the algorithm, the detection is achieved by adding two read operations after the write / read sequence (such as M2(3), M2(4); M2(5)).

[0009] Furthermore, the designed algorithm is for the detection of dTF and dWDF type dynamic faults. The corresponding fault primitives are mainly <xWxWy / ~y / -> and <xWyW(~y) / y / ->. Since there are multiple write operations of specific sequences in this type of fault, an efficient sequence writing method is designed: W1W0, W0W1W1W1, and W0W1, W1W0W0W0, which fully utilizes the FP rule to optimize the algorithm. Writing a continuous sequence to the faulty unit makes the value of the storage unit flip. In the algorithm, the detection is achieved by adding a read operation after the continuous write sequence (such as M1(2), M1(3); M1(4)).

[0010] Furthermore, the designed algorithm is for the detection of dynamic interference coupling faults. It is necessary to consider the address relationship of the coupling unit (a>v / a<v) and the 0 / 1 data background. The algorithm completes ascending and descending operations in the dual data background through M1 - M4, achieving full coverage of dynamic coupling faults. The detection of single - unit dynamic faults, double - unit dynamic faults, and double - unit dynamic interference coupling faults by the algorithm can be seen in Table 1, Table 2, and Table 3.

[0011] The advantages and beneficial effects of the present invention are as follows:

[0012] 1. The above-mentioned method of the present invention can achieve the following beneficial effects: 100% coverage of non-associated static faults (single-cell, coupled faults), non-associated dynamic single-cell faults (SCF), and Saa and Svv type dual-cell dynamic faults (DCF), and completely cover key dynamic fault types such as dTF, dWDF, dCFtr, and dCFwd. The coverage is better than some traditional algorithms.

[0013] 2. The complexity of the March YZ(62n) algorithm of this invention is reduced by 8n compared with March MD2(70n) and by 4n compared with March WY(66n), and the testing time and energy consumption are reduced simultaneously.

[0014] 3. The simplified operation sequence of this invention reduces the area overhead of the built-in memory self-test (MBIST), adapts to the integration requirements of advanced nanometer process SoCs, and balances performance and hardware cost. Attached Figure Description

[0015] Table 1 shows the detection of dynamic faults in a single cell using the March YZ algorithm.

[0016] Table 2 shows the detection of dynamic faults in two-cell systems using the March YZ algorithm.

[0017] Table 3 shows the detection of dynamic disturbance coupling faults in dual-unit systems using the March YZ algorithm.

[0018] Table 4 shows the detection coverage of the March YZ algorithm for dynamic faults.

[0019] Figure 1 This demonstrates the use of the March YZ algorithm for circuit simulation detection of dRDF type faults.

[0020] Figure 2 This demonstrates the circuit simulation detection of dDRDF type faults using the March YZ algorithm.

[0021] Figure 3 This demonstrates the use of the March YZ algorithm for circuit simulation detection of dIRF type faults.

[0022] Figure 4 This demonstrates the use of the March YZ algorithm for circuit simulation detection of dTF type faults.

[0023] Figure 5 Circuit simulation detection of dWDF type faults using the March YZ algorithm;

[0024] Figure 6 This is a schematic diagram of the algorithm of the present invention. Detailed Implementation

[0025] Based on the MBIST circuit architecture (including the MBIST controller, memory interface, comparator, and data register), the MarchYZ algorithm executes as follows:

[0026] 1. Initialization (M0): Performed on all memory units. The operation initializes the data units to 0, establishing a unified data background.

[0027] 2. Ascending Detection 1 (M1): Executes in ascending address order (R0,W1,W0,R0,R0,W0,R0,W1,R1,W0,R0,W0,W1,W1,W1,R1,R1), sensitizing and detecting single-cell dynamic faults. At the same time, it provides a sequence of ascending writes in a 0-data background for the detection of dynamic coupling faults. During the write process, a data detection background is constructed where the low address is data 1 and the high address is data 0.

[0028] 3. Ascending Detection 2 (M2): Executes in ascending order of address (R1,W0,W1,R1,R1,W1,R1,W1,W0,W0,W0,R0,R0), sensitizing and detecting single-cell dynamic faults. At the same time, it provides a sequence of ascending writes in a 1-data background for the detection of dynamic coupling faults. During the write process, a data detection background is constructed where the low address is data 0 and the high address is data 1.

[0029] 4. Descending Order Detection 1 (M3): Executes in descending order of address (R0,W1,W0,R0,R0,W0,R0,W1,R1,W0,R0,W0,W1,W1,W1,R1,R1), sensitizing and detecting single-cell dynamic faults. At the same time, it provides a sequence written in descending order against a 0 data background for the detection of dynamic coupling faults. During the writing process, a data detection background is constructed where the low address is data 0 and the high address is data 1.

[0030] 5. Descending Order Detection 2 (M4): Executes in descending order of address (R1,W0,W1,R1,R1,W1,R1,W1,W0,W0,W0,R0,R0), sensitizing and detecting single-cell dynamic faults. At the same time, it provides a sequence written in descending order against a 0 data background for the detection of dynamic coupling faults. During the writing process, a data detection background is constructed where the low address is data 1 and the high address is data 0.

[0031] 6. Result Reading (M5): Execution The operation involves reading the status of all data units, comparing it with the expected value, and determining whether a fault has occurred.

[0032] The simulation verification of the algorithm of this invention will be clearly and thoroughly described below with reference to specific simulation verification examples. The described simulation examples are for the verification of some dynamic faults of dRDF, dDRDF, dIRF, dTF, and dWDF.

[0033] For dRDF type faults, modeling and analysis are performed on the fault primitive <0w1r1 / ↓ / 0>, based on... Figure 1 Fault simulation shows that the fault address is 0110_0100. During the first to fifth clock cycles shown in the figure, read 0, write 0, read 0, write 1, and read 1 operations were performed respectively, and the detection sequence corresponds to the M2(3), M2(4), and M2(4) sequences in the algorithm. Due to the occurrence of dRDF fault, the data changed, and the read data was inconsistent with the expected value expected_data. The fail signal was pulled high, and the MBIST circuit successfully detected the dRDF type fault.

[0034] For dDRDF type faults, modeling and analysis are performed on the fault primitive <0w1r1 / ↓ / 1>, based on... Figure 2 Fault simulation shows that the fault address is 0110_0100. In the figure, read 1, write 0, write 1, read 1, read 1 were performed in sequence, and the detection sequence corresponds to the M2(3), M2(4), and M2(5) sequences in the algorithm. Due to the occurrence of the dDRDF fault, the read data is inconsistent with the expected value expected_data, and the MBIST circuit successfully detected the dDRDF type fault.

[0035] For dIRF type faults, modeling and analysis were performed on the fault primitive <0w1r1 / 1 / 0>, with the fault address being 0110_0100. The graph shows read 0, write 0, read 0, write 1, and read 1 operations performed sequentially. The detection sequences correspond to the sensitized detection sequences M1(8), M1(9), and M1(9) in the algorithm. Because the occurrence of a dIRF fault resulted in erroneous data being read, and the read data was inconsistent with the expected value (expected_data), the MBIST circuit successfully detected the dIRF type fault.

[0036] For dTF type faults, modeling and analysis are performed on the fault primitive <0w1w0 / 1 / ->, based on fault simulation. Figure 4 It can be seen that the fault address is 0110_0100. In the figure, no operation, read 0, write 1, write 0, read 0 operations were performed in sequence, and the detection sequence corresponds to the M1(2), M1(3), and M1(4) sequences in the algorithm. Due to the occurrence of dTF fault, the data value changed, and the read data was inconsistent with the expected value expected_data. The MBIST circuit successfully detected the dIRF type fault.

[0037] For dWDF type faults, modeling and analysis are performed on the fault primitives <0w1w1 / ↓ / ->, based on fault simulation. Figure 5It can be seen that the fault address is 0110_0100. In the figure, read 0, write 0, write 1, write 1, write 1 and read 1 operations were performed in sequence, and the detection sequence corresponds to the sequence M1(13), M1(14) and M1(16) in the algorithm. Due to the occurrence of the dWDF fault, the data value changed, and the read data was inconsistent with the expected value expected_data. The MBIST circuit successfully detected the dWDF type fault.

[0038] Secondly, for the detection of dynamic interference coupling faults, the address positions of the two coupling units need to be considered, and ascending and descending write and read operations need to be completed under both 0 and 1 data backgrounds. Under the condition that the single-unit dynamic faults can be detected, the algorithm completes ascending and descending operations under dual data backgrounds through M1-M4 to achieve full coverage of dynamic coupling faults. Thus, the algorithm can achieve 100% coverage of non-associated static faults (including single-unit faults and coupling faults), non-associated dynamic single-unit faults (SCF), and Saa and SVV type dual-unit faults (DCF). The detection coverage of the March YZ algorithm for dynamic faults can be seen in Table 4.

[0039]

[0040]

[0041] Table 1. Detection of single-cell dynamic faults using the March YZ algorithm.

[0042]

[0043]

[0044]

[0045] Table 2 shows the detection of two-cell dynamic faults using the March YZ algorithm.

[0046]

[0047]

[0048] Table 3 shows the detection of dynamic disturbance coupling faults in two-unit systems using the March YZ algorithm.

[0049]

[0050]

[0051] Table 4 shows the detection range of the March YZ algorithm for dynamic faults.

Claims

1. A memory full dynamic fault detection algorithm based on March algorithm, characterized in that: The algorithm is integrated in a memory built-in self-test (MBIST) circuit, and a test controller is used to execute an optimized operation sequence to interact with a memory under test to achieve fault detection. The optimized operation sequence is designed based on a combination and simplification rule of fault primitives (FPs, including a data state context x / y, a sensitization operation sequence S1 / S2, and a detection operation sequence D FP ) to retain the activation, sensitization, and detection capabilities for non-associated static faults, non-associated dynamic single-cell faults (SCF), and Saa / Svv type double-cell dynamic faults (DCF), adjust the detection sequences of dTF, dWDF, dCFtr, and dCFwd type dynamic faults, eliminate redundant read and write cycles, and achieve 100% fault coverage with a test complexity of 62n.

2. The algorithm of claim 1, wherein, The merging rule of the FPs includes: for two failure detection requirements, FP(xS1 FP1 S2 FP1 D FP1 and yS1 FP2 S2 FP2 D FP2 , if the final cell state of FP1 is y, then yS1 FP2 S2 FP2 D FP2 is added to xS1 FP1 S2 FP1 D FP1 to form xS1 FP1 S2 FP1 D FP1 S1 FP2 S2 FP2 D FP2 to detect FP1 and FP2 simultaneously.

3. The algorithm of claim 1, wherein, The simplification rules for the FPs include: for two FPs (S1 FP1 S2 FP1 D FP1 and S1 FP2 S2 FP2 D FP2 ), if S1 FP1 = S2 FP1 = S1 FP2 = S2 FP2 , then only one set of operation sequences is kept, through xS1 FP1 / 2 S2 FP1 / 2 D FP1 / 2 detecting FP1 and FP2 simultaneously.

4. The algorithm of claim 1, wherein, The merging rules of the FPs further include: for two failure detection demanding FPs (S1FP1S2FP1DFP1 and S1FP2S2FP2DFP2), if D FP1 =S1 FP2 , then remove S1 FP2 , add S2 FP1 after S1 FP1 , form S1 FP1 S2 FP2 D FP2 , and add S2 FP1 D FP1 after S1 FP1 S2 FP2 D FP2 to simultaneously detect FP1 and FP2.

5. The algorithm of claim 1, wherein, The simplified rules for the FP also include: for two FP of failure detection requirements (S1 FP1 S2 FP1 D FP1 and S1 FP2 S2 FP2 D FP2 ), if S2 FP1 D FP1 =S1 FP2 S2 FP2 , then remove S1 FP2 S2 FP2 , add D FP1 after D FP2 to detect FP1 and FP2 simultaneously.

6. The algorithm of claim 1, wherein, For dCFds type fault, the last read operation (D FP ) of the previous fault detection is directly used as the first operation of the next fault detection, without adding a new read operation.

7. The algorithm of claim 1, wherein, the operation sequence of the March YZ algorithm is specifically:

Images