High-precision sampling power tube charging current circuit and method and electronic equipment

Abstract

The embodiment of the invention provides a high-precision sampling power tube charging current circuit and method and electronic equipment, a plurality of sampling circuits which are arranged in parallel are added on the basis of the prior art, and the offset voltage of the newly added sampling circuits is trimmed, so that the influence of the threshold voltage of a sampling tube can be reduced, and the sampling efficiency is improved. Therefore, the precision of the charging current sampling circuit of the first power tube can be improved, so that the charging efficiency is improved.

Description

Technical Field

[0001] The embodiments of this application belong to the field of circuit technology, and in particular relate to a high-precision sampling power transistor charging current circuit, method and electronic device. Background Technology

[0002] During the charging process of electronic products, it is necessary to accurately sample the charging current of the power transistor. Figure 1 In the sampling power transistor charging current circuit shown, the sampling transistor and the power transistor have different threshold voltages, which causes a deviation in the ratio of the sampling current to the power transistor current, thus affecting the accuracy of the power transistor charging current. Summary of the Invention

[0003] In order to solve or alleviate the technical problems in the prior art, in a first aspect, embodiments of this application provide a sampling power transistor charging current circuit, including: a first power transistor and a plurality of sampling circuits arranged in parallel;

[0004] Each sampling circuit includes a sampling branch and a sampling tube. The first end of the sampling tube is connected to the negative input terminal of the sampling branch, the second end of the sampling tube is connected to the power supply, and the third end of the sampling tube is connected to the third end of the first power tube.

[0005] The first terminal of the first power transistor is connected to the positive input terminal of each sampling branch and the battery to be charged, and the second terminal of the power transistor is connected to the power supply.

[0006] Each sampling branch output terminal is connected to a resistor, and the resistor is connected to a ground terminal.

[0007] When current is sampled at the output terminal of each of the sampling branches, a corresponding voltage will be generated across the resistor, and the charging current of the first power transistor will be determined by the voltage.

[0008] In a preferred embodiment of this application, the third terminal of the power transistor and the third terminal of each sampling transistor are connected to the output of the charge pump.

[0009] In a preferred embodiment of this application, each sampling branch includes an operational amplifier and a second power transistor;

[0010] The positive input terminal of the operational amplifier is connected to the first terminal of the power transistor, the negative input terminal of the operational amplifier is connected to the first terminal of the corresponding sampling transistor, the output terminal of the operational amplifier is connected to the third terminal of the second power transistor, the first terminal of the second power transistor is connected to the first terminal of the corresponding sampling transistor, and the second terminal of the second power transistor is connected to the resistor.

[0011] In a preferred embodiment of this application, both the first power transistor and the sampling transistor are NMOS transistors, and the second power transistor is a PMOS transistor;

[0012] The first end of the power transistor, the first end of the sampling transistor, and the first end of the second power transistor are all sources; the second end of the power transistor, the second end of the sampling transistor, and the second end of the second power transistor are all drains; and the first end of the power transistor, the first end of the sampling transistor, and the first end of the second power transistor are all gates.

[0013] Secondly, embodiments of this application also provide a high-precision sampling method for power transistor charging current, characterized in that the method is implemented using a circuit including the one provided in the first aspect, and the method includes:

[0014] The sampling circuit samples the current flowing through the first terminal of the corresponding sampling tube; the current sampled by each sampling circuit flows to the resistor to generate a voltage, and the charging current flowing through the first power tube is determined by the voltage.

[0015] Thirdly, embodiments of this application also provide an electronic device, including the high-precision sampling power tube charging current circuit provided in the first aspect.

[0016] Compared with the prior art, the embodiments of this application provide a high-precision sampling circuit, method and electronic device for power transistor charging current. By adding multiple parallel sampling circuits on the basis of the prior art and adjusting the offset voltage of the newly added sampling circuits, the influence of the sampling transistor threshold voltage can be reduced, and the deviation of the sampling current will also be reduced. Therefore, this application can improve the accuracy of the first power transistor sampling charging current circuit, thereby improving the charging efficiency. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0018] Figure 1 This is a circuit diagram of a sampling power transistor charging current circuit provided by existing technology;

[0019] Figure 2 This is a circuit diagram of a sampling power transistor charging current circuit provided in an embodiment of this application. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0021] like Figure 1 As shown, a sampling power transistor charging current circuit is provided in the prior art. In the prior art circuit, the first power transistor M0 and the sampling transistor M1 are both NMOS. The sampling transistor M1 and the operational amplifier A1 form a sampling circuit. The output current of the sampling circuit is the sampling current during the charging process of the first power transistor.

[0022] In the prior art, the accuracy of the sampling current of the first power transistor M0 is limited by two factors: (1) the threshold voltage of the sampling transistor M1. Due to layout reasons, the threshold voltage of the sampling transistor M1 will differ from the threshold voltage of the first power transistor M0, which will cause the magnitude of the sampling current to change, thus affecting the accuracy of the charging current of the first power transistor M0. (2) the operational amplifier offset voltage of the operational amplifier A1, which will cause the ratio of the sampling transistor to the first power transistor M0 to change, thus affecting the accuracy of the charging sampling current of the first power transistor.

[0023] To address the problems in the existing technology, the first aspect is, such as Figure 2 As shown, this application embodiment provides a sampling power transistor charging current circuit, including: a first power transistor M0 and multiple sampling circuits connected in parallel; in this application embodiment, a total of 4 sampling circuits are set in parallel, but other numbers of multiple sampling circuits connected in parallel can also be set, and this application implementation does not limit this.

[0024] Each sampling circuit includes a sampling branch and a sampling tube. The first end of the sampling tube is connected to the negative input terminal of the sampling branch, the second end of the sampling tube is connected to power supply 1, and the third end of the sampling tube is connected to the third end of the first power tube.

[0025] The first terminal of the first power transistor M0 is connected to the positive input terminal of each sampling branch and the battery to be charged, and the second terminal of the power transistor is connected to the power supply 1.

[0026] Each sampling branch includes an operational amplifier and a second power transistor;

[0027] The positive input terminal of the operational amplifier is connected to the first terminal of the second power transistor, the negative input terminal of the operational amplifier is connected to the first terminal of the corresponding sampling transistor, the output terminal of the operational amplifier is connected to the third terminal of the second power transistor, the first terminal of the second power transistor is connected to the first terminal of the corresponding sampling transistor, and the second terminal of the second power transistor is connected to the resistor.

[0028] Each sampling branch output terminal is connected to a resistor, and the resistor is connected to a ground terminal.

[0029] When current is sampled at the output terminal of each of the sampling branches, a corresponding voltage will be generated across the resistor, and the charging current of the first power transistor will be determined by the voltage.

[0030] like Figure 2 As shown, the technical solution of this application is described in detail below with four sampling circuits:

[0031] The four sampling circuits are the first sampling branch 4, the second sampling branch 5, the third sampling branch 6, and the fourth sampling branch 7; the first power transistor M0, the first sampling transistor M1, the second sampling transistor M2, the third sampling transistor M3, and the fourth sampling transistor M4 are all NMOS transistors; the first terminal of the first power transistor M0, the first terminal of the first sampling transistor M1, the first terminal of the second sampling transistor M2, the first terminal of the third sampling transistor M3, and the first terminal of the fourth sampling transistor M4 are all sources, the second terminals of the first power transistor M0, the second terminals of the first sampling transistor M1, the second terminals of the second sampling transistor M2, the second terminals of the third sampling transistor M3, and the second terminals of the fourth sampling transistor M4 are all drains, and the third terminals of the first power transistor M0, the third terminals of the first sampling transistor M1, the third terminals of the second sampling transistor M2, the third terminals of the third sampling transistor M3, and the third terminals of the fourth sampling transistor M4 are all gates.

[0032] Specifically, the sampling power transistor charging current circuit includes: first power transistor M0, first sampling transistor M1, second sampling transistor M2, third sampling transistor M3, fourth sampling transistor M4, first sampling branch 4, second sampling branch 5, third sampling branch 6, and fourth sampling branch 7.

[0033] The source of the first power transistor M0 is connected to the positive input terminal of the first sampling branch 4, the positive input terminal of the second sampling branch circuit 5, the positive input terminal of the third sampling branch 6, and the positive input terminal of the fourth sampling branch 7, respectively. The source of the first sampling transistor M1 is connected to the negative input terminal of the first sampling branch 4. The source of the second sampling transistor M2 is connected to the negative input terminal of the second sampling branch 5. The source of the third sampling transistor M3 is connected to the negative input terminal of the third sampling branch 6. The source of the fourth sampling transistor M4 is connected to the negative input terminal of the fourth sampling branch 7.

[0034] The drains of the first power transistor M0, the first sampling transistor M1, the second sampling transistor M2, the third sampling transistor M3, and the fourth sampling transistor M4 are all connected to power supply 1.

[0035] The gates of the first power transistor M0, the first sampling transistor M1, the second sampling transistor M2, the third sampling transistor M3, and the fourth sampling transistor M4 are all connected to the output terminal of the charge pump 3. The charge pump 3 is used to generate an output voltage that is larger than the input voltage and then deliver it to the gates of the first power transistor M0, the first sampling transistor M1, the second sampling transistor M2, the third sampling transistor M3, and the fourth sampling transistor M4.

[0036] The output terminals of the first sampling branch 4, the second sampling circuit 5, the third sampling branch 6, and the fourth sampling branch 7 are all connected to the resistor R; the resistor R is connected to the ground terminal GND; the source of the first power transistor M0 is connected to the battery 2 to be charged.

[0037] The first sampling branch 4 includes a first budget amplifier A1 and a second power transistor M5; the second sampling branch 5 includes a second budget amplifier A2 and a second power transistor M6; the third sampling branch 6 includes a third budget amplifier A3 and a third power transistor M7; and the fourth sampling branch 7 includes a fourth budget amplifier A4 and a fourth power transistor M8.

[0038] The positive input terminal of the first operational amplifier A1 is connected to the first terminal of the second power transistor M5, the negative input terminal of the first operational amplifier A1 is connected to the first terminal of the corresponding sampling transistor M1, the output terminal of the first operational amplifier A1 is connected to the third terminal of the second power transistor M5, the first terminal of the second power transistor M5 is connected to the first terminal of the corresponding sampling transistor M1, and the second terminal of the second power transistor M5 is connected to the resistor R.

[0039] The positive input terminal of the second operational amplifier A2 is connected to the first terminal of the second power transistor M6, the negative input terminal of the second operational amplifier A2 is connected to the first terminal of the corresponding sampling transistor M2, the output terminal of the second operational amplifier A2 is connected to the third terminal of the second power transistor M6, the first terminal of the second power transistor M6 is connected to the first terminal of the corresponding sampling transistor M2, and the second terminal of the second power transistor M6 is connected to the resistor R.

[0040] The positive input terminal of the third operational amplifier A3 is connected to the first terminal of the second power transistor M7, the negative input terminal of the third operational amplifier A3 is connected to the first terminal of the corresponding sampling transistor M3, the output terminal of the third operational amplifier A3 is connected to the third terminal of the second power transistor M7, the first terminal of the second power transistor M7 is connected to the first terminal of the corresponding sampling transistor M3, and the second terminal of the second power transistor M7 is connected to the resistor R.

[0041] The positive input terminal of the fourth operational amplifier A4 is connected to the first terminal of the second power transistor M7, the negative input terminal of the fourth operational amplifier A4 is connected to the first terminal of the corresponding sampling transistor M1, the output terminal of the fourth operational amplifier A4 is connected to the third terminal of the second power transistor M7, the first terminal of the second power transistor M7 is connected to the first terminal of the corresponding sampling transistor M4, and the second terminal of the second power transistor M7 is connected to the resistor R.

[0042] When the output terminals of the first sampling branch 4, the second sampling circuit 5, the third sampling branch 6, and the fourth sampling branch 7 all sample current, a voltage will be generated across the resistor R by the current. The charging current of the first power transistor M0 can be obtained by combining the voltage and the resistance value according to Ohm's law.

[0043] In this embodiment of the application, when the first sampling tube M1 samples the current of the first power tube M0, the second sampling tube M2 samples the current of the first power tube M0, the third sampling tube M3 samples the current of the power tube M0, and the fourth sampling tube M4 samples the current of the first power tube M0, the sum of the four sampling currents is the final charging current of the first power tube M0.

[0044] In this embodiment, the sampling voltage is obtained when the final sampled current flows onto the resistor R. The charging current during the charging process of the battery 2 can be obtained through the sampling voltage.

[0045] In this embodiment, the accuracy of the sampling current of the first power transistor M0 depends on the difference in threshold voltage between the sampling transistor and the power transistor. Compared with the prior art, this application increases the accuracy of the sampling current of the first power transistor M0 by adding a second sampling transistor M2, a third sampling transistor M3, and a fourth sampling transistor M4 to reduce the difference in threshold voltage between the sampling transistor and the power transistor.

[0046] In this embodiment, the charging current I1 of the first power transistor M0 is calculated using the following formula: I1 = un * Cox * W1 / L1 [(Vgs - Vth1) * Vds - 0.5 * Vds * Vds], where un is the electron mobility, Cox is the gate oxide capacitance per unit area, W1 / L1 is the channel width-to-length ratio of the first power transistor M0, Vgs is the gate-source voltage of the first power transistor M0, Vth1 is the threshold voltage of the power transistor, and Vds is the drain-source voltage of the first power transistor M0. The sampling current I2 of each sampling transistor is calculated using the following formula: I2 = un * Cox * W2 / L2 [(Vgs - Vth2) * Vds - 0.5 * Vds * Vds], where un is the electron mobility, Cox is the gate oxide capacitance per unit area, W2 / L2 is the channel width-to-length ratio of the sampling transistor, Vgs is the gate-source voltage of the sampling transistor, Vth2 is the threshold voltage of the sampling transistor, and Vds is the drain-source voltage of the sampling transistor. As can be seen from the above formula, by reducing the difference between Vth1 and Vth2, the ratio error between the charging current I1 of the first power transistor M0 and the sampling current I2 of the sampling transistor is reduced. Therefore, this application uses the second sampling transistor M2, the third sampling transistor M3, and the fourth sampling transistor M4 to reduce the difference between Vth2 and Vth1, thereby improving the accuracy of the sampling current.

[0047] Secondly, embodiments of this application also provide a method for sampling the charging current of a power transistor, the method being implemented using the circuit described in the first aspect, the method comprising:

[0048] The first sampling circuit 4, the second sampling circuit 5, the third sampling circuit 6 and the fourth sampling circuit 7 are used to sample the current flowing through the first end of the first sampling tube M1, the first end of the second sampling tube M2, the first end of the third sampling tube M3 and the first end of the fourth sampling tube M4, respectively.

[0049] The current sampled by the first sampling circuit 4, the second sampling circuit 5, the third sampling circuit 6, and the fourth sampling circuit 7 all flow to the resistor R to generate a sampling voltage, so as to determine the charging current flowing through the first power transistor M0.

[0050] Secondly, embodiments of this application also provide a high-precision sampling method for power transistor charging current, characterized in that the method is implemented using a circuit including the one provided in the first aspect, and the method includes:

[0051] The sampling circuit samples the current flowing through the first terminal of the corresponding sampling tube; the current sampled by each sampling circuit flows to the resistor to generate a voltage, and the charging current flowing through the first power tube is determined by the voltage.

[0052] Thirdly, embodiments of this application also provide an electronic device, including the high-precision sampling power tube charging current circuit provided in the first aspect.

[0053] Compared with the prior art, the embodiments of this application provide a high-precision sampling circuit, method and electronic device for power transistor charging current. By adding multiple parallel sampling circuits on the basis of the prior art and adjusting the offset voltage of the newly added sampling circuits, the influence of the sampling transistor threshold voltage can be reduced, and the deviation of the sampling current will also be reduced. Therefore, this application can improve the accuracy of the first power transistor sampling charging current circuit, thereby improving the charging efficiency.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A circuit for sampling the charging current of a power transistor, characterized in that, include: The first power transistor and multiple sampling circuits connected in parallel; Each sampling circuit includes a sampling branch and a sampling tube. The first end of the sampling tube is connected to the negative input terminal of the sampling branch, the second end of the sampling tube is connected to the power supply, and the third end of the sampling tube is connected to the third end of the first power tube. The first terminal of the first power transistor is connected to the positive input terminal of each sampling branch and the battery to be charged, and the second terminal of the power transistor is connected to the power supply. Each sampling branch output terminal is connected to a resistor, and the resistor is connected to a ground terminal. When current is sampled at the output terminal of each of the sampling branches, a corresponding voltage will be generated across the resistor, and the charging current of the first power transistor will be determined by the voltage.

2. The sampling power transistor charging current circuit as described in claim 1, characterized in that, The third terminal of the power transistor and the third terminal of each sampling transistor are connected to the output of the charge pump.

3. The sampling power transistor charging current circuit as described in claim 1, characterized in that, Each sampling branch includes an operational amplifier and a second power transistor; The positive input terminal of the operational amplifier is connected to the first terminal of the power transistor, the negative input terminal of the operational amplifier is connected to the first terminal of the corresponding sampling transistor, the output terminal of the operational amplifier is connected to the third terminal of the second power transistor, the first terminal of the second power transistor is connected to the first terminal of the corresponding sampling transistor, and the second terminal of the second power transistor is connected to the resistor.

4. The sampling power transistor charging current circuit as described in claim 1, characterized in that, Both the first power transistor and the sampling transistor are NMOS transistors, and the second power transistor is a PMOS transistor; The first terminal of the first power transistor, the first terminal of the sampling transistor, and the first terminal of the second power transistor are all sources; the second terminals of the first power transistor, the second terminal of the sampling transistor, and the second terminal of the second power transistor are all drains; and the first terminals of the first power transistor, the first terminal of the sampling transistor, and the first terminal of the second power transistor are all gates.

5. A high-precision sampling method for power transistor charging current, characterized in that, The method is implemented using the circuit described in any one of claims 1 to 4, and the method includes: The sampling circuit samples the current flowing through the first terminal of the corresponding sampling tube; the current sampled by each sampling circuit flows to the resistor to generate a voltage, and the charging current flowing through the first power tube is determined by the voltage.

6. An electronic device, characterized in that, Includes the high-precision sampling power transistor charging current circuit as described in any one of claims 1 to 4.

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