A low quiescent current start-up circuit

Abstract

The application relates to a low static current starting circuit, which comprises a second resistor, a first transistor and a first resistor connected in series between a power supply and the ground, the gate of the first transistor is connected to an enable voltage, and further comprises a holding circuit for maintaining the static current of the starting circuit at a set low current, the holding circuit comprises a second transistor and a third transistor as control elements, and is configured to form a negative feedback loop for the gate of the first transistor in cooperation with a third resistor, a fourth resistor and a fifth resistor, so as to offset the voltage influence of the change of the enable voltage on the gate of the first transistor and stabilize the voltage of the gate of the first transistor. The application provides a low static current starting circuit, a negative feedback loop is formed by introducing a holding circuit, the influence of the change of the enable voltage on the voltage of the gate of the first transistor is offset, the static current is stabilized, the static current can be maintained at a low level when the enable voltage changes, and the advantages of realizing stable low-power work are achieved.

Description

A low quiescent current startup circuit Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a low quiescent current startup circuit. Background Technology

[0002] The startup circuit, as a key functional module in analog integrated circuits, is widely used in power management, signal processing, and system initialization. Its core function is to generate a stable startup signal during power-up to activate subsequent circuits. In existing technology, as shown in Figure 2, a typical traditional startup circuit structure includes a transistor M1, a current-limiting resistor R1, and a pull-up resistor R2. The gate of transistor M1 is directly connected to an external enable pin EN for real-time monitoring of the enable signal voltage level. When the enable voltage EN exceeds the threshold voltage VTHN of transistor M1, transistor M1 enters the conducting state, forming a current path from the power supply VCC through transistor M1 and the current-limiting resistor R1 to ground. This current is defined as the startup current I1. Simultaneously, the startup current I1 flows through the pull-up resistor R2, generating a voltage drop across R2. Once this voltage reaches a specific threshold, it triggers the startup operation of subsequent circuits, thereby achieving system initialization.

[0003] However, such traditional startup circuits have an inherent drawback: when the enable voltage EN continues to rise after exceeding the threshold voltage VTHN, the source voltage of transistor M1 rises non-linearly, causing the startup current I1 flowing through the current-limiting resistor R1 to continuously increase. In low quiescent current or low-power integrated circuit designs, this current fluctuation directly causes the overall quiescent current of the chip to increase significantly with the increase of the enable voltage EN, making it impossible for the circuit to maintain a stable low-power operating state over a wide voltage range. Especially in modern portable electronic devices and IoT terminals, precise control of quiescent current is crucial for extending battery life. This defect of traditional circuits severely restricts their reliability and applicability in low-power applications, leading to decreased system energy efficiency and potentially causing functional abnormalities. Summary of the Invention

[0004] Therefore, the purpose of this invention is to provide a low quiescent current startup circuit, which has the advantage of maintaining a low quiescent current level when the enable voltage changes, thereby achieving stable and low-power operation.

[0005] To solve the above-mentioned technical problems, the present invention provides a low quiescent current startup circuit, comprising: a second resistor R2 connected in series between the power supply VCC and ground, a first transistor M1 and a first resistor R1, wherein the drain of the first transistor M1 leads to the output voltage OUT of the startup circuit, and the gate of the first transistor M1 is connected to the enable voltage EN, and further comprising a holding circuit for maintaining the quiescent current of the startup circuit at a set low current, configured such that the voltage at the gate of the first transistor M1 no longer increases with the increase of the enable voltage EN, the holding circuit comprising a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second transistor M2 and a third transistor M3, wherein the first resistor R2 is connected in series between the power supply VCC and ground, a first transistor M1 and a second resistor R2 ... transistor M2 connected in series between the power supply VCC and ground, a first transistor M1 and a second transistor M2 connected in series between the power The three resistors R3 and the second transistor M2 are used to detect the output voltage OUT of the startup circuit. The third resistor R3, the fourth resistor R4, and the fifth resistor R5 are used to form a current path and a voltage divider network. The enable voltage EN is connected to the gate of the first transistor M1 in series with the fifth resistor R5. The second transistor M2 and the third transistor M3 are used as control elements and are configured to cooperate with the third resistor R3, the fourth resistor R4, and the fifth resistor R5 to form a negative feedback loop to the gate of the first transistor M1, so as to counteract the influence of the change of the enable voltage EN on the voltage of the gate of the first transistor M1 and stabilize the voltage of the gate of the first transistor M1.

[0006] In one embodiment of the present invention, the first end of the third resistor R3 is connected to the power supply VCC, and the second end of the third resistor R3 is connected to the source of the second transistor M2. The gate of the second transistor M2 is connected to the output voltage OUT. The drain of the second transistor M2 is connected in series with the fourth resistor R4, and the drain of the second transistor M2 is connected to the gate of the third transistor M3. The source of the third transistor M3 is connected to one end of the fourth resistor R4. The first end of the fifth resistor R5 is connected to the enable voltage EN. The second end of the fifth resistor R5 and the drain of the third transistor M3 are connected to the gate of the first transistor M1.

[0007] In one embodiment of the present invention, when the negative feedback loop reaches a steady state, the current I2 flowing through the third resistor R3 and the second transistor M2 is:

[0008] I2 = VTHN / R4;

[0009] Wherein, VTHN is the threshold voltage of the third transistor M3.

[0010] In one embodiment of the present invention, the voltage across the second resistor R2 is equal to the voltage across the third resistor R3 plus the threshold voltage of the second transistor M2, that is:

[0011] I1*R2=I2*R3+VTHP;

[0012] Wherein, VTHP is the threshold voltage of the second transistor M2, and I1 is the current flowing through the first transistor M1.

[0013] In one embodiment of the present invention, I1 is:

[0014] I1=(VTHN / R4)*(R3 / R2)+VTHP / R2.

[0015] In one embodiment of the present invention, the current consumed by the power supply VCC is ICC, that is:

[0016] ICC= I1+I2=(VTHN / R4)*(R3 / R2)+ VTHP / R2+ VTHN / R4.

[0017] In one embodiment of the present invention, the first transistor M1 is an N-channel transistor.

[0018] In one embodiment of the present invention, the second transistor M2 is a P-channel transistor.

[0019] In one embodiment of the present invention, the third transistor M3 is an N-channel transistor.

[0020] The low quiescent current startup circuit of the present invention forms a negative feedback loop by introducing a holding circuit to counteract the influence of enable voltage changes on the gate voltage of the first transistor, thereby stabilizing the quiescent current. It has the advantage of maintaining the quiescent current at a low level when the enable voltage changes, thus achieving stable and low-power operation. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a circuit diagram of the low quiescent current startup circuit of the present invention;

[0023] Figure 2 is a circuit diagram of a prior art startup circuit. Detailed Implementation

[0024] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0027] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0029] In traditional startup circuits, when the external enable signal EN increases, the source voltage of the transistor increases accordingly, leading to a continuous increase in the startup current flowing through the current-limiting resistor. In low quiescent current or low power consumption applications, this phenomenon causes the overall quiescent current of the chip to increase significantly with the increase of the enable voltage EN, thereby affecting the power consumption performance of the system.

[0030] To address this issue, this application proposes a low quiescent current startup circuit, which incorporates a holding circuit 1 based on a conventional startup circuit. The holding circuit 1 is configured to form a negative feedback loop to the gate of the first transistor M1, preventing the gate voltage of the first transistor M1 from increasing with the increase of the enable voltage EN. This counteracts the effect of changes in the enable voltage EN on the gate voltage of the first transistor M1, stabilizes the gate voltage, and ultimately maintains the quiescent current of the startup circuit at a set low current level.

[0031] Referring specifically to Figure 1, the circuit includes: a second resistor R2 connected in series between the power supply VCC and ground, a first transistor M1, and a first resistor R1. The drain of the first transistor M1 outputs the start-up circuit's output voltage OUT, and the gate of the first transistor M1 is connected to the enable voltage EN. The circuit also includes a holding circuit 1 for maintaining the quiescent current of the startup circuit at a set low current. This holding circuit is configured such that the gate voltage of the first transistor M1 no longer increases with the increase of the enable voltage EN. The holding circuit 1 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second transistor M2, and a third transistor M3. The third resistor R3 and the second transistor M2 are used to detect the output voltage OUT of the startup circuit. The third resistor R3, the fourth resistor R4, and the fifth resistor R5 form a current path and a voltage divider network. The enable voltage EN is connected in series with the fifth resistor R5 to the gate of the first transistor M1. The second transistor M2 and the third transistor M3, as control elements, are configured to cooperate with the third resistor R3, the fourth resistor R4, and the fifth resistor R5 to form a negative feedback loop to the gate of the first transistor M1, thereby counteracting the effect of changes in the enable voltage EN on the gate voltage of the first transistor M1 and stabilizing the gate voltage of the first transistor M1. Specifically, after startup, a current I2 is generated in the branch where R3 and M2 are connected in series. After I2 flows through R4, the resulting voltage will turn on M3. When M3 is turned on, it generates a current I3. This current flows through R5, causing a voltage difference across R5. This prevents the gate voltage at point A of M1 from increasing with the increase of the external enable voltage EN. Thus, the magnitude of I1 no longer increases. The quiescent current of the entire startup circuit remains at the set low current and no longer increases with the increase of the enable signal EN voltage. The negative feedback process formed by the third resistor R3, the fourth resistor R4, the fifth resistor R5, the second transistor M2, and the third transistor M3 is as follows: When the external enable signal EN increases → the voltage at point A increases → the gate voltage of M1 increases → the source voltage of M1 increases → the current I1 flowing through R1 increases → the OUT voltage decreases → the current I2 of M3 and R3 increases → the gate voltage of R4 and transistor M3 increases → the current I3 increases → the voltage difference across R5 increases → the voltage at point A decreases → the gate voltage of M1 decreases.

[0032] The startup circuit refers to a circuit that generates an initial voltage or current when the system is powered on or enabled, thus starting subsequent functional modules. The enable voltage EN is an externally input control signal whose voltage state determines whether the startup circuit starts working and its operating state. The output voltage OUT is the voltage drawn from a specific node of the startup circuit under normal operating conditions; this voltage is typically used to drive or enable other circuit modules. The holding circuit 1 is an auxiliary circuit whose main function is to monitor and adjust the voltage of key nodes in the startup circuit to ensure that the circuit maintains a preset low quiescent current under different operating conditions, especially when the enable voltage EN changes. The negative feedback loop refers to a circuit structure in which a portion of the output signal is fed back to the input terminal and connected in a way that weakens the input signal, thereby stabilizing the system, suppressing interference, and improving performance.

[0033] Specifically, the holding circuit 1 consists of multiple discrete components, including a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second transistor M2, and a third transistor M3. These components work together to realize the function of the holding circuit 1. In the holding circuit 1, the third resistor R3 can be connected in series with the third transistor M3 to form a current path. Changes in the current or voltage drop along this path can reflect the state of the output voltage OUT. The third resistor R3, the fourth resistor R4, and the fifth resistor R5 together form a current path and a voltage divider network in the holding circuit 1. By properly configuring the resistance values ​​of these resistors, a specific current path can be established in the circuit, and the voltage can be divided, thereby generating the required reference voltage or control voltage at different nodes of the circuit. The enable voltage EN is connected in series with the fifth resistor R5 before being connected to the gate of the first transistor M1. This connection method allows the enable voltage EN to influence the gate of the first transistor M1 through the fifth resistor R5. The function of the fifth resistor R5 is to limit the current flowing to the gate of the first transistor M1 and participate in the formation of the gate voltage. The second transistor M2 and the third transistor M3 serve as key control elements in circuit 1. They work in conjunction with the third resistor R3, the fourth resistor R4, and the fifth resistor R5 to form a negative feedback loop targeting the gate of the first transistor M1. The core function of this negative feedback loop is to monitor the gate voltage of the first transistor M1 and adjust it in real time according to changes in the enable voltage EN, thereby counteracting the impact of fluctuations in the enable voltage EN on the gate voltage of the first transistor M1. Thus, the gate voltage of the first transistor M1 can be stabilized at a preset level, remaining relatively constant even if the enable voltage EN changes. This stabilization mechanism ensures that the current flowing through the first transistor M1 does not increase indefinitely with rising enable voltage EN, effectively maintaining the quiescent current of the startup circuit in a low-power state.

[0034] The low quiescent current startup circuit of this application effectively solves the problem of increased quiescent current as the enable voltage EN rises in traditional startup circuits by introducing a holding circuit 1 and constructing a negative feedback loop. This negative feedback mechanism stabilizes the gate voltage of the first transistor M1, preventing it from being affected by fluctuations in the enable voltage EN, thereby ensuring that the current flowing through the first transistor M1 remains at a stable and low level. As a result, the overall quiescent current of the chip is significantly reduced, making it particularly suitable for low quiescent current or low power consumption applications with strict power consumption requirements.

[0035] The specific connection method of the third resistor R3, the fourth resistor R4, the fifth resistor R5, the second transistor M2, and the third transistor M3 constituting the holding circuit 1 in this application is as follows: the first end of the third resistor R3 is connected to the power supply VCC, and the second end of the third resistor R3 is connected to the source of the second transistor M2. The gate of the second transistor M2 is connected to the output voltage OUT. The drain of the second transistor M2 is connected in series with the fourth resistor R4, and the drain of the second transistor M2 is connected to the gate of the third transistor M3. The source of the third transistor M3 is connected to one end of the fourth resistor R4. The first end of the fifth resistor R5 is connected to the enable voltage EN. The second end of the fifth resistor R5 and the drain of the third transistor M3 are connected to the gate of the first transistor M1.

[0036] Specifically, the third resistor R3, as a resistive element in the circuit, has its first terminal connected to the power supply VCC, designed to provide a stable power input for circuit 1 and establish an initial current path. The second terminal of the third resistor R3 is connected to the source of the second transistor M2, allowing current to flow through it and laying the foundation for subsequent voltage detection and feedback control. The gate of the second transistor M2 is connected to the output voltage OUT of the startup circuit, enabling it to directly sense and respond to real-time changes in OUT. A fourth resistor R4 is connected in series with the drain of the second transistor M2. This fourth resistor R4 limits the current flowing through the drain of the second transistor M2 and generates a voltage drop across it. This voltage drop is the key signal for controlling the third transistor M3. The fourth resistor R4 can be a fixed-value resistor similar to the third resistor R3; its resistance value is crucial for setting the gain and response speed of the feedback loop. Simultaneously, the drain of the second transistor M2 is connected to the gate of the third transistor M3, transmitting the signal processed by the second transistor M2 to the third transistor M3, thereby controlling its conduction state. The source of the third transistor M3 is connected to one end of the fourth resistor R4. This connection allows the third transistor M3 and the fourth resistor R4 to form a current path, ensuring that the conduction of the third transistor M3 is precisely controlled by the voltage across the fourth resistor R4, further enhancing the accuracy and stability of the feedback loop. The first end of the fifth resistor R5 is connected to the enable voltage EN, introducing the external enable signal into the gate control path of the first transistor M1. The fifth resistor R5 acts as a buffer and voltage divider, applying the enable voltage EN to the gate of the first transistor M1 in an appropriate manner. The fifth resistor R5 can be a fixed-value resistor, whose resistance is related to the circuit's startup characteristics and quiescent current target. The second end of the fifth resistor R5 and the drain of the third transistor M3 are connected to the gate of the first transistor M1. This connection point is the final point of action of the negative feedback loop; the drain voltage of the third transistor M3, together with the enable voltage EN passing through the fifth resistor R5, determines the gate voltage of the first transistor M1.

[0037] Through the above technical solution, this low quiescent current startup circuit constructs a precise and responsive negative feedback loop. The voltage change at the drain of the second transistor M2, through the series connection of the fourth resistor R4, precisely controls the gate of the third transistor M3. The conduction state of the third transistor M3 is thus modulated, and its drain voltage is adjusted accordingly. This adjusted voltage, together with the enable voltage EN, acts on the gate of the first transistor M1 through the fifth resistor R5. This precise connection ensures that the negative feedback loop can effectively counteract the influence of changes in the enable voltage EN on the gate voltage of the first transistor M1, thereby stabilizing the gate voltage of the first transistor M1 at a preset level. Ultimately, even if the enable voltage EN increases, the quiescent current flowing through the first transistor M1 will not increase significantly, thus achieving the goal of maintaining the quiescent current of the startup circuit at a set low current. This effectively solves the problem of the quiescent current increasing with the enable voltage EN in traditional startup circuits, significantly reducing the overall power consumption of the chip.

[0038] In the implementation of this application, when the negative feedback loop reaches a steady state, the current I2 flowing through the third resistor R3 and the second transistor M2 is: I2=VTHN / R4; where VTHN is the threshold voltage of the third transistor M3.

[0039] Specifically, when the negative feedback loop reaches steady state, it refers to the operating state where all voltages and currents have stabilized after the circuit has experienced startup or changes in external conditions, and no significant transient changes occur. Under this steady-state condition, the various parameters of the circuit tend to be constant, allowing the analysis and calculation of circuit behavior to be based on definite values, thereby ensuring that the derived current formula has practical guiding significance and accuracy. The current I2 flowing through the third resistor R3 and the second transistor M2 is a key current path in circuit 1, directly participating in the negative feedback regulation process of the gate voltage of the first transistor M1. As a control variable in the negative feedback loop, the magnitude of this current I2 directly affects the response characteristics of the negative feedback loop and the stabilization effect on the gate voltage of the first transistor M1. By precisely controlling this current I2, the static current level of the entire startup circuit can be effectively adjusted. The formula I2 = VTHN / R4 clarifies the calculation method of the current I2 flowing through the third resistor R3 and the second transistor M2 under steady-state conditions. It shows that the current I2 is jointly determined by the threshold voltage VTHN of the third transistor M3 and the resistance value of the fourth resistor R4. This relationship allows designers to precisely set and control the magnitude of the current I2 by appropriately selecting the value of the fourth resistor R4, combined with the inherent threshold voltage VTHN of the third transistor M3. The threshold voltage VTHN of the third transistor M3 refers to the minimum gate-source voltage required for the third transistor M3 to transition from the off state to the on state. This threshold voltage is an inherent electrical characteristic of the transistor, primarily determined by process parameters such as semiconductor material, doping concentration, and device structure.

[0040] Through the above technical solution, when the negative feedback loop reaches a steady state, this condition limits the application scenario of the formula, ensuring that the circuit is analyzed under stable operating conditions and avoiding transient interference affecting current calculations. The current I2 flowing through the third resistor R3 and the second transistor M2 identifies the critical current path, which is a core component of the negative feedback loop and directly affects the overall quiescent current. The formula I2 = VTHN / R4 indicates that the current I2 is determined by the threshold voltage VTHN of the third transistor M3 and the resistance value of the fourth resistor R4. Utilizing the inherent characteristics of the devices VTHN and the adjustable resistor R4, the current value is independent of external voltage changes, thus providing a predictable quantitative reference. Here, VTHN, the threshold voltage of the third transistor M3, further clarifies the source of the formula parameters, ensuring the accuracy of the calculation and the controllability of the design based on transistor process characteristics. Through this formula, designers can directly calculate the I2 value, optimize resistor selection, and thus accurately control the quiescent current, improving circuit reliability.

[0041] Based on the above scheme, this application further proposes that the voltage across the second resistor R2 is equal to the voltage across the third resistor R3 plus the threshold voltage of the second transistor M2, that is: I1*R2=I2*R3+VTHP; where VTHP is the threshold voltage of the second transistor M2 and I1 is the current flowing through the first transistor M1.

[0042] The equation I1 * R2 = I2 * R3 + VTHP above is a precise mathematical quantification of the voltage balance relationship described above. It establishes a direct functional relationship between the current I1 flowing through the first transistor M1 and other known or controllable parameters in the circuit (such as the third resistor R3, the second resistor R2, the current I2 flowing through the third resistor R3, and the threshold voltage VTHP of the second transistor M2). This quantification allows circuit designers to accurately predict and set the magnitude of I1 by adjusting the resistor values ​​or utilizing the inherent characteristics of the transistors. The threshold voltage VTHP is a key electrical parameter of the second transistor M2, representing the minimum gate-source voltage required to turn the transistor on from the off state. In the above equation, VTHP, as a fixed voltage term, reflects the inherent contribution of the second transistor M2 to the voltage balance during circuit operation and is an indispensable consideration in circuit design. Meanwhile, the current I1 is the current flowing through the main path of the startup circuit (i.e., through the first transistor M1 and the first resistor R1).

[0043] Through the above technical solution, given that the current I2 flowing through the third resistor R3 and the second transistor M2 can be accurately calculated when the negative feedback loop reaches steady state (e.g., I2 = VTHN / R4), this equation allows the current I1 flowing through the first transistor M1 to be accurately calculated and predicted. This solves the problem of difficulty in controlling I1 caused by the lack of precise quantization in traditional solutions. By establishing a direct mathematical relationship between I1 and known parameters, circuit designers can accurately select the second resistor R2, the third resistor R3, and the threshold voltage VTHP of the second transistor M2 according to the preset low quiescent current target, thereby achieving precise control of the startup current I1. This not only ensures that the startup circuit maintains a stable low quiescent current under different enable voltages EN, but also significantly improves the power efficiency and design controllability of the circuit, making the quiescent current management of the entire startup circuit more precise and efficient.

[0044] Based on the above scheme, this application further proposes that I1 is: I1 = (VTHN / R4) * (R3 / R2) + VTHP / R2. Wherein, the current I1 flowing through the first transistor M1 is the core operating current of the startup circuit, and its magnitude directly affects the power consumption of the startup circuit and the startup speed of subsequent circuits. Precise control of I1 is crucial for achieving low quiescent current and stable startup. The threshold voltage VTHN of the third transistor M3 refers to the minimum gate-source voltage required for the third transistor M3 to transition from the off state to the on state. This voltage is an inherent characteristic parameter of the transistor, and its stability plays a fundamental role in the precise operation of the transistor as a control element. The fourth resistor R4, as a key component of the holding circuit 1, directly affects the current flowing through it and the voltage of related nodes. The third resistor R3 is an important component in the holding circuit 1, and its resistance setting has a significant impact on the current distribution and voltage division of the circuit. The threshold voltage VTHP of the second transistor M2 refers to the minimum gate-source voltage required for the second transistor M2 to transition from the off state to the on state. As an inherent characteristic parameter of the transistor, its accuracy is crucial for the accurate switching on and off of the second transistor M2 as a control element.

[0045] This application explicitly provides a formula for calculating I1, directly utilizing key circuit parameters such as the threshold voltage VTHN of the third transistor M3, the fourth resistor R4, the third resistor R3, the second resistor R2, and the threshold voltage VTHP of the second transistor M2, to achieve precise quantification of the current I1. This direct calculation method avoids the error accumulation that may result from indirect derivation, thus ensuring that the current I1 flowing through the first transistor M1 in the negative feedback loop can be accurately set and controlled. This is crucial for maintaining the startup circuit at a set low quiescent current level, effectively preventing the quiescent current from increasing with changes in the external enable voltage EN, thereby significantly improving the low-power performance and stability of the startup circuit.

[0046] Based on the above scheme, this application further proposes that the current consumed by the power supply VCC is ICC, that is:

[0047] ICC= I1+I2=(VTHN / R4)*(R3 / R2)+ VTHP / R2+ VTHN / R4.

[0048] As can be seen from the above formula, the value of ICC is independent of the voltage of the external enable signal EN, and is only related to the threshold voltages of transistors M3 and M2, and resistors R2, R3, and R4. Therefore, by adjusting the values ​​of resistors R2, R3, and R4, the quiescent current of the startup circuit can be adjusted, and it will not increase with the increase of the enable signal EN, thus achieving a low quiescent current design.

[0049] The current ICC consumed by the power supply VCC represents the total current drawn from the power supply VCC by the low quiescent current startup circuit, and is a key indicator for measuring the overall power consumption of the circuit. It can be determined by summing all current paths in the circuit, or by directly measuring it using an ammeter connected in series in the power supply path of VCC. The current I1 flowing through the first transistor M1 refers to the startup current through the first transistor M1 and the first resistor R1, which is the main current during the circuit startup phase. This current can be calculated by measuring the voltage across the first resistor R1 and combining it with its resistance value, or by analyzing the transconductance characteristics of the first transistor M1. The current I2 flowing through the third resistor R3 and the second transistor M2 is the quiescent current consumed to keep circuit 1 in steady state, and is an important component of the total quiescent current. This current can be derived by measuring the voltage across the fourth resistor R4 and combining it with the threshold voltage VTHN of the third transistor M3, or by measuring it using an ammeter connected in series in the path of the third resistor R3 or the second transistor M2. The threshold voltage VTHN of the third transistor M3 is the gate-source voltage required to turn on the third transistor M3. It is a fundamental electrical parameter of the transistor and is usually provided by the device manufacturer or obtained through experimental testing. The threshold voltage VTHP of the second transistor M2 is the gate-source voltage required to turn on the second transistor M2. For P-channel transistors, it usually refers to the absolute value of the negative gate-source voltage required for it to turn on, and is also provided by the device manufacturer or characterized experimentally. The second resistor R2 is a resistor connected in series between the power supply VCC and ground, used to limit current and generate voltage drop. It can be a fixed-value resistor or a resistor structure implemented inside an integrated circuit. The third resistor R3 is part of the holding circuit 1, used to detect the output voltage OUT and form a current path. It can be a standard fixed resistor, an adjustable resistor, or an integrated resistor. The fourth resistor R4 is also part of the holding circuit 1, used to form a current path and voltage divider network. Its resistance value is crucial to the setting of the current I2. It can be a discrete resistor or an integrated resistor.

[0050] By defining the total current ICC consumed by the power supply VCC as the sum of the startup current I1 and the holding circuit current I2, and providing specific calculation expressions based on key circuit parameters (such as transistor threshold voltages VTHN, VTHP, and resistors R2, R3, and R4), designers can accurately predict and control the overall power consumption of the circuit. This quantification capability allows circuit designers to selectively select and optimize resistor values ​​and transistor parameters according to target power consumption requirements, thereby achieving the goal of low quiescent current during the design phase. Furthermore, the introduction of this formula ensures that the power consumption contribution (I2 portion) when the circuit enters a low quiescent current holding state after startup can also be accurately calculated, avoiding the inaccurate power consumption estimation problem caused by the incomplete description of all quiescent current components in traditional solutions. Ultimately, through precise calculation and control of ICC, this application can effectively reduce the overall quiescent power consumption of the circuit and improve power utilization efficiency, making it particularly suitable for power-sensitive portable devices or low-power applications.

[0051] Furthermore, the first transistor M1 is an N-channel transistor. Specifically, an N-channel transistor is a field-effect transistor whose conductive channel is mainly composed of electrons. When its gate voltage relative to the source voltage reaches and exceeds a certain threshold, the transistor turns on, allowing current to flow. Specifying the first transistor M1 as an N-channel transistor ensures that it reliably starts conducting when the enable voltage EN increases. This inherent characteristic of the N-channel transistor matches the rising trend of the enable signal EN, enabling the first transistor M1 to effectively respond to changes in the enable signal EN during startup. Based on this, the negative feedback loop formed by the holding circuit 1 can more precisely control the gate voltage of the first transistor M1, thereby avoiding inaccurate gate voltage control problems that may be caused by channel type mismatch. This precise control helps prevent the source voltage of the first transistor M1 from rising excessively, thus effectively suppressing the increase of the startup current I1 flowing through the first transistor M1 with the increase of the enable voltage EN, ultimately ensuring that the quiescent current of the startup circuit can be stably maintained at a set low level, thereby meeting the design requirements of low quiescent current or low power consumption circuits.

[0052] Furthermore, the second transistor M2 is a P-channel transistor. Specifically, a P-channel transistor (PMOS) is a field-effect transistor whose conductive channel is composed of holes. Unlike N-channel transistors (NMOS), PMOS transistors typically conduct when the gate voltage is lower than the source voltage (i.e., the gate-source voltage Vgs is negative) and its absolute value exceeds the threshold voltage. In the negative feedback loop of the aforementioned low quiescent current startup circuit, the second transistor M2, as a key control element, needs to provide precise current or voltage regulation according to changes in the circuit state. The conduction characteristics of the P-channel transistor (the lower the gate voltage relative to the source voltage, the stronger the conduction) allow it to form a specific response relationship with the changing trend of the output voltage OUT (connected to its gate), thereby providing the necessary control signal for the negative feedback loop.

[0053] By designating the second transistor M2 as a P-channel transistor, the stability and response characteristics of the negative feedback loop are optimized. In the negative feedback loop, the gate of the second transistor M2 is connected to the output voltage OUT, and its source is connected to the third resistor R3. As a P-channel transistor, the second transistor M2 conducts when the gate voltage is low and turns off when it is high, allowing it to precisely control the current path according to changes in the output voltage OUT. Specifically, when the output voltage OUT increases, the gate voltage of the second transistor M2 increases, causing its conduction to decrease or turn off, thereby reducing the current flowing through it. The drain of the second transistor M2 is connected in series with the fourth resistor R4, and its drain is connected to the gate of the third transistor M3. The decrease in the conduction of the second transistor M2 affects the gate voltage of the third transistor M3, thereby regulating the conduction state of the third transistor M3. The drain of the third transistor M3 and the second terminal of the fifth resistor R5 are connected together to the gate of the first transistor M1. This synergistic effect forms a reliable negative feedback mechanism that can effectively counteract the interference of the increase in the enable voltage EN on the gate voltage of the first transistor M1, ensuring that the gate voltage of the first transistor M1 remains constant. Through the above technical solution, even if the enable voltage EN continues to rise, the gate voltage of the first transistor M1 can be precisely maintained at a stable level, avoiding the problem that the conduction current I1 of the first transistor M1 continuously increases with the increase of the enable voltage EN. This is crucial for realizing a startup circuit with low quiescent current and low power consumption, because it ensures that the quiescent current of the circuit can be effectively controlled at a set low current level over a wide range of enable voltage EN, thereby significantly reducing the overall power consumption of the chip.

[0054] Furthermore, the third transistor M3 is an N-channel transistor. In the holding circuit 1 of the aforementioned low quiescent current startup circuit, the third transistor M3 serves as a control element. Its gate is connected to the drain of the second transistor M2, its source is connected to one end of the fourth resistor R4, and its drain and the second end of the fifth resistor R5 are connected together to the gate of the first transistor M1. The main function of the third transistor M3 is to cooperate with the second transistor M2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 to form a negative feedback loop to the gate of the first transistor M1. By changing its conduction state, the third transistor M3 can regulate the current flowing to the gate of the first transistor M1, thereby stabilizing the gate voltage of the first transistor M1 to counteract the influence of changes in the enable voltage EN.

[0055] Through the above technical solution, the third transistor M3 is explicitly designated as an N-channel transistor, forming a complementary or synergistic working relationship with the configuration of the second transistor M2 as a P-channel transistor. This explicit transistor type designation solves the problem of transistor characteristic mismatch in the feedback loop, ensuring the stability and efficiency of the negative feedback loop. Specifically, when the second transistor M2 (P-channel) detects a change in the output voltage OUT and generates a corresponding control signal, this signal can effectively drive the third transistor M3 (N-channel) for precise on / off control. This combination of P-channel and N-channel transistors allows the negative feedback loop to more accurately counteract the influence of the enable voltage EN on the gate voltage of the first transistor M1, thereby stabilizing the gate voltage of the first transistor M1. Ultimately, this ensures that the quiescent current of the startup circuit can be reliably maintained at the set low current level, avoiding the problem of the quiescent current increasing with the increase of the enable voltage EN in traditional circuits, thus achieving low-power operation.

[0056] Through the above design, the quiescent current of the startup circuit is precisely controlled at a low level determined by circuit parameters (such as resistance value and transistor threshold voltage), and is no longer affected by fluctuations in the external enable voltage EN. This contrasts with the situation in traditional startup circuits where the quiescent current increases with the increase of EN voltage, significantly reducing the overall power consumption of the integrated circuit in standby or low-power modes and improving the system's energy efficiency. The introduction of holding circuit 1, through its ingenious negative feedback mechanism, effectively clamps the gate voltage of the first transistor M1, thereby stabilizing the startup current and solving the problem of excessively high quiescent current in traditional circuits.

[0057] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A low quiescent current startup circuit, comprising: A second resistor R2, a first transistor M1, and a first resistor R1 are connected in series between the power supply VCC and ground. The drain of the first transistor M1 leads to the output voltage OUT of the startup circuit, and the gate of the first transistor M1 is connected to the enable voltage EN. The system is characterized by further including a holding circuit for maintaining the quiescent current of the startup circuit at a set low current, configured such that the voltage at the gate of the first transistor M1 no longer increases with the increase of the enable voltage EN. The holding circuit includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second transistor M2, and a third transistor M3. The third resistor R3 and the second transistor M2 are used to detect the output voltage OUT of the startup circuit. The third resistor R3, the fourth resistor R4, and the fifth resistor R5 form a current path and a voltage divider network. The enable voltage EN is connected in series with the fifth resistor R5 and then connected to the gate of the first transistor M1. The second transistor M2 and the third transistor M3... As a control element, it is configured to cooperate with the third resistor R3, the fourth resistor R4, and the fifth resistor R5 to form a negative feedback loop to the gate of the first transistor M1, so as to counteract the influence of the change of the enable voltage EN on the gate voltage of the first transistor M1 and stabilize the gate voltage of the first transistor M1; the first end of the third resistor R3 is connected to the power supply VCC, and the second end of the third resistor R3 is connected to the source of the second transistor M2, the gate of the second transistor M2 is connected to the output voltage OUT, the drain of the second transistor M2 is connected in series with the fourth resistor R4, and the drain of the second transistor M2 is connected to the gate of the third transistor M3, the source of the third transistor M3 is connected to one end of the fourth resistor R4, the first end of the fifth resistor R5 is connected to the enable voltage EN, and the second end of the fifth resistor R5 and the drain of the third transistor M3 are connected to the gate of the first transistor M1.

2. The low quiescent current startup circuit according to claim 1, characterized in that: When the negative feedback loop reaches a steady state, the current I2 flowing through the third resistor R3 and the second transistor M2 is: I2 = VTHN / R4; where VTHN is the threshold voltage of the third transistor M3.

3. The low quiescent current startup circuit according to claim 2, characterized in that: The voltage across the second resistor R2 is equal to the voltage across the third resistor R3 plus the threshold voltage of the second transistor M2, i.e.: I1*R2=I2*R3+VTHP; where VTHP is the threshold voltage of the second transistor M2 and I1 is the current flowing through the first transistor M1.

4. The low quiescent current startup circuit according to claim 3, characterized in that: The I1 is: I1 = (VTHN / R4) * (R3 / R2) + VTHP / R2.

5. The low quiescent current startup circuit according to claim 4, characterized in that: The current consumed by the power supply VCC is ICC, that is: ICC = I1 + I2 = (VTHN / R4) * (R3 / R2) + VTHP / R2 + VTHN / R4.

6. The low quiescent current startup circuit according to claim 1, characterized in that: The first transistor M1 is an N-channel transistor.

7. The low quiescent current startup circuit according to claim 6, characterized in that: The second transistor M2 is a P-channel transistor.

8. The low quiescent current startup circuit according to claim 7, characterized in that: The third transistor M3 is an N-channel transistor.

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