Adaptive PWM suppression circuit for current sensing

Abstract

This application discloses an adaptive PWM suppression circuit for current detection, relating to the field of integrated circuits. It includes a PWM detection circuit and a logic control circuit. The PWM detection circuit includes a cascaded amplitude-frequency detection module and a time detection module. The amplitude-frequency detection module receives the PWM signal and detects the amplitude-frequency information. The time detection module determines the signal shielding duration based on the amplitude-frequency information and outputs a shielding signal and a shielding release signal according to the shielding duration. When the output stage shielding module receives the shielding signal, it initiates signal shielding, stabilizing the output to the steady-state value before the PWM signal jump. When the output stage shielding module receives the shielding release signal, it releases the signal shielding and controls the circuit to resume normal output. This adaptive mechanism avoids the problems of over-shielding or under-shielding that may occur with a fixed shielding time, thereby effectively suppressing glitches while maximizing signal continuity and real-time performance.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to an adaptive PWM suppression circuit for current detection. Background Technology

[0002] Against the backdrop of rapid development in new energy technologies, optimizing the operating efficiency of motor systems places higher demands on control precision. Phase current, as a key monitoring indicator, directly impacts motor control performance through accurate detection. Ideally, the measurement unit should be directly connected in series with the phase line loop to obtain a continuous signal. However, the PWM signal generated by the motor drive circuit can trigger a large common-mode voltage jump within a very short time. This voltage jump causes significant glitches at the output of the non-ideal amplifier, with high amplitude and long recovery time, severely interfering with system control stability. Figure 1 The diagram illustrating phase current detection applications in the related technologies illustrates that, due to the continuity of the measurement signal and its direct correlation with the phase current, the ideal current detection method is to connect the measurement unit directly in series in each phase circuit. The PWM signal generated by the motor drive circuit is used to control motor operation, but this modulation method causes the detection circuit connected in series in each phase circuit to experience large common-mode voltage jumps. These voltages can switch between large magnitudes in a very short time. Non-ideal amplifiers do not possess infinite common-mode rejection capability; every step change in the input voltage can introduce significant unintended interference at the output. The amplitude of these output interferences (i.e., glitches) can be very high and often takes a long time to recover to a stable state, adversely affecting system control.

[0003] Common current sensing circuits typically employ methods such as increasing the input common-mode rejection ratio (CMRR), increasing bandwidth, and adding additional filters to suppress interference caused by common-mode voltage jumps. However, these methods all have limitations. For example, their suppression effect on PWM signals is limited, and they usually lead to a significant increase in power consumption and cost, or require increased system complexity and reduced integration. They cannot effectively address the adverse effects of common-mode voltage jumps caused by PWM signals on the accuracy and stability of current sensing.

[0004] Therefore, traditional technologies urgently need to be improved to address the aforementioned problems. Summary of the Invention

[0005] This application provides an adaptive PWM suppression circuit for current sensing, which has the advantages of adaptively suppressing glitches caused by PWM signals while maintaining the continuity and accuracy of the current sensing signal.

[0006] The adaptive PWM suppression circuit includes a PWM detection circuit and a logic control circuit; the PWM detection circuit includes a cascaded amplitude-frequency detection module and a time detection module; the amplitude-frequency detection module receives the PWM signal and detects and generates a shielding trigger signal; the shielding trigger signal is used to characterize the amplitude-frequency information of the PWM signal.

[0007] The time detection module determines the signal shielding duration based on amplitude-frequency information, and outputs a shielding signal and a shielding release signal according to the shielding duration; the shielding duration is positively correlated with the high-frequency components of the PWM signal;

[0008] The logic control circuit is equipped with an output stage shielding module. When the output stage shielding module receives the shielding signal, it activates signal shielding and stabilizes the circuit output to the steady-state value before the PWM signal jump. When the output stage shielding module receives the shielding release signal, it releases the signal shielding and the control circuit resumes normal output.

[0009] Specifically, the logic control circuit also includes a shielding timing module, which is set with a maximum shielding time;

[0010] The shielding timing module starts timing based on the shielding signal. When the shielding duration corresponding to the amplitude-frequency information is greater than the maximum shielding time, and the shielding timing module reaches the set maximum shielding time, it outputs a forced release signal. The forced release signal is used to control the output stage shielding module to release the signal shielding, and the control circuit resumes normal output.

[0011] Specifically, the logic control circuit further includes a time delay module, which connects the shielded timing module and the time detection module;

[0012] The time delay module is set with a delay shielding time. When the shielding timing module outputs the forced release signal or the time detection module outputs the shielding release signal, the time delay module is triggered to start the delay shielding timer.

[0013] When the delay shielding timer is started, the time delay module sends a delay trigger signal to the time timing detection module, controlling the time detection module to output the shielding release signal; when the delay shielding time is reached, the time detection module is controlled to resume the function of outputting the shielding signal.

[0014] Specifically, the amplitude-frequency detection module includes an RC high-pass network, a current mirror comparison circuit, and a signal output circuit;

[0015] A coupling point is provided at the connection between the RC high-pass network and the current mirror comparison circuit. The RC high-pass network inputs a common-mode signal, filters out the low-frequency component of the common-mode signal, and sends the filtered high-frequency component to the coupling point.

[0016] The current mirror comparison circuit generates reference currents through two current mirror structures. When the filtered high-frequency component generates a rising transition time disturbance, the two generated reference currents are compared and competed. Voltage output terminals are provided at the reference current output terminals of the two current mirror structures, and the voltage value of the voltage output terminals changes with the result of the current comparison competition.

[0017] The two inputs of the signal output circuit are respectively connected to the voltage output terminals, and the shielding trigger signal is generated through logic gate circuit operations.

[0018] Specifically, the current mirror comparison circuit includes a first current mirror composed of NMOS transistors NM1, NM2 and NM3, a second current mirror composed of PMOS transistors PM1 and PM2, and a current comparator composed of NMOS transistor NM0 and PMOS transistor PM0.

[0019] NM0, NM1, NM2, and NM3 are connected in a common gate configuration, with the drain and gate of NM3 sharing the voltage Vs and current source I0; the sources of NM1, NM2, and NM3 are grounded; PM0, PM1, and PM2 are connected in a common gate configuration, with the sources of PM1 and PM2 sharing the voltage Vs, and the drain and gate of PM2 sharing the drain of NM2.

[0020] NM0 and PM0 share a common source connection; NM0 and PM1 share a common drain connection; PM0 and NM1 share a common drain connection.

[0021] The first current mirror generates a first reference current I on NM1. N The second current mirror generates a second reference current I on PM1. P The first voltage output terminal V is located at the common drain connection of NM1 and PM0. P The common drain connection point of NM0 and PM1 is the second voltage lead-out terminal V. N The common drain connection between NM0 and PM0 is the coupling point.

[0022] Specifically, the RC high-pass network includes a resistor divider network and two filter capacitors C. P and C N And a current-limiting resistor R1; the resistor divider network includes two cascaded voltage divider resistors R0 and R1. 01 The voltage divider resistor R0 is connected to the voltage Vs, and after passing through the cascaded voltage divider R... 01 Rear grounding;

[0023] Filter capacitor C Pand C N The positive terminals are respectively input with common-mode signal IN P and IN N The negative terminal is connected to one end of the current-limiting resistor R1, corresponding to the coupling point; the other end of the current-limiting resistor R1 is connected to the voltage divider resistors R0 and R... 01 The pressure dividing point B between them;

[0024] Common-mode signal IN P and IN N The two common-mode inputs, which serve as current comparators, are used to detect the amplitude and frequency information of the common-mode signal at the coupling point through the RC high-pass network.

[0025] Specifically, the signal output circuit includes two inputs, one of which is connected to the first voltage output terminal V. N It includes two cascaded NOT gates, and the outputs of the two NOT gates are connected to one input of the NAND gate;

[0026] The other path is connected to the second voltage output terminal V. P It includes a NOT gate, and the output of the NOT gate is connected to the other input of the NAND gate, through which the shielding trigger signal is output.

[0027] Specifically, the time detection module includes two D flip-flops. The D terminal of the first D flip-flop is input with a high level, the CP port is input with the shielding trigger signal, and the Q port is output with the shielding signal.

[0028] The D input of the second D flip-flop is connected to the Q output of the first D flip-flop, the CP port is input with the inverted signal of the shielding trigger signal, and the Q port outputs the shielding release signal.

[0029] When the PWM signal contains high-frequency components, the shielding trigger signal is a valid signal, and the Q port of the first D flip-flop outputs a valid shielding signal.

[0030] When the high-frequency components contained in the PWM signal disappear, the shielding trigger signal becomes invalid, and the Q port output of the second D flip-flop becomes an effective shielding release signal.

[0031] Specifically, the output stage shielding module includes a first operational amplifier Av1, a second operational amplifier Av2, a shielding switch S, and a voltage regulator capacitor C; the first operational amplifier is a fully differential operational amplifier, and the second operational amplifier is a differential input, single-ended output operational amplifier;

[0032] Common-mode signal IN P and IN N The two first-stage input terminals of the first operational amplifier are respectively input, and the two output terminals are respectively cascaded to the two second-stage input terminals of the second operational amplifier. The shielding switch S is set between the two second-stage input terminals.

[0033] A first feedback loop is provided between the non-inverting input and the non-inverting output of the first operational amplifier, including a first feedback resistor and a first voltage-regulating capacitor connected in series; the positive terminal of the first voltage-regulating capacitor is connected to the non-inverting input of the second operational amplifier, and the negative terminal is connected to the reference voltage REF.

[0034] A second feedback loop is provided between the negative input and negative output of the first operational amplifier, including a second feedback resistor and a second voltage-regulating capacitor connected in series; the positive terminal of the second voltage-regulating capacitor is connected to the negative input of the second operational amplifier, and the negative terminal is connected to the output of the second operational amplifier.

[0035] Specifically, when the output stage shielding module receives a valid shielding signal, the shielding switch S closes, signal shielding is activated, and the voltage regulator capacitor maintains a regulated output during the shielding time.

[0036] When the output stage shielding module receives a valid shielding release signal, the shielding switch S opens, the signal shielding is released, and the operational amplifier outputs normally.

[0037] Specifically, the output is triggered by the rising edge of the CP terminal of the two D flip-flops. During the forced release of signal shielding and within the delayed shielding time, the RSTN of the two D flip-flops is set to a low level to interrupt the signal shielding detection.

[0038] After the delay shielding time is reached, the RSTN of the two D flip-flops is set to high level to restore signal shielding detection.

[0039] The beneficial effects of the technical solution provided in this application include at least the following: The solution of this application achieves adaptive processing of PWM signal interference by introducing a PWM detection circuit and a logic control circuit. The amplitude-frequency detection module can accurately identify high-frequency components outside the effective bandwidth of the CMRR, which are interference sources that are difficult to effectively handle using traditional methods. The time detection module dynamically determines the signal shielding duration based on this amplitude-frequency information, ensuring that the shielding time matches the interference intensity and duration. This adaptive mechanism avoids the problems of over-shielding or under-shielding that may result from a fixed shielding time, thereby effectively suppressing glitches while maximizing the continuity and real-time performance of the signal. Attached Figure Description

[0040] Figure 1 This is a diagram illustrating the application of phase current detection using related technologies;

[0041] Figure 2 This is a schematic diagram of the adaptive PWM suppression circuit for current detection provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the circuit structure of the PWM signal amplitude and frequency detection module;

[0043] Figure 4 A schematic diagram of the current mirror comparator circuit, RC high-pass network, and signal output circuit in one possible form is shown.

[0044] Figure 5 A schematic diagram of the circuit structure of the time detection module in one possible form is shown;

[0045] Figure 6 A schematic diagram of the specific circuit structure of the output stage shielding module is shown. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0047] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0048] Conventional current sensing circuits typically use the following methods to suppress the interference caused by common-mode voltage jumps to the output:

[0049] 1. Improve the input common-mode rejection ratio (CMRR). This can suppress the amplitude of output interference within a certain frequency range. However, the CMRR of an amplifier decreases as the frequency increases, and the spectral components of a PWM signal (square wave signal) are extremely rich, including DC, low-frequency, and high-frequency components. Therefore, the suppression effect on the high-frequency components will be significantly weakened.

[0050] 2. Increase bandwidth. If the signal bandwidth reaches more than 10 times the PWM modulation frequency, output glitches can quickly recover and stabilize after a jump in the input common-mode voltage. However, increasing bandwidth usually leads to an increase in power consumption and chip area.

[0051] 3. Add an additional filter. Adding a filter can effectively reduce output glitches, but it will reduce the signal bandwidth, making it impossible to detect changes in current in a timely manner.

[0052] In summary, conventional methods have limited effectiveness in suppressing PWM signals and typically lead to a significant increase in power consumption and cost, or require an increase in system complexity and a decrease in integration.

[0053] Therefore, this application provides an adaptive PWM suppression circuit for current detection, such as... Figure 2As shown, the circuit includes a PWM detection circuit and a logic control circuit. The PWM detection circuit analyzes the input PWM signal, identifies potential interference information, and transmits this information to the logic control circuit. The logic control circuit then precisely controls the signal shielding operation of the output stage based on the received information, thereby effectively suppressing common-mode interference caused by the PWM signal without affecting normal signal detection.

[0054] In this embodiment, the PWM detection circuit may include a cascaded amplitude-frequency detection module and a time detection module; the amplitude-frequency detection module first performs preliminary processing on the original PWM signal to extract key amplitude-frequency information; then, the time detection module calculates the specific shielding duration based on this amplitude-frequency information.

[0055] Specifically, the amplitude-frequency detection module receives the PWM signal and detects its amplitude-frequency information. This detection primarily focuses on high-frequency components outside the effective bandwidth of the common-mode rejection ratio (CMRR), as these components are the main cause of output glitches in the current sensing circuit. For example, the amplitude-frequency detection module can be implemented using a simple combination of an RC high-pass filter and a comparator. When the PWM signal undergoes a rapid transition, the high-pass filter filters out its high-frequency components, and the comparator converts them into a digital signal, which is then output as a shielding trigger signal. Alternatively, the amplitude-frequency detection module can employ a Fourier transform-based digital signal processing unit to perform spectral analysis on the PWM signal, identify high-frequency energy exceeding a specific frequency threshold, and generate a shielding trigger signal accordingly.

[0056] The shielding trigger signal is used to characterize the amplitude-frequency information of the PWM signal, directly reflecting the presence and intensity of high-frequency components in the PWM signal. For example, when a high-frequency component is detected, the shielding trigger signal can be a high-level pulse; when no high-frequency component is detected, it is a low-level pulse.

[0057] The time detection module determines the signal shielding duration based on amplitude-frequency information and outputs a shielding signal and a shielding release signal according to the shielding duration. The shielding duration is positively correlated with the high-frequency component of the PWM signal. This means that the stronger or longer the high-frequency component in the PWM signal, the longer the shielding duration determined by the time detection module will be to ensure sufficient suppression of interference. Conversely, when the high-frequency component is weak or short-lived, the shielding duration will be shortened accordingly to reduce the impact on normal signal detection. This module can be implemented based on a trigger. For example, the shielding time can be determined based on the duration of the high-level period when the high-frequency component appears, and the low-level period after the high-frequency component disappears (or falls below the detection accuracy) releases the signal shielding, thus generating a shielding release signal.

[0058] The logic control circuit includes an output stage shielding module. When the output stage shielding module receives a shielding signal, it activates signal shielding, stabilizing the circuit output to the steady-state value before the PWM signal transition. This operation aims to quickly respond to rapid PWM signal transitions, maintaining the output to the circuit's operating state before the PWM transition (i.e., the steady-state value before the PWM signal transition, determined based on the differential-mode voltage and voltage amplification factor specified in the circuit design) within the shielding time, effectively preventing large glitches at the output. For example, the output stage shielding module can include a fast-response switching circuit. Upon receiving the shielding signal, it connects a digitally controlled reference voltage or a stabilizing capacitor, which maintains the circuit's operating state before the PWM transition (e.g., when the switching circuit is externally connected, the circuit system output still reflects the input differential-mode voltage with the target amplification factor). If it is a voltage regulator capacitor, it can be directly connected to the circuit, and the voltage during shielded startup is the normal operating voltage. If it is a voltage source (or voltage input signal) controlled by a digital circuit, the output voltage value can be converted into a digital value by an ADC and stored. When the PWM signal changes abruptly, the previous operating state is given to the circuit through a DAC to stabilize the output, thereby effectively suppressing the output glitches caused by the PWM signal change and achieving rapid output stabilization.

[0059] When the output stage shielding module receives the shielding release signal, it releases the signal shield, and the control circuit resumes normal output. This means that after the interference event ends, the circuit can quickly return to normal operation and continue to perform accurate current detection, ensuring signal continuity and real-time performance. For example, when the aforementioned switching circuit receives the shielding release signal, it will quickly disconnect the voltage source input or discharge the voltage regulator capacitor to achieve normal signal output.

[0060] Compared to traditional solutions, this application's solution achieves adaptive processing of PWM signal interference by introducing a PWM detection circuit and a logic control circuit. The amplitude-frequency detection module can accurately identify high-frequency components outside the effective bandwidth of the CMRR (Continuous Response Range), which are interference sources that are difficult to effectively handle using traditional methods. The time detection module dynamically determines the signal shielding duration based on this amplitude-frequency information, ensuring that the shielding time matches the interference intensity and duration. This adaptive mechanism avoids the problems of over-shielding or under-shielding that may occur with a fixed shielding time, thereby effectively suppressing glitches while maximizing the continuity and real-time performance of the signal.

[0061] Specifically, when the PWM signal undergoes a rapid transition, the circuit of this application can quickly activate the output stage shielding, stabilizing the output signal to its steady-state value before the signal transition, thereby suppressing output glitches at the first moment of interference. Once the interference ends, the circuit can quickly deshield and restore normal signal output. This combination of rapid response and adaptive control makes the circuit of this application more efficient and flexible in suppressing PWM interference, effectively improving the accuracy and stability of current detection, while avoiding the drawbacks of traditional solutions in terms of power consumption, cost, and system complexity.

[0062] In some of the solutions described above in this application, a logic control circuit is proposed to shield the output when the PWM signal changes abruptly in order to reduce glitches. However, if the adaptive shielding time is too long, it will lead to an excessively long interruption time in the input signal detection, affecting the continuity and accuracy of current detection.

[0063] To address this, this application further proposes adding a shielding timing module to the logic control circuit, and setting a maximum shielding time for the shielding timing module. This shielding timing module can be a circuit unit used to measure and manage time intervals, and has a signal triggering function after the timing ends; for example, it can be a combination of a counter, oscillator, and comparator. The maximum shielding time is a preset upper limit value, designed to limit the duration of signal shielding.

[0064] The shielding timing module starts timing based on the shielding signal; that is, timing begins synchronously when the output-stage shielding module receives the shielding signal and initiates signal shielding. This starting mechanism can be achieved by detecting the rising edge or valid level of the shielding signal to trigger the timer. When the shielding duration corresponding to the amplitude-frequency information exceeds the maximum shielding time, and the shielding timing module reaches the set maximum shielding time, it outputs a forced release signal. This forced release signal controls the output-stage shielding module to release the signal shielding, directly controlling the circuit to resume normal output. This signal can be a high-level pulse, a low-level pulse, or a continuous valid level, depending on the control logic of the output-stage shielding module. This conditional judgment ensures that the system can intervene promptly if the adaptive shielding time is potentially too long.

[0065] Through the above technical solution, this application effectively solves the problem that the adaptive shielding time may be too long during adaptive PWM suppression, leading to excessively long interruptions in input signal detection. By introducing a shielding timing module and setting a maximum shielding time, this solution can control the upper limit of the signal shielding duration, avoiding prolonged shielding caused by the continuous presence of high-frequency components of the PWM signal, thereby ensuring the continuity and accuracy of current detection. This enables the system to maintain stable signal detection capability while effectively suppressing PWM interference, improving the overall system reliability and performance.

[0066] In some of the solutions described above in this application, a shielding timing module is proposed to forcibly release the signal shielding when the shielding time is too long. However, this mechanism is designed for high-frequency interference times exceeding the maximum shielding timing. Even if the shielding is released beforehand, the timing detection module will still detect and output the shielding signal normally. This may immediately re-detect the high-frequency component, leading to frequent activation of the signal shielding and affecting the detection accuracy and stability of the input signal.

[0067] In response, this application further proposes that the logic control circuit also include a time delay module, such as... Figure 2 As shown, the time delay module connects the shielding timing module and the adaptive time detection module. The time delay module is set with a delay shielding time, which is used to trigger the time delay module to start the delay shielding timer when the shielding timing module outputs a forced release signal or the time detection module outputs a shield release signal (at which time the output stage shielding module releases the signal shielding).

[0068] In cases where the maximum shielding time is exceeded, when the shielding timer module outputs a forced release signal, this signal will simultaneously trigger the time delay module to start the delayed shielding timer. In cases of short-term shielding, the release of shielding is triggered by the time detection module. When the time delay module receives the shielding release signal, it triggers the delayed shielding timer.

[0069] When the delayed shielding time is activated, the time delay module sends a delayed trigger signal to the time timing detection module, controlling the time detection module to output a shield release signal, keeping the system in the unshielded state. The purpose of setting the delayed shielding time is to provide a "blank period" for the system after forced shield release, avoiding frequent activation and deactivation of the shielding function due to immediate re-detection of high-frequency components, thereby ensuring the stability of the output signal and the detection accuracy.

[0070] Upon reaching the delayed shielding time, the time detection module will no longer be subject to the forced control of the delayed trigger signal, and its output will revert to being determined by its own amplitude-frequency information detection results. The time detection module will then output a shielding signal as normal, reactivating the signal shielding. This step signifies the system's transition from the "blank period" following forced deactivation to the normal adaptive PWM suppression operating mode, ensuring continued suppression of high-frequency interference when necessary.

[0071] Considering the insufficient detection accuracy or slow response speed of traditional PWM suppression circuits, which affects the stability and adaptability of subsequent suppression circuits, this application designs an amplitude-frequency detection module circuit structure. Figure 3 This is a circuit structure diagram of a PWM signal amplitude and frequency detection module, which may include an RC high-pass network, a current mirror comparison circuit, and a signal output circuit.

[0072] A coupling point is provided at the connection between the RC high-pass network and the current mirror comparator circuit. The RC high-pass network inputs a common-mode signal, filters out the low-frequency component of the common-mode signal, and sends the filtered high-frequency component to the coupling point.

[0073] An RC high-pass network is a passive filter circuit composed of resistors and capacitors. Its main function is to allow signals above a certain cutoff frequency to pass through while attenuating signals below that frequency. In this application, the RC high-pass network is used to filter out low-frequency components in the common-mode signal, ensuring that subsequent circuits only process high-frequency components that may cause interference.

[0074] The implementation methods can include: one method is to use a single resistor and capacitor connected in series or in parallel to form a first-order high-pass filter; another method is to use multiple resistors and capacitors cascaded to form a higher-order high-pass filter in order to obtain a steeper frequency response characteristic.

[0075] The current mirror comparator circuit generates reference currents through two current mirror structures. When the filtered high-frequency components cause a rising transition disturbance, a current comparison competition is performed between the two generated reference currents. Voltage output terminals are provided at the reference current output terminals of the two current mirror structures, and the voltage values ​​at these terminals change according to the result of the current comparison competition.

[0076] This current mirror comparator circuit utilizes the characteristics of a current mirror to detect changes in the input signal by replicating and comparing current. Its function is to convert high-frequency components into comparable current signals and generate voltage changes through a current competition mechanism, thereby indicating the presence and intensity of the high-frequency components.

[0077] The implementation methods can include: one method is to use a differential pair input stage, combined with a current mirror as an active load, to amplify the small changes in the input signal and convert them into changes in the output voltage; another method is to use multiple current mirror structures, and by setting different bias currents, to achieve accurate comparison and judgment of the input current.

[0078] The two inputs of the signal output circuit are connected to the voltage leads, and a shielded trigger signal is generated through logic gate circuit operations. Its function is to convert the detection results in the analog domain into control commands in the digital domain for subsequent processing by the logic control circuit.

[0079] The implementation methods may include: one method is to use a Schmitt trigger to shape and threshold the signal at the voltage output terminal, and directly output a digital signal; another method is to use a combinational logic circuit composed of basic logic gates such as AND gates, OR gates, and NOT gates to perform logical operations on the signals at multiple voltage output terminals and generate the final shielding trigger signal.

[0080] Through the above technical solution, the PWM amplitude-frequency detection module of this application can efficiently and reliably detect high-frequency components in the PWM signal. The design of the RC high-pass network ensures that only high-frequency components that may interfere with the system are transmitted, effectively isolating low-frequency noise and improving the focus of detection. The current mirror comparison circuit, utilizing its inherent high sensitivity and fast response characteristics, can quickly capture the minute jumps of high-frequency components and convert them into identifiable electrical signals. The signal output circuit then accurately converts these analog signals into digital logic signals, i.e., shielding trigger signals, providing clear and accurate instructions for subsequent logic control. This precise amplitude-frequency detection mechanism enables the entire adaptive PWM suppression circuit to more accurately determine when signal shielding needs to be activated and to provide more refined amplitude-frequency information based on the characteristics of high-frequency components, thereby allowing the time detection module to more accurately determine the signal shielding duration. This not only significantly improves the suppression effect on common-mode voltage jump interference and reduces output glitches, but also avoids unnecessary or excessively long shielding times due to the accuracy of detection, ensuring the continuity and real-time performance of the current detection signal, ultimately improving the accuracy and stability of current detection in motor control systems or similar applications.

[0081] Figure 4 A schematic diagram of a possible current mirror comparator circuit, an RC high-pass network, and a signal output circuit is shown below, which are explained in detail below:

[0082] 1. Current mirror comparison circuit

[0083] The current mirror comparator circuit includes a first current mirror composed of NMOS transistors NM1, NM2 and NM3, a second current mirror composed of PMOS transistors PM1 and PM2, and a current comparator composed of NMOS transistor NM0 and PMOS transistor PM0.

[0084] NM0, NM1, NM2, and NM3 are connected via a common gate, and the drain and gate of NM3 are connected to both voltage Vs and current source I0. The sources of NM1, NM2, and NM3 are grounded; PM0, PM1, and PM2 are connected via a common gate, and the sources of PM1 and PM2 are connected to voltage Vs, with the drain and gate of PM2 connected to the drain of NM2.

[0085] NM0 and PM0 are connected to the same source, NM0 and PM1 are connected to the same drain, and PM0 and NM1 are connected to the same drain. That is, PM1, NM0, PM0 and NM1 are cascaded in sequence, the power supply Vs is connected to the source of PM1, the drain of PM1 is connected to the drain of NM0, the source of NM0 is connected to the source of PM0, the drain of PM0 is connected to the drain of NM1, and the source of NM1 is grounded.

[0086] The first current mirror generates a first reference current I on NM1. NThe second current mirror generates a second reference current I on PM1. P In one possible embodiment, I can be set. N =I P V BN and V BP These are the bias voltages for NM1 and PM1, respectively. The first voltage output terminal V is located at the common drain connection of NM1 and PM0. P The common drain connection point of NM0 and PM1 is the second voltage lead-out terminal V. N The common drain connection between NM0 and PM0 is the coupling point A.

[0087] 2. RC Qualcomm Network

[0088] Based on this, the RC high-pass network can be further designed to include a resistor divider network and two filter capacitors C. P and C N The structure of the current-limiting resistor R1 is also shown. The resistor divider network consists of two cascaded voltage divider resistors R0 and R1. 01 The voltage divider resistor R0 is connected to the voltage Vs, and after passing through the cascaded voltage divider R... 01 Grounded afterward.

[0089] Filter capacitor C P and C N The positive terminals are respectively input with common-mode signal IN P and IN N The negative terminal is connected to one end of the current-limiting resistor R1, corresponding to coupling point A. The other end of the current-limiting resistor R1 is connected to the voltage divider resistors R0 and R... 01 The voltage divider point B between them. Common-mode signal IN. P and IN N The two common-mode inputs, which serve as current comparators, are used at coupling point A to detect the amplitude and frequency information of the common-mode signal through an RC high-pass network.

[0090] In this embodiment, C can be set P and C N The capacitance values ​​are equal, and the voltage divider resistors R0 and R... 01 When the input terminal IN P and IN N When no signal is coupled to point A, V A =V B =V S / 2, at this time PM0 and NM0 each have |V GS |<|V TH | is in the cutoff state, due to the current source (i.e., the two reference currents generated by the current mirror) I P and I N The existence of V N and V P They were pulled to V respectivelyS and GND. In this state, the RC network has a high-pass characteristic for the common-mode input signal, and its cut-off frequency:

[0091]

[0092] Therefore, this circuit has the function of detecting the amplitude-frequency information of the common-mode signal.

[0093] When the PWM signal has a rapid transition, it is coupled to point A in the form of the input common-mode voltage through the above-mentioned RC high-pass network, and the change in V A depends on the signal transition speed and amplitude; in this embodiment, it can be set that R0 << R1, so the voltage V B at point B changes only slightly with the change in V A , so it is approximately considered that the voltage of V B is constant. When the PWM signal has a rapid rising transition, if V A rises to make |V A -V BP | > |V TH |, then PM0 conducts and generates a current to compete with I N to form a current comparator. When the current of PM0 is greater than I N , the voltage of V P increases, and the rising edge of the output at point C of the signal output circuit triggers the output stage shielding. Conversely, when the PWM signal has a rapid falling transition, if V A decreases to make the gate-source voltage of NM0 |V <​​​​​​​​​​​​​​​​​​​​​​​​​​​​

[0096] When V A After raising or lowering, in addition to the large resistor R1 slowly supplying C P C N Besides capacitor discharge and charge, I N I P It is also gradually discharging and charging the capacitor. When V A As the voltage gradually recovers, PM0 and NM0 are cut off again, V P V N The voltages were restored to GND and V respectively. S Point C outputs a falling edge, at which point the output stage is unshielded. This time varies depending on the amplitude and frequency information of the PWM signal; the higher the high-frequency component, the longer the shielding time, and vice versa, thus achieving adaptive time control. In addition, C... P C N The charging and discharging speed of a capacitor can be controlled by I. N I P The current value is adjusted to further set the length of the adaptive shielding time.

[0097] When a fast differential voltage V appears DM In the most extreme case, the change in point A is V. DM / 2, at the effective input differential voltage V DM Within the range (generally power supply voltage / gain), set I appropriately. N I P The current value and the amplitude detection threshold of the size adjustment signals of PM0 and NM0 can make V P V N The signal remains unchanged, so the differential voltage does not trigger the output stage shielding function.

[0098] 3. Signal output circuit

[0099] The signal output circuit includes two inputs, one of which is connected to the first voltage output terminal V. N This includes two cascaded NOT gates, with the outputs of the two NOT gates connected to one input of a NAND gate. The other path is connected to the second voltage output terminal V. P It includes a NOT gate, and the output of the NOT gate is connected to the other input of the NAND gate. The trigger signal is shielded through the output of the NAND gate.

[0100] By using NAND gates to precisely combine these two optimized signals, the generation of the shielding trigger signal becomes more accurate and timely. This improvement ensures that the PWM detection circuit can capture the transition moment of the PWM signal more quickly and accurately, thereby providing a high-quality trigger signal for the subsequent output stage shielding module.

[0101] Figure 5 A schematic diagram of a possible time detection module is shown, which can be implemented by controlling two D flip-flops. The first D flip-flop has a high-level input at its D terminal, a shield trigger signal input at its CP port, and a shield signal output at its Q port. Correspondingly, the input of the second D flip-flop is connected to the output of the first D flip-flop's Q terminal (i.e., the shield signal), the inverted shield trigger signal is input at its CP port, and the shield release signal is output at its Q port.

[0102] Assuming the rising edge of the CP clock is used as the trigger output, under normal operating conditions,

[0103] When the PWM signal contains high-frequency components, the shielding trigger signal is a valid signal (C is the rising edge pulse), the Q port of the first D flip-flop outputs a valid shielding signal (Q=D high level), and the Q port of the second D flip-flop outputs an invalid signal (CP input falling edge clock, Q=0).

[0104] When the high-frequency component of the PWM signal disappears, the shielding trigger signal is invalid (C is a falling edge pulse) signal. The output of the Q port of the first D flip-flop should remain unchanged (i.e., Q=D high level is maintained). At this time, the input of the CP terminal of the second D flip-flop is a valid (rising edge) signal because C is inverted. Therefore, the output of the Q port is a valid shielding release signal (Q=D=high level).

[0105] Here, the digital logic for the signal shielding switch in the digital circuit can be defined, using 2-bit signal control. When both D flip-flops output a "10" signal, shielding is enabled; when they output an "11" signal, shielding is disabled. Similarly, an output of "00" can be defined to indicate a reset. In chip control, this can be achieved by setting the RSTN port of the D flip-flops low. Likewise, setting the RSTN ports of both D flip-flops high will restore signal shielding detection, ultimately enabling digital control of the output stage shielding module.

[0106] Control based on the RSTN signal can be linked with the time delay module and the shielding timing module. The output is triggered by the rising edge of the CP terminal of the two D flip-flops. During the forced release of signal shielding and within the delayed shielding time, the RSTN of the two D flip-flops is set low, interrupting signal shielding detection. After the delayed shielding time is reached, the RSTN of the two D flip-flops is set high, resuming signal shielding detection. The control logic is similar for the case where the delay is triggered by the shielding release signal, and will not be elaborated further in this embodiment.

[0107] Of course, in some other embodiments, "falling edge" triggering logic can also be used for control, as long as the digital switch logic is designed reasonably.

[0108] Regarding the implementation of the output stage shielding module Figure 6 The schematic diagram of the output stage shielding module is shown. This output stage shielding module includes a first operational amplifier Av1, a second operational amplifier Av2, a shielding switch S, and a voltage regulator capacitor C. It should be noted that the first operational amplifier is a fully differential operational amplifier, and the second operational amplifier is a differential input, single-ended output operational amplifier; the non-inverting inputs of the two operational amplifiers are cascaded together.

[0109] Common-mode signal IN P and IN N The two primary input terminals of the first operational amplifier are respectively input, and the two output terminals are respectively cascaded to the two secondary input terminals of the second operational amplifier. The shielding switch S is set between the two secondary input terminals.

[0110] A first feedback loop is set between the non-inverting input and the non-inverting output of the first operational amplifier, including a first feedback resistor R11 and a first voltage regulator capacitor C1 connected in series; the positive terminal of the first voltage regulator capacitor C1 is connected to the non-inverting input of the second operational amplifier, and the negative terminal is connected to the reference voltage REF.

[0111] A second feedback loop is provided between the negative input and negative output of the first operational amplifier, including a second feedback resistor R20 and a second voltage regulator capacitor C2 connected in series; the positive terminal of the second voltage regulator capacitor C2 is connected to the negative input of the second operational amplifier, and the negative terminal is connected to the output of the second operational amplifier.

[0112] In this circuit structure, the shielded switch S is the main controlled object, and the common-mode signal IN... P and IN N Alternatively, R12 and R21 can be connected in series and then fed into the positive and negative inputs of the first op-amp.

[0113] When the "C" signal transitions to a high level, indicating that the output stage shielding module has received a valid shielding signal, the circuit reacts quickly via the shortest path, shorting the input of the output stage circuit (shielding switch S closes). Stabilizing capacitors C1 and C2 maintain a regulated output voltage during the shielding period, preventing significant output glitches. Conversely, when the output stage shielding module receives a valid shielding release signal, the shielding switch S opens, releasing the signal shielding, and the operational amplifier outputs normally.

[0114] As described above, the shielding switch S can also be controlled to open based on the forced release signal output by the shielding timing module, and it can also be controlled by combinational logic signals or individual logic signals. After the output stage shielding is released, the digital logic will begin a blank time delay timing, during which the PWM suppression function cannot be activated temporarily. This operation ensures that the output has sufficient time to respond to the input differential signal, and avoids the circuit being in a PWM suppression state at high frequencies. High-frequency output shielding would affect the time continuity of the output signal, thus affecting the detection accuracy of the input signal.

[0115] In summary, this solution detects the amplitude-frequency information of the PWM signal and quickly shields the output response when the PWM signal undergoes abrupt changes to reduce output glitches. Furthermore, it adaptively sets the output shielding time based on the amplitude-frequency information to balance PWM suppression effectiveness and signal continuity, thus achieving adaptive PWM suppression. The proposed technology offers advantages such as low cost, high performance, and high reliability, making it well-suited for current detection in fields such as motors, solenoid control, and switching power supplies.

[0116] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. An adaptive PWM suppression circuit for current detection, characterized in that, It includes a PWM detection circuit and a logic control circuit; the PWM detection circuit includes a cascaded amplitude-frequency detection module and a time detection module; the amplitude-frequency detection module receives the PWM signal and detects and generates a shielding trigger signal; the shielding trigger signal is used to characterize the amplitude-frequency information of the PWM signal; The time detection module determines the signal shielding duration based on amplitude-frequency information, and outputs a shielding signal and a shielding release signal according to the shielding duration; the shielding duration is positively correlated with the high-frequency components of the PWM signal; The logic control circuit is equipped with an output stage shielding module and a shielding timing module. When the output stage shielding module receives the shielding signal, it activates signal shielding and stabilizes the circuit output to the steady-state value before the PWM signal jump. When the output stage shielding module receives the shielding release signal, it releases the signal shielding and the control circuit resumes normal output. The shielding timing module is set with a maximum shielding time; The shielding timing module starts timing based on the shielding signal. When the shielding duration corresponding to the amplitude-frequency information is greater than the maximum shielding time, and the shielding timing module reaches the set maximum shielding time, it outputs a forced release signal. The forced release signal is used to control the output stage shielding module to release the signal shielding, and the control circuit resumes normal output.

2. The adaptive PWM suppression circuit for current detection according to claim 1, characterized in that, The logic control circuit also includes a time delay module, which is connected to the shielded timing module and the time detection module. The time delay module is set with a delay shielding time. When the shielding timing module outputs the forced release signal or the time detection module outputs the shielding release signal, the time delay module is triggered to start the delay shielding timer. When the delay shielding timer is started, the time delay module sends a delay trigger signal to the time timing detection module, controlling the time detection module to output the shielding release signal; when the delay shielding time is reached, the time detection module is controlled to resume the function of outputting the shielding signal.

3. The adaptive PWM suppression circuit for current detection according to claim 1 or 2, characterized in that, The amplitude-frequency detection module includes an RC high-pass network, a current mirror comparison circuit, and a signal output circuit. A coupling point is provided at the connection between the RC high-pass network and the current mirror comparison circuit. The RC high-pass network inputs a common-mode signal, filters out the low-frequency component of the common-mode signal, and sends the filtered high-frequency component to the coupling point. The current mirror comparison circuit generates reference currents through two current mirror structures. When the filtered high-frequency component generates a rising jump time disturbance, it compares and competes the two generated reference currents. A voltage output terminal is provided at the reference current output terminals of the two current mirror structures, and the voltage value of the voltage output terminal changes with the result of the current comparison competition. The two inputs of the signal output circuit are respectively connected to the voltage output terminals, and the shielding trigger signal is generated through logic gate circuit operations.

4. The adaptive PWM suppression circuit for current detection according to claim 3, characterized in that, The current mirror comparison circuit includes a first current mirror composed of NMOS transistors NM1, NM2 and NM3, a second current mirror composed of PMOS transistors PM1 and PM2, and a current comparator composed of NMOS transistor NM0 and PMOS transistor PM0. NM0, NM1, NM2, and NM3 are connected in a common gate configuration, with the drain and gate of NM3 sharing the voltage Vs and current source I0; the sources of NM1, NM2, and NM3 are grounded; PM0, PM1, and PM2 are connected in a common gate configuration, with the sources of PM1 and PM2 sharing the voltage Vs, and the drain and gate of PM2 sharing the drain of NM2. NM0 and PM0 share a common source connection; NM0 and PM1 share a common drain connection; PM0 and NM1 share a common drain connection. The first current mirror generates a first reference current I on NM1. N The second current mirror generates a second reference current I on PM1. P The first voltage output terminal V is located at the common drain connection of NM1 and PM0. P The common drain connection point of NM0 and PM1 is the second voltage lead-out terminal V. N The common drain connection between NM0 and PM0 is the coupling point.

5. The adaptive PWM suppression circuit for current detection according to claim 3, characterized in that, The RC high-pass network includes a resistor divider network and two filter capacitors C. P and C N And a current-limiting resistor R1; the resistor divider network includes two cascaded voltage divider resistors R0 and R... 01 The voltage divider resistor R0 is connected to the voltage Vs, and after passing through the cascaded voltage divider R... 01 Rear grounding; Filter capacitor C P and C N The positive terminals are respectively input with common-mode signal IN P and IN N The negative terminal is connected to one end of the current-limiting resistor R1, corresponding to the coupling point; the other end of the current-limiting resistor R1 is connected to the voltage divider resistors R0 and R... 01 The pressure dividing point B between them; Common-mode signal IN P and IN N The two common-mode inputs, which serve as current comparators, are used to detect the amplitude and frequency information of the common-mode signal at the coupling point through the RC high-pass network.

6. The adaptive PWM suppression circuit for current detection according to claim 4, characterized in that, The signal output circuit includes two inputs, one of which is connected to the first voltage output terminal V. N It includes two cascaded NOT gates, and the outputs of the two NOT gates are connected to one input of the NAND gate; The other path is connected to the second voltage output terminal V. P It includes a NOT gate, and the output of the NOT gate is connected to the other input of the NAND gate, through which the shielding trigger signal is output.

7. The adaptive PWM suppression circuit for current detection according to claim 1, characterized in that, The time detection module includes two D flip-flops. The D terminal of the first D flip-flop is input with a high level, the CP port is input with the shielding trigger signal, and the Q port is output with the shielding signal. The D input of the second D flip-flop is connected to the Q output of the first D flip-flop, the CP port is input with the inverted signal of the shielding trigger signal, and the Q port outputs the shielding release signal. When the PWM signal contains high-frequency components, the shielding trigger signal is a valid signal, and the Q port of the first D flip-flop outputs a valid shielding signal. When the high-frequency components contained in the PWM signal disappear, the shielding trigger signal becomes invalid, and the Q port output of the second D flip-flop becomes an effective shielding release signal.

8. The adaptive PWM suppression circuit for current detection according to claim 1, characterized in that, The output stage shielding module includes a first operational amplifier Av1, a second operational amplifier Av2, a shielding switch S, and a voltage regulator capacitor C; the first operational amplifier is a fully differential operational amplifier, and the second operational amplifier is a differential input, single-ended output operational amplifier. Common-mode signal IN P and IN N The two first-stage input terminals of the first operational amplifier are respectively input, and the two output terminals are respectively cascaded to the two second-stage input terminals of the second operational amplifier. The shielding switch S is set between the two second-stage input terminals. A first feedback loop is provided between the non-inverting input and the non-inverting output of the first operational amplifier, including a first feedback resistor and a first voltage-regulating capacitor connected in series; the positive terminal of the first voltage-regulating capacitor is connected to the non-inverting input of the second operational amplifier, and the negative terminal is connected to the reference voltage REF. A second feedback loop is provided between the negative input and negative output of the first operational amplifier, including a second feedback resistor and a second voltage-regulating capacitor connected in series; the positive terminal of the second voltage-regulating capacitor is connected to the negative input of the second operational amplifier, and the negative terminal is connected to the output of the second operational amplifier.

9. The adaptive PWM suppression circuit for current detection according to claim 8, characterized in that, When the output stage shielding module receives a valid shielding signal, the shielding switch S closes, signal shielding is activated, and the voltage regulator capacitor maintains a stable output voltage during the shielding time. When the output stage shielding module receives a valid shielding release signal, the shielding switch S opens, the signal shielding is released, and the operational amplifier outputs normally.

10. The adaptive PWM suppression circuit for current detection according to claim 7, characterized in that, The output is triggered by the rising edge of the CP terminal of the two D flip-flops. During the forced release of signal shielding and within the delayed shielding time, the RSTN of the two D flip-flops is set to a low level to interrupt the signal shielding detection. After the delay shielding time is reached, the RSTN of the two D flip-flops is set to high level to restore signal shielding detection.

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