Circuit board, preparation method thereof and display module

Abstract

The invention discloses a circuit board, a preparation method thereof and a display module, and solves the problem of poor micro-motion performance of a circuit board in the prior art. The circuit board comprises a base material layer; the plurality of extending conductive layers are respectively overlapped on two opposite sides of the base material layer, and the extending conductive layers extend from the non-micro-motion area to the micro-motion area; the extending conductive layer comprises at least one hole plating bonding pad; the plurality of main body conductive layers are respectively positioned on two sides, far away from the base material layer, of the extension conductive layer, and the main body conductive layers are positioned in the non-micro-motion area; the main body conductive layer comprises at least one plate plating bonding pad; at least one hole penetrating at least one of the extended conductive layer and the body conductive layer, the hole plating pad and the board plating pad surrounding the hole; and the at least one connecting part is positioned in the hole and is connected with the hole plating bonding pad and the board plating bonding pad.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a circuit board, a preparation method thereof and a display module. BACKGROUND

[0002] In recent years, with the rapid development of flexible display technology, folding display products have emerged as the times require. The folding display products integrated with touch control function are often subject to micro deformation caused by touch pressing. The micro motion area of the circuit board in the folding display products is prone to breakage under the action of high-frequency micro deformation, resulting in abnormal function. SUMMARY

[0003] Therefore, the present application provides a circuit board, a preparation method thereof and a display module, which solve the problem of poor micro motion performance of the circuit board in the prior art.

[0004] The first aspect of the present application provides a circuit board having a non-micro motion area and a micro motion area. The circuit board comprises: a substrate layer; a plurality of extended conductive layers respectively stacked on opposite sides of the substrate layer, the extended conductive layers extending from the non-micro motion area to the micro motion area; the extended conductive layer comprises a first wiring and at least one hole plating pad, the hole plating pad and the first wiring are electrically connected; a plurality of main body conductive layers are respectively located on the two sides of the extended conductive layer away from the substrate layer, and the main body conductive layer is located in the non-micro motion area; the main body conductive layer comprises a second wiring and at least one plate plating pad, the plate plating pad and the second wiring are electrically connected; at least one hole, the hole penetrates at least one of the extended conductive layer and the main body conductive layer, the hole plating pad and the plate plating pad are arranged around the hole; at least one connecting part, the connecting part is located in the hole and connected with the hole plating pad and the plate plating pad.

[0005] In combination with the first aspect, in some possible implementation manners, the thickness of the hole plating pad is greater than the thickness of the first wiring; preferably, the hole plating pad comprises a stacked pad base and a plating layer part, the plating layer part is located on the side of the pad base away from the substrate layer, and the pad base and the first wiring are arranged in the same layer; preferably, the material of the pad base and the first wiring comprises rolled copper, and the material of the plating layer part comprises electrolytic copper.

[0006] In combination with the first aspect, in some possible implementation manners, the thickness of the plate plating pad is equal to the thickness of the second wiring; preferably, the main body conductive layer comprises a stacked conductive substrate layer and a plating layer, the plating layer is located on the side of the conductive substrate layer away from the substrate layer; part of the second wiring is located in the conductive substrate layer, and the other part is located in the plating layer; part of the plate plating pad is located in the conductive substrate layer, and the other part is located in the plating layer; preferably, the materials of the conductive substrate layer and the plating layer are the same; preferably, the material of the conductive substrate layer comprises electrolytic copper.

[0007] In conjunction with the first aspect, in some possible implementations, the diameter of the board-mounted pad is less than or equal to the diameter of the via-mounted pad; preferably, the diameter of the board-mounted pad is greater than or equal to 0.25 micrometers and less than or equal to 0.35 micrometers; preferably, the diameter of the board-mounted pad includes 0.3 micrometers; preferably, the diameter of the via-mounted pad is greater than or equal to 0.3 micrometers and less than or equal to 0.5 micrometers; preferably, the diameter of the via-mounted pad includes any one of 0.3 micrometers, 0.35 micrometers, and 0.45 micrometers; preferably, the circuit board includes gold fingers located on the main conductive layer.

[0008] In conjunction with the first aspect, in some possible implementations, the plurality of extended conductive layers include a first extended conductive layer and a second extended conductive layer respectively located on both sides of the substrate layer; the plurality of main conductive layers include a first main conductive layer and a second main conductive layer, wherein the first main conductive layer is located on the side of the first extended conductive layer away from the substrate layer, and the second main conductive layer is located on the side of the second extended conductive layer away from the substrate layer.

[0009] In conjunction with the first aspect, in some possible implementations, at least one hole includes a first hole that penetrates a first extended conductive layer and a first main conductive layer; the first extended conductive layer includes a first hole pad, the first main conductive layer includes a first plate pad, and the first hole pad and the first plate pad respectively surround the first hole; the orthographic projection of the first plate pad on the substrate layer is located within the orthographic projection range of the first hole pad on the substrate layer; preferably, the difference between the diameters of the first plate pad and the first hole pad is greater than or equal to 0.1 micrometers and less than or equal to 0.2 micrometers; preferably, the diameter of the first plate pad includes 0.3 micrometers; preferably, the diameter of the first hole pad includes 0.45 micrometers.

[0010] In conjunction with the first aspect, in some possible implementations, the first hole also penetrates a second extended conductive layer, the second extended conductive layer including a second hole pad, the second hole pad being disposed around the first hole, and the orthographic projection of the second hole pad on the substrate layer falling within the orthographic projection range of the first hole pad on the substrate layer; preferably, the difference in diameter between the second hole pad and the first hole pad is greater than or equal to 0.05 and less than or equal to 0.15; preferably, the orthographic projection of the second hole pad on the substrate layer covers the orthographic projection of the first plate pad on the substrate layer; preferably, the diameter of the second hole pad includes 0.35 micrometers; preferably, the non-micro-motion region includes a first main region, and the first hole is located in the first main region.

[0011] In conjunction with the first aspect, in some possible implementations, at least one hole includes a second hole that penetrates the first extended conductive layer and the second extended conductive layer; the first extended conductive layer includes a third hole pad, and the second extended conductive layer includes a fourth hole pad, with the third and fourth hole pads respectively surrounding the second hole; the orthographic projections of the third hole pad and the fourth hole pad on the substrate layer are equal; preferably, the non-micromotion region includes a first main region, and the second hole is located in the micromotion region or the first main region.

[0012] In conjunction with the first aspect, in some possible implementations, at least one hole includes a third hole that penetrates the first main conductive layer, the first extended conductive layer, the second extended conductive layer, and the second main conductive layer; the first main conductive layer includes a second plated pad, the second main conductive layer includes a third plated pad, the first extended conductive layer includes a fifth hole plated pad, and the second extended conductive layer includes a sixth hole plated pad; the second plated pad, the third plated pad, the fifth hole plated pad, and the sixth hole plated pad respectively surround the third hole and their orthographic projections on the substrate layer coincide; preferably, the non-micro-motion region includes the first main region, and the third hole is located in the first main region.

[0013] In conjunction with the first aspect, in some possible implementations, at least one hole includes a fourth hole that penetrates the first main conductive layer. The first main conductive layer includes a fourth plated pad that surrounds the fourth hole. A connection in the fourth hole connects the first main conductive layer and the first extended conductive layer. Preferably, the first extended conductive layer includes a seventh hole plated pad, and the orthographic projection of the seventh hole plated pad on the substrate layer coincides with the orthographic projection of the fourth plated pad on the substrate layer. Preferably, the non-micro-motion region includes a first main region or a transition region, and the fourth hole is located in the first main region or the transition region.

[0014] In conjunction with the first aspect, in some possible implementations, the multiple main conductive layers also include a third main conductive layer and a fourth main conductive layer, wherein the third main conductive layer is located on the side of the first main conductive layer away from the substrate layer, and the fourth main conductive layer is located on the side of the second main conductive layer away from the substrate layer.

[0015] In conjunction with the first aspect, in some possible implementations, at least one hole includes a first hole that penetrates the third main conductive layer and the first main conductive layer; the third main conductive layer includes a fifth plated pad, the first main conductive layer includes a first plated pad, the fifth plated pad and the first plated pad respectively surround the first hole, and the orthographic projection of the fifth plated pad on the substrate layer coincides with the orthographic projection of the first plated pad on the substrate layer.

[0016] In conjunction with the first aspect, in some possible implementations, at least one hole includes a fifth hole that penetrates the first main conductive layer and the third main conductive layer. The first main conductive layer includes a sixth plated pad, and the third main conductive layer includes a seventh plated pad. The orthographic projections of the sixth plated pad and the seventh plated pad on the substrate layer coincide. Preferably, the connecting portion in the fifth hole connects to a first extended conductive layer. The first extended conductive layer includes an eighth hole plated pad, and the orthographic projections of the eighth hole plated pad and the seventh plated pad on the substrate layer coincide. Preferably, the non-micro-motion region includes a first main region, and the fifth hole is located in the first main region.

[0017] In conjunction with the first aspect, in some possible implementations, the non-micro-motion area includes a transition area, and the fourth hole is located in the transition area; the circuit board also includes a second main body area, which is located on the side of the transition area away from the micro-motion area; the first main body conductive layer and the second main body conductive layer extend from the transition area to the second main body area.

[0018] In conjunction with the first aspect, in some possible implementations, at least one hole further includes a sixth hole, which penetrates the first extended conductive layer, and the connection portion in the sixth hole connects to the second extended conductive layer; preferably, the first extended conductive layer includes a ninth hole plating pad, and the second extended conductive layer includes a tenth hole plating pad, the orthographic projection of the ninth hole plating pad on the substrate layer and the orthographic projection of the tenth hole plating pad on the substrate layer coincide; preferably, the sixth hole is located in the micro-motion region.

[0019] In conjunction with the first aspect, in some possible implementations, at least one hole further includes a seventh hole, which penetrates the first main conductive layer and the second main conductive layer. The first main conductive layer includes an eighth plated pad, and the second main conductive layer includes a ninth plated pad. The eighth and ninth plated pads respectively surround the seventh hole, and the orthographic projection of the eighth plated pad on the second main conductive layer coincides with the ninth plated pad. Preferably, the seventh hole is located in the second main body region.

[0020] In conjunction with the first aspect, in some possible implementations, the ductility of the extended conductive layer is greater than that of the main conductive layer; preferably, the circuit board further includes multiple insulating layers, which are located between adjacent main conductive layers, between adjacent extended conductive layers, or between adjacent main conductive layers and extended conductive layers; preferably, the circuit board further includes a first protective layer and a second protective layer, the first protective layer being located on one side of the substrate layer, on the side of the main conductive layer furthest from the substrate layer, and the second protective layer being located on the other side of the substrate layer, on the side of the main conductive layer furthest from the substrate layer.

[0021] The second aspect of this application provides a method for fabricating a circuit board, the circuit board including a micro-motion region and a non-micro-motion region; the fabrication method includes: fabricating a plurality of extended conductive layers, at least one first sub-hole, and at least one first sub-connection on a substrate layer to obtain a first sub-board, the plurality of extended conductive layers being located on opposite sides of the substrate layer, the extended conductive layers extending from the non-micro-motion region to the micro-motion region, the extended conductive layers including a first wiring and at least one hole plating pad, the hole plating pad surrounding the first sub-hole, the first sub-connection being located inside the first sub-hole, the first sub-connection, the hole plating pad, and the first wiring being electrically connected in sequence; fabricating at least one main conductive layer, at least one second sub-hole, and at least one second sub-connection on the first sub-board to obtain a second sub-board, the main conductive layer being located on the side of the extended conductive layer away from the substrate layer and located in the non-micro-motion region; the main conductive layer including a second wiring and at least one plate plating pad, the plate plating pad surrounding the second sub-hole, the second sub-connection being located inside the second sub-hole, the second sub-connection, the plate plating pad, and the second wiring being electrically connected in sequence, the second sub-hole and the first sub-hole being stacked or staggered. In conjunction with the second aspect, in some possible implementations, fabricating multiple extended conductive layers, at least one first sub-hole, and at least one first sub-connection on a substrate layer to obtain a first sub-board includes: fabricating a first conductive layer and a second conductive layer on opposite sides of the substrate layer to obtain a copper-clad substrate; drilling a hole in the copper-clad substrate to obtain at least one first sub-hole, the first sub-hole penetrating the copper-clad substrate; metallizing the first sub-hole using a hole plating process to obtain a first sub-connection; and patterning the metallized first and second conductive layers to obtain an extended conductive layer. Preferably, fabricating at least one main conductive layer, at least one second sub-hole, and at least one second sub-connection on the first sub-board to obtain a second sub-board includes: fabricating a third conductive layer on the side of the first conductive layer away from the substrate layer using a lamination process, and fabricating a fourth conductive layer on the side of the second conductive layer away from the substrate layer to obtain a third sub-board, wherein the ductility of the third and fourth conductive layers is less than that of the first conductive layer. The third sub-board is formed by drilling holes to obtain at least one second sub-hole, which penetrates at least one of the third and fourth conductive layers, or the first, second, third, and fourth conductive layers are stacked or misaligned with each other. The second sub-hole is metallized using a plate plating process to obtain a second sub-connection. The metallized third and fourth conductive layers are patterned to obtain a first and second main conductive layers, respectively. Preferably, in the step of preparing the third conductive layer on the side of the first conductive layer away from the substrate layer and the fourth conductive layer on the side of the second conductive layer away from the substrate layer using a lamination process to obtain the third sub-board, the third and fourth conductive layers further extend into the second main body region. In the step of drilling holes to obtain at least one second sub-hole, some of the second sub-holes are located in the second main body region, and the second sub-holes in the second main body region penetrate the third and fourth conductive layers.

[0022] A third aspect of this application provides a display module, including: a display panel; and a circuit board provided in any embodiment of this application, or a circuit board prepared according to the preparation method provided in any embodiment of this application, wherein the circuit board and the display panel are bonded together.

[0023] According to the circuit board and its fabrication method and display module provided in the embodiments of this application, by extending the highly ductile conductive layer in the circuit board from the non-micro-motion area to the micro-motion area, and placing the low-ductile conductive layer in the circuit board in the non-micro-motion area without extending it to the micro-motion area, the micro-motion performance of the micro-motion area is improved. At the same time, since the hole plating process has less impact on the ductility of the conductive layer than the board plating process, that is, the hole plating process reduces the ductility of the conductive layer less than the board plating process reduces its elongation. Therefore, by using the hole plating process for hole metallization of the highly ductile conductive layer and the board plating process for hole metallization of the low-ductile conductive layer, the micro-motion area only contains conductive holes formed by the hole plating process, and the non-micro-motion area only contains conductive holes formed by the board plating process. This further improves the micro-motion performance of the micro-motion area while ensuring that the conductive layer thickness in the non-micro-motion area meets the requirements, thereby improving the current carrying capacity of the circuit board power supply. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a display module in related technologies.

[0025] Figure 2 This is a schematic diagram of the cross-sectional structure of the circuit board provided in the first embodiment of this application.

[0026] Figure 3 for Figure 2 The first enlarged view of the circuit board shown.

[0027] Figure 4 for Figure 2 A second enlarged view of the circuit board shown.

[0028] Figure 5 for Figure 2 The third enlarged view of the circuit board shown.

[0029] Figure 6 for Figure 2 The fourth enlarged view of the circuit board shown.

[0030] Figure 7 This is a schematic diagram of the cross-sectional structure of the circuit board provided in the second embodiment of this application.

[0031] Figure 8 for Figure 7 The first enlarged view of the circuit board shown.

[0032] Figure 9for Figure 7 A second enlarged view of the circuit board shown.

[0033] Figure 10 This is a schematic cross-sectional view of the circuit board provided in the third embodiment of this application.

[0034] Figure 11 This is a schematic flowchart illustrating a method for fabricating a circuit board according to an embodiment of this application.

[0035] Figures 12a-12k To execute Figure 11 A schematic diagram of the structure of the intermediate product obtained during the preparation method shown.

[0036] Figure 13 The diagram shown is a top view of a display module provided in an embodiment of this application. Detailed Implementation

[0037] Figure 1 This is a schematic diagram of the structure of a display module in related technologies. For example... Figure 1 As shown, the display module includes a display panel 100 and a circuit board 200, which are electrically connected. The circuit board 200 is stacked on the non-display side of the display panel 100. The circuit board 200 has a micro-motion area DA, which is bent and plugged into the main board. Exemplarily, the display panel 100 includes a flexible display panel.

[0038] like Figure 1 As shown, when the user frequently touches the display surface of the display panel 100, the display panel undergoes slight deformation. This slight deformation will cause the circuit board 200 to vibrate. Frequent vibration will cause the circuit of the micro-motion area DA to break, resulting in abnormal display or touch function.

[0039] In view of this, this application provides a circuit board and its manufacturing method, as well as a display device. By extending a highly ductile conductive layer from the non-micro-motion area to the micro-motion area in the circuit board, and placing a less ductile conductive layer in the non-micro-motion area without extending it to the micro-motion area, the micro-motion performance of the micro-motion area is improved. Meanwhile, since the hole plating process has less impact on the ductility of the conductive layer than the board plating process (i.e., the hole plating process reduces the ductility of the conductive layer less than the board plating process), the hole plating process is used to metallize the highly ductile conductive layer, and the board plating process is used to metallize the less ductile conductive layer. This ensures that the micro-motion area only contains conductive holes formed by the hole plating process, and the non-micro-motion area only contains conductive holes formed by the board plating process. This further improves the micro-motion performance of the micro-motion area while ensuring that the conductive layer thickness in the non-micro-motion area meets the requirements, thereby improving the current carrying capacity of the circuit board power supply.

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0042] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0043] Figure 2 This is a schematic cross-sectional view of the circuit board provided in the first embodiment of this application. Figure 2 As shown, circuit board 200 has a non-micro-motion area FA and a micro-motion area DA. The micro-motion area DA refers to a specific area on circuit board 200 designed for frequent bending, flexing, and twisting. This area is not intended to remain static, but rather to undergo repeated dynamic movement throughout the product's lifecycle. For example, in a display module, circuit board 200 is used to connect display panel 100 and the motherboard. As the name suggests, the non-micro-motion area FA refers to areas other than the micro-motion area DA, such as component areas, transition areas, and non-wiring areas.

[0044] The circuit board 200 includes: a substrate layer 1, a plurality of extended conductive layers 2, a plurality of main conductive layers 3, at least one via H, and at least one connecting portion 4. The plurality of extended conductive layers 2 are stacked on opposite sides of the substrate layer 1, extending from a non-micro-motion region FA to a micro-motion region DA. Each extended conductive layer 2 includes a first wiring 21 and at least one via plating pad 22, which is electrically connected to the first wiring 21. The plurality of main conductive layers 3 are located on opposite sides of the extended conductive layers 2 away from the substrate layer 1, and are located in the non-micro-motion region FA. Each main conductive layer 3 includes a second wiring 31 and at least one plated pad 32, which is electrically connected to the second wiring 31. The via H penetrates at least one of the extended conductive layers 2 and the main conductive layers 3, and the via plating pad 22 and the plated pad 32 are arranged around the via H. The connecting portion 4 is located within the via H and is connected to the via plating pad 22 and the plated pad 32.

[0045] The substrate layer 1, also known as the insulating base film, is made of materials such as polyimide, polyester, and polyethylene naphthalate.

[0046] The substrate layer 1 has a first side C1 and a second side C2 disposed opposite to each other. The circuit board 200 includes a plurality of extended conductive layers 2, which can be divided into two parts, one part located on the first side C1 of the substrate layer 1 and the other part located on the second side C2 of the substrate layer 1. The number of extended conductive layers 2 on both sides of the substrate layer 1 may be equal or unequal.

[0047] In one embodiment, the ductility of the main conductive layer 3 is less than that of the extended conductive layer 2. Exemplarily, the ductility of the main conductive layer 3 and the extended conductive layer 2 can be measured by a tensile test. Specifically, firstly, a main conductive layer sample and an extended conductive layer sample are prepared according to predetermined standards. Secondly, both ends of the two samples are clamped in the grips of a universal testing machine. Next, the testing machine applies a circumferential tensile force to the sample at a constant rate until the sample breaks. During the test, the testing machine automatically records the "tension-displacement" curve throughout the process. Subsequently, data such as elongation after fracture and reduction of area are determined based on the "tension-displacement" curve. Elongation after fracture is a key indicator of "ductility"; a higher value indicates a greater amount of plastic deformation that the material can withstand before fracture, and thus better ductility. Reduction of area is a key indicator of "ductility"; a higher value indicates better ductility.

[0048] The circuit board 200 also includes a plurality of main conductive layers 3, which can be divided into two parts. One part of the main conductive layer 3 is located on the side of the extended conductive layer 2 on the first side C1 away from the substrate layer 1, and the other part of the main conductive layer 3 is located on the side of the extended conductive layer 2 on the second side C2 away from the substrate layer 1.

[0049] The extended conductive layer 2 includes a first wiring 21 and at least one via plating pad 22. The via plating pad 22 is connected to the first wiring 21 and is prepared by a via plating process. The thickness of the via plating pad 22 is greater than the thickness of the first wiring 21. Specifically, the via plating pad 22 includes a stacked pad base 221 and a plating portion 222. The plating portion 222 is located on the side of the pad base 221 away from the substrate layer 1. The pad base 221 and the first wiring 21 are disposed in the same layer, and the pad base 221 and the first wiring 21 are made of the same material and have the same thickness. Thus, the thickness of the via plating pad 22 is greater than the thickness of the first wiring 21. Exemplarily, the plating portion 222 and the connection portion 24 within the hole H surrounding the via plating pad 22 are integrally formed. Exemplarily, the materials of the pad base 221 and the first wiring 21 include rolled copper, and the material of the plating portion 222 includes electrolytic copper.

[0050] In terms of the number of stacked film layers, the main conductive layer 3 includes a stacked conductive substrate layer 301 and a plating layer 302. The plating layer 302 is located on the side of the conductive substrate layer 301 away from the substrate layer 1, and the plating layer 302 is obtained by a plate-mount process. The plating layer 302 and the connecting portion 4 in the hole in the main conductive layer 3 are integrally formed. For example, the conductive substrate layer 301 and the plating layer 302 are made of the same material, such as electrolytic copper. In terms of component function, the main conductive layer 3 includes a second wiring 31 and at least one plate-mount pad 32, which is connected to the second wiring 31. A portion of the second wiring 31 is located in the conductive substrate layer 301, and another portion is located in the plating layer 302. A portion of the plate-mount pad 32 is located in the conductive substrate layer 301, and another portion is located in the plating layer 302. Therefore, the thickness of the second wiring 31 is equal to the thickness of the plate-mount pad 32.

[0051] The connecting portion 4 can either completely fill the hole H or only cover the inner wall of the hole H. When the connecting portion 4 only covers the inner wall of the hole H, the connecting portion 4 forms a tubular structure within the hole H. For example, the connecting portion 4 can fill blind holes and buried holes; for instance, the first hole H1 is a blind hole, and the connecting portion 4 fills the first hole H1. As another example, the second hole H2 is a buried hole, and the connecting portion 4 fills the second hole H2. Alternatively, the connecting portion 4 can only cover the inner wall of a through hole. For example, the third hole H3 is a through hole, and the connecting portion 4 only covers the inner wall of the third hole H3, forming a tubular structure within the third hole H3.

[0052] In one embodiment, the circuit board includes gold fingers located on the main conductive layer 3. The advantage is that, compared to the extended conductive layer 2, the main conductive layer 3 exhibits more stable expansion and contraction properties during the lamination process in the circuit board fabrication process, making it easier to meet the size requirements of the gold fingers.

[0053] In one embodiment, such as Figure 2 As shown, the circuit board 200 also includes a plurality of insulating layers 5, which are located between adjacent main conductive layers 3, between adjacent extended conductive layers 2, or between adjacent main conductive layers 3 and extended conductive layers 2. That is, an insulating layer 5 is disposed between adjacent main conductive layers 3, between adjacent extended conductive layers 2, and between adjacent main conductive layers 3 and extended conductive layers 2. For example, the material of the insulating layer 5 is the same as the material of the substrate layer 1.

[0054] In one embodiment, such as Figure 2 As shown, the circuit board 200 also includes a first protective layer 61 and a second protective layer 62. The first protective layer 61 is located on one side of the substrate layer 1, on the side where the main conductive layer 3 furthest from the substrate layer 1 is away from the substrate layer 1. The second protective layer 62 is located on the other side of the substrate layer 1, on the side where the main conductive layer 3 furthest from the substrate layer 1 is away from the substrate layer 1.

[0055] According to the circuit board provided in this embodiment, by extending the highly ductile extended conductive layer 2 from the non-micro-motion region FA to the micro-motion region DA, and placing the low-ductile main conductive layer 3 in the non-micro-motion region FA without extending it to the micro-motion region DA, the micro-motion performance of the micro-motion region DA is improved. Simultaneously, the highly ductile extended conductive layer 2 is metallized using a hole plating process, and the low-ductile main conductive layer 3 is metallized using a board plating process. This ensures that the micro-motion region DA only has conductive holes formed by the hole plating process (including the connection portion 4 of hole H and filling hole H), while the non-micro-motion region FA only has conductive holes formed by the board plating process. This further improves the micro-motion performance of the micro-motion region DA while ensuring that the conductive layer thickness in the non-micro-motion region FA meets the requirements, thereby improving the current-carrying capacity of the circuit board power supply.

[0056] In one embodiment, the diameter of the board-mounted pad 32 is less than or equal to the diameter of the hole-mounted pad 22. For ease of explanation, the diameter of the board-mounted pad 32 is denoted as d, and the diameter of the hole-mounted pad 22 is denoted as D, where d ≤ D. For example, as shown... Figure 2 As shown, the plurality of extended conductive layers 2 include a first extended conductive layer 210, which includes a first via plating pad Hh1. The plurality of main conductive layers 3 include a first main conductive layer 310, which includes a first plated pad Hb1, the diameter of which is smaller than the diameter of the first via plating pad Hh1. For example, as... Figure 2 As shown, the first extended conductive layer 210 also includes a fifth hole plating pad Hh5, and the first main conductive layer 310 also includes a second plate plating pad Hb2, the second plate plating pad Hb2 and the fifth hole plating pad Hh5 having the same diameter.

[0057] For example, the diameter of the board-plated pad 32 is greater than or equal to 0.25 micrometers and less than or equal to 0.35 micrometers, i.e., 0.25 ≤ d ≤ 0.35. For instance, the diameter of the first board-plated pad Hb1 and the second board-plated pad Hb2 is both 0.3 micrometers.

[0058] For example, the diameter of the hole-plating pad 22 is greater than or equal to 0.3 micrometers and less than or equal to 0.5 micrometers, i.e., 0.3 ≤ D ≤ 0.5. For example, the diameter of the fifth hole-plating pad Hh5 is 0.3 micrometers, and the diameter of the first hole-plating pad Hh1 is 0.45 micrometers. The plurality of extended conductive layers 2 also include a second extended conductive layer 220, which includes a second hole-plating pad Hh2, the diameter of which is 0.35 micrometers.

[0059] According to the circuit board provided in this embodiment, by differentiating the diameters of the hole-plating pads 22 and the board-plating pads 32, the area occupied by the hole-plating pads 22 and the board-plating pads 32 on their respective layers is optimized, and they are neither too large nor too small, thereby increasing the wiring space and ensuring the reliability of the circuit.

[0060] The following section will provide a detailed description of the structure of hole H and the differentiated design of the diameters of the hole-plating pad 22 and the plate-plating pad 32 that mate with hole H.

[0061] In one embodiment, such as Figure 2 As shown, the multiple extended conductive layers 2 include a first extended conductive layer 210 and a second extended conductive layer 220 located on both sides of the substrate layer 1, respectively. The multiple main conductive layers 3 include a first main conductive layer 310 and a second main conductive layer 320, with the first main conductive layer 310 located on the side of the first extended conductive layer 210 away from the substrate layer 1, and the second main conductive layer 320 located on the side of the second extended conductive layer 220 away from the substrate layer 1. In this case, the circuit board 200 can be a four-layer circuit board. Correspondingly, the non-micro-motion area FA can be the first main area ZA, which is adjacent to the micro-motion area DA. The first main area ZA includes wiring areas, device areas, etc., capable of realizing predetermined functions.

[0062] In order to accommodate the stacked structure of the circuit board 200 and the structure of the hole H, the dimensions of the hole plating pad 22 in the extended conductive layer 2 and the board plating pad 32 in the main conductive layer 3 have been improved in this embodiment.

[0063] like Figure 2 As shown, taking a four-layer circuit board as an example, the holes H in the circuit board 200 include various types of holes, such as at least one of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4.

[0064] Figure 3 for Figure 2 The first enlarged view of the circuit board shown. (Combined with...) Figure 2 and Figure 3As shown, at least one hole H includes a first hole H1, which penetrates the first extended conductive layer 210 and the first main conductive layer 310. The first extended conductive layer 210 includes a first hole plating pad Hh1, and the first main conductive layer 310 includes a first plated plating pad Hb1. The first hole plating pad Hh1 and the first plated plating pad Hb1 are respectively disposed around the first hole H1. The orthographic projection of the first plated plating pad Hb1 on the substrate layer 1 is within the orthographic projection range of the first hole plating pad Hh1 on the substrate layer 1. In one embodiment, the difference between the diameters of the first hole plating pad Hh1 and the first plated plating pad Hb1 is greater than or equal to 0.1 micrometers and less than or equal to 0.2 micrometers. The diameter of the first plated plating pad Hb1 is denoted as d1, and the diameter of the first hole plating pad Hh1 is denoted as D1, then 0.1 ≤ D1 - d1 ≤ 0.2. For example, the diameter of the first plated plating pad Hb1 includes 0.3 micrometers. The diameter of the first hole plating pad Hh1 is 0.45 micrometers.

[0065] In this embodiment, the plurality of connecting portions 4 include a first connecting portion 41, which fills the first hole H1 and connects the first main conductive layer 310 and the first extended conductive layer 210.

[0066] According to the circuit board provided in this embodiment, when hole H penetrates adjacent extended conductive layer 2 and main conductive layer 3, such as the first extended conductive layer 210 and the first main conductive layer 310, the diameter of the first hole plating pad Hh1 in the first extended conductive layer 210 is larger than the diameter of the first plate plating pad Hb1 in the first main conductive layer 310, and the difference in diameter is between 0.1 and 0.2. The advantage of this is that the diameter difference can compensate for the expansion and contraction differences between the first extended conductive layer 210 and the first main conductive layer 310 during the circuit board manufacturing process, ensuring the drilling position accuracy of the first hole H1, and thus ensuring the reliability of the electrical connection between the first extended conductive layer 210 and the first main conductive layer 310.

[0067] In one embodiment, see below. Figure 2 and Figure 3The first hole H1 also penetrates the second extended conductive layer 220, which includes a second hole plating pad Hh2. The second hole plating pad Hh2 is disposed around the first hole H1, and its orthographic projection on the substrate layer 1 lies within the orthographic projection range of the first hole plating pad Hh1 on the substrate layer 1. The orthographic projection of the second hole plating pad Hh2 on the substrate layer 1 covers the orthographic projection of the first plate plating pad Hb1 on the substrate layer 1. The difference between the diameters of the first hole plating pad Hh1 and the second hole plating pad Hh2 is greater than or equal to 0.05 and less than or equal to 0.15. The diameter of the second hole plating pad Hh2 is denoted as D2, where 0.05 ≤ D1 - D2 ≤ 0.15. For example, the diameter of the second hole plating pad Hh2 includes 0.35 micrometers. For example, the first hole H1 is located in the first body region ZA1.

[0068] In this embodiment, the first connecting portion 41 connects the first main conductive layer 310, the first extended conductive layer 210, and the second extended conductive layer 220.

[0069] According to the circuit board provided in this embodiment, when the first hole H1 simultaneously penetrates the first main conductive layer 310, the first extended conductive layer 210, and the second extended conductive layer 220, the diameter of the second hole plating pad Hh2 in the second extended conductive layer 220 is between the first plate plating pad Hb1 and the first hole plating pad Hh1, and the difference between the diameters of the second hole plating pad Hh2 and the first hole plating pad Hh1 is between 0.05 and 0.15. The advantage of this is that this diameter difference can compensate for the expansion and contraction differences between the first extended conductive layer 210 and the second extended conductive layer 220 during the circuit board manufacturing process, ensuring the drilling position accuracy of the first hole H1, and thus ensuring the electrical connection reliability of the first extended conductive layer 210 and the second extended conductive layer 220.

[0070] Figure 4 for Figure 2 A second enlarged view of the circuit board shown. (Combined with...) Figure 2 and Figure 4 As shown, at least one hole H includes a second hole H2, which penetrates the first extended conductive layer 210 and the second extended conductive layer 220. The first extended conductive layer 210 includes a third hole plating pad Hh3, and the second extended conductive layer 220 includes a fourth hole plating pad Hh4. The third hole plating pad Hh3 and the fourth hole plating pad Hh4 respectively surround the second hole H2. The orthographic projection of the third hole plating pad Hh3 on the substrate layer 1 and the orthographic projection of the fourth hole plating pad Hh4 on the substrate layer 1 are equal. For example, the diameters of the third hole plating pad Hh3 and the fourth hole plating pad Hh4 are 0.35 micrometers. For example, the second hole H2 is located in the first main body region ZA1 and the micro-motion region DA.

[0071] In this embodiment, the plurality of connecting portions 4 include a second connecting portion 42, which fills the second hole H2 and connects the first extended conductive layer 210 and the second extended conductive layer 220.

[0072] According to the circuit board provided in this embodiment, the third hole plating pad Hh3 and the fourth hole plating pad Hh4 are prepared before the lamination process, without the need for lamination alignment, and their expansion and contraction properties are consistent. Therefore, setting their diameters to be consistent can ensure the reliability of the electrical connection between the first extended conductive layer 210 and the second extended conductive layer 220.

[0073] Figure 5 for Figure 2 The third enlarged view of the circuit board shown. (Combined with...) Figure 2 and Figure 5 As shown, at least one hole H includes a third hole H3, which penetrates the first main conductive layer 310, the first extended conductive layer 210, the second extended conductive layer 220, and the second main conductive layer 320. The first main conductive layer 310 includes a second plated pad Hb2, the second main conductive layer 320 includes a third plated pad Hb3, the first extended conductive layer 210 includes a fifth hole plated pad Hh5, and the second extended conductive layer 220 includes a sixth hole plated pad Hh6. The second plated pad Hb2, the third plated pad Hb3, the fifth hole plated pad Hh5, and the sixth hole plated pad Hh6 respectively surround the third hole H3 and their orthographic projections on the substrate layer 1 coincide. For example, the diameters of the second plated pad Hb2, the third plated pad Hb3, the fifth hole plated pad Hh5, and the sixth hole plated pad Hh6 are all 0.3 micrometers. For example, the third hole H3 is located in the first main body region ZA1.

[0074] In this embodiment, the plurality of connecting portions 4 include a third connecting portion 43, which fills the third hole H3 and connects the first main conductive layer 310, the first extended conductive layer 210, the second extended conductive layer 220 and the second main conductive layer 320.

[0075] According to the circuit board provided in this embodiment, the third hole H3 penetrates the first main conductive layer 310, the first extended conductive layer 210, the second extended conductive layer 220, and the second main conductive layer 320. It can be seen that for a four-layer circuit board, the third hole H3 is a through hole, which can be obtained in one drilling operation after the lamination process. Therefore, the diameters of the second board plating pad Hb2, the third board plating pad Hb3, the fifth hole plating pad Hh5, and the sixth hole plating pad Hh6 are consistent, thus ensuring the reliability of the electrical connection between the first main conductive layer 310, the first extended conductive layer 210, the second extended conductive layer 220, and the second main conductive layer 320.

[0076] Figure 6 for Figure 2The fourth enlarged view of the circuit board shown. (Combined with...) Figure 2 and Figure 6 As shown, at least one hole H includes a fourth hole H4, which penetrates the first main conductive layer 310. The first main conductive layer 310 includes a fourth plated pad Hb4 surrounding the fourth hole H4. A plurality of connecting portions 4 include a fourth connecting portion 44, which fills the fourth hole H4 and connects the first main conductive layer 310 and the first extended conductive layer 210. Exemplarily, the fourth hole H4 is located in the first main body region ZA1.

[0077] In one embodiment, the first extended conductive layer 210 includes a seventh hole plating pad Hh7, the orthographic projection of the seventh hole plating pad Hh7 on the substrate layer 1 and the orthographic projection of the fourth plate plating pad Hb4 on the substrate layer 1 coincide. For example, the diameters of both the fourth plate plating pad Hb4 and the seventh hole plating pad Hh7 are 0.3 micrometers.

[0078] Figure 7 This is a schematic cross-sectional view of the circuit board provided in the second embodiment of this application. Figure 7 The circuit board shown and Figure 2 The difference in the circuit board shown is that the multiple main conductive layers 3 also include a third main conductive layer 330 and a fourth main conductive layer 340. The third main conductive layer 330 is located on the side of the first main conductive layer 310 away from the substrate layer 1, and the fourth main conductive layer 340 is located on the side of the second main conductive layer 320 away from the substrate layer 1. For example, the circuit board provided in this embodiment can be a six-layer circuit board. Figure 2 Holes H1, H2, H3, and H4 in the four-layer circuit board shown can also be used in a six-layer circuit board. For detailed technical information, please refer to [link / reference needed]. Figure 2 The embodiments shown are not described in detail here.

[0079] In a six-layer circuit board, the first hole H1 can be set as in a four-layer circuit board, or it can further penetrate the third main conductive layer 330 based on the first hole H1 shown in the four-layer circuit board. At the same time, the six-layer circuit board can also include a fifth hole H5, as described below.

[0080] Figure 8 for Figure 7 The first enlarged view of the circuit board shown. (Combined with...) Figure 7 and Figure 8 As shown, the first hole H1 is in Figure 3Based on the above, the third main conductive layer 330 is further extended, and the first connecting portion 41 is further connected to the third main conductive layer 330. The third main conductive layer 330 includes a fifth plated pad Hb5, and the first main conductive layer 310 includes a first plated pad Hb1. The fifth plated pad Hb5 and the first plated pad Hb1 respectively surround the first hole H1, and the orthographic projection of the fifth plated pad Hb5 on the substrate layer 1 and the orthographic projection of the first plated pad Hb1 on the substrate layer 1 coincide. For example, the diameter of both the fifth plated pad Hb5 and the first plated pad Hb1 is 0.3 micrometers.

[0081] Figure 9 for Figure 7 A second enlarged view of the circuit board shown. (Combined with...) Figure 7 and Figure 9 As shown, at least one hole H includes a fifth hole H5, which penetrates the first main conductive layer 310 and the third main conductive layer 330. The first main conductive layer 310 includes a sixth plated pad Hb6, and the third main conductive layer 330 includes a seventh plated pad Hb7. The orthographic projections of the sixth plated pad Hb6 and the seventh plated pad Hb7 on the substrate layer 1 coincide. For example, the diameters of both the sixth plated pad Hb6 and the seventh plated pad Hb7 are 0.3 micrometers. For example, the fifth hole H5 is located in the first main body region ZA1.

[0082] In this embodiment, the plurality of connecting portions 4 include a fifth connecting portion 45, which fills the fifth hole and connects the first main conductive layer 310 and the third main conductive layer 330.

[0083] In one embodiment, the fifth connection portion 45 is also connected to the first extended conductive layer 210. The first extended conductive layer 210 includes an eighth hole plating pad Hh8, the orthographic projection of the eighth hole plating pad Hh8 on the substrate layer 1 and the orthographic projection of the seventh plate plating pad Hb7 on the substrate layer 1 coincide. For example, the diameter of the eighth hole plating pad Hh8 is 0.3 micrometers.

[0084] Figure 10 This is a schematic cross-sectional view of the circuit board provided in the third embodiment of this application. Figure 10 The circuit board shown differs from the circuit board provided in any of the above embodiments in that, in this embodiment, the non-micro-motion region FA includes a transition region GA. In this case, the circuit board 200 also includes a second main body region ZA2, which is located on the side of the transition region GA away from the micro-motion region DA. The first main conductive layer 310 and the second main conductive layer 320 extend from the transition region GA to the second main body region ZA2.

[0085] The circuit board provided in this embodiment can be referred to as a pseudo two-layer circuit board, that is, most of the area of ​​the circuit board includes two conductive layers, but the transition area GA includes four conductive layers, which are used to transition the two extended conductive layers 2 of the micro-motion area DA to the two main conductive layers 3 of the second main body area ZA2.

[0086] In this embodiment, the circuit board 200 may include a fourth hole H4, which is located in the transition region GA. The specific structure of the fourth hole H4 is described in [reference needed]. Figure 6 The description of the illustrated embodiments will not be repeated here.

[0087] In one embodiment, such as Figure 10 As shown, the circuit board 200 may further include a sixth hole H6. The sixth hole H6 penetrates the first extended conductive layer 210. A plurality of connection portions 4 include a sixth connection portion 46, which fills the sixth hole H6 and connects to the second extended conductive layer 220. Exemplarily, the sixth hole H6 is located in the micro-motion region DA.

[0088] In one embodiment, the first extended conductive layer 210 includes a ninth hole plating pad Hh9, and the second extended conductive layer 220 includes a tenth hole plating pad Hh10. The orthographic projections of the ninth hole plating pad Hh9 and the tenth hole plating pad Hh10 on the substrate layer 1 coincide. The diameter of the ninth hole plating pad Hh9 is denoted as D9, and the diameter of the tenth hole plating pad Hh10 is denoted as D10, so D9 = D10. For example, the diameters of both the ninth hole plating pad Hh9 and the tenth hole plating pad Hh10 are 0.35 micrometers.

[0089] In one embodiment, such as Figure 10 As shown, the circuit board 200 may further include a seventh hole H7. The seventh hole H7 penetrates the first main conductive layer 310 and the second main conductive layer 320. The first main conductive layer 310 includes an eighth plated pad Hb8, and the second main conductive layer 320 includes a ninth plated pad Hb9. The eighth plated pad Hb8 and the ninth plated pad Hb9 respectively surround the seventh hole H7. The orthographic projection of the eighth plated pad Hb8 onto the second main conductive layer 320 coincides with the ninth plated pad Hb9. The diameter of the eighth plated pad Hb8 is denoted as d8, and the diameter of the ninth plated pad Hb9 is denoted as d9, so d8 = d9. For example, the diameters of the eighth plated pad Hb8 and the ninth plated pad Hb9 are 0.3 micrometers. For example, the seventh hole H7 is located in the second main body region ZA2.

[0090] In this embodiment, the plurality of connecting portions 4 further include a seventh connecting portion 47, which fills a seventh hole and connects the first main conductive layer 310 and the second main conductive layer 320.

[0091] The pseudo-two-layer circuit board provided in this embodiment satisfies micro-motion performance while being less expensive.

[0092] This application also provides a method for manufacturing a circuit board. Figure 11 This is a schematic flowchart illustrating a method for fabricating a circuit board according to an embodiment of this application. Figure 11 As shown, the circuit board fabrication method 1100 includes: Step S1110: A plurality of extended conductive layers, at least one first sub-hole, and at least one first sub-connection are prepared on the substrate layer to obtain a first sub-board. The plurality of extended conductive layers are located on opposite sides of the substrate layer. The extended conductive layers extend from the non-micro-motion region to the micro-motion region. The extended conductive layers include a first wiring and at least one hole plating pad. The hole plating pad surrounds the first sub-hole. The first sub-connection is located inside the first sub-hole. The first sub-connection, the hole plating pad, and the first wiring are electrically connected in sequence.

[0093] In step S1120, at least one main conductive layer, at least one second sub-hole, and at least one second sub-connection are prepared on the first sub-board to obtain the second sub-board. The main conductive layer is located on the side of the extended conductive layer away from the substrate layer and is located in the non-micro-motion region. The main conductive layer includes a second wiring and at least one board-plated pad. The board-plated pad surrounds the second sub-hole, and the second sub-connection is located inside the second sub-hole. The second sub-connection, the board-plated pad, and the second wiring are electrically connected in sequence. The second sub-hole and the first sub-hole are stacked or misaligned.

[0094] Figures 12a-12k To execute Figure 11 A schematic diagram of the intermediate product obtained during the fabrication process shown. The circuit board 200 includes a micro-motion region DA and a non-micro-motion region FA. See also... Figures 12a-12k The structural diagram of the intermediate product shown is for... Figure 11 The preparation method shown will be explained in detail.

[0095] According to step S1110, refer to Figure 12a A first conductive layer 11 and a second conductive layer 12 are respectively prepared on opposite sides of the substrate layer 1 to obtain a copper-clad substrate 10. The copper-clad substrate 10 is drilled to obtain at least one first sub-hole H11. The first conductive layer 11 and the second conductive layer 12 extend from the micro-motion region DA to the non-micro-motion region FA, and the first sub-hole H11 penetrates the copper-clad substrate 10.

[0096] The copper-clad laminate 10 in this application is a flexible copper-clad laminate (FCCL), a key substrate used in the manufacture of flexible printed circuit boards (FPCBs). It features thinness, flexibility, and fold resistance, and is widely used in modern electronic devices. The FCCL 10 includes a substrate layer 1 and a conductive layer. The substrate layer 1 is commonly made of materials such as polyimide (PI, high temperature resistance, high flexibility), polyester (PET, low cost), or liquid crystal polymer (LCP, excellent high-frequency performance). The conductive layer uses rolled copper (RA, better flexibility). In some embodiments, the FCCL 10 may also include an adhesive for bonding the substrate layer 1 and the conductive layer. Some models use acrylic or epoxy adhesives to bond the substrate layer 1 and the conductive layer, but adhesives are not essential; adhesive-free FCCL 10 offers superior performance.

[0097] For example, a laser drilling process is used to drill a hole in the copper-clad substrate 10 to obtain at least one first sub-hole H11. The first sub-hole H11 penetrates the first conductive layer 11, the substrate layer 1, and the second conductive layer 12. The first sub-hole H11 is located in the micro-motion region DA or the non-micro-motion region FA, where the non-micro-motion region FA can be the first main region ZA1.

[0098] See Figure 12b A hole plating process is used to metallize the first sub-hole H11 to obtain the first sub-connector portion 401 and the plating portion 222. This metallization step is used to prepare the first sub-connector portion 401 and the plating portion 222, which are integrally formed. The first sub-connector portion 401 fills the first sub-hole H11. The plating portion 222 is connected to the first sub-connector portion 401, or it is formed independently of the first sub-connector portion 401 and directly on the side of the conductive layer (including the first conductive layer 11 and the second conductive layer 12) away from the substrate layer 1.

[0099] Specifically, firstly, through a series of chemical treatments (such as descaling, activation, and acceleration), a very thin layer of chemical copper is deposited on the wall of the first sub-hole H11 and around the first sub-hole H11. This layer of chemical copper acts like a "seed," providing a conductive substrate for subsequent copper electroplating.

[0100] Next, the plate containing the chemical copper "seed" is placed in an electroplating bath and energized as the cathode. Under the influence of the electric field, copper ions are attracted to the cathode and reduced to metallic copper on the surface of the chemical copper.

[0101] See Figure 12c The first conductive layer 11 and the second conductive layer 12 after metallization are patterned to obtain an extended conductive layer.

[0102] This patterning process is used to form the first wiring 21 and the via plating pad 22. Taking the first conductive layer 11 as an example, the first wiring 21 is located on the first conductive layer 11. The via plating pad 22 includes a pad base 221 and a plating portion 222, with the plating portion 222 located on the side of the pad base 221 away from the substrate layer 1. The pad base 221 is located on the first conductive layer 11.

[0103] Step S1120, see Figure 12d A third conductive layer 13 is prepared on the side of the first conductive layer 11 facing away from the substrate layer 1 using a lamination process, and a fourth conductive layer 14 is prepared on the side of the second conductive layer 12 facing away from the substrate layer 1, to obtain a third sub-board 110. The third conductive layer 13 and the fourth conductive layer 14 are located in the non-micro-motion region DA, and the micro-motion performance of the third conductive layer 13 and the fourth conductive layer 14 is less than that of the first conductive layer 11 and the second conductive layer 12.

[0104] Specifically, a prepreg and a conductive layer (i.e., the third conductive layer 13 and the fourth conductive layer 14) are laminated on the top and bottom of the copper-clad substrate 10, respectively, and a first lamination is performed, with the prepreg forming the insulating layer 5. For example, the third conductive layer 13 and the fourth conductive layer 14 are made of electrolytic copper.

[0105] See Figure 12e Drill holes in the third sub-board 110 to obtain at least one second sub-hole H12. The second sub-hole H12 penetrates at least one of the third conductive layer 13 and the fourth conductive layer 14, or the first conductive layer 11, the second conductive layer 12, the third conductive layer 13 and the fourth conductive layer 14. The second sub-hole H12 and the first sub-hole H11 are stacked or misaligned.

[0106] For a four-layer circuit board, when the second sub-hole H12 and the first sub-hole H11 are stacked, the second sub-hole H12 and the first sub-hole H11 form a hole H; when the second sub-hole H12 and the first sub-hole H11 are misaligned, the first sub-hole H11 forms a hole H and the second sub-hole H12 forms a hole H.

[0107] See Figure 12f The second sub-hole H12 is metallized using a plate plating process to obtain the second sub-connection portion 402. This metallization process is used to form the plating layer 302 and the second sub-connection portion 402. The plating layer 302 is stacked on the side of the conductive layer (including the third conductive layer 13 and the fourth conductive layer 14) away from the substrate layer 1, and the second sub-connection portion 402 fills the second sub-hole H12.

[0108] For a four-layer circuit board, when the second sub-hole H12 and the first sub-hole H11 are stacked, the second sub-connecting part 402 and the first sub-connecting part 401 are connected to form a connecting part 4. When the second sub-hole H12 and the first sub-hole H11 are misaligned, the first sub-connecting part 401 and the second sub-connecting part 402 each form a connecting part 4.

[0109] Specifically, firstly, through a series of chemical treatments (such as descaling, activation, and acceleration), a very thin layer of chemical copper is deposited on the wall of the first sub-hole H11 and around the first sub-hole H11. This layer of chemical copper acts like a "seed," providing a conductive substrate for subsequent copper electroplating.

[0110] Next, the plate containing the chemical copper "seed" is placed in the electroplating tank and energized as the cathode. Copper ions are attracted to the cathode under the influence of the electric field and reduced to metallic copper on the surface of the chemical copper. Electroplating continues, and the current continues to deposit copper ions onto the surfaces of the third conductive layer 13 and the fourth conductive layer 14.

[0111] The goal of plate plating is to increase the copper thickness of the third conductive layer 13 and the fourth conductive layer 14 from the initial thickness to the final required thickness.

[0112] Step S1170, see Figure 12g The metallized third conductive layer 13 and fourth conductive layer 14 are patterned to obtain the first main conductive layer 310 and the second main conductive layer 320, respectively. This patterning process is used to form the second wiring 31 and the plated pad 32. Both the second wiring 31 and the plated pad 32 are composed of two conductive layers: one is the original conductive layer, also known as the conductive substrate layer 301 (including the third conductive layer 13 and the fourth conductive layer 14), and the other is the plating layer 302.

[0113] Thus, a four-layer circuit board is obtained. This four-layer circuit board includes a substrate layer 1, a first extended conductive layer 210 and a first main conductive layer 310 stacked on the first side C1 of the substrate layer 1, and a second extended conductive layer 220 and a second main conductive layer 320 stacked on the second side C2 of the substrate layer 1. Specifically, the first extended conductive layer 210 includes the portion of the first conductive layer 11 and the plating layer prepared during the via plating process located on the first side C1 of the substrate layer 1, but excludes the portion of the plating layer filling the first sub-via H11. The second extended conductive layer 220 includes the second conductive layer 12 and the portion of the plating layer prepared during the via plating process located on the second side C2 of the substrate layer 1, but excludes the portion of the plating layer filling the first sub-via H11. The first main conductive layer 310 includes the third conductive layer 13 and the portion of the plating layer prepared during the board plating process located on the first side C1 of the substrate layer, but excludes the portion filling the second sub-via H12. The second main conductive layer 320 includes the fourth conductive layer 14 and the portion of the plating layer prepared during the board plating process located on the second side C2 of the substrate layer, but excludes the portion filling the second sub-via H12.

[0114] For further details, please refer to [link / reference]. Figure 12g The preparation method 1100 may further include the step of attaching a protective film to both sides of the four-layer circuit board.

[0115] In one embodiment, when fabricating a pseudo-two-layer circuit board according to fabrication method 1100, refer to... Figure 10 As shown, in step S1140, the prepreg, the third conductive layer 13, and the fourth conductive layer 14 further extend into the second main body region ZA2. In step S1150, a portion of the second sub-hole H12 is located in the second main body region ZA2, and the second sub-hole H12 of the second main body region ZA2 penetrates the third conductive layer 13 and the fourth conductive layer 14.

[0116] In one embodiment, when fabricating a six-layer circuit board according to fabrication method 1100, fabrication method 1100 further includes the following steps.

[0117] See Figure 12h A fifth conductive layer 15 is prepared on the side of the first main conductive layer 310 away from the substrate layer 1 using a lamination process, and a sixth conductive layer 16 is prepared on the side of the second main conductive layer 320 away from the substrate layer 1 to obtain the second sub-board. The fifth conductive layer 15 and the sixth conductive layer 16 are located in the non-micro-motion region FA. The materials of the fifth conductive layer 15 and the sixth conductive layer 16 can be electrolytic copper.

[0118] See Figure 12i Drill holes in the second sub-board to obtain at least one third sub-hole H13. The third sub-hole H13 penetrates the fifth conductive layer 15 or the sixth conductive layer 16. The third sub-hole H13 and the second sub-hole H12 are stacked.

[0119] See Figure 12j The third sub-hole H13 is metallized using a plate plating process.

[0120] See Figure 12k The fifth conductive layer 15 and the sixth conductive layer 16, after metallization, are patterned to obtain the third main conductive layer 330 and the fourth main conductive layer 340, respectively. Subsequently, protective layers are attached to the surfaces of the third main conductive layer 330 and the fourth main conductive layer 340 to obtain a six-layer circuit board.

[0121] During the fabrication of this six-layer circuit board, Figures 12h-12k For detailed technical information regarding the preparation process shown, please refer to the documentation. Figures 12d-12g The preparation process will not be described in detail here.

[0122] This application also provides a display module. Figure 13 The diagram shown is a top view of a display module provided in an embodiment of this application. Figure 13 As shown, the display module includes: a display panel 100; and a circuit board 200 provided in any embodiment of this application, or a circuit board 200 prepared by the preparation method 1100 provided in any embodiment of this application, wherein the circuit board 200 and the display panel 100 are bonded together.

[0123] A display device is a product with image display capabilities. For example, a display device can be used to display static images, such as pictures or photographs. A display device can also be used to display dynamic images, such as videos.

[0124] Display devices can be laptops, mobile phones, handheld or portable computers, cameras, camcorders, in-vehicle smart central control screens, calculators, smartwatches, GPS navigators, electronic photographs, electronic billboards or signs, projectors, etc.

[0125] In addition, the display device can also perform functions such as taking photos, recording videos, fingerprint recognition, and facial recognition. Accordingly, the display device also includes at least one functional module for implementing the above functions, such as an under-display camera or an under-display fingerprint recognition sensor.

[0126] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0127] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A circuit board, characterized in that, The circuit board includes a non-micro-motion area and a micro-motion area; the circuit board comprises: Substrate layer; Multiple extended conductive layers are stacked on opposite sides of the substrate layer, the extended conductive layers extending from the non-micro-motion region to the micro-motion region; the extended conductive layers include a first wiring and at least one via plating pad, the via plating pad and the first wiring are electrically connected. Multiple main conductive layers are respectively located on both sides of the extended conductive layer away from the substrate layer, and the main conductive layers are located in the non-micro-motion region; the main conductive layer includes a second wiring and at least one board-plated pad, and the board-plated pad and the second wiring are electrically connected. At least one hole, the hole penetrating at least one of the extended conductive layer and the main conductive layer, and the hole plating pad and the board plating pad are disposed around the hole; At least one connecting portion is located within the hole and connected to the hole plating pad and the plate plating pad.

2. The circuit board according to claim 1, characterized in that, The hole plating pad includes a stacked pad base and a plating layer, the plating layer being located on the side of the pad base away from the substrate layer, and the pad base and the first wiring are disposed on the same layer; Preferably, the thickness of the hole-plated pad is greater than the thickness of the first wiring; Preferably, the material of the pad base and the first wiring includes rolled copper, and the material of the plating portion includes electrolytic copper.

3. The circuit board according to claim 1, characterized in that, The main conductive layer includes a stacked conductive substrate layer and a plating layer, wherein the plating layer is located on the side of the conductive substrate layer away from the substrate layer; a portion of the second wiring is located on the conductive substrate layer, and another portion is located on the plating layer; a portion of the board-plated pads is located on the conductive substrate layer, and another portion is located on the plating layer. Preferably, the thickness of the plated pad is equal to the thickness of the second wiring; Preferably, the conductive substrate layer and the plating layer are made of the same material; Preferably, the material of the conductive substrate layer includes electrolytic copper.

4. The circuit board according to claim 1, characterized in that, The diameter of the plated pad is less than or equal to the diameter of the hole-plated pad; Preferably, the diameter of the plated pads is greater than or equal to 0.25 micrometers and less than or equal to 0.35 micrometers; Preferably, the diameter of the plated pads includes 0.3 micrometers; Preferably, the diameter of the hole-plating pad is greater than or equal to 0.3 micrometers and less than or equal to 0.5 micrometers; Preferably, the diameter of the hole plating pad includes any one of 0.3 micrometers, 0.35 micrometers, and 0.45 micrometers; Preferably, the circuit board includes gold fingers located in the main conductive layer.

5. The circuit board according to claim 1, characterized in that, The plurality of extended conductive layers include a first extended conductive layer and a second extended conductive layer located on both sides of the substrate layer, respectively; the plurality of main conductive layers include a first main conductive layer and a second main conductive layer, wherein the first main conductive layer is located on the side of the first extended conductive layer away from the substrate layer, and the second main conductive layer is located on the side of the second extended conductive layer away from the substrate layer.

6. The circuit board according to claim 5, characterized in that, The at least one hole includes a first hole that penetrates the first extended conductive layer and the first main conductive layer; the first extended conductive layer includes a first hole plating pad, the first main conductive layer includes a first plate plating pad, the first hole plating pad and the first plate plating pad are respectively arranged around the first hole; the orthogonal projection of the first plate plating pad on the substrate layer is located within the orthogonal projection range of the first hole plating pad on the substrate layer. Preferably, the difference between the diameter of the first hole plating pad and the diameter of the first plate plating pad is greater than or equal to 0.1 micrometers and less than or equal to 0.2 micrometers; Preferably, the diameter of the first plated pad includes 0.3 micrometers; Preferably, the diameter of the first hole plating pad includes 0.45 micrometers.

7. The circuit board according to claim 6, characterized in that, The first hole also penetrates the second extended conductive layer, the second extended conductive layer includes a second hole plating pad, the second hole plating pad is disposed around the first hole, and the orthographic projection of the second hole plating pad on the substrate layer is located within the orthographic projection range of the first hole plating pad on the substrate layer; Preferably, the difference in diameter between the first hole plating pad and the second hole plating pad is greater than or equal to 0.05 and less than or equal to 0.

15. Preferably, the orthographic projection of the second hole plating pad on the substrate layer covers the orthographic projection of the first plate plating pad on the substrate layer; Preferably, the diameter of the second hole plating pad includes 0.35 micrometers; Preferably, the non-micro-motion area includes a first main body area, and the first hole is located in the first main body area.

8. The circuit board according to claim 5, characterized in that, The at least one hole includes a second hole that penetrates the first extended conductive layer and the second extended conductive layer; the first extended conductive layer includes a third hole plating pad, and the second extended conductive layer includes a fourth hole plating pad, the third hole plating pad and the fourth hole plating pad respectively surround the second hole; the orthographic projection of the third hole plating pad on the substrate layer and the orthographic projection of the fourth hole plating pad on the substrate layer are equal; Preferably, the non-micro-motion area includes a first main body area, and the second hole is located in the micro-motion area or the first main body area.

9. The circuit board according to claim 5, characterized in that, The at least one hole includes a third hole, which penetrates the first main conductive layer, the first extended conductive layer, the second extended conductive layer, and the second main conductive layer; the first main conductive layer includes a second plated pad, the second main conductive layer includes a third plated pad, the first extended conductive layer includes a fifth hole plated pad, and the second extended conductive layer includes a sixth hole plated pad; the second plated pad, the third plated pad, the fifth hole plated pad, and the sixth hole plated pad respectively surround the third hole and their orthographic projections on the substrate layer coincide. Preferably, the non-micro-motion zone includes a first main body zone, and the third hole is located in the first main body zone.

10. The circuit board according to claim 5, characterized in that, The at least one hole includes a fourth hole, the fourth hole penetrates the first main conductive layer, the first main conductive layer includes a fourth plated pad, the fourth plated pad surrounds the fourth hole, and the connecting portion in the fourth hole connects the first main conductive layer and the first extended conductive layer. Preferably, the first extended conductive layer includes a seventh hole plating pad, the orthographic projection of the seventh hole plating pad on the substrate layer and the orthographic projection of the fourth plate plating pad on the substrate layer coincide; Preferably, the non-micro-motion area includes a first main body area or a transition area, and the fourth hole is located in the first main body area or the transition area.

11. The circuit board according to any one of claims 5-10, characterized in that, The plurality of main conductive layers further include a third main conductive layer and a fourth main conductive layer, wherein the third main conductive layer is located on the side of the first main conductive layer away from the substrate layer, and the fourth main conductive layer is located on the side of the second main conductive layer away from the substrate layer.

12. The circuit board according to claim 11, characterized in that, The at least one hole includes a first hole that penetrates the third main conductive layer and the first main conductive layer; the third main conductive layer includes a fifth plated pad, the first main conductive layer includes a first plated pad, the fifth plated pad and the first plated pad respectively surround the first hole, and the orthographic projection of the fifth plated pad on the substrate layer and the orthographic projection of the first plated pad on the substrate layer coincide.

13. The circuit board according to claim 11, characterized in that, The at least one hole includes a fifth hole, which penetrates the first main conductive layer and the third main conductive layer. The first main conductive layer includes a sixth plated pad, and the third main conductive layer includes a seventh plated pad. The orthographic projection of the sixth plated pad on the substrate layer and the orthographic projection of the seventh plated pad on the substrate layer coincide. Preferably, the connecting portion in the fifth hole is connected to the first extended conductive layer; the first extended conductive layer includes an eighth hole plating pad, the orthographic projection of the eighth hole plating pad on the substrate layer and the orthographic projection of the seventh plate plating pad on the substrate layer coincide; Preferably, the non-micro-motion zone includes a first main body zone, and the fifth hole is located in the first main body zone.

14. The circuit board according to claim 10, characterized in that, The non-micro-motion area includes a transition area, and the fourth hole is located in the transition area; the circuit board also includes a second main body area, which is located on the side of the transition area away from the micro-motion area; the first main body conductive layer and the second main body conductive layer extend from the transition area to the second main body area.

15. The circuit board according to claim 14, characterized in that, The at least one hole further includes a sixth hole, the sixth hole penetrating the first extended conductive layer, and the connecting portion in the sixth hole connecting to the second extended conductive layer; Preferably, the first extended conductive layer includes a ninth hole plating pad, and the second extended conductive layer includes a tenth hole plating pad, wherein the orthographic projection of the ninth hole plating pad on the substrate layer and the orthographic projection of the tenth hole plating pad on the substrate layer coincide. Preferably, the sixth hole is located in the micro-motion zone.

16. The circuit board according to claim 14, characterized in that, The at least one hole also includes a seventh hole, which penetrates the first main conductive layer and the second main conductive layer. The first main conductive layer includes an eighth plated pad, and the second main conductive layer includes a ninth plated pad. The eighth plated pad and the ninth plated pad respectively surround the seventh hole. The orthographic projection of the eighth plated pad on the second main conductive layer coincides with the ninth plated pad. Preferably, the seventh hole is located in the second main body area.

17. The circuit board according to claim 1, characterized in that, The ductility of the extended conductive layer is greater than that of the main conductive layer; Preferably, the circuit board further includes a plurality of insulating layers, the insulating layers being located between adjacent main conductive layers, between adjacent extended conductive layers, or between adjacent main conductive layers and extended conductive layers; Preferably, the circuit board further includes a first protective layer and a second protective layer. The first protective layer is located on one side of the substrate layer, on the side where the main conductive layer furthest from the substrate layer is away from the substrate layer. The second protective layer is located on the other side of the substrate layer, on the side where the main conductive layer furthest from the substrate layer is away from the substrate layer.

18. A method for manufacturing a circuit board, characterized in that, The circuit board includes a micro-motion region and a non-micro-motion region; the fabrication method includes: A first sub-board is obtained by fabricating multiple extended conductive layers, at least one first sub-hole, and at least one first sub-connection on a substrate layer. The multiple extended conductive layers are respectively located on opposite sides of the substrate layer. The extended conductive layers extend from the non-micro-motion region to the micro-motion region. The extended conductive layers include a first wiring and at least one hole plating pad. The hole plating pad is arranged around the first sub-hole. The first sub-connection is located in the first sub-hole. The first sub-connection, the hole plating pad, and the first wiring are electrically connected. A second sub-board is obtained by fabricating at least one main conductive layer, at least one second sub-hole, and at least one second sub-connection on the first sub-board. The main conductive layer is located on the side of the extended conductive layer away from the substrate layer and is located in the non-micro-motion region. The main conductive layer includes a second wiring and at least one board-plated pad. The board-plated pad is disposed around the second sub-hole. The second sub-connection is located in the second sub-hole. The second sub-connection, the board-plated pad, and the second wiring are electrically connected. The second sub-hole and the first sub-hole are stacked or misaligned.

19. The method for manufacturing a circuit board according to claim 18, characterized in that, The step of fabricating multiple extended conductive layers, at least one first sub-hole, and at least one first sub-connection on a substrate layer to obtain a first sub-board includes: A first conductive layer and a second conductive layer are respectively prepared on opposite sides of the substrate layer to obtain a copper-clad substrate. The copper-clad substrate is drilled to obtain at least one first sub-hole, and the first sub-hole penetrates the copper-clad substrate; The first sub-hole is metallized using a hole plating process to obtain the first sub-connection portion; The metallized first conductive layer and the second conductive layer are patterned to obtain the extended conductive layer. Preferably, at least one main conductive layer, at least one second sub-via, and at least one second sub-connection portion are fabricated on the first sub-board to obtain the second sub-board, comprising: A third conductive layer is prepared on the side of the first conductive layer away from the substrate layer using a lamination process, and a fourth conductive layer is prepared on the side of the second conductive layer away from the substrate layer to obtain a third sub-board. The ductility of the third conductive layer and the fourth conductive layer is less than that of the first conductive layer and the second conductive layer. Drill holes in the third sub-board to obtain at least one second sub-hole. The second sub-hole penetrates at least one of the third conductive layer and the fourth conductive layer, or the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are connected. The second sub-hole and the first sub-hole are stacked or misaligned. The second sub-hole is metallized using a plate plating process to obtain the second sub-connection portion; The metallized third and fourth conductive layers are patterned to obtain the first main conductive layer and the second main conductive layer, respectively. Preferably, in the step of using a lamination process to prepare a third conductive layer on the side of the first conductive layer away from the substrate layer and a fourth conductive layer on the side of the second conductive layer away from the substrate layer to obtain a third sub-board, the third conductive layer and the fourth conductive layer further extend into the second main body region. In the step of drilling holes in the third sub-board to obtain at least one second sub-hole, a portion of the second sub-hole is located in the second main body region, and the second sub-hole in the second main body region penetrates the third conductive layer and the fourth conductive layer.

20. A display module, characterized in that, include: Display panel; and The circuit board according to any one of claims 1-17, or the circuit board prepared by the preparation method according to any one of claims 18 and 19, wherein the circuit board and the display panel are bonded together.

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