SiC LDMOS device, manufacturing method and chip

Abstract

The embodiment of the invention provides a SiC LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, a manufacturing method and a chip, and the device comprises a source P-type heavily doped region which is located in a P-type body region; the N-type injection layer is located in the N-type epitaxial layer; the source N-type heavily doped region is positioned in the P-type body region; the drain N-type heavily doped region is positioned in the N-type epitaxial layer; the gate oxide layer is located on the partial surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type injection layer and the partial surface of the N-type epitaxial layer; the polycrystalline silicon gate is positioned on a part of the surface of the gate oxide layer; and the P-type polycrystalline silicon region is positioned on a part of the surface of the gate oxide layer. The drift region of the device is composed of the N-type injection layer and the N-type epitaxial layer, the P-type polycrystalline silicon region, the gate oxide layer and the N-type injection layer form an MIS structure, an electron accumulation layer can be formed below the gate oxide layer during forward conduction, and a low-resistance conduction path is formed, so that the conduction resistance of the device is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a SiC LDMOS device, a manufacturing method and a chip. BACKGROUND

[0002] Silicon carbide (SiC) has outstanding advantages in high-voltage power devices due to its three times wider band gap than silicon (Si) material and higher thermal conductivity. A lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) has the advantages of high gain, wide linear range and small distortion, and has the advantage of easy integration because the source, gate and drain of the device are located on the surface of the device. The LDMOS device prepared by using SiC material is commonly used in high-voltage integrated circuits and intelligent power integrated circuits. However, there is still a problem of high on-resistance in the conventional SiC LDMOS device. SUMMARY

[0003] In view of the above problems, the present application is proposed to provide a SiC LDMOS device, a manufacturing method and a chip which overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, the present application discloses a SiC LDMOS device, which comprises: a P-type substrate; an N-type epitaxial layer located on the surface of the P-type substrate; a P-type body region located in the N-type epitaxial layer; a source P-type heavily doped region located in the P-type body region; an N-type implant layer located in the N-type epitaxial layer; the side surface of the N-type implant layer is connected with the side surface of the P-type body region; a source N-type heavily doped region located in the P-type body region; the side surface of the source N-type heavily doped region is connected with the side surface of the source P-type heavily doped region; a drain N-type heavily doped region located in the N-type epitaxial layer; a gate oxide layer located on part of the surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type implant layer and part of the surface of the N-type epitaxial layer; a polysilicon gate located on part of the surface of the gate oxide layer; a P-type polysilicon region located on part of the surface of the gate oxide layer; the side surface of the P-type polysilicon region is connected with the side surface of the polysilicon gate.

[0005] Optionally, the device further comprises: a metal source located on the surface of the source P-type heavily doped region and part of the surface of the source N-type heavily doped region; a metal drain on a part of a surface of the drain N-type heavily doped region.

[0006] Optionally, the P-type polysilicon region has a thickness same as that of the polysilicon gate, a width greater than that of the polysilicon gate, and a doping concentration less than that of the polysilicon gate.

[0007] Optionally, the P-type body region has a doping concentration greater than that of the N-type implant layer, and the N-type implant layer has a doping concentration greater than that of the N-type epitaxial layer.

[0008] Optionally, the P-type polysilicon region has a doping concentration same as that of the N-type implant layer, and a thickness same as that of the N-type implant layer.

[0009] Correspondingly, the application discloses a manufacturing method of the SiC LDMOS device, which is used for manufacturing the SiC LDMOS device, and the method comprises the following steps: providing a P-type substrate; forming an N-type epitaxial layer by epitaxial growth on a surface of the P-type substrate; forming a P-type body region by implanting P-type ions into the N-type epitaxial layer; forming a source P-type heavily doped region by implanting P-type ions into the P-type body region; forming an N-type implant layer by implanting N-type ions into the N-type epitaxial layer, and a side surface of the N-type implant layer is connected with a side surface of the P-type body region; forming a source N-type heavily doped region by implanting N-type ions into the P-type body region, and a side surface of the source N-type heavily doped region is connected with a side surface of the source P-type heavily doped region; forming a drain N-type heavily doped region by implanting N-type ions into the N-type epitaxial layer; forming a gate oxide layer by performing thermal oxidation on a part of a surface of the source N-type heavily doped region, a surface of the P-type body region, a surface of the N-type implant layer and a part of a surface of the N-type epitaxial layer; forming a polysilicon gate by depositing P-type polysilicon on a part of a surface of the gate oxide layer; forming a P-type polysilicon region by depositing P-type polysilicon on a part of a surface of the gate oxide layer, and a side surface of the P-type polysilicon region is connected with a side surface of the polysilicon gate.

[0010] Optionally, the method further comprises: forming a metal source by metallizing a surface of the source P-type heavily doped region and a part of a surface of the source N-type heavily doped region; Part of the surface of the N-type heavily doped drain region is metallized to form a metal drain.

[0011] Optionally, the surface of the N-type heavily doped source region, the surface of the P-type body region, the surface of the N-type implanted layer and part of the surface of the N-type epitaxial layer are thermally oxidized to form a gate oxide layer, including: The surface of the P-type heavily doped source region, the surface of the N-type heavily doped source region, the surface of the P-type body region, the surface of the N-type implanted layer and the surface of the N-type epitaxial layer are thermally oxidized to form an oxide layer, and the oxide layer of the surface of the N-type heavily doped source region, part of the surface of the N-type heavily doped source region and part of the surface of the N-type epitaxial layer are removed to form a gate oxide layer.

[0012] Optionally, the thickness of the P-type polysilicon region is the same as the thickness of the polysilicon gate, the width of the P-type polysilicon region is greater than the width of the polysilicon gate, and the doping concentration of the P-type polysilicon region is less than the doping concentration of the polysilicon gate.

[0013] Optionally, the doping concentration of the P-type body region is greater than the doping concentration of the N-type implanted layer, and the doping concentration of the N-type implanted layer is greater than the doping concentration of the N-type epitaxial layer.

[0014] Optionally, the doping concentration of the P-type polysilicon region is the same as the doping concentration of the N-type implanted layer, and the thickness of the P-type polysilicon region is the same as the thickness of the N-type implanted layer.

[0015] Correspondingly, the embodiment of the present application discloses a chip comprising the SiC LDMOS device as described in any of the above.

[0016] The embodiment of the present application has the following advantages: The SiC LDMOS device of the embodiment of the application comprises a P-type substrate; an N-type epitaxial layer located on the surface of the P-type substrate; a P-type body region located in the N-type epitaxial layer; a source P-type heavily doped region located in the P-type body region; an N-type implanted layer located in the N-type epitaxial layer; the side surface of the N-type implanted layer is connected with the side surface of the P-type body region; a source N-type heavily doped region located in the P-type body region; the side surface of the source N-type heavily doped region is connected with the side surface of the source P-type heavily doped region; a drain N-type heavily doped region located in the N-type epitaxial layer; a gate oxide layer located on part of the surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type implanted layer and part of the surface of the N-type epitaxial layer; a polysilicon gate located on part of the surface of the gate oxide layer; a P-type polysilicon region located on part of the surface of the gate oxide layer; the side surface of the P-type polysilicon region is connected with the side surface of the polysilicon gate. The drift region of the device of the embodiment of the application is composed of the N-type implanted layer and the N-type epitaxial layer, the MIS (Metal-Insulator-Semiconductor) structure is composed of the P-type polysilicon region, the gate oxide layer and the N-type implanted layer, the electron accumulation layer can be formed below the gate oxide layer when the device is turned on in the forward direction, thereby forming a low-resistance conduction path, and thus the on-resistance of the device is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 FIG. 1 is a structure schematic diagram of a SiC LDMOS device of an embodiment of the application; Figure 2 FIG. 2 is a structure schematic diagram of a SiC LDMOS device manufacturing of an embodiment of the application; Figure 3 FIG. 3 is a structure schematic diagram of another SiC LDMOS device manufacturing of an embodiment of the application; Figure 4 FIG. 4 is a structure schematic diagram of another SiC LDMOS device manufacturing of an embodiment of the application; Figure 5 FIG. 5 is a structure schematic diagram of another SiC LDMOS device manufacturing of an embodiment of the application; Figure 6 FIG. 6 is a structure schematic diagram of the inversion layer channel of a SiC LDMOS device of an embodiment of the application; Figure 7 FIG. 7 is a structure schematic diagram of another SiC LDMOS device of an embodiment of the application; Figure 8 FIG. 8 is a step flow chart of a SiC LDMOS device manufacturing of an embodiment of the application.

[0018] Reference signs: P-type substrate 10, N-type epitaxial layer 11, P-type body region 12, source P-type heavily doped region 13, N-type implanted layer 14, source N-type heavily doped region 15, drain N-type heavily doped region 16, gate oxide layer 17, polysilicon gate 18, P-type polysilicon region 19, inversion layer channel 20, metal source 21, metal drain 22. DETAILED DESCRIPTION

[0019] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0020] Silicon carbide has outstanding advantages in high-voltage power devices due to its three times wider band gap than silicon material and higher thermal conductivity. A lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) has the advantages of high gain, wide linear range and small distortion, and has the advantage of easy integration because the source, gate and drain of the device are located on the surface of the device. The LDMOS device prepared using SiC material is often used in high-voltage integrated circuits and intelligent power integrated circuits. However, in the conventional SiC LDMOS device, there is still a problem of high on-resistance. First, the high gate oxide interface state density of the SiC LDMOS device causes low channel mobility, resulting in an increase in device channel resistance and thus an overall increase in device on-resistance. Second, there is a contradictory relationship between the on-resistance and the withstand voltage of the device. Increasing the withstand voltage of the device often requires a long drift region length and a low drift region doping concentration, which will result in an increase in the on-resistance of the device.

[0021] One of the core ideas of the embodiments of the present application is to introduce a P-type polysilicon region and an N-type implanted layer in the drift region of the conventional SiC LDMOS. The P-type polysilicon region, the gate oxide layer and the N-type implanted layer in the drift region form a MIS structure, which can form an electron accumulation layer below the oxide layer when turned on in the forward direction, thereby forming a low-resistance conduction path, thereby effectively reducing the on-resistance of the device. At the same time, when the reverse withstand voltage, the P-type polysilicon region and the N-type implanted layer are mutually depleted, and the two modulate the electric field of the drift region to lift the surface electric field of the device, so that the withstand voltage of the device can be improved.

[0022] REFERENCE Figure 1 Fig. 1 shows a structure schematic diagram of a SiC LDMOS device according to an embodiment of the present application, which can specifically include the following structure: A P-type substrate 10.

[0023] The 4H-SiC crystal is grown by gas phase transmission, and then the crystal is shaped to form a standard crystal bar, the crystal bar is cut and ground to form a substrate, and then chemical mechanical polishing (CMP) is used to clean the substrate to the required standard to form a P-type substrate 10. Exemplarily, the thickness of the P-type substrate 10 is 100 μm ~ 400 μm, and the doping concentration is 5e15 cm -3 ~1e16cm -3 .

[0024] An N-type epitaxial layer 11 is formed on the surface of the P-type substrate 10.

[0025] Referring to Figure 2 The N-type epitaxial layer 11 is formed on the surface of the P-type substrate 10 by chemical vapor deposition (CVD) epitaxial growth. Exemplarily, the thickness of the N-type epitaxial layer 11 is 3 μm ~ 5 μm, and the doping concentration is 1e15 cm -3 ~2e16cm -3 .

[0026] A P-type body region 12 is formed in the N-type epitaxial layer 11.

[0027] Referring to Figure 3 The P-type body region 12 is formed by P-type ion implantation in a part of the N-type epitaxial layer 11, the upper surface of the P-type body region 12 is in the same plane as the upper surface of the N-type epitaxial layer 11, the P-type ion implantation element is Al, and exemplarily, the thickness of the P-type body region 12 is 0.7 μm ~ 3.0 μm, the width is 1.5 μm ~ 5 μm, and the doping concentration is 5e16 cm -3 ~6e17cm -3 .

[0028] A source P-type heavily doped region 13 is formed in the P-type body region 11.

[0029] The source P-type heavily doped region 13 is formed by P-type ion implantation in a part of the P-type body region 12, the upper surface of the source P-type heavily doped region 13 is in the same plane as the upper surface of the P-type body region 11, the P-type ion implantation element is Al, and exemplarily, the thickness of the source P-type heavily doped region 13 is 0.2 μm ~ 0.8 μm, the width is 0.2 μm ~ 2 μm, and the doping concentration is 1e19 cm -3 ~1e20cm -3 .

[0030] An N-type implantation layer 14 is formed in the N-type epitaxial layer 11, and the side surface of the N-type implantation layer 14 is connected to the side surface of the P-type body region 12.

[0031] Referring to Figure 4N-type ion implantation is performed in the N-type epitaxial layer 11 to form an N-type implantation layer 14, the upper surface of the N-type implantation layer 14 is in the same plane as the upper surface of the N-type epitaxial layer 11, the side surface of the N-type implantation layer 14 is connected to part of the side surface of the P-type body region 12, and the N-type ion implantation element is nitrogen N or phosphorus P. Exemplarily, the thickness of the N-type implantation layer 14 is 0.5 μm ~ 1.5 μm, the width is 2.0 μm ~ 5.0 μm, and the doping concentration is 7e15 cm -3 ~3e16cm -3 .

[0032] The source N-type heavily doped region 15 is located in the P-type body region 12, and the side surface of the source N-type heavily doped region 15 is connected to the side surface of the source P-type heavily doped region 13.

[0033] N-type ion implantation is performed in part of the P-type body region 12 close to the source P-type heavily doped region 13 to form the source N-type heavily doped region 15, the upper surface of the source N-type heavily doped region 15 is in the same plane as the upper surface of the P-type body region 12, the side surface of the source N-type heavily doped region 15 is connected to the side surface of the source P-type heavily doped region 13, and the N-type ion implantation element is nitrogen N or phosphorus P. Exemplarily, the thickness of the source N-type heavily doped region 15 is 0.2 μm ~ 0.8 μm, the width is 0.2 μm ~ 2 μm, and the doping concentration is 1e19 cm -3 ~1e20cm -3 .

[0034] The drain N-type heavily doped region 16 is located in the N-type epitaxial layer 11.

[0035] N-type ion implantation is performed in another part of the N-type epitaxial layer 11 to form the drain N-type heavily doped region 16, the upper surface of the drain N-type heavily doped region 16 is in the same plane as the upper surface of the N-type epitaxial layer 11, and the drain N-type heavily doped region 16 is located on both sides of the N-type epitaxial layer 11 with the source P-type heavily doped region 13 and the source N-type heavily doped region 15 respectively, and the N-type ion implantation element is nitrogen N or phosphorus P. Exemplarily, the thickness of the drain N-type heavily doped region 16 is 0.2 μm ~ 0.8 μm, the width is 0.2 μm ~ 2 μm, and the doping concentration is 1e19 cm -3 ~1e20cm -3 .

[0036] After the ion implantation in all regions is completed, high-temperature annealing (annealing temperature: 1600 ℃ ~ 1800 ℃, annealing time: 10 min ~ 40 min) is performed to repair the crystal lattice and activate the impurities to achieve a high electrical activation rate.

[0037] Gate oxide layer 17, located on part of the surface of source N-type heavily doped region 15, surface of P-type body region 12, surface of N-type implanted layer 14 and part of the surface of N-type epitaxial layer 11.

[0038] Referring to Figure 5 On part of the surface of source N-type heavily doped region 15, surface of P-type body region 12, surface of N-type implanted layer 14 and part of the surface of N-type epitaxial layer 11, thermal oxidation is performed to form gate oxide layer 17. Exemplarily, the width of gate oxide layer 8 is 1.5 μm ~ 5.5 μm, and the thickness is 30 nm ~ 70 nm.

[0039] In practical application, first, thermal oxidation is performed on the surface of the entire device, i.e. on the surface of source P-type heavily doped region, source N-type heavily doped region, P-type body region, N-type implanted layer and N-type epitaxial layer to form an oxide layer. Then, the oxide layer on the surface of source N-type heavily doped region, part of the surface of source N-type heavily doped region and part of the surface of N-type epitaxial layer is removed by etching to form gate oxide layer 17.

[0040] Poly-silicon gate 18, located on part of the surface of gate oxide layer 17.

[0041] On part of the surface of gate oxide layer 17, P-type poly-silicon is deposited on part of the surface of gate oxide layer 17 close to one side of source P-type heavily doped region 13 to form poly-silicon gate 18. Exemplarily, the doping concentration of poly-silicon gate 18 is 1e19 cm -3 ~ 1e20 cm -3 , the thickness is 0.5 μm ~ 1.5 μm, and the width is 0.5 μm ~ 1.5 μm.

[0042] The side surface of poly-silicon gate 18 is substantially in the same vertical line as the side surface of P-type body region 12, and the side surface of poly-silicon gate 18 can slightly exceed the side surface of P-type body region 3.

[0043] P-type poly-silicon region 19, located on part of the surface of gate oxide layer 17; the side surface of P-type poly-silicon region 19 is connected with the side surface of poly-silicon gate 18.

[0044] On part of the surface of gate oxide layer 17, i.e. on the surface of the remaining part of gate oxide layer 17 except the part on which poly-silicon gate 18 is formed, P-type poly-silicon is deposited to form P-type poly-silicon region 19, and the side surface of P-type poly-silicon region 19 is connected with the side surface of poly-silicon gate 18. Exemplarily, the doping concentration of P-type poly-silicon region 19 is 7e15 cm 3 ~ 3e16 cm 3 , the thickness is 0.5 μm ~ 1.5 μm, and the width is 2.0 μm ~ 5.5 μm.

[0045] The drift region of the SiC LDMOS device refers to the whole of the N-type implant layer 14 and the N-type epitaxial layer 11. The drift region is a lightly doped semiconductor region between the channel and the drain of the LDMOS. In a typical lateral structure, the current flows from the source, through the channel, then through the drift region, and finally reaches the drain. Therefore, the drift region is the only way for the current to flow from the channel to the drain. The drift region can withstand high voltage (voltage withstanding function). When the LDMOS is off (i.e. no voltage or negative voltage on the gate), a high voltage is applied between the drain and the source, which mainly falls on the drift region and the depletion region below the channel. Since the drift region is lightly doped, its depletion layer can be very wide, effectively sharing the high voltage and preventing avalanche breakdown of the device at low voltage. The length and doping concentration of the drift region are the main factors that determine the breakdown voltage of the device; affect the on-resistance (conductivity function). When the LDMOS is on, the current needs to flow from the channel through the drift region to the drain. The resistance of the drift region is an important part of the total on-resistance of the device. The longer the drift region or the lower the doping, the greater the resistance, resulting in increased on-state loss. This is a trade-off with the voltage withstanding requirement.

[0046] When the device is forward on, the gate voltage is applied to the polysilicon gate 18, and the potential will be transmitted to the P-type polysilicon region 19 through the polysilicon gate 18. The MIS structure formed by the P-type polysilicon region 19, the gate oxide layer 17 extending to the middle of the drift region, and the N-type implant layer 14 will induce an electron accumulation layer on the surface of the N-type implant layer 14. The on-channel extends from the surface of the P-type body region 12 to the drift region of the device, forming a low-resistance on-path between the inversion layer channel and the drain of the device, greatly reducing the resistance of the drift region of the device. Therefore, the generation of the electron accumulation layer will greatly reduce the on-resistance of the device.

[0047] Figure 6 The structure of the inversion layer channel is shown in the figure. The inversion layer channel refers to the electron inversion layer induced under the gate oxide layer 17 by the voltage of the polysilicon gate 18 acting on the upper surface of the P-type body region 12.

[0048] The SiC LDMOS device of the embodiment of the application comprises a P-type substrate; an N-type epitaxial layer located on the surface of the P-type substrate; a P-type body region located in the N-type epitaxial layer; a source P-type heavily doped region located in the P-type body region; an N-type implanted layer located in the N-type epitaxial layer; the side surface of the N-type implanted layer is connected with the side surface of the P-type body region; a source N-type heavily doped region located in the P-type body region; the side surface of the source N-type heavily doped region is connected with the side surface of the source P-type heavily doped region; a drain N-type heavily doped region located in the N-type epitaxial layer; a gate oxide layer located on part of the surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type implanted layer and part of the surface of the N-type epitaxial layer; a polysilicon gate located on part of the surface of the gate oxide layer; a P-type polysilicon region located on part of the surface of the gate oxide layer; the side surface of the P-type polysilicon region is connected with the side surface of the polysilicon gate. The drift region of the device of the embodiment of the application is composed of the N-type implanted layer and the N-type epitaxial layer, the MIS structure is composed of the P-type polysilicon region, the gate oxide layer and the N-type implanted layer, the electron accumulation layer can be formed below the gate oxide layer when the device is turned on in a forward direction, thereby forming a low-resistance conduction path, and thus the on-resistance of the device is effectively reduced.

[0049] Referring to Figure 7 , another structure schematic diagram of the SiC LDMOS device of the embodiment of the application is shown, and the device further comprises: a metal source 21 located on the surface of the source P-type heavily doped region 13 and part of the surface of the source N-type heavily doped region 15.

[0050] The surface of the source P-type heavily doped region 13 and part of the surface of the source N-type heavily doped region 15 are metallized to form the metal source 21. The metal material of the metal source 21 is nickel Ni / aluminum Al, the thickness of the Ni layer is generally 100 nm-300 nm, and the thickness of the Al layer is generally 3 μm-5 μm. The Ni layer in the metal source 21 will be in contact with the source P-type heavily doped region 13 and the source N-type heavily doped region 15 to form an ohmic contact, which can provide a low-resistance current path for the source; the P-type body region 12 is electrically connected to the source potential, which prevents the parasitic transistor from being turned on and ensures the normal operation of the device; reduces the overall contact resistance, improves the performance and reliability of the device; and forms a stable silicide by using Ni to realize high-quality ohmic contact.

[0051] a metal drain 22 located on part of the surface of the drain N-type heavily doped region 16.

[0052] The metal drain 22 is formed by metallizing part of the surface of the drain N-type heavily doped region 16, and needs to cover the drain N-type heavily doped region 16 entirely and cannot exceed the drain N-type heavily doped region 16, the metal material of the metal drain 22 is nickel Ni / aluminum Al, the thickness of the Ni layer is generally 100 nm-300 nm, the thickness of the Al layer is generally 3 μm-5 μm, the Ni layer in the metal drain 22 will contact the drain N-type heavily doped region 16 to form an ohmic contact, can establish a low-resistance current path, reduce the on-resistance of the device to improve the current carrying capacity and thermal stability; improve the overall efficiency, performance and reliability of the device; form a stable silicide contact by using the mature process of Ni.

[0053] In the embodiment of the present application, the thickness of the P-type polysilicon region 19 is the same as that of the polysilicon gate 18, the width of the P-type polysilicon region 19 is greater than that of the polysilicon gate 18, and the doping concentration of the P-type polysilicon region 19 is less than that of the polysilicon gate 18.

[0054] For example, the doping concentration of the P-type polysilicon region 19 is 7e15 cm-3e16 cm, the thickness is 0.5 μm-1.5 μm, and the width is 2.0 μm-5.5 μm. -3 -3 The doping concentration of the polysilicon gate 18 is 1e19 cm-1e20 cm, the thickness is 0.5 μm-1.5 μm, and the width is 0.5 μm-1.5 μm. -3 -3

[0055] When the device is forward conducting, the gate voltage is applied to the polysilicon gate 18, and the potential is transmitted to the P-type polysilicon region 19 through the polysilicon gate 18, and the MIS structure formed by the P-type polysilicon region 19, the gate oxide layer 17 extending to the middle position of the drift region, and the N-type injection layer 14 will induce an electron accumulation layer on the surface of the N-type injection layer 14, and the conducting channel extends from the surface of the P-type body region 12 to the drift region of the device, which forms a low-resistance conducting path connecting the inversion layer channel and the device drain, greatly reducing the resistance of the drift region of the device, so that the on-resistance of the device is greatly reduced.

[0056] In the embodiment of the present application, the doping concentration of the P-type body region 12 is greater than that of the N-type injection layer 14, and the doping concentration of the N-type injection layer 14 is greater than that of the N-type epitaxial layer 11.

[0057] For example, the doping concentration of the P-type body region 12 is 5e16 cm-6e17 cm, and the doping concentration of the N-type injection layer 14 is 7e15 cm-1e16 cm. -3 -3 The doping concentration of the N-type injection layer 14 is 7e15 cm-1e16 cm.​​​​-3 ~3e16cm -3 , the doping concentration of the N-type epitaxial layer 11 is 1e15 cm -3 ~2e16cm -3 .

[0058] The doping concentration of the N-type epitaxial layer 11, the P-type body region 12 and the N-type implanted layer 14 is in descending order of the P-type body region 12, the N-type implanted layer 14 and the N-type epitaxial layer 11. The device drift region is the whole formed by the N-type implanted layer 14 and the N-type epitaxial layer 11.

[0059] In the embodiment of the application, the doping concentration of the P-type polysilicon region 19 is the same as that of the N-type implanted layer 14, and the thickness of the P-type polysilicon region 19 is the same as that of the N-type implanted layer 14.

[0060] Exemplarily, the doping concentration of the P-type polysilicon region 19 is 7e15 cm -3 ~3e16cm -3 , the thickness is 0.5-1.5 μm, and the doping concentration of the N-type implanted layer 14 is 7e15 cm -3 ~3e16cm -3 , the thickness is 0.5-1.5 μm.

[0061] In the reverse withstand voltage, the P-type polysilicon region 19 and the N-type implanted layer 14 are mutually depleted, can modulate the electric field of the device drift region, and can introduce an electric field peak at the central position of the surface of the device drift region, lift the overall electric field of the device drift region, thereby improving the withstand voltage of the device.

[0062] The embodiment of the application introduces the P-type polysilicon region 19, the gate oxide layer 17 and the N-type implanted layer 14 to form the MIS structure in the drift region of the SiC LDMOS. In the forward conduction, an electron accumulation layer can be formed below the gate oxide layer 17, thereby forming a low-resistance conduction path, thereby effectively reducing the on-resistance of the device. At the same time, in the reverse withstand voltage, the P-type polysilicon region 19 and the N-type implanted layer 14 are mutually depleted, and the two modulate the electric field of the drift region and lift the surface electric field of the device, thereby improving the withstand voltage of the device. The embodiment of the application is not limited to the N-channel LDMOS, and can also be applied to the P-channel LDMOS.

[0063] Referring to Figure 8 , a step flow chart of manufacturing the SiC LDMOS device of the embodiment of the application is shown, which can specifically include the following steps: Step 101, providing a P-type substrate.

[0064] Step 102, epitaxially growing on the surface of the P-type substrate to form an N-type epitaxial layer.

[0065] Step 103, P-type ions are implanted into the N-type epitaxial layer to form a P-type body region.

[0066] Step 104, P-type ions are implanted into the P-type body region to form a source P-type heavily doped region.

[0067] Step 105, N-type ions are implanted into the N-type epitaxial layer to form an N-type implanted layer; the side surface of the N-type implanted layer is connected to the side surface of the P-type body region.

[0068] Step 106, N-type ions are implanted into the P-type body region to form a source N-type heavily doped region; the side surface of the source N-type heavily doped region is connected to the side surface of the source P-type heavily doped region.

[0069] Step 107, N-type ions are implanted into the N-type epitaxial layer to form a drain N-type heavily doped region.

[0070] Step 108, thermal oxidation is performed on part of the surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type implanted layer, and part of the surface of the N-type epitaxial layer to form a gate oxide layer.

[0071] Step 109, P-type polysilicon is deposited on part of the surface of the gate oxide layer to form a polysilicon gate.

[0072] Step 110, P-type polysilicon is deposited on part of the surface of the gate oxide layer to form a P-type polysilicon region; the side surface of the P-type polysilicon region is connected to the side surface of the polysilicon gate.

[0073] The 4H-SiC crystal is grown by gas phase transmission, and then the crystal is shaped and processed to form a standard crystal bar. The crystal bar is cut and ground to form a substrate, and then chemical mechanical polishing (CMP) is used to clean and reach the required standard to form a P-type substrate 10. For example, the thickness of the P-type substrate 10 is 100 μm ~400 μm, and the doping concentration is 5e15 cm -3 ~1e16cm -3 .

[0074] An N-type epitaxial layer 11 is formed by chemical vapor deposition (CVD) epitaxial growth on the surface of the P-type substrate 10. For example, the thickness of the N-type epitaxial layer 11 is 3 μm ~5 μm, and the doping concentration is 1e15 cm -3 ~2e16cm -3 .

[0075] A P-type ion implantation is performed in a partial region of one side of the N-type epitaxial layer 11 to form a P-type body region 12, the upper surface of the P-type body region 12 is in the same plane as the upper surface of the N-type epitaxial layer 11, the P-type ion implantation element is Al. Exemplarily, the thickness of the P-type body region 12 is 0.7 μm ~ 3.0 μm, the width is 1.5 μm ~ 5 μm, and the doping concentration is 5e16 cm -3 ~6e17cm -3 .

[0076] A P-type ion implantation is performed in a partial region of one side of the P-type body region 12 to form a source P-type heavily doped region 13, the upper surface of the source P-type heavily doped region 13 is in the same plane as the upper surface of the P-type body region 11, the P-type ion implantation element is Al. Exemplarily, the thickness of the source P-type heavily doped region 13 is 0.2 μm ~ 0.8 μm, the width is 0.2 μm ~ 2 μm, and the doping concentration is 1e19 cm -3 ~1e20cm -3 .

[0077] An N-type ion implantation is performed in the N-type epitaxial layer 11 to form an N-type implanted layer 14, the upper surface of the N-type implanted layer 14 is in the same plane as the upper surface of the N-type epitaxial layer 11, the side surface of the N-type implanted layer 14 is connected to a partial side surface of the P-type body region 12, the N-type ion implantation element is nitrogen N or phosphorus P. Exemplarily, the thickness of the N-type implanted layer 14 is 0.5 μm ~ 1.5 μm, the width is 2.0 μm ~ 5.0 μm, and the doping concentration is 7e15 cm -3 ~3e16cm -3 .

[0078] An N-type ion implantation is performed in a partial region of one side of the P-type body region 12 close to the source P-type heavily doped region 13 to form a source N-type heavily doped region 15, the upper surface of the source N-type heavily doped region 15 is in the same plane as the upper surface of the P-type body region 12, the side surface of the source N-type heavily doped region 15 is connected to the side surface of the source P-type heavily doped region 13, the N-type ion implantation element is nitrogen N or phosphorus P. Exemplarily, the thickness of the source N-type heavily doped region 15 is 0.2 μm ~ 0.8 μm, the width is 0.2 μm ~ 2 μm, and the doping concentration is 1e19 cm -3 ~1e20cm -3 .

[0079] In another side part region of the N-type epitaxial layer 11, N-type ion implantation is performed to form a drain N-type heavily doped region 16, the upper surface of the drain N-type heavily doped region 16 is in the same plane with the upper surface of the N-type epitaxial layer 11, the drain N-type heavily doped region 16 is located on the two sides of the N-type epitaxial layer 11 respectively with the source P-type heavily doped region 13 and the source N-type heavily doped region 15, the N-type ion implantation element is nitrogen N or phosphorus P. Exemplarily, the thickness of the drain N-type heavily doped region 16 is 0.2 μm ~ 0.8 μm, the width is 0.2 μm ~ 2 μm, and the doping concentration is 1e19 cm -3 ~1e20cm -3 .

[0080] After the ion implantation in all regions is completed, high-temperature annealing (annealing temperature is 1600 ℃ ~ 1800 ℃, annealing time is 10 min ~ 40 min) is performed to repair the lattice and activate the impurities to achieve a high electrical activation rate.

[0081] On part of the surface of the source N-type heavily doped region 15, the surface of the P-type body region 12, the surface of the N-type implanted layer 14 and part of the surface of the N-type epitaxial layer 11, thermal oxidation is performed to form a gate oxide layer 17. Exemplarily, the width of the gate oxide layer 8 is 1.5 μm ~ 5.5 μm, and the thickness is 30 nm ~ 70 nm.

[0082] On part of the surface of the gate oxide layer 17, P-type polysilicon is deposited on part of the surface of the gate oxide layer 17 near the side of the source P-type heavily doped region 13 to form a polysilicon gate 18. Exemplarily, the doping concentration of the polysilicon gate 18 is 1e19 cm -3 ~1e20cm -3 , the thickness is 0.5 μm ~ 1.5 μm, and the width is 0.5 μm ~ 1.5 μm.

[0083] On part of the surface of the gate oxide layer 17, i.e. the surface of the remaining part of the gate oxide layer 17 except the part on which the polysilicon gate 18 is formed, P-type polysilicon is deposited to form a P-type polysilicon region 19, the side surface of the P-type polysilicon region 19 is connected with the side surface of the polysilicon gate 18. Exemplarily, the doping concentration of the P-type polysilicon region 19 is 7e15 ~ 3e16 cm 3 , the thickness is 0.5 μm ~ 1.5 μm, and the width is 2.0 μm ~ 5.5 μm.

[0084] The SiC LDMOS device of the embodiment of the present application comprises a P-type substrate; an N-type epitaxial layer located on the surface of the P-type substrate; a P-type body region located in the N-type epitaxial layer; a source P-type heavily doped region located in the P-type body region; an N-type implanted layer located in the N-type epitaxial layer; the side surface of the N-type implanted layer is connected with the side surface of the P-type body region; a source N-type heavily doped region located in the P-type body region; the side surface of the source N-type heavily doped region is connected with the side surface of the source P-type heavily doped region; a drain N-type heavily doped region located in the N-type epitaxial layer; a gate oxide layer located on part of the surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type implanted layer and part of the surface of the N-type epitaxial layer; a polysilicon gate located on part of the surface of the gate oxide layer; a P-type polysilicon region located on part of the surface of the gate oxide layer; the side surface of the P-type polysilicon region is connected with the side surface of the polysilicon gate. The drift region of the device of the embodiment of the present application is composed of the N-type implanted layer and the N-type epitaxial layer, the MIS (Metal-Insulator-Semiconductor) structure is composed of the P-type polysilicon region, the gate oxide layer and the N-type implanted layer, the electron accumulation layer can be formed below the gate oxide layer when the device is turned on in the forward direction, thereby forming a low-resistance conduction path, so as to effectively reduce the on-resistance of the device.

[0085] When the device is turned on in the forward direction, the gate voltage is applied on the polysilicon gate 18, the potential is transmitted to the P-type polysilicon region 19 through the polysilicon gate 18, and the MIS structure composed of the P-type polysilicon region 19, the gate oxide layer 17 extending to the middle position of the drift region and the N-type implanted layer 14 can induce the electron accumulation layer on the surface of the N-type implanted layer 14, and the conduction channel extends from the surface of the P-type body region 12 to the drift region of the device, thereby forming a low-resistance conduction path connecting the inversion layer channel and the drain of the device, which can greatly reduce the resistance of the drift region of the device, so that the on-resistance of the device can be greatly reduced due to the generation of the electron accumulation layer.

[0086] When the device is turned on in the reverse direction, the P-type polysilicon region 19 and the N-type implanted layer 14 are mutually depleted, which can modulate the electric field of the drift region of the device, introduce an electric field peak at the central position of the surface of the drift region of the device, and lift the overall electric field of the drift region of the device, thereby improving the withstand voltage of the device.

[0087] Therefore, the high on-resistance problem of the SiC LDMOS device is solved, and the withstand voltage of the device can be ensured to be improved, so that the comprehensive performance of the device is improved.

[0088] In the embodiment of the present application, the method further comprises: The surface of the source P-type heavily doped region and part of the surface of the source N-type heavily doped region are metallized to form a metal source; Part of the surface of the drain N-type heavily doped region is metallized to form a metal drain.

[0089] The surface of the source P-type heavily doped region 13 and part of the surface of the source N-type heavily doped region 15 are metallized to form a metal source 21. The metal material of the metal source 21 is nickel Ni / aluminum Al, the thickness of the Ni layer is generally 100 nm-300 nm, and the thickness of the Al layer is generally 3 μm-5 μm. The Ni layer in the metal source 21 will be in contact with the source P-type heavily doped region 13 and the source N-type heavily doped region 15 to form an ohmic contact, which can provide a low-resistance current path for the source; electrically connect the P-type body region 12 to the source potential to prevent the parasitic transistor from being turned on and ensure the normal operation of the device; reduce the overall contact resistance and improve the performance and reliability of the device; form a stable silicide with Ni to achieve high-quality ohmic contact.

[0090] Part of the surface of the drain N-type heavily doped region 16 is metallized to form a metal drain 22, which needs to be entirely covered on the drain N-type heavily doped region 16 and cannot exceed the drain N-type heavily doped region 16. The metal material of the metal drain 22 is nickel Ni / aluminum Al, the thickness of the Ni layer is generally 100 nm-300 nm, and the thickness of the Al layer is generally 3 μm-5 μm. The Ni layer in the metal drain 22 will be in contact with the drain N-type heavily doped region 16 to form an ohmic contact, which can establish a low-resistance current path and reduce the on-resistance of the device; improve the current carrying capacity and thermal stability; improve the overall efficiency, performance and reliability of the device; form a stable silicide contact with the mature process of Ni.

[0091] In the embodiment of the present application, the surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type implanted layer and part of the surface of the N-type epitaxial layer are thermally oxidized to form a gate oxide layer, including: The surfaces of the source P-type heavily doped region, the source N-type heavily doped region, the P-type body region, the N-type implanted layer and the N-type epitaxial layer are thermally oxidized to form an oxide layer. The oxide layers on the surface of the source N-type heavily doped region, part of the surface of the source N-type heavily doped region and part of the surface of the N-type epitaxial layer are removed to form a gate oxide layer.

[0092] In actual application, the surfaces of the source P-type heavily doped region, the source N-type heavily doped region, the P-type body region, the N-type implanted layer and the N-type epitaxial layer are first thermally oxidized to form an oxide layer, and then the oxide layers on the surface of the source N-type heavily doped region, part of the surface of the source N-type heavily doped region and part of the surface of the N-type epitaxial layer are removed by etching to form a gate oxide layer 17.

[0093] In the embodiment of the present application, the thickness of the P-type polysilicon region is the same as that of the polysilicon gate, the width of the P-type polysilicon region is greater than that of the polysilicon gate, and the doping concentration of the P-type polysilicon region is less than that of the polysilicon gate.

[0094] In the embodiment of the present application, the doping concentration of the P-type body region is greater than the doping concentration of the N-type implanted layer, and the doping concentration of the N-type implanted layer is greater than the doping concentration of the N-type epitaxial layer.

[0095] In the embodiment of the present application, the doping concentration of the P-type polysilicon region is the same as the doping concentration of the N-type implanted layer, and the thickness of the P-type polysilicon region is the same as the thickness of the N-type implanted layer.

[0096] When the device is in forward conduction, the gate voltage is applied to the polysilicon gate 18, and the potential will be transmitted to the P-type polysilicon region 19 through the polysilicon gate 18. The MIS structure formed by the P-type polysilicon region 19, the gate oxide layer 17 extending to the middle position of the drift region, and the N-type implanted layer 14 will induce an electron accumulation layer on the surface of the N-type implanted layer 14. The conduction channel extends from the surface of the P-type body region 12 to the drift region of the device, which forms a low-resistance conduction path connecting the inversion layer channel and the drain of the device, greatly reducing the resistance of the drift region of the device. Therefore, the generation of the electron accumulation layer will greatly reduce the on-resistance of the device.

[0097] When the device is in reverse voltage, the P-type polysilicon region 19 and the N-type implanted layer 14 are mutually depleted, which can modulate the electric field of the drift region of the device, introduce an electric field peak at the central position of the surface of the drift region of the device, and raise the overall electric field of the drift region of the device, thereby improving the voltage resistance of the device.

[0098] It should be noted that, for the method embodiments, in order to simply describe, they are all described as a combination of a series of actions, but those skilled in the art should know that the embodiments of the present application are not limited to the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily necessary for the embodiments of the present application.

[0099] For the method embodiments, since they are basically similar to the structural embodiments, the description is relatively simple, and the relevant parts are referred to the part of the description of the structural embodiments.

[0100] The embodiments of the present application also provide a chip comprising the SiC LDMOS device according to any one of the above.

[0101] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0102] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer program code thereon for use by or in connection with an instruction execution system. For the purposes of this description, a computer-usable or computer readable storage medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

[0103] Embodiments of the present application are described herein with reference to the drawings, which are as follows: Figure 1 one or more functions specified by one or more blocks Figure 1 one or more functions specified by one or more blocks

[0104] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the Figure 1 one or more functions specified by one or more blocks Figure 1 one or more functions specified by one or more blocks

[0105] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the Figure 1 one or more functions specified by one or more blocks Figure 1 one or more functions specified by one or more blocks

[0106] While preferred embodiments of the present application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such modifications and variations as fall within the scope of the present application.

[0107] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other closure, are intended to cover the non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include those elements alone but can include other elements not expressly listed or even include elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0108] The SiC LDMOS device, manufacturing method and chip provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in the present article. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description should not be understood as a limitation on the present application.

Claims

1. A SiC LDMOS device, characterized in that, The device includes: P-type substrate; An N-type epitaxial layer is located on the surface of the P-type substrate; The P-type body region is located within the N-type epitaxial layer; The source P-type heavily doped region is located within the P-type bulk region; An N-type implantation layer is located within the N-type epitaxial layer; the side of the N-type implantation layer is connected to the side of the P-type body region. The source N-type heavily doped region is located within the P-type body region; the side of the source N-type heavily doped region is connected to the side of the source P-type heavily doped region; The drain N-type heavily doped region is located within the N-type epitaxial layer; A gate oxide layer is located on a portion of the surface of the source N-type heavily doped region, the surface of the P-type body region, the surface of the N-type implanted layer, and a portion of the surface of the N-type epitaxial layer. A polycrystalline silicon gate is located on a portion of the surface of the gate oxide layer; A P-type polysilicon region is located on a portion of the surface of the gate oxide layer; the side of the P-type polysilicon region is connected to the side of the polysilicon gate.

2. The SiC LDMOS device according to claim 1, characterized in that, The device also includes: A metal source electrode is located on the surface of the heavily doped P-type region of the source electrode and on a portion of the surface of the heavily doped N-type region of the source electrode. A metal drain electrode is located on a portion of the surface of the heavily doped N-type region of the drain electrode.

3. The SiC LDMOS device according to claim 1, characterized in that, The thickness of the P-type polysilicon region is the same as the thickness of the polysilicon gate, the width of the P-type polysilicon region is greater than the width of the polysilicon gate, and the doping concentration of the P-type polysilicon region is less than the doping concentration of the polysilicon gate.

4. The SiC LDMOS device according to claim 1, characterized in that, The doping concentration of the P-type body region is greater than the doping concentration of the N-type implanted layer, and the doping concentration of the N-type implanted layer is greater than the doping concentration of the N-type epitaxial layer.

5. The SiC LDMOS device according to claim 1, characterized in that, The doping concentration of the P-type polysilicon region is the same as that of the N-type implanted layer, and the thickness of the P-type polysilicon region is the same as that of the N-type implanted layer.

6. A method for manufacturing a SiC LDMOS device, characterized in that, The method for manufacturing a SiC LDMOS device as described in any one of claims 1 to 5 comprises: P-type substrates are provided; An N-type epitaxial layer is formed by epitaxial growth on the surface of the P-type substrate. P-type ions are implanted into the N-type epitaxial layer to form a P-type bulk region; P-type ions are implanted into the P-type body region to form a source P-type heavily doped region; N-type ions are implanted into the N-type epitaxial layer to form an N-type implanted layer; the side of the N-type implanted layer is connected to the side of the P-type body region. N-type ions are implanted into the P-type body region to form a source N-type heavily doped region; the side of the source N-type heavily doped region is connected to the side of the source P-type heavily doped region. N-type ions are implanted into the N-type epitaxial layer to form a heavily doped N-type drain region. A gate oxide layer is formed by thermal oxidation of a portion of the surface of the heavily doped N-type source region, the surface of the P-type body region, the surface of the N-type implanted layer, and a portion of the surface of the N-type epitaxial layer. P-type polysilicon is deposited on a portion of the surface of the gate oxide layer to form a polysilicon gate. P-type polysilicon is deposited on a portion of the surface of the gate oxide layer to form a P-type polysilicon region; the side of the P-type polysilicon region is connected to the side of the polysilicon gate.

7. The method for manufacturing a SiC LDMOS device according to claim 6, characterized in that, The method further includes: Metallization is performed on the surface of the heavily doped P-type region of the source electrode and on a portion of the surface of the heavily doped N-type region of the source electrode to form a metal source electrode. Metallization is performed on a portion of the surface of the heavily doped N-type drain region to form a metal drain.

8. The method for manufacturing a SiC LDMOS device according to claim 6, characterized in that, The process of thermally oxidizing a portion of the surface of the heavily doped N-type source region, the surface of the P-type body region, the surface of the N-type implanted layer, and a portion of the surface of the N-type epitaxial layer to form a gate oxide layer includes: Thermal oxidation is performed on the surfaces of the source P-type heavily doped region, the source N-type heavily doped region, the P-type body region, the N-type implantation layer, and the N-type epitaxial layer to generate oxide layers. The oxide layers on the surface of the source N-type heavily doped region, a portion of the surface of the source N-type heavily doped region, and a portion of the surface of the N-type epitaxial layer are then removed to form a gate oxide layer.

9. The method for manufacturing a SiC LDMOS device according to claim 6, characterized in that, The thickness of the P-type polysilicon region is the same as the thickness of the polysilicon gate, the width of the P-type polysilicon region is greater than the width of the polysilicon gate, and the doping concentration of the P-type polysilicon region is less than the doping concentration of the polysilicon gate.

10. The method for manufacturing a SiC LDMOS device according to claim 6, characterized in that, The doping concentration of the P-type body region is greater than the doping concentration of the N-type implanted layer, and the doping concentration of the N-type implanted layer is greater than the doping concentration of the N-type epitaxial layer.

11. The method for manufacturing a SiC LDMOS device according to claim 6, characterized in that, The doping concentration of the P-type polysilicon region is the same as that of the N-type implanted layer, and the thickness of the P-type polysilicon region is the same as that of the N-type implanted layer.

12. A chip, characterized in that, Including the SiC LDMOS device as described in any one of claims 1-5.

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