A method for fabricating a semiconductor structure

Abstract

This invention discloses a method for fabricating a semiconductor structure, belonging to the field of semiconductor technology. The method includes the following steps: providing a substrate, on which a buffer oxide layer is disposed, and on which a gate structure and sidewalls are disposed, the sidewalls comprising an inner nitride layer, an intermediate oxide layer, and an outer nitride layer; a silicon-germanium epitaxial layer is disposed in the substrate between adjacent gate structures; removing the outer nitride layer; reacting the buffer oxide layer and the intermediate oxide layer with a dry etching gas to generate a solid byproduct layer in situ; and removing the solid byproduct layer using sublimation or ashing. The semiconductor structure fabrication method disclosed in this invention can improve the performance of the formed semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for preparing a semiconductor structure. Background Technology

[0002] In some semiconductor manufacturing processes, there is a need to remove sidewalls. For example, in advanced processes for semiconductor devices such as FinFETs, after sigma etching, it is necessary to remove the silicon nitride in the sidewalls, followed by the silicon oxide and the buffer oxide layers on the substrate on both sides of the sidewalls. Then, a new oxide layer is redeposited to protect the etched device sidewalls and the silicon-germanium epitaxial layer in the sigma trenches.

[0003] Wet etching is typically used to remove silicon oxide from the sidewalls and the buffer oxide layers on the substrates on both sides of the sidewalls. Due to the isotropic nature of wet etching, the buffer oxide layer at the bottom of the sidewalls is etched, creating a gap at the bottom of the sidewalls. This gap forms a channel, allowing the etchant to penetrate along the channel during subsequent processes such as etching high-k dielectric layers, directly eroding the high-k dielectric layer and causing abnormal threshold voltages or device damage. After removing the dummy gate structure, the substrate at the bottom of the channel is exposed, and the wet etching solution can damage the substrate. The sidewall gap leaves the bottom of the gate structure hollow, leading to uneven stress on the sidewalls during subsequent sidewall formation, causing them to tilt or collapse. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor structure that can solve the problem of gaps forming at the bottom of the sidewalls when removing the sidewalls and buffer oxide layers.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] This invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0007] A substrate is provided, on which a buffer oxide layer is disposed, and on which a gate structure and a sidewall are disposed, wherein the sidewall includes an inner nitride layer, an intermediate oxide layer and an outer nitride layer, and a silicon-germanium epitaxial layer is disposed in the substrate between adjacent gate structures;

[0008] Remove the outer nitrided layer;

[0009] A dry etching gas is used to react with the buffer oxide layer and the intermediate oxide layer to generate a solid byproduct layer in situ; and

[0010] The solid byproduct layer is removed by sublimation or ashing.

[0011] In one embodiment of the present invention, the dry etching gas includes hydrofluoric acid and nitrogen trifluoride, and the generated solid byproduct layer is ammonium fluorosilicate.

[0012] In one embodiment of the present invention, removing the buffer oxide layer and the intermediate oxide layer includes the following steps:

[0013] The semiconductor structure is placed inside the plasma reaction chamber;

[0014] Hydrofluoric acid and nitrogen trifluoride are introduced into the plasma reaction chamber, causing the solid byproduct layer to form on the surfaces of the buffer oxide layer and the intermediate oxide layer; and

[0015] The solid byproduct layer is removed by sublimation.

[0016] In one embodiment of the present invention, the temperature at which the solid byproduct layer is removed by sublimation is greater than or equal to 190°C.

[0017] In one embodiment of the present invention, removing the buffer oxide layer and the intermediate oxide layer further includes the following steps: repeating the process of forming the solid by-product layer and sublimating to remove the solid by-product layer until the intermediate oxide layer and the buffer oxide layer not covered by the gate structure are completely removed.

[0018] In one embodiment of the present invention, the dry etching gas includes perfluorobutadiene, trifluoromethane and oxygen, and the resulting solid byproduct layer is a carbon-containing fluoropolymer.

[0019] In one embodiment of the present invention, removing the buffer oxide layer and the intermediate oxide layer includes the following steps:

[0020] A semiconductor structure is placed within a plasma reaction chamber, and the initial settings for the pressure, temperature, and radio frequency power supply within the plasma reaction chamber are established; and

[0021] The perfluorobutadiene, trifluoromethane, and oxygen are introduced into the plasma reaction chamber, and a radio frequency power supply is activated to generate plasma, causing the buffer oxide layer and the intermediate oxide layer to be converted into a solid byproduct layer; and

[0022] The solid byproduct layer is removed using an ashing process.

[0023] In one embodiment of the present invention, the pressure of the plasma reaction chamber is set to less than 10 mTorr, the temperature of the plasma reaction chamber is set to less than 80°C, and the initial mode of the radio frequency power supply is set to continuous power mode.

[0024] In one embodiment of the present invention, removing the buffer oxide layer and the intermediate oxide layer further includes the following steps:

[0025] The conversion progress of the buffer oxide layer and the intermediate oxide layer was monitored using a dual-wavelength laser interferometer and a multi-channel emission spectrometer.

[0026] When the remaining thickness of the buffer oxide layer or the intermediate oxide layer is less than the preset thickness, the radio frequency power supply is switched to pulse mode.

[0027] In one embodiment of the present invention, the removal of the buffer oxide layer and the intermediate oxide layer further includes the following steps: initiating real-time feedback of the impedance change of the silicon substrate interface by radio frequency harmonics, and stopping the etching process when the impedance of the substrate interface shows a phase angle jump greater than 5%.

[0028] In summary, the semiconductor structure fabrication method provided by this invention has the following unexpected effect: When removing the oxide layer in the sidewalls and the buffer oxide layer on the substrate, a dry etching gas is used to react with the oxide layer in the sidewalls and the buffer oxide layer on the substrate, generating a solid byproduct layer in situ. This solid byproduct layer is then removed by sublimation or ashing. During this process, the generated solid byproduct layer protects the buffer oxide layer at the bottom of the gate structure and part of the bottom of the sidewalls, preventing the buffer oxide layer at the bottom of the gate structure and part of the bottom of the sidewalls from reacting with the etching gas, thereby preventing the removal of the buffer oxide layer at the bottom of the gate structure and part of the bottom of the sidewalls, thus avoiding the formation of gaps at the bottom of the gate structure and part of the bottom of the sidewalls. In subsequent processes, because the bottom of the gate structure and part of the bottom of the sidewalls are protected by the buffer oxide layer, the etching solution will not damage the high-dielectric-constant layer and the substrate, improving the performance of the formed semiconductor device. Furthermore, compared to using wet etching to remove the oxide layer, using ashing and sublimation processes can effectively reduce costs.

[0029] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart of a method for forming a semiconductor structure in one embodiment.

[0032] Figure 2 This is a schematic diagram of the structure forming sigma trenches in one embodiment.

[0033] Figure 3 This is a schematic diagram of the structure forming a silicon-germanium epitaxial layer in one embodiment.

[0034] Figure 4 This is a schematic diagram of the structure with the outer nitrided layer removed in one embodiment.

[0035] Figure 5 This is a schematic diagram of the structure in one embodiment for forming a solid by-product layer.

[0036] Figure 6 This is a schematic diagram of the structure for removing the solid byproduct layer in one embodiment.

[0037] Figure 7 This is a flowchart illustrating the removal of the buffer oxide layer and the oxide layer in the sidewalls in one embodiment.

[0038] Figure 8 This is a flowchart illustrating the removal of the buffer oxide layer and the oxide layer in the sidewalls in another embodiment.

[0039] Label Explanation:

[0040] 101. Substrate; 102. Buffer oxide layer; 103. Gate dielectric layer; 104. Gate structure; 1041. Polysilicon gate; 1042. First hard mask layer; 1043. Second hard mask layer; 105. Sidewall; 1051. Inner nitride layer; 1052. Intermediate oxide layer; 1053. Outer nitride layer; 106. Sigma trench; 107. Silicon-germanium epitaxial layer; 108. Solid by-product layer. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0044] Please see Figure 2 As shown, in an advanced semiconductor device manufacturing process, an ion implantation region is formed in a substrate 101, a buffer oxide layer 102 is formed on the substrate 101, and a gate structure 104 and a sidewall 105 are formed on the buffer oxide layer 102, with the sidewall 105 covering the sidewall of the gate structure 104. During ion implantation of the substrate 101, the buffer oxide layer 102 and the sidewall 105 prevent ions from penetrating the gate structure 104 and entering its interior, thus preventing damage to the electrical performance of the gate structure 104.

[0045] Please see Figures 1 to 6 As shown, this application provides a method for fabricating a semiconductor structure, which can remove a portion of the sidewalls 105 and the buffer oxide layer 102 without damage after fabricating the doped region and the gate structure 104. Specifically, the method for fabricating a semiconductor structure provided in this application includes steps S101 to S105.

[0046] Step S101: Provide a substrate, on which a buffer oxide layer is disposed, a gate structure and a sidewall are disposed on the buffer oxide layer, and a silicon-germanium epitaxial layer is disposed in the substrate between adjacent gate structures.

[0047] Step S102: Remove the outer nitrided layer from the sidewall.

[0048] Step S103: Use dry etching gas to react with the buffer oxide layer and the oxide layer in the sidewalls to generate a solid byproduct layer in situ.

[0049] Step S104: Remove the solid byproduct layer using sublimation or ashing.

[0050] Please see Figure 2 As shown, in one embodiment of the present invention, the substrate 101 is a silicon substrate forming a semiconductor structure. The material of the substrate 101 may be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc.

[0051] Please see Figure 2 As shown, in one embodiment of the present invention, a buffer oxide layer 102 is provided on the substrate 101. The oxide layer covers the surface of the substrate 101, and the buffer oxide layer 102 is, for example, a silicon oxide layer. During ion implantation, the buffer oxide layer 102 can protect the substrate 101 from damage during ion implantation.

[0052] Please see Figure 2 As shown, in one embodiment of the present invention, a gate structure 104 is disposed on a buffer oxide layer 102, and each gate structure 104 includes a gate dielectric layer 103, a polysilicon gate 1041, a first hard mask layer 1042, and a second hard mask layer 1043. The gate dielectric layer 103 is disposed on the buffer oxide layer 102, and the gate dielectric layer 103 is, for example, a gate oxide layer or a high-dielectric-constant layer. The polysilicon gate 1041 is disposed on the gate dielectric layer 103, the first hard mask layer 1042 is disposed on the polysilicon gate 1041, and the second hard mask layer 1043 is disposed on the first hard mask layer 1042. The first hard mask layer 1042 is, for example, silicon nitride, and the second hard mask layer 1043 is, for example, silicon oxide. The first hard mask layer 1042 and the second hard mask layer 1043 can protect the polysilicon gate 1041 from damage during subsequent etching of the substrate 101.

[0053] Please see Figure 2 As shown, in one embodiment of the present invention, a sidewall 105 is disposed on the sidewall of the gate, and the sidewall 105 includes an oxide layer and a nitride layer stacked thereon. In one embodiment of the present invention, the sidewall 105 includes, from the inside out, an inner nitride layer 1051, an intermediate oxide layer 1052, and an outer nitride layer 1053. The inner nitride layer 1051 and the outer nitride layer 1053 are silicon nitride layers, and the intermediate oxide layer 1052 is a silicon oxide layer.

[0054] Please see Figure 2 As shown, in one embodiment of the present invention, after forming a buffer oxide layer 102, a gate structure 104, and a sidewall 105 on a substrate 101, ions are implanted into the substrate 101 to form the desired doped region. However, during the ion implantation process, the energy and ions implanted can cause uneven thickness of the buffer oxide layer 102 and the sidewall 105, resulting in a loss of uniform protection.

[0055] Please see Figure 2 and Figure 3As shown, in one embodiment of the present invention, a silicon-germanium epitaxial layer 107 is further disposed between adjacent gate structures 104. In this application, a sigma trench 106 can be formed by first etching the substrate 101 between the two gate structures 104, and then silicon-germanium epitaxial growth can be performed in the sigma trench 106 by selective epitaxy to form the silicon-germanium epitaxial layer 107. The silicon-germanium epitaxial layer 107 can improve the migration rate of hole carriers in the formed semiconductor device, thereby increasing the driving current and improving the performance of the semiconductor device.

[0056] Please see Figures 4 to 6 As shown, in one embodiment of the present invention, after forming the silicon-germanium epitaxial layer 107, it is necessary to remove the portion of the sidewalls 105 that have lost their ability to provide uniform protection and a portion of the buffer oxide layer 102. In subsequent processes, the sidewalls are re-formed. Specifically, in this application, the portion of the sidewalls 105 that needs to be removed consists of the intermediate oxide layer 1052 and the outer nitride layer 1053, and the portion of the buffer oxide layer 102 that needs to be removed consists of the buffer oxide layer 102 not covered by the gate structure 104. Therefore, when removing the portion of the sidewalls 105 and the portion of the buffer oxide layer 102, the outer nitride layer 1053 in the sidewalls 105 can be removed first, and then the intermediate oxide layer 1052 and the buffer oxide layer 102 not covered by the gate structure 104 can be removed simultaneously.

[0057] Please see Figure 1 , Figure 3 and Figure 4 As shown, in one embodiment of the present invention, in step S102, the outer nitride layer 1053 can be removed by wet etching. Specifically, a hot phosphoric acid (H3PO4) solution at 140°C to 200°C can be used to remove the outer nitride layer 1053. Since the hot phosphoric acid solution has a high selectivity for silicon oxide, the wet etching process of the outer nitride layer 1053 will not affect the buffer oxide layer 102 and the intermediate oxide layer 1052, and therefore will not damage the gate and the substrate 101.

[0058] Please see Figure 1 , Figures 4 to 6 As shown, in one embodiment of the present invention, after removing the outer nitride layer 1053, steps S103 to S104 are performed, in which dry etching gas is used to react with the oxide layer in the buffer oxide layer 102 and the sidewall 105 to generate a solid byproduct layer 108 in situ, and then sublimation or ashing is used to remove the solid byproduct layer 108.

[0059] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, the dry etching gas includes hydrofluoric acid (HF) and nitrogen trifluoride (NF3), and the generated solid byproduct layer 108 is ammonium fluorosilicate. At this time, removing the oxide layer in the buffer oxide layer 102 and the sidewall 105 includes steps S201 to S204.

[0060] Step S201: Place the semiconductor structure inside the plasma reaction chamber.

[0061] Please see Figure 7 As shown, in one embodiment of the present invention, the following can be used: Figure 4 The diagram shows a semiconductor structure placed inside a plasma reaction chamber. Afterwards, interfering gases such as water vapor and oxygen need to be removed from the plasma reaction chamber to maintain a stable low-pressure environment, thus preventing uneven gas reactions in the subsequent process.

[0062] Step S202: Hydrofluoric acid and nitrogen trifluoride are introduced into the plasma reaction chamber, so that a solid by-product layer is formed on the surface of the buffer oxide layer and the intermediate oxide layer.

[0063] Please see Figure 4 and Figure 7 As shown, in one embodiment of the present invention, after hydrofluoric acid and nitrogen trifluoride are introduced into the plasma reaction chamber, nitrogen trifluoride decomposes in the plasma environment to form active fluorine radicals and ammonia (NH3) precursors. Specifically, hydrofluoric acid gas and nitrogen trifluoride gas can be introduced into the plasma reaction chamber, and after the pressure in the plasma reaction chamber stabilizes, plasma is generated using radio frequency glow discharge. Under the action of plasma and other energies, the NF bonds of nitrogen trifluoride molecules will break, decomposing to form active fluorine radicals and nitrogen-containing active species, which are precursors for the generation of ammonia.

[0064] Please see Figure 4 and Figure 7 As shown, in one embodiment of the present invention, an ammonia precursor reacts with a hydrogen source to generate ammonia. The hydrogen source can be trace amounts of hydrogen in hydrofluoric acid gas, or hydrogen-containing material in the substrate 101 or sidewall 105. In some embodiments, hydrogen atoms in the hydrofluoric acid gas decompose into hydrogen radicals under the influence of energy such as plasma. These hydrogen radicals react with the ammonia precursor to generate ammonia. In other embodiments, trace amounts of hydrogen may remain on the surface of the substrate 101, in the sidewall 105, or in the silicon-germanium epitaxial layer during previous processes. Under radio frequency power, these trace amounts of hydrogen are released, further replenishing the hydrogen source and promoting ammonia generation.

[0065] Please see Figure 4 , Figure 5 and Figure 7 As shown, in one embodiment of the present invention, ammonia reacts with hydrofluoric acid, and silicon dioxide in the buffer oxide layer 102 and the intermediate oxide layer 1052 to form a solid byproduct layer 108. The solid byproduct layer 108 is ammonium fluorosilicate (NH4)2SiF6, and the reaction formula for the solid byproduct layer 108 is as follows:

[0066] SiO2+4HF+2NH3→(NH4)2SiF6↓+2H2O;

[0067] During this process, the introduced nitrogen trifluoride gas does not directly participate in the reaction, but rather enhances the reaction rate of HF and SiO2 through surface catalysis, ensuring a uniform reaction.

[0068] Please see Figure 4 , Figure 5 and Figure 7 As shown, in one embodiment of the present invention, the ammonium fluorosilicate formed is a white solid, and the ammonium fluorosilicate formed is located at the position of silicon dioxide that has reacted in the buffer oxide layer 102 and the intermediate oxide layer 1052, that is, the solid by-product layer 108 is generated in situ.

[0069] Step S203: Remove the solid byproduct layer by sublimation.

[0070] Please see Figure 5 , Figure 6 and Figure 7 As shown, in one embodiment of the present invention, the temperature of the plasma reaction chamber is increased to, for example, 190°C or higher. Ammonium fluorosilicate will sublimate directly at 190°C, and the sublimated gas is discharged through a pumping system within the plasma reaction chamber.

[0071] Step S204: Repeat the process of forming a solid byproduct layer and sublimating to remove the solid byproduct layer until the intermediate oxide layer and the buffer oxide layer not covered by the gate structure are completely removed.

[0072] Please see Figure 5 , Figure 6 and Figure 7 As shown, in one embodiment of the present invention, during the reaction, after the silicon dioxide on the surfaces of the buffer oxide layer 102 and the intermediate oxide layer 1052 reacts, the resulting solid ammonium fluorosilicate byproduct layer prevents the reaction from continuing. Therefore, after the ammonium fluorosilicate is sublimated, the unreacted buffer oxide layer 102 and the intermediate oxide layer 1052 are exposed. Then, steps S202 and S203 are repeated until all buffer oxide layers 102 and the intermediate oxide layer 1052 not covered by the gate structure 104 are removed.

[0073] Please see Figure 5 , Figure 6 and Figure 7As shown, in one embodiment of the present invention, during the process of generating a solid byproduct layer 108 on the surface of the buffer oxide layer 102 and the intermediate oxide layer 1052 using hydrofluoric acid gas and nitrogen trifluoride gas, the decomposition products (containing nitrogen-containing active species) of nitrogen trifluoride gas react with a trace amount of hydrogen source in the reaction chamber to generate ammonia gas, which immediately participates in the synthesis of the solid byproduct layer 108. This avoids additional contamination or damage to the substrate 101 caused by excessive ammonia gas. Furthermore, the solid byproduct layer 108 is repeatedly generated and removed by high-temperature sublimation. Through multiple cycles, silicon dioxide is gradually converted into the solid byproduct layer 108, which avoids damage to the gate structure 104 and the substrate 101.

[0074] Please see Figure 4 and Figure 8 As shown, in another embodiment of the present invention, the dry etching gas includes perfluorobutadiene (C4F6), trifluoromethane (CHF3), and oxygen (O2), and the resulting solid byproduct layer 108 is a carbon-containing fluoropolymer. In this case, removing the oxide layer from the buffer oxide layer 102 and the sidewall 105 includes steps S301 to S306.

[0075] Step S301: Place the semiconductor structure in the plasma reaction chamber and set the initial mode of the plasma reaction chamber pressure, temperature and radio frequency power supply.

[0076] Please see Figure 8 As shown, in another embodiment of the present invention, the following will be used: Figure 4 The semiconductor structure is placed within the plasma reaction chamber. The plasma reaction chamber then needs to be set to a low-pressure, low-temperature environment. Specifically, setting the pressure of the plasma reaction chamber to less than, for example, 10 mTorr reduces plasma bombardment damage to the sidewalls. Setting the temperature of the plasma reaction chamber to less than, for example, 80°C avoids changes in silicon-germanium performance due to high temperatures. The initial mode of the RF power supply is set to continuous power mode, and the initial RF power range is set to, for example, 500W~800W to ensure initial reaction efficiency.

[0077] Step S302: Perfluorobutadiene, trifluoromethane and oxygen are introduced into the plasma reaction chamber, and the radio frequency power supply is started to generate plasma, so that the buffer oxide layer and the intermediate oxide layer are converted into a solid by-product layer.

[0078] Please see Figure 4 and Figure 8As shown, in another embodiment of the present invention, after perfluorobutadiene, trifluoromethane, and oxygen are introduced into the plasma reaction chamber and the radio frequency power supply is activated to generate plasma, the perfluorobutadiene and trifluoromethane dissociate into active species. Specifically, under the action of radio frequency plasma, the C-C bonds and CF bonds of perfluorobutadiene partially break, generating fluorocarbon active species containing double bonds and active fluorine radicals, such as CF2=CF- or CF2=. The CH bonds and CF bonds of trifluoromethane break, generating hydrofluorocarbon active species such as -CF3 and -CHF2, while releasing a small amount of active hydrogen radicals. Among them, the active hydrogen radicals can inhibit excessive fluorine dissociation and reduce the etching rate. Oxygen reacts with some carbon active species to generate carbon monoxide (CO) or carbon dioxide (CO2), which can regulate the polymer stacking rate and avoid excessive accumulation of counter byproducts that block the etching channels.

[0079] Please see Figure 4 and Figure 8 As shown, in another embodiment of the present invention, after perfluorobutadiene and trifluoromethane dissociate into active species, the active species react with silica in the buffer oxide layer 102 and the intermediate oxide layer 1052 to form a solid byproduct layer 108. The solid byproduct layer 108 is a carbon-containing fluoropolymer.

[0080] Specifically, during the reaction, active fluorine radicals first react with the silica in the buffer oxide layer 102 and the intermediate oxide layer 1052 to complete the etching of silica, generating volatile silicon-containing fluorides and surface intermediate active oxygen radicals, providing anchoring sites for polymer deposition. Subsequently, fluorocarbon active species containing double bonds adsorb onto the surface intermediate active oxygen radicals on the silica surface, forming long-chain structures through radical polymerization.

[0081] During this process, oxygen reacts with some of the active carbon species at the polymer chain ends to generate oxygen-containing functional groups such as -CF2-C(=O)-O-. These functional groups can increase the adhesion between the polymer and the sidewalls, preventing lateral erosion. Furthermore, they can control the degree of crosslinking of the fluoropolymer, preventing excessively long chains from causing excessive buildup, ultimately forming a fluoropolymer film with uniform thickness and strong adhesion. The main component of the fluoropolymer is an oligomer similar to polytetrafluoroethylene, with a specific structure such as [-CF2-CF2-]. n Or [-CF2-CF(CF3)-] n .

[0082] Step S303: Use a dual-wavelength laser interferometer and a multi-channel emission spectrometer to monitor the conversion progress of the buffer oxide layer and the intermediate oxide layer.

[0083] Please see Figure 4 and Figure 8As shown, in another embodiment of the present invention, after perfluorobutadiene, trifluoromethane and oxygen are introduced into the plasma reaction chamber and the radio frequency power supply is started to generate plasma, the dual-wavelength laser interferometer system and the multi-channel emission spectrometer are started to monitor the conversion progress of the buffer oxide layer 102 and the intermediate oxide layer 1052.

[0084] Specifically, the dual-wavelength laser interferometry system uses visible light, such as 633nm, and infrared light, such as 1550nm, to illuminate the surface of substrate 101. By analyzing the interference signal of the reflected light, the thickness of the unreacted buffer oxide layer 102 and the intermediate oxide layer 1052 can be monitored, i.e., the remaining thickness of the buffer oxide layer 102 and the intermediate oxide layer 1052 can be monitored. The 1550nm infrared light can penetrate the solid byproduct layer 108, ensuring accurate detection of the remaining thickness of the buffer oxide layer 102 and the intermediate oxide layer 1052.

[0085] A multichannel optical emission spectrometer (OES) can monitor the reaction process of the solid byproduct layer 108. The OES includes SiF and CO spectra. The intensity of the SiF spectra increases with the amount of silicon dioxide etched, reflecting the progress of the silicon dioxide reaction. The intensity of the CO spectra varies with the amount of carbon-containing polymer generated, reflecting the stacking state of the solid byproduct layer 108.

[0086] The conversion progress of the buffer oxide layer 102 and the intermediate oxide layer 1052 is monitored simultaneously using a dual-wavelength laser interferometry system and a multi-channel emission spectrometer. Specifically, the dual-wavelength laser interferometry system can detect the remaining thickness of the buffer oxide layer 102 and the intermediate oxide layer 1052, while the multi-channel emission spectrometer can monitor the state of the chemical reaction in real time. During the reaction, process parameters can be adjusted according to the chemical reaction state to avoid excessive concentration of active materials in the reaction chamber, which could lead to runaway reaction rates. Simultaneously, the deposition state of the solid byproduct layer 108 can be determined by the CO spectral intensity, preventing over-deposition that could clog etching channels and under-deposition that could lead to sidewall erosion.

[0087] Step S304: When the remaining thickness of the buffer oxide layer or intermediate oxide layer is less than the preset thickness, switch the RF power supply to pulse mode.

[0088] Please see Figure 4 and Figure 8As shown, in another embodiment of the present invention, the preset thickness of the buffer oxide layer 102 or the intermediate oxide layer 1052 is, for example, 20 Å. When the dual-wavelength laser interferometry system detects that the remaining thickness of the buffer oxide layer 102 or the intermediate oxide layer 1052 is less than 20 Å, the RF power supply is switched from continuous power mode to pulsed power mode, and the RF power of the RF power supply is reduced to 200W. In pulsed power mode, the etching rate of the buffer oxide layer 102 and the intermediate oxide layer 1052 is slowed down, and silicon oxide conversion can be performed separately in sparse and dense regions. In addition, the low-power RF power supply can reduce plasma bombardment damage to the substrate 101.

[0089] Step S305: When an impedance change at the substrate interface is detected, the etching process is stopped.

[0090] Please see Figure 5 and Figure 8 As shown, in another embodiment of the present invention, real-time feedback of the impedance change at the interface of the silicon substrate 101 is initiated using radio frequency harmonics. When the buffer oxide layer 102 is substantially removed and the plasma contacts the silicon substrate 101, the impedance at the interface of the substrate 101 will exhibit a phase angle jump greater than 5%. At this point, the radio frequency power supply and gas supply are immediately stopped, and the etching process ends.

[0091] Step S306: Remove the solid byproduct layer by ashing.

[0092] Please see Figure 5 , Figure 6 and Figure 8 As shown, in another embodiment of the present invention, when the formed solid by-product layer 108 is a carbon-containing fluoropolymer, it will be as follows: Figure 5 The semiconductor structure shown is transferred to a desmearing chamber, into which sufficient oxygen is introduced, and the temperature of the desmearing chamber is raised to 300℃~400℃. At high temperature, oxygen reacts with the fluoropolymer containing carbon dioxide (ashing) to generate gases such as carbon dioxide (CO2), carbon monoxide (CO), or carbon tetrafluoride (CF4). The reaction gases and generated gases are discharged through a vacuum system, ultimately resulting in a clean surface free of oxides and byproducts, without corroding the gate structure 104 and the buffer oxide layer 102 beneath the inner nitride layer 1051.

[0093] In summary, the present invention provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate, wherein a buffer oxide layer is disposed on the substrate, a gate structure and a sidewall are disposed on the buffer oxide layer, the sidewall comprising an inner nitride layer, an intermediate oxide layer and an outer nitride layer, and a silicon-germanium epitaxial layer is disposed in the substrate between adjacent gate structures; removing the outer nitride layer; reacting the buffer oxide layer and the intermediate oxide layer with a dry etching gas to generate a solid byproduct layer in situ; and removing the solid byproduct layer by sublimation or ashing.

[0094] The present invention provides a method for fabricating a semiconductor structure with the unexpected effect of using a dry etching gas to react with the oxide layer in the sidewalls and the buffer oxide layer on the substrate during the removal of the oxide layer in the sidewalls and the buffer oxide layer on the substrate. This generates a solid byproduct layer in situ, which is then removed by sublimation or ashing. During this process, the generated solid byproduct layer protects the buffer oxide layer at the bottom of the gate structure and part of the bottom of the sidewalls, preventing the buffer oxide layer at the bottom of the gate structure and part of the bottom of the sidewalls from reacting with the etching gas. This prevents the buffer oxide layer at the bottom of the gate structure and part of the bottom of the sidewalls from being removed, thus avoiding the formation of gaps at the bottom of the gate structure and part of the bottom of the sidewalls. In subsequent processes, because the bottom of the gate structure and part of the bottom of the sidewalls are protected by the buffer oxide layer, the etching solution will not damage the high-dielectric-constant layer and the substrate, improving the performance of the formed semiconductor device. Furthermore, compared to using wet etching to remove the oxide layer, using ashing and sublimation processes can effectively reduce costs.

[0095] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, on which a buffer oxide layer is disposed, and on which a gate structure and a sidewall are disposed, the sidewall comprising an inner nitride layer, an intermediate oxide layer and an outer nitride layer, and a silicon-germanium epitaxial layer is disposed in the substrate between adjacent gate structures; Remove the outer nitrided layer; A dry etching gas is used to react with the buffer oxide layer and the intermediate oxide layer to generate a solid byproduct layer in situ; and The solid byproduct layer was removed by sublimation or ashing. The dry etching gas includes hydrofluoric acid and nitrogen trifluoride, and the resulting solid by-product layer is ammonium fluorosilicate; or the dry etching gas includes perfluorobutadiene, trifluoromethane and oxygen, and the resulting solid by-product layer is a carbon-containing fluoropolymer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing the buffer oxide layer and the intermediate oxide layer includes the following steps: The semiconductor structure is placed inside the plasma reaction chamber; Hydrofluoric acid and nitrogen trifluoride are introduced into the plasma reaction chamber, causing the solid byproduct layer to form on the surfaces of the buffer oxide layer and the intermediate oxide layer; and The solid byproduct layer is removed by sublimation.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The temperature at which the solid byproduct layer is removed by sublimation is greater than or equal to 190°C.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The removal of the buffer oxide layer and the intermediate oxide layer further includes the following steps: repeating the process of forming the solid by-product layer and sublimating to remove the solid by-product layer until the intermediate oxide layer and the buffer oxide layer not covered by the gate structure are completely removed.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing the buffer oxide layer and the intermediate oxide layer includes the following steps: A semiconductor structure is placed within a plasma reaction chamber, and the initial settings for the pressure, temperature, and radio frequency power supply within the plasma reaction chamber are established; and The perfluorobutadiene, trifluoromethane, and oxygen are introduced into the plasma reaction chamber, and a radio frequency power supply is activated to generate plasma, causing the buffer oxide layer and the intermediate oxide layer to be converted into a solid byproduct layer; and The solid byproduct layer is removed using an ashing process.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The pressure of the plasma reaction chamber is set to less than 10 mTorr, the temperature of the plasma reaction chamber is set to less than 80°C, and the initial mode of the radio frequency power supply is set to continuous power mode.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, Removing the buffer oxide layer and the intermediate oxide layer further includes the following steps: The conversion progress of the buffer oxide layer and the intermediate oxide layer was monitored using a dual-wavelength laser interferometer and a multi-channel emission spectrometer. When the remaining thickness of the buffer oxide layer or the intermediate oxide layer is less than the preset thickness, the radio frequency power supply is switched to pulse mode.

8. The method for preparing a semiconductor structure according to claim 5, characterized in that, The removal of the buffer oxide layer and the intermediate oxide layer also includes the following steps: initiating real-time feedback of the impedance change of the silicon substrate interface by radio frequency harmonics, and stopping the etching process when the impedance of the substrate interface shows a phase angle jump greater than 5%.

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