Infrared chip low-temperature testing device with double thermal interface materials

Abstract

The invention relates to an infrared chip low-temperature testing device with a double-thermal interface material. The infrared chip low-temperature testing device comprises refrigeration equipment, a first heat conduction layer, a substrate and a second heat conduction layer which are sequentially arranged from bottom to top, the first heat conduction layer is located between the refrigeration equipment and the base plate and attached to the surface of the refrigeration equipment and the surface of the base plate. The second heat conduction layer is located between the substrate and the chip and is attached to the surface of the substrate and the surface of the chip. The thermal interface materials are respectively arranged between the substrate and the chip and between the refrigeration equipment and the substrate, so that the double-interface thermal resistance accumulative effect can be relieved through the synergistic effect of the two thermal interface materials, heat can be stably and efficiently conducted, and the situation that the infrared chip coke temperature test result fluctuates greatly, and the test accuracy is high is avoided. The stability of a coke temperature test result is ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a low-temperature testing device for infrared chips with dual thermal interface materials. Background Technology

[0002] Infrared focal plane arrays are a core component of infrared detectors. Rapid and accurate evaluation of their performance is crucial for improving the overall performance of the detector. Response testing of cooled infrared focal plane array chips requires establishing a cryogenic environment at liquid nitrogen temperature. Currently, the cryogenic inspection and screening process for cooled infrared detector chips is typically based on liquid nitrogen Dewars, which provide a stable and durable cryogenic operating environment (typically 77K, or -196℃) for the infrared chip.

[0003] like Figure 1a As shown, the current infrared chip low-temperature testing structure includes a Dewar cold finger and a substrate. The substrate is supported by a thermally conductive material, such as copper. The Dewar and the substrate are in direct contact, and the chip is bonded together with an organic adhesive.

[0004] In the aforementioned structure, due to processing techniques and wear, both the Dewar cold fingers and the substrate surface develop uneven, rough surfaces. This results in numerous air gaps between the substrate and the Dewar cold fingers, and between the chip and the substrate, after bonding. Air has a thermal conductivity of only 0.024 W / (m²). K) is a poor conductor of heat, which results in very high contact thermal resistance at the interface between the substrate and the cold finger, and at the interface between the chip and the substrate. This leads to a cumulative effect of thermal resistance at both interfaces, which severely hinders heat conduction. Ultimately, this results in low thermal conduction efficiency between the substrate and the Dewar, and between the substrate and the chip, affecting the accuracy of infrared chip performance test results (such as focal temperature test results).

[0005] Furthermore, the chip manufacturing materials may include narrow bandgap materials. In low-temperature testing, such chips experience excessive focal temperature noise interference due to anisotropic thermal conductivity and the aforementioned cumulative effect of dual-interface thermal resistance. Figure 1b As shown in the figure, the scorch temperature fluctuation is more prominent, and local (such as chip edge) scorch temperature is prone to be too high, which leads to the distortion of test data.

[0006] To address these issues, thermally conductive adhesives or silicone pads, or other highly thermally conductive interface materials, are typically added between the substrate and the chip to fill the gaps, eliminating air and establishing an effective heat conduction channel. This significantly reduces contact thermal resistance, allowing the liquid nitrogen Dewar to function optimally. However, the method of adding conductive adhesive pads is highly dependent on the mounting method, leading to large fluctuations in chip temperature. Adding silicone pads results in unstable connection structures, and the silicone medium is difficult to remove later. Furthermore, this approach only solves the problem of high thermal resistance between the chip and the substrate; it cannot alleviate the cumulative effect of thermal resistance at the dual interfaces. Summary of the Invention

[0007] The purpose of this invention is to provide an infrared chip low-temperature testing device with dual thermal interface materials. By setting thermal interface materials between the substrate and the chip, and between the cooling device and the substrate, the synergistic effect of the two thermal interface materials can alleviate the cumulative effect of dual interface thermal resistance, so that heat can be conducted stably and efficiently, thereby avoiding large fluctuations in the infrared chip focal temperature test results and ensuring the stability of the focal temperature test results.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] A chip low-temperature testing device with dual thermal interface materials is provided, which includes a refrigeration device, a first thermally conductive layer, a substrate and a second thermally conductive layer arranged sequentially from bottom to top.

[0010] The first thermally conductive layer is located between the refrigeration device and the substrate, and is respectively attached to the surface of the refrigeration device and the surface of the substrate;

[0011] The second thermally conductive layer is located between the substrate and the chip, and is attached to the surfaces of the substrate and the chip, respectively.

[0012] Preferably, the first thermally conductive layer is made of a thermal interface material with high flexibility and low temperature adaptability, and is used to fill the air gap at the contact interface between the refrigeration device and the substrate to compensate for the thermal deformation difference between the contact interface between the substrate and the refrigeration device.

[0013] Preferably, the thickness of the first thermally conductive layer is 50-300 μm and the thermal conductivity is ≥50 W / (m·K).

[0014] Preferably, the second thermally conductive layer is made of a thermal interface material with high thermal conductivity and low thermal resistance, used to fill the air gap at the interface between the substrate and the chip to ensure stable heat conduction in the vertical direction.

[0015] Preferably, the thickness of the second thermally conductive layer is 20-100 μm and the thermal conductivity is ≥50 W / (m·K).

[0016] Preferably, the first thermally conductive layer is made of graphene or indium.

[0017] Preferably, the first thermally conductive layer is fixed at the contact interface between the refrigeration equipment and the substrate under the action of the clamp.

[0018] Preferably, the second thermally conductive layer is made of any one of silver epoxy resin, indium, or conductive copper paste.

[0019] Preferably, the second thermally conductive layer is coated at the contact interface between the substrate and the chip and then subjected to pressure curing.

[0020] Preferably, the cooled infrared detector chip is made of a narrow bandgap superlattice material.

[0021] In summary, the present invention has the following advantages compared with the prior art:

[0022] This invention provides thermal interface materials between the substrate and the chip, and between the cooling device and the substrate. This effectively reduces the contact thermal resistance at the substrate-chip contact interface and the substrate-cooling device contact interface. The synergistic effect of the two thermal interface materials alleviates the cumulative effect of dual-interface thermal resistance, enabling stable and efficient heat conduction. This avoids large fluctuations in the infrared chip focal temperature test results and ensures the stability of the focal temperature test results. Attached Figure Description

[0023] Figure 1a This is a schematic diagram of the structure of an infrared chip cryogenic testing device using existing thermal interface materials.

[0024] Figure 1b A focal plane image obtained using an existing infrared chip cryogenic testing device;

[0025] Figure 2 This is an overall structural diagram of the chip low-temperature testing device in this invention;

[0026] Figure 3 This is a longitudinal sectional view of the chip low-temperature testing device in this invention. Detailed Implementation

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] Example 1:

[0029] like Figure 2-3As shown, this embodiment provides a chip low-temperature testing device with dual thermal interface materials, which includes a refrigeration device 1, a first thermally conductive layer 2, a substrate 3 and a second thermally conductive layer 4 arranged sequentially from bottom to top;

[0030] The refrigeration device 1 has a cold end. For example, in this embodiment, the refrigeration device includes a Dewar with a cold finger. The first thermally conductive layer 2 is located between the cold end of the refrigeration device 1 and the substrate 3, and is respectively attached to the surface of the cold end of the refrigeration device 1 and the surface of the substrate 3. The second thermally conductive layer 4 is located between the substrate 3 and the chip 100, and is respectively attached to the surface of the substrate 3 and the chip 100.

[0031] In this embodiment, the chip 100 is a cooled infrared detector chip (i.e., an infrared chip), and the cooled infrared detector chip is made of a narrow bandgap superlattice material;

[0032] The first thermally conductive layer 2 is made of thermal interface materials (TIM) (such as graphene, indium, etc.), with a thickness of 50-300 μm and a thermal conductivity ≥50 W / (m·K). It is fixed to the contact interface between the cooling device 1 and the substrate 3 under the action of a clamp. Therefore, the first thermally conductive layer 2 has high flexibility and low-temperature adaptability. It is used to fill the air gap at the contact interface between the cooling device 1 and the substrate 3 to compensate for the difference in thermal deformation between the substrate 3 and the cooling device 1. Simultaneously, it can reduce the contact thermal resistance of the substrate 3 and the cooling device 1 to 0.01-0.5℃•cm. 2 / W.

[0033] The substrate 3 is made of a thermally conductive material, such as a metal (e.g., copper), and has a thickness of 0.4-0.6 mm.

[0034] The second thermally conductive layer 4 can also be made of a thermal interface material (such as silver epoxy resin, indium, conductive copper paste, etc.), with a thickness of 20-100 μm and a thermal conductivity ≥50 W / (m·K), and is fixed to the contact interface between the cooling device 1 and the substrate 3 under the action of a clamp. Thus, the second thermally conductive layer 4 has high thermal conductivity and low thermal resistance. It is used to fill the air gap at the contact interface between the substrate 3 and the chip 100, and is pressurized at 80°C for 1 hour to ensure the stability of thermal conduction in the vertical direction. Simultaneously, it also reduces the contact thermal resistance of the substrate 3 and the chip 100 contact interface to 0.01-0.5°C·cm. 2 / W.

[0035] Therefore, the test device in this embodiment has a simple structure and is easy to assemble and disassemble. When performing low-temperature testing on the chip, it is only necessary to connect the chip 100 and the substrate 3 through the second thermal conductive layer 4. The first thermal conductive layer 2 and the substrate 3 can be reused without frequent replacement. When the chip 100 needs to be removed after the test, the second thermal conductive layer 4 can be removed with an organic solvent to complete the disassembly of the chip 100. Therefore, the chip 100 can be protected from damage during disassembly, assembly and testing, and non-destructive testing of the chip can be achieved.

[0036] Furthermore, in this embodiment, a non-contact first thermal conductive layer 2 and a second thermal conductive layer 4 are provided, and each performs a corresponding function based on the different material properties (such as thickness, thermal conductivity, etc.) of the first thermal conductive layer 2 and the second thermal conductive layer 4. That is, the first thermal conductive layer 2 compensates for the thermal deformation difference at the contact interface between the substrate 3 and the cooling device 1, and the second thermal conductive layer 4 ensures the stability of thermal conduction in the vertical direction, thereby improving the thermal contact conditions between the cooling device 1 and the substrate 3, and between the substrate 3 and the chip 100, and reducing the cumulative effect of thermal resistance at the dual interfaces.

[0037] To verify the accuracy of the chip testing results of the low-temperature chip testing device of the present invention, this embodiment designs Comparative Example 1 and Comparative Example 2 to compare the test results with the solution of the present invention.

[0038] Among them, Comparative Example 1 adopts Figure 1a The test apparatus shown involves placing a substrate between the chip and the Dewar cold plate (finger), with the substrate in direct contact with both the chip and the Dewar cold plate (finger). Then, a metal clamp or similar device is used to press the substrate together to make it adhere to the Dewar cold plate (finger).

[0039] Comparative Example 2 is in Figure 1a Based on the test device structure, a thermal interface material is placed between the chip and the substrate. The substrate and the Dewar cold plate (finger) are still in direct contact without thermal interface material. Then, the substrate is pressed with metal pressure blocks and other devices to make it fit with the Dewar cold plate (finger).

[0040] Further, several infrared chips of the same type were installed on Comparative Example 1, Comparative Example 2, and the test device in this embodiment, respectively. Then, the infrared chips output the corresponding focal plane image, and the focal plane image was used to determine whether there was an abnormality in the focal temperature of the infrared chip. The number of chips with abnormal focal temperature corresponding to the three sets of test devices, as well as the ratio between the number of chips with abnormal focal temperature under the set of test devices and the total number of test chips, were statistically analyzed. The statistics of the number of chips with abnormal focal temperature and the proportion of the number of chips with abnormal focal temperature under the set of test devices in Comparative Example 1, Comparative Example 2, and this embodiment are shown in Table 1.

[0041] Table 1. Number and percentage of chips with abnormal coke temperature

[0042]

[0043] Whether the focal temperature is abnormal can be determined by testing the image. If there is a lot of noise in the image and the image cannot be stably formed, it is determined to be an abnormal focal temperature (e.g., Figure 1b (As shown).

[0044] As can be seen from Table 1, the test device in Comparative Example 1, due to the lack of any thermal interface material, exhibits the most significant cumulative effect of dual-interface thermal resistance. This test device has the highest number of chips with abnormal burn-temperature and the highest percentage of chips with abnormal burn-temperature. In contrast, this embodiment, by employing a dual-layer thermal interface material, effectively reduces the cumulative effect of dual-interface thermal resistance, significantly decreasing the thermal resistance of the contact surface. This results in more accurate temperature measurement results, reducing the percentage of chips with abnormal burn-temperature to approximately 5%. This demonstrates that this embodiment can reduce the cumulative effect of dual-interface thermal resistance through the design of a dual-layer thermal interface material, thereby preventing excessively high local burn-temperature of the chip during testing, suppressing abnormal burn-temperature, and stabilizing the burn-temperature test results.

[0045] In summary, this invention effectively reduces the contact thermal resistance at the substrate-chip and substrate-cooling device contact interfaces by setting thermal interface materials between the substrate and chip, and between the cooling device and the substrate. The synergistic effect of the two thermal interface materials greatly alleviates the cumulative effect of dual-interface thermal resistance, enabling stable and efficient heat conduction between the cooling device, substrate, and chip. This avoids large fluctuations in the infrared chip focal temperature test results and ensures the stability of the focal temperature test results.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-temperature testing device for infrared chips with dual thermal interface materials, characterized in that, It includes, from bottom to top, a refrigeration device, a first heat-conducting layer, a substrate, and a second heat-conducting layer; The first thermally conductive layer is located between the refrigeration device and the substrate, and is respectively attached to the surface of the refrigeration device and the surface of the substrate; The second thermally conductive layer is located between the substrate and the chip, and is attached to the surfaces of the substrate and the chip, respectively.

2. The infrared chip low-temperature testing device as described in claim 1, characterized in that, The first thermally conductive layer is made of a thermal interface material with high flexibility and low temperature adaptability, and is used to fill the air gap at the contact interface between the refrigeration device and the substrate to compensate for the thermal deformation difference between the contact interface between the substrate and the refrigeration device.

3. The chip low-temperature testing device as described in claim 1, characterized in that, The thickness of the first thermally conductive layer is 50-300 μm and the thermal conductivity is ≥50 W / (m·K).

4. The infrared chip low-temperature testing device as described in claim 1 or 2, characterized in that, The second thermally conductive layer is made of a thermal interface material with high thermal conductivity and low thermal resistance. It is used to fill the air gap at the interface between the substrate and the chip to ensure stable heat conduction in the vertical direction.

5. The infrared chip low-temperature testing device as described in claim 1, characterized in that, The second thermally conductive layer has a thickness of 20-100 μm and a thermal conductivity of ≥50 W / (m·K).

6. The infrared chip low-temperature testing device as described in claim 1, characterized in that, The first thermally conductive layer is made of graphene or indium.

7. The infrared chip low-temperature testing device as described in claim 1, characterized in that, The first thermally conductive layer is fixed to the contact interface between the refrigeration equipment and the substrate under the action of the clamp.

8. The infrared chip low-temperature testing device as described in claim 1, characterized in that, The second thermally conductive layer is made of any one of silver epoxy resin, indium, or conductive copper paste.

9. The infrared chip low-temperature testing device as described in claim 1, characterized in that, The second thermally conductive layer is coated at the contact interface between the substrate and the chip and then subjected to pressure curing.

10. The infrared chip low-temperature testing device as described in claim 9, characterized in that, The chip is made of a narrow bandgap superlattice material.

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