SOI substrate current test structure

Abstract

The invention discloses an SOI (Silicon On Insulator) substrate current test structure. An MOS (Metal Oxide Semiconductor) transistor of a first conductive type is formed on a first active region formed by an SOI substrate. The first active region is divided into a device main body region and a device extension region which are adjacently arranged in a strip-shaped extension direction of a first gate structure of the MOS transistor; the first gate structure extends from the device main body region into the device extension region, and the top of the first gate structure is connected to a gate composed of the front metal layer. Heavily doped source and drain regions of the first conduction type are formed in the device main body region on the two sides of the first gate structure in a self-alignment manner, and the two source and drain regions are connected to a source electrode and a drain electrode respectively. And a second conductive type heavily doped SOI substrate leading-out region is formed in the device extension region at the two sides of the first gate structure in a self-alignment manner, and the SOI substrate leading-out region is connected to an SOI substrate electrode. According to the invention, the SOI substrate current of the MOS transistor can be tested, the process deviation can be monitored in time, and the optimal HCI reliability test condition can be determined.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a current testing structure for an SOI substrate. Background Technology

[0002] As device feature sizes continue to shrink, the short-channel effect becomes increasingly severe, rendering existing traditional planar MOSFET structures largely unsuitable. Multi-gate devices, including SOI devices, with stronger gate control capabilities are now required.

[0003] For transistors with buried oxide (BOX) layers, the BOX layer can effectively isolate the electric field between the device and the substrate, reduce parasitic capacitance, and better control the short-channel effect, making it a very attractive low-power application solution; however, due to the obstruction of the BOX, it is impossible to test the substrate current (Isub) of the device itself.

[0004] In wafer acceptance testing (WAT), Isub can reflect fluctuations in process parameters. By monitoring Isub, process deviations can be detected in a timely manner, and the process flow can be optimized, thereby improving device performance. The Isub parameter is also crucial in reliability testing of hot carrier injection (HCI) effects.

[0005] For input / output (IO) devices, due to the thick gate oxide layer and strong lateral electric field, the movement mechanism of hot carriers can be explained by the lucky electron model: after the channel hot carriers gain sufficient energy under the action of the lateral electric field, they change their direction of motion without losing energy, and after a series of complex movements, they cross the Si-SiO2 barrier and pass through the oxide layer to form the gate current. Si-SiO2 represents the silicon substrate and the SiO2 of the gate oxide layer.

[0006] Furthermore, as the gate voltage (Vg) of the I / O device increases, the substrate current reaches its maximum when Vg reaches a certain bias condition, at which point the collisional ionization of hot carriers is most intense. When using the Vg@Ibmax mode for testing, the Vgstress corresponding to the most severe degradation is determined based on the Ib-Vgs characteristic curve. Therefore, the Isub parameter can be used to determine the worst-case gate stress bias voltage Vgstress. Here, Ib is Isub, and Ibmax is the maximum value of Ib in the Ib-Vgs characteristic curve.

[0007] However, dual-gate devices containing a BOX layer cannot be tested in WAT testing due to the obstruction of the BOX; in HCI process reliability testing, when using the Vg@Ibmax mode, the Vgstress condition cannot be accurately determined, thus making it impossible to accurately obtain the device lifetime under the worst test conditions.

[0008] like Figure 1AThe diagram shown is a layout of an existing FDSOIPMOS. Figure 1B Is Figure 1A The layout was expanded with the addition of contact holes and metal layers. Figure 2 yes Figure 1A A cross-sectional view of an existing FDSOIPMOS; a cross-sectional view along a direction perpendicular to the first direction; the existing FDSOIPMOS is formed on a first active region 101 formed from an SOI substrate 203. The first active region 101 is referenced. Figure 1A As shown, the SOI substrate 203 is referred to Figure 2 As shown. The SOI substrate 203 is formed on the top surface of the buried dielectric layer 202, which is formed in the bulk substrate. The bulk substrate below the bottom surface of the buried dielectric layer 202 is the bottom bulk substrate 201. Figure 2 As shown, a shallow trench isolation 204 is formed around the first active region 101, and the first active region 101 is composed of the SOI substrate 203 surrounding the corresponding area of ​​the shallow trench isolation 204. The shallow trench isolation 204 passes through the SOI substrate 203, the buried dielectric layer 202 and enters the bottom body substrate 201.

[0009] The material of the buried dielectric layer 202 includes an oxide layer. The material of the bulk substrate includes silicon.

[0010] The FDSOIPMOS includes a first gate structure formed on the top surface of the SOI substrate 203 and in the shape of a strip, wherein the extension direction of the strip of the first gate structure is a first direction. Figure 1B In this context, L1 represents the length of the first gate structure, i.e., the dimension in the first direction, and W represents the width of the first gate structure.

[0011] like Figure 2 As shown, the first gate structure includes a gate dielectric layer 206 and a gate conductive material layer 103 stacked sequentially. The gate conductive material layer 103 includes a polysilicon gate. The gate dielectric layer 206 is made of an oxide layer. (Back) Figure 1B As shown, the gate conductive material layer 103 extends to the outside of the first active region 101 and forms a contact hole 108 on top. The top of the contact hole 108 is connected to the first front metal layer 109 (M1) and finally connected to the gate G.

[0012] like Figure 2 As shown, P-type heavily doped source / drain regions are self-aligned and formed in the first active regions 101 on both sides of the first gate structure. One of the two source / drain regions serves as source region 207a connected to the source S, and the other serves as drain region 207b connected to the drain D. (Back) Figure 1BAs shown, a contact hole 108 is formed on the top of the source region 207a, connecting to the first front-side metal layer 109 and finally to the source electrode S. A contact hole 108 is formed on the top of the drain region 207b, connecting to the first front-side metal layer 109 and finally to the drain electrode D. On the layout, the P-type source / drain injection layer 104 of the source / drain regions extends to the outside of the first active region 101, by… Figure 1B As can be seen, when the source / drain region is implanted, it is implanted according to the definition of the P-type source / drain implantation layer 104. After ion implantation, the region where the first active region 101 on both sides of the P-type source / drain implantation layer 104 and the gate conductive material layer 103 intersects will self-align to form the source / drain region.

[0013] like Figure 2 As shown, a hybrid substrate 107 is also included outside the shallow trench isolation 204 surrounding the first active region 101. The hybrid substrate 107 does not include the buried dielectric layer and is directly composed of the bulk substrate. The layout of the hybrid substrate 107 is shown in [reference needed]. Figure 1B As shown.

[0014] like Figure 2 As shown, an N-type well region 205 is formed in the bottom body substrate 201 of the FDSOIPMOS bottom region. The N-type well region 205 also extends into the region of the hybrid substrate 107 and is connected to the body substrate electrode B through a contact hole 108 on the top of the hybrid substrate 107. (Back) Figure 1B As shown, the N-type well region 205 is defined by the ion implantation layer 105. That is, when the N-type well region 205 is implanted, the implantation is performed according to the definition of the ion implantation layer 105. After ion implantation, the N-type well region 205 will be formed in the area where the ion implantation layer 106, the bulk substrate 201, and the hybrid substrate 107 intersect.

[0015] like Figure 2 As shown, an N-type doped region 208 is also formed in the surface region of the hybrid substrate 107. The N-type doped region 208 is heavily doped to reduce the contact resistance between the substrate and the top contact hole 108. Figure 1B As shown, the ion implantation region of the N-type doped region 208 is defined by the ion implantation layer 106. That is, when the N-type doped region 208 is implanted, the implantation is performed according to the definition of the ion implantation layer 106. After ion implantation, the N-type doped region 208 will be formed by self-alignment in the area where the ion implantation layer 106 and the mixed substrate 107 intersect.

[0016] like Figure 2 As shown, metal silicides 209 are formed on the surface of each of the source / drain regions, the gate conductive material layer 103, and the N-type doped region 208.

[0017] like Figure 2 As shown, a first epitaxial layer is also formed on the surface of the SOI substrate 203 in the source / drain region formation area, and the top surfaces of the source / drain regions are higher than the top surface of the SOI substrate 203.

[0018] Depend on Figure 2 As shown, the substrate current is measured through the body substrate electrode B. However, the body substrate electrode B is only connected to the body substrate 201. Since the buried dielectric layer 202 isolates the SOI substrate 203 from the bottom body substrate 201, the current of the SOI substrate 203 cannot be measured through the body substrate electrode B. The current of the SOI substrate 203 is the substrate current of the FDSOIPMOS. Summary of the Invention

[0019] The technical problem to be solved by the present invention is to provide an SOI substrate current testing structure that can test the SOI substrate current of MOS transistors.

[0020] To solve the above-mentioned technical problems, the SOI substrate current testing structure provided by the present invention includes: a MOS transistor of a first conductivity type, the MOS transistor being formed on a first active region formed by the SOI substrate; the SOI substrate is composed of a body substrate located above the top surface of a buried dielectric layer, the buried dielectric layer being formed in the body substrate, and the body substrate below the bottom surface of the buried dielectric layer being a bottom body substrate.

[0021] The MOS transistor includes a first gate structure, which is formed on the top surface of the SOI substrate and is strip-shaped, with the strip of the first gate structure extending in a first direction.

[0022] The first active region is divided into a device body region and a device extension region arranged adjacent to each other in a first direction; the first gate structure extends from the device body region into the device extension region, and the top of the first gate structure is connected to a gate composed of a front metal layer.

[0023] In the device body region on both sides of the first gate structure, a heavily doped source / drain region of the first conductivity type is formed by self-alignment, and one of the two source / drain regions is connected to the source and the other is connected to the drain.

[0024] In the device extension regions on both sides of the first gate structure, heavily doped SOI substrate lead-out regions of the second conductivity type are formed by self-alignment, and both SOI substrate lead-out regions are connected to the SOI substrate electrode.

[0025] A further improvement is that the first gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.

[0026] A further improvement is that the gate conductive material layer comprises a polysilicon gate.

[0027] A further improvement is that a shallow trench isolation is formed on the periphery of the first active region, the shallow trench isolation passing through the SOI substrate, the dielectric buried layer and entering the bottom body substrate.

[0028] A further improvement is that the shallow trench isolation surrounding the first active region also includes a hybrid substrate, which does not include the dielectric buried layer and is directly composed of the bulk substrate.

[0029] A further improvement is that a second conductivity type well region is formed in the bottom body substrate in the bottom region of the MOS transistor.

[0030] A further improvement is that, in the first direction, there is a gap between the source / drain region and the adjacent SOI substrate lead-out region.

[0031] A further improvement is that metal silicides are formed on the surface of each of the source / drain regions and the surface of the SOI substrate lead-out region.

[0032] A metal silicide barrier layer is formed on the surface of the first active region between the source / drain region and the SOI substrate lead-out region.

[0033] A further improvement is that a first epitaxial layer is formed on the surface of the SOI substrate in the formation regions of the source / drain region and the SOI substrate lead-out region, and the top surface of the source / drain region and the top surface of the SOI substrate lead-out region are both higher than the top surface of the SOI substrate.

[0034] A further improvement is that, on the layout, the first conductivity type source / drain injection layer of the source / drain region extends to the outside of the device body region.

[0035] The second conductivity type source / drain injection layer of the SOI substrate lead-out region extends to the outside of the device extension region.

[0036] In the first direction, there is a gap between the first conductivity type source / drain injection layer and the second conductivity type source / drain injection layer to ensure that there is a gap between the source / drain region and the adjacent SOI substrate lead-out region; or, on the layout, a second conductivity type source / drain blocking layer is further provided on the periphery of the device extension region to prevent the growth of the first epitaxial layer, so as to ensure that there is a gap between the source / drain region and the adjacent SOI substrate lead-out region.

[0037] A further improvement is that the material of the buried medium includes an oxide layer.

[0038] A further improvement is that the material of the bulk substrate includes silicon.

[0039] A further improvement is that the material of the gate dielectric layer includes an oxide layer.

[0040] A further improvement is that, in the first active region, an SOI well region doped with a second conductivity type is formed over the entire thickness of the SOI substrate.

[0041] A further improvement is that the MOS transistor is an NMOS, with the first conductivity type being N-type and the second conductivity type being P-type; or, the MOS transistor is a PMOS, with the first conductivity type being P-type and the second conductivity type being N-type.

[0042] This invention extends both the first active region and the first gate structure of the MOS transistor from the device body region into the device extension region. Simultaneously, a heavily doped SOI substrate lead-out region of the second conductivity type (opposite to the first conductivity type) is formed in the device extension region, and this SOI substrate lead-out region is connected to the SOI substrate electrode. This allows for SOI substrate lead-out via the SOI substrate electrode, overcoming the defect in existing MOS transistors where the SOI substrate is blocked by the buried dielectric layer. This invention enables the testing of the SOI substrate current of the MOS transistor, thereby accurately determining the worst-case gate stress bias voltage in HCI reliability testing and precisely obtaining the device lifetime under worst-case test conditions. Furthermore, monitoring the SOI substrate current can detect process deviations, optimize the process flow, and improve device performance. Attached Figure Description

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0044] Figure 1A This is the existing layout of FDSOIPMOS;

[0045] Figure 1B Is Figure 1A The layout was expanded with the addition of contact holes and metal layers.

[0046] Figure 2 yes Figure 1A A cross-sectional view of an existing FDSOIPMOS structure;

[0047] Figure 3A This is a layout of the SOI substrate current testing structure according to an embodiment of the present invention;

[0048] Figure 3B Is Figure 3A The layout was expanded with the addition of contact holes and metal layers.

[0049] Figure 4A yes Figure 3A A cross-sectional view of the device in the main body area;

[0050] Figure 4B yes Figure 3B A cross-sectional view of the device in the device extension region;

[0051] Figure 5 yes Figure 3A A schematic diagram of the structure after the device and test pad are connected. Detailed Implementation

[0052] like Figure 3A The diagram shown is a layout of the SOI substrate current testing structure according to an embodiment of the present invention. Figure 3B Is Figure 3A The layout of the additional contact hole 311 and metal layer was added to the existing layout. Figure 4A yes Figure 3A The cross-sectional view of the device in the main body region is a cross-sectional view along a direction perpendicular to the first direction; Figure 4B yes Figure 3B A cross-sectional view of the device in the device extension region; the SOI substrate current testing structure of this embodiment includes:

[0053] A first conductivity type MOS transistor is formed on a first active region 301 formed from an SOI substrate 403. The first active region 301 is referenced. Figure 3A As shown, the SOI substrate 403 is referred to Figure 4A As shown. The SOI substrate 403 is formed on the top surface of the buried dielectric layer 402. The SOI substrate 403 consists of a body substrate located above the top surface of the buried dielectric layer 402. The buried dielectric layer 402 is formed within the body substrate. The body substrate below the bottom surface of the buried dielectric layer 402 is a bottom body substrate 401. Figure 4A As shown, a shallow trench isolation 404 is formed on the periphery of the first active region 301. The shallow trench isolation 404 passes through the SOI substrate 403, the dielectric buried layer 402 and enters the bottom body substrate 401.

[0054] In this embodiment of the invention, the material of the buried dielectric layer 402 includes an oxide layer. The material of the bulk substrate includes silicon.

[0055] In the first active region 301, an SOI well region doped with a second conductivity type is formed throughout the entire thickness of the SOI substrate 403.

[0056] The MOS transistor includes a first gate structure, which is formed on the top surface of the SOI substrate 403 and is strip-shaped, with the strip of the first gate structure extending in a first direction. Figure 3B In this context, L1 represents the length of the first gate structure, i.e., the dimension in the first direction, and W represents the width of the first gate structure.

[0057] The first active region 301 is divided into a device body region and a device extension region arranged adjacent to each other in a first direction; the first gate structure extends from the device body region into the device extension region, and the top of the first gate structure is connected to the gate G composed of the front metal layer.

[0058] In embodiments of the present invention, such as Figure 4A As shown, the first gate structure includes a gate dielectric layer 406 and a gate conductive material layer 303 stacked sequentially. The gate conductive material layer 303 includes a polysilicon gate. The gate dielectric layer 406 is made of an oxide layer. (Back) Figure 3B As shown, the gate conductive material layer 303 extends to the outside of the first active region 301 and forms a contact hole 311 on top. The top of the contact hole 311 is connected to the first front metal layer 312 (M1) and finally connected to the gate G.

[0059] like Figure 4A As shown, heavily doped source / drain regions of the first conductivity type are self-aligned and formed in the device body region on both sides of the first gate structure. One of the two source / drain regions serves as source region 407a connected to the source S, and the other serves as drain region 407b connected to the drain D. (Back) Figure 3B As shown, a contact hole 311 is formed on the top of the source region 407a, connecting to the first front-side metal layer 312 and finally to the source electrode S. A contact hole 311 is formed on the top of the drain region 407b, connecting to the first front-side metal layer 312 and finally to the drain electrode D. On the layout, the first conductivity type source / drain injection layer 304 of the source / drain regions extends to the outside of the device body region, by… Figure 3B It can be seen that when the source / drain region is implanted, it is implanted according to the definition of the first conductivity type source / drain implantation layer 304. After ion implantation, the source / drain region is formed by self-alignment in the area where the first active region 301 on both sides of the first conductivity type source / drain implantation layer 304 and the gate conductive material layer 303 intersect.

[0060] like Figure 4BAs shown, heavily doped SOI substrate lead-out regions 410 of a second conductivity type are self-aligned and formed in the device extension regions on both sides of the first gate structure. Both SOI substrate lead-out regions 410 are connected to the SOI substrate electrode B1. On the layout, the second conductivity type source / drain implantation layer 307 of the SOI substrate lead-out regions 410 extends to the outside of the device extension regions, by… Figure 3B It can be seen that when the SOI substrate lead-out region 410 is implanted, it is implanted according to the definition of the second conductivity type source / drain implantation layer 307. After ion implantation, the area where the first active region 301 on both sides of the second conductivity type source / drain implantation layer 307 and the gate conductive material layer 303 intersects will self-align to form the SOI substrate lead-out region 410.

[0061] In embodiments of the present invention, such as Figure 4A As shown, a hybrid substrate 309 is also included outside the shallow trench isolation 404 surrounding the first active region 301. This hybrid substrate does not include the buried dielectric layer 402 and is directly composed of the bulk substrate. The layout of the hybrid substrate 309 is shown in the attached diagram. Figure 3B As shown.

[0062] like Figure 4A As shown, a second conductivity type well region 405 is formed in the bottom body substrate 401 in the bottom region of the MOS transistor. (Back) Figure 3B As shown, the second conductivity type well region 405 is defined by the ion implantation layer 305. That is, when implanting the second conductivity type well region 405, the implantation is performed according to the definition of the ion implantation layer 305. After ion implantation, the second conductivity type well region 405 will be located in the area where the ion implantation layer 305 and the bottom body substrate 401 intersect.

[0063] Figure 4A The diagram also shows a doped region formed in the hybrid substrate 309 and connected to the body substrate electrode B via contact holes 311. However, the structure within the hybrid substrate 309 is independent of the SOI substrate current testing structure of this embodiment, meaning that structures related to the body substrate electrode B can be omitted.

[0064] like Figure 4A As shown, a second conductivity type doped region 408 is also formed in the surface region of the top region layer 302 of the hybrid substrate 309. The second conductivity type doped region 408 is heavily doped to reduce the contact resistance between itself and the top contact hole 311; Return to Figure 3BAs shown, the ion implantation region of the second conductivity type doped region 408 is defined by the ion implantation layer 306. That is, when implanting the second conductivity type doped region 408, the implantation is performed according to the definition of the ion implantation layer 306. After ion implantation, the second conductivity type doped region 408 will be formed by self-alignment in the area where the ion implantation layer 306 and the top region layer 302 of the mixed substrate 309 intersect.

[0065] like Figure 4A and Figure 4B As shown, metal silicide 409 is formed on the surface of each of the source / drain regions and the surface of the SOI substrate lead-out region 410. Metal silicide 409 is also formed on the surface of the gate conductive material layer 303 and the second conductivity type doped region 408.

[0066] like Figure 3B As shown, in the first direction, there is a gap between the source / drain region and the adjacent SOI substrate lead-out region 410.

[0067] A metal silicide barrier layer 308 is formed on the surface of the first active region 301 between the source / drain region and the SOI substrate lead-out region 410.

[0068] like Figure 4A and Figure 4B As shown, a first epitaxial layer is also formed on the surface of the SOI substrate 403 in the formation regions of the source / drain region and the SOI substrate lead-out region 410. The top surface of the source / drain region and the top surface of the SOI substrate lead-out region 410 are both higher than the top surface of the SOI substrate 403.

[0069] In embodiments of the present invention, such as Figure 3B As shown, on the layout, a second conductivity type source / drain blocking layer 310 is also provided on the periphery of the device extension region to prevent the growth of the first epitaxial layer. At the location where the second conductivity type source / drain blocking layer 310 is formed, the first epitaxial layer cannot grow; that is, the first epitaxial layer corresponding to the edge region of the SOI substrate lead-out region 410 cannot grow. Therefore, the source / drain region and the first epitaxial layer of the SOI substrate lead-out region 410 do not overlap, thereby ensuring a gap between the source / drain region and the adjacent SOI substrate lead-out region 410. In some embodiments, the first conductivity type source / drain injection layer 304 and the second conductivity type source / drain injection layer 307 can also be spaced in the first direction to ensure a gap between the source / drain region and the adjacent SOI substrate lead-out region 410.

[0070] like Figure 5 As shown, is Figure 3AThe diagram shows the structure of the device and test pads after connection. The MOS transistor also includes five test pads: the SOI substrate electrode B1 is connected to the first test pad 502a, the source S is connected to the second test pad 502b, the drain D is connected to the third test pad 502c, the body substrate electrode B is connected to the fourth test pad 502d, and the gate G is connected to the fifth test pad 502e. Figure 5 In the diagram, the layout corresponding to the dashed box 501 is... Figure 3B The abbreviation of the image. Figure 5 In the middle, the five test pads are labeled as pad1, pad2, pad3, pad4 and pad5 respectively.

[0071] In this embodiment of the invention, the MOS transistor is a PMOS, with a first conductivity type of P-type and a second conductivity type of N-type. In other embodiments, the MOS transistor can also be an NMOS, with a first conductivity type of N-type and a second conductivity type of P-type.

[0072] This invention extends the first active region 301 and the first gate structure corresponding to the MOS transistor simultaneously from the device body region into the device extension region. Simultaneously, a heavily doped SOI substrate lead-out region 410, representing the second conductivity type opposite to the first conductivity type of the MOS transistor, is formed in the device extension region. This SOI substrate lead-out region 410 is then connected to the SOI substrate electrode B1. This allows the SOI substrate 403 to be led out through the SOI substrate electrode B1, overcoming the defect in existing MOS transistors where the SOI substrate 403 is blocked by the buried dielectric layer 402 and thus cannot be led out. Therefore, this invention can test the SOI substrate 403 current of the MOS transistor, thereby accurately determining the worst-case gate G stress bias voltage in HCI reliability testing and precisely obtaining the device lifetime under worst-case test conditions. Furthermore, monitoring the SOI substrate current can detect process deviations, optimize the process flow, and improve device performance.

[0073] The embodiments of the present invention solve the problem that the Isub of the SOI well of dual-gate devices cannot be tested due to the presence of the BOX insulating layer. The Isub can monitor the degradation phenomenon of semiconductor devices under different stress conditions, thereby accurately evaluating the process reliability of the device; at the same time, it can monitor the leakage current characteristics of the device, which is particularly important for low power design.

[0074] like Figure 5As shown, during WAT testing of the substrate current, Vd = VDD is applied to pad 3, and voltage Vg is applied to pad 5. Vg is linearly scanned from 0V to VDD. The testing device is connected to pad 1, and the current Ib flowing from the SOI Well to the substrate can be measured. The maximum substrate current Ibmax can be calculated using Isub / W, where W is the width of the gate conductive material layer 303.

[0075] In HCI reliability testing, pad3 applies a fixed voltage Vd, and pad5 applies a voltage Vg. Vg is gradually increased to obtain the Ib-Vg curve. The Vg corresponding to Ibmax is then determined, and HCI testing can be performed.

[0076] In the transistor test structure containing a BOX implemented in this embodiment of the invention, the active region (AA) and the polysilicon (poly) gate are extended without violating design rules. The ion implantation layer (IMP layer) of the extended portion is the same as the bulk of the device itself. At the same time, a metal silicide barrier layer (SAB layer) is used to separate the bulk of the device from the extended portion to ensure that the width of the bulk of the test device remains unchanged.

[0077] A marking layer, namely a second conductivity type source / drain blocking layer 310, is added to the extended portion to prevent the formation of the epitaxial layer; or a certain space is set between the N-type source / drain injection (SDN), namely the second conductivity type source / drain injection layer 307, and the P-type source / drain injection (SDP) layer, namely the first conductivity type source / drain injection layer 304, to prevent the Bulk portion epitaxial layer from overlapping with the device body epitaxial layer.

[0078] The device implemented in this embodiment of the invention can directly measure the Ib of SOI Well.

[0079] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A current testing structure for an SOI substrate, characterized in that, include: A first conductivity type MOS transistor, the MOS transistor being formed on a first active region formed from an SOI substrate; The SOI substrate consists of a body substrate located above the top surface of the buried dielectric layer, the buried dielectric layer being formed in the body substrate, and the body substrate below the bottom surface of the buried dielectric layer being a bottom body substrate; The MOS transistor includes a first gate structure, which is formed on the top surface of the SOI substrate and is strip-shaped, with the extension direction of the strip of the first gate structure being a first direction. The first active region is divided into a device body region and a device extension region arranged adjacent to each other in a first direction; The first gate structure extends from the device body region into the device extension region, and the top of the first gate structure is connected to a gate composed of a front metal layer. In the device body region on both sides of the first gate structure, a source-drain region heavily doped with a first conductivity type is formed by self-alignment, and one of the two source-drain regions is connected to the source and the other is connected to the drain. In the device extension regions on both sides of the first gate structure, heavily doped SOI substrate lead-out regions of the second conductivity type are formed by self-alignment, and both SOI substrate lead-out regions are connected to the SOI substrate electrode.

2. The SOI substrate current testing structure as described in claim 1, characterized in that: The first gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.

3. The SOI substrate current testing structure as described in claim 2, characterized in that: The gate conductive material layer includes a polysilicon gate.

4. The SOI substrate current testing structure as described in claim 1, characterized in that: A shallow trench isolation is formed on the periphery of the first active region. The shallow trench isolation passes through the SOI substrate, the dielectric buried layer and enters the bottom body substrate.

5. The SOI substrate current testing structure as described in claim 4, characterized in that: The shallow trench isolation surrounding the first active region also includes a hybrid substrate, which does not include the dielectric buried layer and is directly composed of the bulk substrate.

6. The SOI substrate current testing structure as described in claim 5, characterized in that: A second conductivity type well region is formed in the bottom body substrate of the bottom region of the MOS transistor.

7. The SOI substrate current testing structure as described in claim 1, characterized in that: In the first direction, there is a gap between the source / drain region and the adjacent SOI substrate lead-out region.

8. The SOI substrate current testing structure as described in claim 7, characterized in that: Metal silicides are formed on the surface of each of the source / drain regions and the surface of the SOI substrate lead-out regions; A metal silicide barrier layer is formed on the surface of the first active region between the source / drain region and the SOI substrate lead-out region.

9. The SOI substrate current testing structure as described in claim 7, characterized in that: A first epitaxial layer is also formed on the surface of the SOI substrate in the formation regions of the source / drain region and the SOI substrate lead-out region. The top surface of the source / drain region and the top surface of the SOI substrate lead-out region are both higher than the top surface of the SOI substrate.

10. The SOI substrate current testing structure as described in claim 9, characterized in that: On the layout, the first conductivity type source / drain injection layer of the source / drain region extends to the outside of the device body region; The second conductivity type source / drain injection layer of the SOI substrate lead-out region extends to the outside of the device extension region; In the first direction, there is a gap between the first conductivity type source / drain injection layer and the second conductivity type source / drain injection layer to ensure that there is a gap between the source / drain region and the adjacent SOI substrate lead-out region; or, on the layout, a second conductivity type source / drain blocking layer is further provided on the periphery of the device extension region to prevent the growth of the first epitaxial layer, so as to ensure that there is a gap between the source / drain region and the adjacent SOI substrate lead-out region.

11. The SOI substrate current testing structure as described in claim 1, characterized in that: The material of the buried medium includes an oxide layer.

12. The SOI substrate current testing structure as described in claim 1, characterized in that: The substrate material includes silicon.

13. The SOI substrate current testing structure as described in claim 2, characterized in that: The material of the gate dielectric layer includes an oxide layer.

14. The SOI substrate current testing structure as described in claim 1, characterized in that: In the first active region, an SOI well region doped with a second conductivity type is formed over the entire thickness of the SOI substrate.

15. The SOI substrate current testing structure according to any one of claims 1 to 14, characterized in that: The MOS transistor is an NMOS, with the first conductivity type being N-type and the second conductivity type being P-type; or, the MOS transistor is a PMOS, with the first conductivity type being P-type and the second conductivity type being N-type.

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