Chip packaging method with high heat dissipation performance, chip structure, medium and equipment

Abstract

The invention relates to the field of chip packaging, in particular to a chip packaging method with high heat dissipation performance, a chip structure, a medium and equipment. Comprising the following steps: pasting and fixing a warping suppression component in a preset area on the surface of a substrate packaged with a target chip to form a first initial packaging body; the first initial packaging body is fixedly attached to a preset area of the target PCB through reflow soldering, and a second initial packaging body is formed; and de-bonding the bonding layer between the warping suppression component in the second initial packaging body and the target PCB so as to remove the warping suppression component and form a target chip packaging body. According to the present invention, after the adhesive layer is de-bonded, the warpage suppressing member can be removed. Therefore, the system-on-chip can be completely exposed, the radiator can be in direct contact with the system-on-chip, the thermal resistance on a heat dissipation path can be greatly reduced, and the heat dissipation efficiency of the chip can be greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip packaging, in particular to a chip packaging method with high heat dissipation performance, a chip structure, a medium and equipment. BACKGROUND

[0002] The Moore's Law limit, heterogeneous integration, 5G communication, artificial intelligence, high-performance computing and physical network promote the rapid development of chip packaging towards system-in-package and advanced packaging. Under the demand of high computing power, the process of the chip is getting lower and lower, and the power consumption of the chip is getting higher and higher, which brings problems of chip electrical performance, chip heat dissipation and packaging stress that need to be solved.

[0003] A qualified advanced packaging design scheme needs to find a reasonable balance and solution among chip layout, packaging structure design, substrate design, material selection and packaging process. High-density advanced packaging integration not only leads to the increasing influence of interconnection channels on electrical signal transmission, but also may cause local hot spots due to excessive chip power consumption, resulting in difficulty in chip heat dissipation. Finally, in the chip packaging process and the later assembly process, the coefficients of thermal expansion of various materials do not match, and when the external temperature changes (especially during reflow soldering), a large stress will be generated inside the package, causing the warping and delamination of the substrate, chip molding compound and other components, thereby causing the electrical performance and function of the system-in-package to fail.

[0004] In the prior art, the mainstream advanced packaging often adopts flip chip (FC), multi-chip module (MCM) or 2.5D CoWoS / EMIB technology, and a ring of hard stainless steel or copper material reinforcing ribs (Ring) or a heat dissipation cover (Lid) is arranged around the substrate to control the warping of the chip during reflow soldering, assembly and use. At the same time, the use of Ring is more conducive to chip heat dissipation, and the use of Lid is more conducive to warping suppression and mechanical protection.

[0005] However, since there are some core chips in the system-on-chip, the power of which is much higher than that of other cores in the later use process, and the heat generated in the corresponding area is also more, and the heat flux density is also higher. The heat dissipation efficiency of the heat dissipation system in the existing packaging structure is insufficient to meet the heat dissipation demand in this case, and thus the existing heat dissipation becomes a bottleneck for the performance of the system-on-chip. SUMMARY

[0006] To solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0007] According to one aspect of the present application, a chip packaging method with high heat dissipation performance is provided, the method comprising the following steps:

[0008] The warping suppression component is fixed and pasted on a preset area of a substrate surface where the target chip is packaged, to form a first initial package;

[0009] The first initial package is fixed and pasted on a preset area of a target PCB board by reflow soldering, to form a second initial package;

[0010] The bonding layer between the warping suppression component and the target PCB board in the second initial package is debonded to remove the warping suppression component, to form a target chip package.

[0011] Further, after the target chip package is formed, the method further comprises:

[0012] TIM material is coated on the target chip in the target chip package;

[0013] A heat dissipation component is arranged against the surface of the target chip, and the TIM material is arranged between the heat dissipation component and the target chip.

[0014] Further, the warping suppression component comprises a warping suppression cover or a warping suppression ring.

[0015] Further, the glue used to form the bonding layer is 3M EW3011 series glue;

[0016] The debonding of the bonding layer between the warping suppression component and the target PCB board in the second initial package comprises:

[0017] The bonding layer is heated to a preset debonding temperature by electrical heating, and then debonded.

[0018] Further, the glue used to form the bonding layer is 3M EW3011 series glue;

[0019] The debonding of the bonding layer between the warping suppression component and the target PCB board in the second initial package comprises:

[0020] The bonding layer is heated to a preset debonding temperature by blowing hot air flow to the bonding layer area, and then debonded.

[0021] Further, the bonding layer is heated by a heating circuit, and the heating circuit comprises an IC555 chip, a thermistor, a first voltage division detection circuit, a second voltage division detection circuit, and a heating module;

[0022] The first voltage division detection circuit and the second voltage division detection circuit are arranged in parallel to form a parallel detection circuit;

[0023] The thermistor is arranged in series with the parallel detection circuit; and the thermistor and the heating module are arranged on the warping suppression component;

[0024] The first voltage division detection circuit comprises a first fixed resistor, a first voltage division slide rheostat and a first resistance matching slide rheostat which are sequentially and serially arranged from a high voltage end to a low voltage end; a trigger input end of the IC555 chip is arranged in parallel with an output end of the first voltage division slide rheostat;

[0025] The second voltage division detection circuit comprises a second voltage division slide rheostat, a second fixed resistor and a second resistance matching slide rheostat which are sequentially and serially arranged from a high voltage end to a low voltage end; a threshold input end of the IC555 chip is arranged in parallel with an output end of the second voltage division slide rheostat; the resistance value of the second voltage division slide rheostat is less than the sum of the resistance values of the first fixed resistor and the first voltage division slide rheostat;

[0026] An output end of the IC555 chip is connected with the heating module for controlling the on-off of the heating module; a control voltage input end of the IC555 chip is connected to the ground through a bypass capacitor.

[0027] Further,

[0028] The first voltage division detection circuit further comprises a first voltage stabilizing capacitor which is arranged in parallel with the first resistance matching slide rheostat;

[0029] The second voltage division detection circuit further comprises a second voltage stabilizing capacitor which is arranged in parallel with the second fixed resistor and the second resistance matching slide rheostat.

[0030] As a second aspect of the present application, a chip structure with high heat dissipation performance is also provided, comprising: a target chip package, a TIM material layer and a heat sink;

[0031] The target chip package is prepared according to the above chip packaging method with high heat dissipation performance;

[0032] The heat sink is connected to the target PCB through spring screws; the base of the heat sink is arranged on the surface of the target chip;

[0033] The TIM material layer is arranged between the heat sink and the target chip.

[0034] According to a third aspect of the present application, a non-transitory computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the above chip packaging method with high heat dissipation performance.

[0035] According to a fourth aspect of the present application, an electronic device is provided, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the above chip packaging method with high heat dissipation performance when executing the computer program.

[0036] The present application has at least the following beneficial effects:

[0037] The packaging method in the present application fixes the warpage suppression member (i.e. the ring or the heat dissipation lid) on the corresponding position of the substrate by means of gluing before reflow soldering in the whole packaging process of the chip. Thus, when reflow soldering is performed, although the temperature change range is extremely large, the warpage of the chip substrate in the reflow soldering process can be effectively controlled and the adverse effects caused by the stress concentration of the silicon wafer can be prevented under the mechanical strength suppression of the warpage suppression member, thereby ensuring the reliability of the chip packaging and the high yield of the chip.

[0038] In addition, after the chip is packaged on the PCB, the corresponding warpage will be greatly reduced because the temperature change range in the subsequent use process is no longer as large as that in the reflow soldering process. Instead, the demand for heat dissipation of the chip is greatly improved in this process. In the present application, the warpage suppression member can be removed after the adhesive layer is debonded. Thus, the system-level chip is completely exposed, the heat sink can directly contact the system-level chip, the thermal resistance on the heat dissipation path can be greatly reduced, and the heat dissipation efficiency of the chip can be greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 A flowchart of a chip packaging method with high heat dissipation performance provided by an embodiment of the present application;

[0041] Figure 2 The warpage deformation results of each substrate solder ball side in the reflow soldering (125-240°C) between the clamping of the ring or the lid on the substrate and the case without adding anything are shown in the figure. The horizontal axis represents the distance value of each detection point on the diagonal line of the substrate from the center point of the substrate; the vertical axis represents the warpage degree of the substrate at each detection point on the diagonal line; Case 1 represents an experimental example of the packaging body with a copper lid, and the thickness of the lid cover plate is 1.5 mm; Case 2 represents an experimental example of the packaging body with a copper ring, and the thickness of the ring is 1.8 mm; Case 3 represents an experimental example of the packaging body with a stainless steel ring, and the thickness of the ring is 1.8 mm; and Case 4 represents an experimental example of the packaging body without the ring or the lid, i.e. the packaging body in the present application;

[0042] Figure 3The warping deformation results of each substrate solder ball side in reflow soldering (125-30℃) between the clamping of Ring or Lid on the substrate and the case of nothing added are provided for the embodiment of the present application, wherein the horizontal axis represents the distance value of each detection point on the diagonal line of the substrate from the center point of the substrate, and the vertical axis represents the warping degree of the substrate at each detection point on the diagonal line.

[0043] Figure 4 A circuit structure schematic diagram of a heating circuit is provided for the embodiment of the present application.

[0044] Figure 5 A structure schematic diagram of a chip structure with high heat dissipation performance is provided for the embodiment of the present application.

[0045] Figure 6 A flow chart of a method for debonding of a chip package adhesive layer is provided for the embodiment of the present application.

[0046] Figure 7 Corresponding components of two heating circuits arranged in the warping suppression member are provided for the embodiment of the present application, and the setting positions in the square ring are shown. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0048] As a possible embodiment of the present application, as shown in Figure 1 a chip packaging method with high heat dissipation performance is provided, which comprises the following steps:

[0049] S100: paste and fix a warping suppression member on a preset area on the surface of a substrate in which a target chip is packaged to form a first initial package. Specifically, the warping suppression member comprises a warping suppression cover (Lid) or a warping suppression ring 1 (Ring). Generally, the warping suppression cover or the warping suppression ring 1 is made of high-strength metal, such as stainless steel or copper. In addition, the glue for forming the adhesive layer is 3M EW3011 series glue. Specifically, the thermal expansion coefficient of the 3M EW3011 series glue is 45 / 300*10^-6 / ℃ (Tg is 130℃), and the Young's modulus is 5200MPa.

[0050] S200: fix and paste the first initial package on a preset area of a target PCB 5 by reflow soldering to form a second initial package.

[0051] Because the coefficient of thermal expansion (CTE) of the organic substrate and the silicon middle layer, silicon wafer, HBM, molding, and other materials in the first initial package do not match, and the Young's modulus of various materials is different, it will cause the substrate to warp in different temperature ranges during the packaging process and the mounting process, and the substrate warping will cause the chip to fail or the reliability to be greatly reduced.

[0052] In this step, the Lid / Ring is pasted on the surface of the substrate to effectively reduce the warping deformation of the substrate. In the conventional packaging process, the Lid / Ring is pasted around the substrate by 3M EW3011 series glue, and the warping deformation of the substrate is suppressed by the rigidity of the Lid / Ring. Compared with the Ring, the Lid has a larger structural hardness, so the warping control effect is also stronger. The warping amplitude of the chip with the Lid / Ring pasted on it changes with temperature during the mounting of the Mother Board (i.e. the target PCB board 5), and the overall warping amplitude is smaller, which can meet the requirements of the JEDEC standard (established by the Joint Electron Device Engineering Council (Joint Electron Device Engineering Council) to develop, promote and maintain engineering standards for the semiconductor industry) (high-temperature warping limit-140um, room-temperature warping limit 230um).

[0053] Specifically, between the cases of clamping the Ring or the Lid on the substrate and the case of not clamping anything, the warping deformation results of the substrates in the reflow soldering (30℃-240℃) are as shown in the simulation results in Figure 2 and Figure 3 The sizes of the various components in the chip package to which the simulation is directed are shown in Table 1:

[0054] Table 1

[0055]

[0056] According to the simulation results in Figure 2 and Figure 3 It can be known that the inhibition effect of the Ring / Lid on the warping of the substrate during the reflow soldering process is much better than that of the case without the Ring / Lid. Because of the high temperature generated during the reflow soldering process, the solder balls used for electrical connection will melt (the general temperature range corresponding to the melting of solder balls with different ingredients is 217℃-250℃), and in this state, because the solder balls become liquid and the hardness decreases, the warping of the substrate will easily cause the solder balls used to connect the substrate and the target PCB board 5 to be pulled or crushed, resulting in reliability problems of the chip package. The warping of the substrate can be effectively inhibited by the Ring / Lid at this stage.

[0057] S300: unbond the adhesive layer between the warpage suppression member in the second initial package and the target PCB 5 to remove the warpage suppression member, and form a target chip package.

[0058] In this embodiment, 3M EW3011 series glue is used to form the corresponding adhesive layer, which has a high Young's modulus, that is, has good anti-deformation ability, and can thus suppress the warpage deformation of the substrate. In addition, the glue can also be unbonded (i.e., lose adhesion) at a high temperature (usually at 150-160°C), and the Lid / Ring can be directly removed by a certain mechanical stress, thereby removing the Lid / Ring and the adhesive glue of the package, and leaving the substrate and the chip and other remaining components. In this embodiment, the high temperature at which the unbonding occurs can be provided in the following two ways.

[0059] Firstly:

[0060] S301: unbond the adhesive layer after the adhesive layer reaches the preset unbonding temperature by blowing hot air flow to the adhesive layer area.

[0061] Specifically, a hot air gun can be used to warm the corresponding area to reach the unbonding temperature. However, this method cannot accurately warm the area corresponding to the adhesive layer, and thus the high-temperature air flow will affect other components in the chip, such as resistors, capacitors, and system-on-chip. At the same time, this method has poor uniformity and consistency of the temperature of each area.

[0062] Secondly:

[0063] S302: unbond the adhesive layer after the adhesive layer reaches the preset unbonding temperature by electrically heating the adhesive layer.

[0064] Specifically, in this scheme, the heating module (electric heating wire or electric heating sheet 2) is built into the part where the Ring / Lid contacts the substrate, and the part where the Ring / Lid contacts the substrate is heated by the heating module, and then the heat is transferred to the adhesive layer, so that the adhesive layer is unbonded. This way can make the heat more uniformly and accurately applied to the adhesive layer area, without affecting other components.

[0065] In practical applications, the area where the warp suppression component contacts the substrate (i.e., the area where the adhesive layer is located) is typically a square annular region. Therefore, to correspond to this area, a corresponding square annular channel 11 is formed within the warp suppression component. This square annular channel 11 is used to install the heating module and the thermistor 3 for real-time temperature detection. Generally, to facilitate faster heat transfer to the adhesive layer, the square annular channel 11 needs to be positioned as close to the adhesive layer as possible. Simultaneously, the height of the square annular channel 11 needs to be greater than the height of the heating wire or heating element 2. This creates an air gap between the top of the heating wire or heating element 2 and the top of the square annular channel 11, preventing direct contact and thus slowing down the efficiency of heat transfer to the upward warp suppression component. Furthermore, the air gap causes the heat transfer medium to change during upward propagation, passing through air with lower heat transfer efficiency, further reducing the efficiency of heat transfer to the upward warp suppression component. Ultimately, by appropriately reducing the temperature of the metal above the warp suppression structure, the risk of burns to personnel can be appropriately reduced.

[0066] Specifically, such as Figure 4 As shown, the heating circuit includes: an IC555 chip, a thermistor 3 (RT in the figure), a first voltage divider detection circuit, a second voltage divider detection circuit, and a heating module.

[0067] The first and second voltage divider detection circuits are connected in parallel to form a parallel detection circuit. Thermistor 3 is connected in series with the parallel detection circuit. Thermistor 3 and the heating module are both mounted on the warp suppression component.

[0068] The first voltage divider detection circuit includes a first fixed resistor (R2 in the figure), a first voltage divider sliding rheostat (RP1 in the figure), and a first resistance-matching sliding rheostat (RP3 in the figure), which are connected in series from the high voltage end to the low voltage end. The trigger input terminal (pin 2 in the figure) of the IC555 chip is connected in parallel with the output terminal of the first voltage divider sliding rheostat.

[0069] The second voltage divider detection circuit includes a second voltage divider sliding rheostat (RP2 in the figure), a second fixed resistor (R3 in the figure), and a second resistance-matching sliding rheostat (RP4 in the figure), which are connected in series from the high-voltage end to the low-voltage end. The threshold input terminal (pin 6 in the figure) of the IC555 chip is connected in parallel with the output terminal of the second voltage divider sliding rheostat. The resistance of the second voltage divider sliding rheostat is less than the sum of the resistances of the first fixed resistor and the first voltage divider sliding rheostat.

[0070] In this embodiment, two slide rheostats and one fixed resistor are arranged on each voltage division detection circuit, and the detection points of the voltage are arranged on the corresponding slide rheostats. The circuit structure is arranged on one hand, the voltage division slide rheostat can be flexibly adjusted to adjust the voltage division ratio of each detection point, and on the other hand, the fixed resistor and the slide rheostat can be used to roughly determine the resistance level in the whole circuit, that is, each voltage division detection circuit has a larger resistance, thereby reducing the current of the circuit, so that the energy consumption of the whole control circuit is smaller, and the long-term control is facilitated.

[0071] IC555 chip, commonly known as 555 timer, is a very practical integrated circuit, mainly used for generating timing pulses and oscillation signals. It has 8 pins, each with specific functions. The following is the detailed function of each pin of IC555 chip:

[0072] Pin 1: GND (Ground)

[0073] Function: This is the ground pin of the chip, used to connect the ground of the circuit as a reference point.

[0074] Pin 2: TRIGGER (Trigger)

[0075] Function: When the voltage of this pin drops to about 1 / 3 VCC, the output OUT will switch to high level. In the Schmidt trigger configuration, it has a hysteresis voltage characteristic.

[0076] Pin 3: OUTPUT (Output)

[0077] Function: This is the output pin of the timer, which can output high or low level. According to the configuration of the circuit, it can generate pulse, square wave or constant high / low level.

[0078] Pin 4: RESET (Reset)

[0079] Function: When this pin is at low level, regardless of the state of other pins, the timer will be reset, and the output OUT will be forced to low level.

[0080] Pin 5: CONTROL VOLTAGE (Control Voltage)

[0081] Function: This pin can be used to adjust the reference voltage of the internal comparator, thereby changing the threshold and trigger level of the timer. When not in use, it is usually connected to ground through a small capacitor (such as 0.01 μF) to prevent noise interference.

[0082] Pin 6: THRESHOLD (Threshold)

[0083] Function: When the voltage on this pin rises to approximately 2 / 3 VCC, the output OUT will switch to a low level. It also features hysteresis voltage characteristics in a Schmitt trigger configuration.

[0084] Pin 7: DISCHARGE

[0085] Function: This pin connects to the collector of the internal discharge transistor and can be used to quickly discharge capacitors connected to this pin. In some configurations, such as monostable or astable oscillators, it is used to control the pulse width or oscillation period.

[0086] Pin 8: VCC (Positive Power Supply)

[0087] Function: This is the chip's power supply pin, which needs to be connected to a positive power supply voltage, typically 5V to 16V, and some models can reach 18V or higher.

[0088] As described above, the IC555 timer contains two comparators, associated with pin 2 (trigger) and pin 6 (threshold), respectively, used to determine the switching of the output state. By default, the voltage thresholds of pins 2 and 6 are set by the internal circuitry, but can be adjusted via external circuitry to suit different application requirements.

[0089] Specifically, in this embodiment, pin 2 of the IC555 chip is connected to the output terminal of the first voltage divider sliding rheostat in the first voltage divider detection circuit, used to obtain the voltage value at the output terminal of the first voltage divider sliding rheostat. Pin 6 of the IC555 chip is connected to the output terminal of the second voltage divider sliding rheostat in the second voltage divider detection circuit, used to obtain the voltage value at the output terminal of the second voltage divider sliding rheostat. Since the resistance of the thermistor 3 changes with temperature, the voltage supplied to the parallel detection circuit also changes. Furthermore, because pins 2 and 6 are at different voltage monitoring points in the two voltage divider detection circuits, their corresponding resistance values ​​are different, resulting in different voltage divisions. This leads to different voltage changes at pins 2 and 6, ultimately controlling the high and low levels output by pin 3. Therefore, based on the real-time temperature feedback from the thermistor 3, the on / off state of the heating module can be controlled to maintain the temperature within a constant range.

[0090] Specifically, the various resistance values, capacitance values, and threshold values ​​in the heating circuit can be set according to actual conditions. (The appendix of this invention...) Figure 4 The circuit described is only one possible implementation.

[0091] In addition, the first voltage division detection circuit further comprises a first voltage stabilizing capacitor (C3 in the figure) which is connected in parallel with the first adjustable resistor. The second voltage division detection circuit further comprises a second voltage stabilizing capacitor (C2 in the figure) which is connected in parallel with the second fixed resistor and the second adjustable resistor.

[0092] The output end (pin 3 in the figure) of the IC 555 chip is connected with the heating module for controlling the on-off of the heating module. The control voltage input end of the IC 555 chip is connected to the ground through a bypass capacitor (C4 in the figure).

[0093] Meanwhile, a voltage stabilizing circuit composed of a voltage stabilizing diode (VS in the figure) and a voltage stabilizing resistor (R1 in the figure) is connected in parallel at the power supply end. This configuration can also be used as a reference voltage source to provide a stable and accurate reference voltage for other parts of the circuit.

[0094] Through the above, the setting of the voltage stabilizing capacitor, the bypass capacitor and the voltage stabilizing circuit can ensure the accuracy of the electrical signal in the control circuit part of the entire heating circuit, so as to ensure the accuracy of the control of the heating module. Since the corresponding un-bonding temperature range in the embodiment is relatively small, approximately within the interval of 10℃, when the heating module needs to be heated, the temperature control can be more accurate.

[0095] S400: Apply a TIM material on a target chip in a target chip package.

[0096] S500: Place a heat dissipation component on the surface of the target chip, with the TIM material sandwiched between the heat dissipation component and the target chip.

[0097] For the chip package with the board attached and the Ring / Lid removed, a layer of TIM1.5 material (common high-performance TIMs include phase change thermal conductive material PCM, liquid metal TIM, graphite gasket, etc.) is directly applied on the chip silicon wafer before the heat sink 4 is installed. At this time, since the chip heat source and the system heat sink 4 are in direct contact through the TIM1.5, the multiple thermal resistances in the heat transfer chain are omitted. For common forced air cooling or liquid cooling systems (system heat dissipation scheme with low thermal resistance), the chip heat dissipation efficiency is greatly improved, thereby ensuring that the maximum junction temperature of the chip during operation is reduced, and thus the system-level chip can achieve higher computing performance.

[0098] Table 2 below shows the maximum junction temperature of the system-level chip when the chip package with or without Ring / Lid is used with the same heat sink 4 under a working condition of 260W chip power.

[0099] Table 2

[0100]

[0101]

[0102] From the heat dissipation simulation results of the chip package with or without Ring / Lid in Table 2, it can be seen that the chip package in the present embodiment (i.e. Project 4) has better heat dissipation effect on the chip in actual use.

[0103] As another possible embodiment of the present application, as shown in Figure 5 , a chip structure with high heat dissipation performance is also provided, which comprises a target chip package, a TIM material layer and a heat sink 4.

[0104] The target chip package is prepared according to the above-mentioned chip packaging method with high heat dissipation performance.

[0105] The heat sink 4 is connected to the target PCB 5 by spring screws 6. The base of the heat sink 4 is abutted against the surface of the target chip, and the TIM material layer is sandwiched between the heat sink 4 and the target chip. The spring screws 6 can be used to adjust the pressing force of the heat sink 4 on the system-level chip.

[0106] As another embodiment of the present application, as shown in Figure 6 , a method for debonding the adhesive layer of a chip package is also provided, which is applied to the above-mentioned target chip preparation method, and specifically used to control the debonding operation of the adhesive layer. In the present embodiment, since the Lid and Ring in the chip package are usually small, the metal heat conduction capability of the Lid and Ring is utilized to quickly transfer heat to the corresponding area of the entire adhesive layer, thereby achieving the debonding of the adhesive layer. In this way, the amount of heating sheet 2 or heating wire can be reduced.

[0107] Preferably, two heating circuits are arranged in a warping suppression member. Specifically, as shown in Figure 7 , the heating modules in the two heating circuits are arranged at two diagonal positions of the square ring channel 11; the heating module is a right-angle heating sheet 2, which is fixedly arranged on an inner side wall of the square ring channel 11 close to the adhesive layer. The thermistors 3 in the two heating circuits are arranged in two opposite edge groove channels of the square ring channel 11; and the thermistor 3 is located in the edge groove channel away from the corresponding heating module.

[0108] The method for debonding the adhesive layer comprises the following steps:

[0109] A100: respectively obtaining the time sequence of the temperature of the position of the thermistor 3 arranged in the two heating circuits reaching a plurality of preset temperature intervals after the two heating circuits start to work. Wherein, Ta and T b are the time length sequences corresponding to the two heating circuits respectively. a i and t b i are the time length sequences corresponding to the two heating circuits respectively. a and T b are the time length sequences corresponding to the two heating circuits respectively. a and T b are the time length sequences corresponding to the two heating circuits respectively. Each preset temperature interval is 10℃.

[0110] The real-time temperature can be obtained through the mapping relationship between the resistance value of the thermistor 3 and the temperature. The resistance value of the thermistor 3 can be calculated through the input values of the No. 2 pin and the No. 6 pin. Therefore, the warming-up process before reaching the minimum unbonding temperature (such as the process from room temperature to 140℃) can be divided into multiple sections with 10℃ as an interval, and then the time length sequence is formed.

[0111] A200: generates the thermal efficiencies P a and P b of the two heating modules respectively according to T a and T b . P a and P b respectively satisfy the following conditions:

[0112]

[0113] Where ΔTem is the temperature change amplitude of each preset temperature interval. d is a preset early ranking coefficient, n-d>1. d can be an integer of 3-5.

[0114] In A200, the average time consumption in the later temperature intervals in the time length sequence can be used to roughly determine the heating efficiency performance of different heating pieces 2 in the high temperature section. Therefore, the specific time length of the two heating circuits to heat to the preset unbonding temperature interval can be more accurately estimated by the obtained thermal efficiency. It is also convenient for subsequent A300 to determine the temperature control interval corresponding to each heating circuit according to the actual heating efficiency performance of the two heating circuits.

[0115] A300: generates the temperature control intervals corresponding to the two heating circuits according to T a , T b , P a and P b , where W a and W b are the maximum endpoint temperatures of the two temperature control intervals respectively, and W a and W b are the minimum endpoint temperatures of the two temperature control intervals respectively.All belong to the temperature range of the adhesive layer debonding [T min , T max ]. The minimum endpoint temperature of the two temperature control ranges is T min . W a and W b respectively satisfy the following conditions:

[0116] If , W a = Max(T max -(Δt×P b ), T min +k); W b =T max .

[0117] If , W b = Max(T max -(Δt×P a ), T min +k); W a =T max ;

[0118] Where, sum T a and sum T b are the total duration of T a and T b corresponding. T max n is the maximum temperature value in multiple preset temperature ranges. k is the minimum temperature change amplitude. Specifically, k = 2℃.

[0119] In this step, the size relationship between Δt and 0 can be used to determine which of the two heating circuits can reach the minimum bonding temperature T min faster. Specifically, Δt can represent the difference in time taken by the two heating circuits to reach T min . From this difference, the temperature control range of the two heating circuits can be determined. Specifically, a wider temperature control range can be set for the circuit with higher heating efficiency, while a narrower temperature control range can be set for the circuit with lower heating efficiency. As a result, during actual heating, the circuit with high heating efficiency can quickly heat to a higher temperature due to its wider temperature control range, and the time for temperature dissipation can be extended, thereby reducing the number of on-off times of the circuit when maintaining the temperature range, and thereby improving the service life of the high heating efficiency heating sheet 2. In addition, the high heating efficiency circuit can also use the extra time to reach a higher temperature. During this process, the low heating efficiency circuit can be waited for to reach its corresponding temperature control range, thereby ensuring the synchronization of the on-off of the two heating circuits.

[0120] A400: According to the temperature control interval corresponding to the two heating circuits, the on-off of the two corresponding heating modules is controlled.

[0121] Specifically, after A300, the method further includes:

[0122] A310: If T max -(Δt×P b )<T min +k, then T b the heating efficiency of the heating module in the corresponding heating circuit is reduced in the subsequent heating process.

[0123] A320: If T max -(Δt×P a )<T min +k, then T a the heating efficiency of the heating module in the corresponding heating circuit is reduced in the subsequent heating process.

[0124] Therefore, in the embodiment, the temperature interval for the entire debonding is only 10℃, and thus there is a problem that the range of the maximum temperature control temperature of the high-efficiency heating circuit is limited. Therefore, by using the steps in A310 and A320, it is determined that when the maximum temperature control temperature is increased and cannot be met, the heating efficiency of the heating module of the high-efficiency circuit can be appropriately reduced. In addition, the high-heating-efficiency circuit can be started later than the low-heating-efficiency circuit when the two circuits are used next time.

[0125] In addition, although the steps of the method in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0126] Through the above description of the embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a U disk, a mobile hard disk, etc.) or a network, and includes a plurality of instructions to make a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) execute the method according to the embodiments of the present disclosure.

[0127] In the example embodiments of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0128] Those skilled in the art can understand that each aspect of the present application can be implemented as a system, a method or a program product. Therefore, each aspect of the present application can be embodied in a form of entirely hardware, entirely software (including firmware, microcode, etc.), or a combination of hardware and software, which can be collectively referred to as "circuitry", "module" or "system".

[0129] The electronic device according to this embodiment of the present application. The electronic device is merely an example and should not bring any limitation to the function and use range of the embodiments of the present application.

[0130] The electronic device is in the form of a general computing device. The components of the electronic device can include, but are not limited to, the at least one processor described above, the at least one memory described above, and a bus connecting different system components, including the memory and the processor.

[0131] The memory stores program codes which can be executed by the processor, so that the processor executes the steps according to various exemplary embodiments of the present application described in the "Exemplary Method" section of the present specification.

[0132] The memory can include a readable medium in the form of a volatile memory, such as a random access memory (RAM) and / or a cache memory, and can further include a read-only memory (ROM).

[0133] The memory can further include programs / utilities with a set of (at least one) program modules, such as an operating system, one or more application programs, other program modules, and program data, each of which or some combination of which can include the implementation of a network environment.

[0134] The bus can be one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or a local bus using any of a variety of bus structures.

[0135] The electronic device can also communicate with one or more external devices such as a keyboard or a pointing device, a Bluetooth device, or a device for enabling

[0136] Those skilled in the art will readily understand that the example embodiments described herein can be implemented by software and / or by hardware combined with software essential for the software, with the foregoing embodiments being implemented by one or more computer components or modules. Accordingly, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium (e.g., a CD-ROM, a USB flash drive, a mobile hard disk, or the like) or on a network, and includes a number of instructions for causing one or more computing devices (e.g., a personal computer, a server, a terminal device, or a network device) to perform the methods described above according to the embodiments of the present disclosure.

[0137] In the example embodiments of the present disclosure, a computer-readable storage medium is also provided, which stores a program product capable of implementing the methods described above. In some possible embodiments, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program codes for causing a terminal device to perform the steps described in the “Example Method” section above according to various example embodiments of the present disclosure when the program product is run on the terminal device.

[0138] The program product can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium may, for example, be but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any combination thereof. More specific examples (a non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or a flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0139] Computer readable signal media can include a propagated data signal with instructions embodied in data signals. Such propagated signal can take a wide variety of forms, including but not limited to electro-magnetic signals, optical signals, and so forth. A computer readable medium of the present application can also be any medium that can be read by a computer. Such mediums can include, but are not limited to optical storage devices (e.g., CD-ROMs, optical disks, etc.), semi-conductor memory devices (e.g., RAM, ROM, etc.), and further can include any medium that can be used to store the desired information dynamically accessible by a computer.

[0140] The code can be transmitted in any form including radio frequency, optical, electrical, or the like, or any suitable combination thereof. A code can be implemented in any of a variety of programming languages including, for example, C++.

[0141] The program code may

[0142] Further, the above-described diagrams are only schematic and are non-limiting. It is expressly

[0143] It should be noted that, although the above detailed description refers to several modules or units of the device for action execution, such a division is not mandatory. Indeed, according to an embodiment of the present disclosure, the features and functionalities of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functionalities of one module or unit described above can be further divided into several modules or units embodied.

[0144] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip packaging method with high heat dissipation performance, characterized in that, The method includes the following steps: A warp suppression component is attached and fixed to a predetermined area on the surface of a substrate containing the target chip to form a first initial package. By reflow soldering, the first initial package is fixedly mounted on a preset area of ​​the target PCB board to form the second initial package; The adhesive layer between the warp suppression component and the target PCB board in the second initial package is debonded to remove the warp suppression component and form the target chip package.

2. The method according to claim 1, characterized in that, After forming the target chip package, the method further includes: TIM material is coated onto the target chip within the target chip package. A heat dissipation component is placed against the surface of the target chip, and TIM material is sandwiched between the heat dissipation component and the target chip.

3. The method according to claim 1, characterized in that, The warpage suppression component includes a warpage suppression cap or a warpage suppression ring.

4. The method according to claim 1, characterized in that, The adhesive used to form the bonding layer is 3M EW3011 series adhesive; Debonding the adhesive layer between the warp suppression component in the second initial package and the target PCB board includes: The adhesive layer is electrically heated to reach a preset debonding temperature before debonding.

5. The method according to claim 1, characterized in that, The adhesive used to form the bonding layer is 3M EW3011 series adhesive; Debonding the adhesive layer between the warp suppression component in the second initial package and the target PCB board includes: By blowing hot air into the adhesive layer area, the adhesive layer is debonded after reaching a preset debonding temperature.

6. The method according to claim 4, characterized in that, The adhesive layer is electrically heated by a heating circuit, which includes an IC555 chip, a thermistor, a first voltage divider detection circuit, a second voltage divider detection circuit, and a heating module. The first voltage divider detection circuit and the second voltage divider detection circuit are connected in parallel to form a parallel detection circuit; The thermistor is connected in series with the parallel detection circuit; both the thermistor and the heating module are mounted on the warp suppression component. The first voltage divider detection circuit includes a first fixed resistor, a first voltage divider sliding rheostat, and a first resistance-matching sliding rheostat, which are connected in series from the high voltage end to the low voltage end; the trigger input terminal of the IC555 chip is connected in parallel with the output terminal of the first voltage divider sliding rheostat. The second voltage divider detection circuit includes a second voltage divider sliding rheostat, a second fixed resistor, and a second resistance-matching sliding rheostat, which are connected in series from the high voltage end to the low voltage end; the threshold input terminal of the IC555 chip is connected in parallel with the output terminal of the second voltage divider sliding rheostat; the resistance value of the second voltage divider sliding rheostat is less than the sum of the resistance values ​​of the first fixed resistor and the first voltage divider sliding rheostat. The output terminal of the IC555 chip is connected to the heating module and is used to control the on / off state of the heating module; the control voltage input terminal of the IC555 chip is connected to ground through a bypass capacitor.

7. The method according to claim 6, characterized in that, The first voltage divider detection circuit also includes a first voltage stabilizing capacitor, which is connected in parallel with the first resistance-matching sliding rheostat; The second voltage divider detection circuit also includes a second voltage stabilizing capacitor, which is connected in parallel with the second fixed resistor and the second resistance sliding rheostat.

8. A chip structure with high heat dissipation performance, characterized in that, include: Target chip package, TIM material layer and heat sink; The target chip package is prepared according to a high heat dissipation chip packaging method according to any one of claims 1 to 7; The heat sink is fastened to the target PCB board by spring screws; the base of the heat sink abuts against the surface of the target chip. A TIM material layer is sandwiched between the heat sink and the target chip.

9. A non-transitory computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements a chip packaging method with high heat dissipation performance as described in any one of claims 1 to 7.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements a chip packaging method with high heat dissipation performance as described in any one of claims 1 to 7.

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