Electrostatic protection circuit, chip and equipment

Abstract

The invention discloses an electrostatic protection circuit, a chip and equipment, and belongs to the technical field of semiconductors. A detection module in the circuit outputs a first signal under the condition that electrostatic current exists in the positive electrode of a power supply of the electrostatic protection circuit; the driving module outputs a second signal to the discharging module based on the first signal, and the level value of the second signal is greater than that of the first signal; and the discharge module discharges the electrostatic current under the condition that the second signal meets the conduction condition, and the change rates of the discharged electrostatic current under different power supply voltages are different. Different change rates of the electrostatic current indicate that the discharge module discharges the electrostatic current matched with the power supply voltage, for example, the larger the power supply voltage is, the larger the electrostatic current is, more electrostatic current is released as much as possible, and the electrostatic protection performance is good.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular to an electrostatic protection circuit, a chip and a device. BACKGROUND

[0002] In the technical field of semiconductor technology, if static electricity occurs at the positive electrode of a power supply of an integrated circuit, the integrated circuit can be damaged, for example, elements in the integrated circuit can be short-circuited, open-circuited or burned. Therefore, an electrostatic protection circuit needs to be provided for the integrated circuit, and the electrostatic protection circuit is connected to the positive electrode of the power supply, which can be understood as the positive electrode of the power supply of the integrated circuit also serving as the positive electrode of the power supply of the electrostatic protection circuit. The electrostatic protection circuit can discharge static current in the case of static electricity occurring at the positive electrode of the power supply, so as to reduce damage of static electricity to the integrated circuit. SUMMARY

[0003] Embodiments of the present application provide an electrostatic protection circuit, a chip and a device, which can be used to discharge static current. The technical solutions are as follows: In a first aspect, an embodiment of the present application provides an electrostatic protection circuit, which includes a detection module, a driving module and a discharging module. The detection module is configured to output a first signal in the case of detecting that static current exists at the positive electrode of the power supply of the electrostatic protection circuit. The driving module is configured to output a second signal to the discharging module based on the first signal, and the level value of the second signal is greater than the level value of the first signal. The discharging module is configured to discharge the static current in the case that the second signal satisfies a conduction condition, and the change rate of the discharged static current is different under different supply voltages, the supply voltage refers to the voltage of the positive electrode of the power supply in the case of no static current, and the change rate refers to the change rate of the static current relative to the voltage of the positive electrode of the power supply.

[0004] In a possible implementation manner, the driving module includes a PMOS (P-metal-oxide-semiconductor, P-channel metal-oxide-semiconductor) and a first NMOS (N-metal-oxide-semiconductor, N-channel metal-oxide-semiconductor). An output end of the detection module is connected to the gate of the PMOS and the gate of the first NMOS. The source of the PMOS is connected to the positive electrode of the power supply, the drain of the PMOS is connected to the drain of the first NMOS, and the source of the first NMOS is connected to the negative electrode of the power supply. In a case where the first signal satisfies the turn-on condition of the PMOS and the turn-on condition of the first NMOS, the PMOS has a higher turn-on priority than the first NMOS, and the level of the second signal is the same as the voltage of the positive electrode of the power supply.

[0005] In a possible implementation, the driving module further includes a first resistor, the drain of the PMOS is connected to a first end of the first resistor, and the drain of the first NMOS is connected to a second end of the first resistor. The level of the second signal indicates the voltage at the first end of the first resistor.

[0006] In a possible implementation, the resistance of the first resistor is determined based on at least one of the turn-on resistance of the first NMOS or the discharge rate of the first NMOS, the discharge rate of the first NMOS indicating a rate at which the first NMOS, when turned on, pulls down the voltage at the first end of the first resistor to the negative electrode of the power supply.

[0007] In a possible implementation, the detection module includes a second resistor and a first capacitor. A first end of the second resistor is connected to the positive electrode of the power supply, a second end of the second resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the negative electrode of the power supply. The first signal is used to describe the voltage at the second end of the second resistor.

[0008] In a possible implementation, the first capacitor is a second NMOS, a gate of the second NMOS is connected to the second end of the second resistor, and a source and a drain of the second NMOS are connected to the negative electrode of the power supply.

[0009] In a possible implementation, the discharge module includes a third NMOS, a gate of the third NMOS is configured to receive the second signal, a drain of the third NMOS is connected to the positive electrode of the power supply, and a source of the third NMOS is connected to the negative electrode of the power supply. The discharge module is configured to discharge the electrostatic current to the negative electrode of the power supply based on the voltage of the positive electrode of the power supply at the current time.

[0010] In a possible implementation, the third NMOS has a channel width greater than that of the first NMOS in the driving module.

[0011] In a second aspect, a chip is provided, which is configured with the electrostatic protection circuit of the first aspect or any possible implementation of the first aspect.

[0012] In a third aspect, an electronic device is provided, which includes the chip provided in the second aspect.

[0013] The technical scheme provided in the application has at least the following beneficial effects: When static electricity occurs, the second signal can be used to turn on the discharge module in time to discharge the static current by the discharge module, so as to avoid the static damage caused by the overhigh voltage of the positive electrode of the power supply. The change rate of the static current discharged under different power supply voltages is different, which indicates that the discharge module will discharge the static current matched with the voltage of the positive electrode of the power supply after being turned on. Under different power supply voltages, the voltage of the positive electrode of the power supply is different, and the size of the static current to be discharged is also different, so the change rate of the static current is different. By rapidly discharging the static current matched with the voltage of the positive electrode of the power supply, more static current can be discharged in the case that static electricity occurs at the positive electrode of the power supply, and the static protection performance is good. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical scheme in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0015] Figure 1 is a structural schematic diagram of a static protection circuit provided by an embodiment of the present application; Figure 2 is a structural schematic diagram of a detection module provided by an embodiment of the present application; Figure 3 is a structural schematic diagram of a driving module provided by an embodiment of the present application; Figure 4 is a structural schematic diagram of another static protection circuit provided by an embodiment of the present application; Figure 5 is a statistical diagram of a released current provided by an embodiment of the present application; Figure 6 is a structural schematic diagram of a static protection chip provided by an embodiment of the present application; Figure 7 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0017] With the development of semiconductor technology, more and more application scenarios involve ICs (Integrated Circuit). Among them, the integrated circuit refers to a certain number of commonly used electronic components, such as resistors, capacitors, transistors, and the connections between these components, which are integrated together by semiconductor technology to form a circuit with a specific function. The chip configured with the integrated circuit can be used as a display control chip to control the display of the display device, such as a computer, a mobile phone, a television, a vehicle-mounted central control screen, and other smart devices with display panels.

[0018] However, the integrated circuit may be subject to static electricity. For example, if the integrated circuit is contacted by a human body, a machine, or other objects during production, assembly, transportation, or use, static electricity may be generated, which may flow into the integrated circuit through the interface or pin of the chip where the integrated circuit is located, thereby causing physical damage to the integrated circuit. Among them, the interface or pin of the chip is used to supply power to the integrated circuit, which can be understood as the positive electrode of the power supply of the integrated circuit. Therefore, a static protection circuit is needed to discharge the static current caused by static electricity in a timely manner to avoid damage to the circuit caused by excessive current of the integrated circuit.

[0019] Figure 1 A structural diagram of a static protection circuit provided by an embodiment of the present application is shown in FIG. 1. The static protection circuit includes a detection module 01, a driving module 02, and a discharge module 03. The output end of the detection module 01 is connected to the input end of the driving module 02, and the output end of the driving module 02 is connected to the input end of the discharge module 03. The detection module 01, the driving module 02, and the discharge module 03 are all connected to the positive electrode and the negative electrode of the power supply. The positive electrode of the power supply is, for example, the VDD (Voltage Drain Drain) end, and the negative electrode of the power supply can also be referred to as ground, for example, the VSS (Voltage Source and Sink) end.

[0020] It should be understood that the voltage of a certain point in the static protection circuit involved in the embodiments of the present application refers to the potential difference between the potential of the point and the low potential provided by the negative electrode of the power supply. Taking the positive electrode of the power supply as an example, the voltage of the positive electrode of the power supply refers to the potential difference between the high potential provided by the positive electrode of the power supply and the low potential provided by the negative electrode of the power supply. If the low potential provided by the negative electrode of the power supply is 0V, the voltage of the positive electrode of the power supply is equal to the potential value of the high potential provided by the positive electrode of the power supply.

[0021] In some cases, the positive power supply terminal is connected to the power pads of the IC chip. This can be understood as the positive power supply terminal also supplying power to the integrated circuit within the IC chip. If the integrated circuit experiences static electricity, it can cause an abnormal voltage rise at the positive power supply terminal. This abnormal rise can be, for example, a voltage increase exceeding a second threshold value within a fixed time period. Both the fixed time period and the second threshold value can be set based on experience.

[0022] The embodiments of this application do not limit the cause of electrostatic current appearing at the positive terminal of the power supply. It could be caused by static electricity in the connected integrated circuit, or it could be that the electrostatic protection circuit is not connected to the integrated circuit to be protected. That is, the electrostatic protection circuit is in the testing phase and will adjust the voltage at the positive terminal of the power supply to simulate the situation where the integrated circuit has electrostatic current.

[0023] Furthermore, the embodiments of this application do not limit the voltage at the positive terminal of the power supply when there is no electrostatic current. This voltage can be called the supply voltage of the positive terminal of the power supply, or it can be called the initial voltage. The supply voltage can be, for example, 0V, or it can be a non-0V. The following uses the electrostatic protection circuit in the testing phase as an example to explain why the supply voltage has different values.

[0024] Optionally, the electrostatic discharge protection circuit may be tested under different scenarios during the testing phase. Different test scenarios are used to simulate electrostatic discharge under different conditions. These different test scenarios include, but are not limited to, HBM (Human Body Model), CDM (Charged Device Model), MM (Machine Model), and system testing.

[0025] Among them, HBM is used to simulate static electricity caused by a charged human body touching an IC chip, CDM is used to simulate static electricity caused by friction within the IC chip itself, and MM is used to simulate static electricity that occurs when charged metal machinery (such as automatic placement machines or test probes) comes into contact with the IC chip. These three test scenarios are typically performed on a single IC chip, simulating static electricity scenarios that occur during the IC chip manufacturing process. During manufacturing, the IC chip is in a power-off state, therefore the supply voltage is 0V.

[0026] System testing, on the other hand, tests assembled complete products (such as mobile phones and laptops). This involves simulating a user discharging a sharp object like a key onto the device's interface or gaps, or simulating a user touching the screen. This falls under electrostatic discharge testing of IC chips in operational scenarios. During operation, IC chips are powered through the positive terminal of the power supply, meaning the supply voltage is not 0V. The specific value can be determined based on the actual operating voltage, including but not limited to 5V and 10V.

[0027] No matter what the supply voltage is, the detection module 01 can output a first signal when the voltage of the positive electrode of the power supply of the electrostatic protection circuit rises due to static electricity. Figure 2 A structural diagram of a detection module 01 provided by an embodiment of the present application is shown in FIG. 1. The detection module 01 includes a second resistor and a first capacitor, Figure 2 The first capacitor in FIG. 1 is an NMOS, which can be referred to as a second NMOS. VDD indicates the positive electrode of the power supply, and VSS indicates the negative electrode of the power supply. The detection module 01 can also be referred to as an RC clamp circuit in some cases.

[0028] The detection module 01 is an RC clamp formed by a resistor and a capacitor. The first end of the second resistor (indicated by the black circular mark in FIG. 1) is connected to the positive electrode of the power supply, and the second end of the second resistor (indicated by the white circular mark in FIG. 1) is connected to one end of the first capacitor. The other end of the first capacitor is connected to the negative electrode of the power supply. Figure 2 Figure 2 In FIG. 1, since the first capacitor is a second NMOS, the gate of the second NMOS is connected to the second end of the second resistor, and the source and drain of the second NMOS are connected to the negative electrode of the power supply. Figure 2

[0029] In FIG. 1, the oxide insulating layer between the gate and the substrate of the second NMOS can form a structure similar to a parallel-plate capacitor. When a voltage is applied to the gate, the change in the electric field between the oxide insulating layer and the substrate will cause charge accumulation, resulting in a parasitic capacitor. Exemplarily, the parallel-plate capacitor includes a MIM (Metal-Insulator-Metal Capacitor) capacitor and a MOM (Metal-Oxide-Metal Capacitor) capacitor. By using the second NMOS as a capacitor, the second NMOS can be implemented without any additional masks, compared to the MIM capacitor which requires a special insulating layer and additional mask costs. In addition, the MOM capacitor, which is composed of only metal layers, will occupy metal area and may interfere with wiring, while using the second NMOS as a capacitor only occupies one layer of metal for the connection of the drain, source and gate, which is more efficient in terms of area and cost.

[0030] In this connection, since the second end of the second resistor is connected as the output end of the detection module 01 and the input end of the driving module 02, the detection module 01 outputs a first signal to describe the voltage of the second end of the second resistor, for example, the level value of the first signal is the voltage of the second end of the second resistor. The voltage of the second end of the second resistor is different in the case of static electricity and the case of no static electricity, which will be described in the following examples.

[0031] Case 1: No static electricity.

[0032] ​​Case 1 is a normal working mode of the integrated circuit under normal power-on. The voltage of the positive power supply is slowly and smoothly rising to the supply voltage, for example, it takes several milliseconds to rise from 0V to 1.8V, that is, the voltage rise value in a fixed time period is not greater than the second threshold value. In case 1, due to the slow voltage rise speed of the positive power supply, the voltage rise speed is much greater than the RC time constant, the first capacitor can be slowly charged through the second resistor, and the capacitor voltage of the first capacitor is close to the voltage difference between the positive power supply and the negative power supply. Since the other end of the first capacitor is connected to the negative power supply, the voltage at the other end is 0V, the voltage at the second end is equivalent to the voltage of the positive power supply. The level value of the third signal output by the detection module 01 in case 1 is the voltage of the positive power supply at the current time.

[0033] Alternatively, the voltage of the positive power supply has completed the rise and is stable at the supply voltage, for example, it is stable at 1.8V, and under the working condition that the voltage of the positive power supply does not change with time, that is, under the direct current condition, the impedance of the first capacitor is theoretically infinite, which can be understood as that the first capacitor belongs to an insulator. Therefore, the voltage of the positive power supply will be directly transmitted to the output end of the detection module 01 through the second resistor, and the voltage at the output end is the supply voltage. The level value of the third signal output is the supply voltage, and the third signal is a high-level signal.

[0034] Case 2, static electricity occurs.

[0035] In case 2, the voltage of the positive power supply will be mutated due to static electricity, that is, static electricity rise will occur. The mutation is, for example, that a rapid change ESD (Electro Static Discharge, static electricity discharge) surge current flows into the positive power supply, the ESD surge current is, for example, a large current of 1~10A, and the voltage of the positive power supply will sharply rise from the supply voltage in about 2~10 microseconds.

[0036] The capacitor voltage of the first capacitor cannot be mutated in a short time, which can be understood as that the first capacitor does not have time to charge, and the voltage across the first capacitor remains at 0V. The first capacitor is equivalent to a very small impedance, and the second resistor is similar to a short circuit connected to the negative power supply. The above process can be understood as that when the first capacitor detects the alternating signal component, the impedance changes from infinity to a lower value as the frequency of the input alternating signal increases.

[0037] Since the second resistor and the first capacitor are both turned on, the voltage at the second end of the second resistor is the voltage division between the voltage of the positive power supply and the voltage of the negative power supply. In some cases, if the impedance of the first capacitor is lower than the impedance of the second resistor, for example, the impedance of the first capacitor is close to 0. Then the voltage at the second end of the second resistor is 0V, and the level value of the first signal is close to 0V, which is a stable low-level signal.

[0038] In summary, the detection module 01 outputs signals with different voltage levels in the static electricity case and the non-static electricity case, and the driving module 02 and the discharging module 03 have different responses based on the signals with different voltage levels. For example, in the case that the third signal belonging to a high-level signal is output by the detection module 01, the driving module 02 can output a fourth signal belonging to a low-level signal to the discharging module 03 based on the third signal, and the discharging module 03 is in a truncated state based on the fourth signal, so that the ESD circuit is not activated.

[0039] Referring to Figure 3 , the black circle indicates the output end of the detection module 01, VDD indicates the positive electrode of the power supply, VSS indicates the negative electrode of the power supply, the driving module 02 includes a PMOS and a first NMOS, the output end of the detection module 01 is connected to the gate of the PMOS and the gate of the first NMOS, the source of the PMOS is connected to the positive electrode of the power supply, the drain of the PMOS is connected to the drain of the first NMOS, and the drain of the first NMOS is connected to the negative electrode of the power supply. In some cases, the driving module 03 can be referred to as an inverter circuit or a CMOS inverter.

[0040] Figure 3 The PMOS and the first NMOS shown exist in a conduction condition, and the conduction condition is Vgs>Vth, wherein Vgs refers to the difference between the gate voltage and the source voltage, and Vth is a conduction threshold value which varies greatly based on the process of the MOS tube and is about 0.3V to 1V, and in some cases can be 0.7V.

[0041] The process of the driving module 02 outputting the fourth signal based on the third signal is, for example, as follows: since the voltage level of the third signal is VDD voltage, which belongs to a high-level signal, and the source of the PMOS is connected to VDD, the source voltage is VDD voltage, so that the Vgs of the PMOS is 0, the PMOS is OFF, and the source of the first NMOS is connected to VSS, the source voltage is VSS voltage, which can be regarded as 0V, the Vgs of the first NMOS is VDD voltage-VSS voltage, which is greater than Vth, the first NMOS is ON (conduction), the fourth signal net2 is pulled down to VSS voltage through the first NMOS, and the voltage level of the fourth signal is 0V.

[0042] In the static electricity case, the driving module 02 outputs a second signal to the discharging module based on the first signal, and the voltage level of the second signal is greater than that of the first signal. Figure 3In the shown drive module 02, if the PMOS is turned on, the first signal output by the detection module 01 is pulled up to the VDD voltage, and if the first NMOS is turned on, the first signal output by the detection module 01 is pulled down to the VSS voltage. In a possible implementation, the first signal may satisfy the turn-on condition of the PMOS and the turn-on condition of the first NMOS, and the turn-on priority of the PMOS is higher than that of the first NMOS (that is, the PMOS is turned on first), and the PMOS is turned on, and the level value of the second signal output by the drive module 02 is the same as the voltage of the positive power supply.

[0043] In the case that the first signal received by the gates of the PMOS and the first NMOS is a low-level signal, the PMOS and the first NMOS are both turned on because Vgs>Vth is satisfied. For example, the first signal is an intermediate value between the supply voltage and 0V, which causes the PMOS and the first NMOS to be turned on at the same time.

[0044] Since the source of the first NMOS is connected to the negative power supply, the source voltage is 0V, and the gate voltage is the first signal output by the detection module 01, Vgs=the level of the first signal-0V, that is, the level of the first signal. Taking the PMOS as an example, the source is connected to VDD, so the source voltage is VDD voltage, and the difference between the gate voltage and the source voltage is VDD voltage-the level of the first signal. Taking the VDD voltage rising from 4V to 6V in the presence of ESD discharge and the turn-on threshold of the first NMOS and the PMOS being 0.7V as an example, if the first signal is a low level of 0.8V, the Vgs of the first NMOS is 0.8V, which is greater than the turn-on threshold, and the Vgs of the PMOS is 5.2V, which is also greater than the turn-on threshold. Therefore, the PMOS and the first NMOS both satisfy the turn-on condition. This case can be referred to as a through current or punch-through current condition in some cases.

[0045] In this case, the second signal is determined based on the MOS tube with higher turn-on priority between the PMOS and the first NMOS. The turn-on priority of the MOS tube is positively correlated with the driving capability of the MOS tube, that is, the stronger the driving capability, the higher the turn-on priority. In some cases, the driving capability of the MOS tube is determined based on the turn-on resistance between the source and the drain of the MOS tube, and the greater the turn-on resistance, the weaker the driving capability. Therefore, the turn-on resistance of the first NMOS can be amplified to control the turn-on priority of the PMOS to be higher than that of the NMOS.

[0046] Referring to Figure 4 , the drive module 02 further includes a first resistor, the drain of the PMOS is connected to a first end of the first resistor, the drain of the first NMOS is connected to a second end of the first resistor, and the level value of the second signal indicates the voltage of the first end of the first resistor.

[0047] Since the level value of the second signal is the voltage of the first end of the first resistor, the first resistor changes the on-resistance of the first NMOS, and the on-resistance of the first NMOS is equivalent to the resistance in series of the first resistor and the resistance between the source and the drain of the NMOS, while the on-resistance of the PMOS is the resistance between the source and the drain of the PMOS. In this case, the on-resistance of the PMOS is smaller than the on-resistance of the first NMOS, the driving capability of the PMOS is stronger than the driving capability of the first NMOS, and the on-priority of the PMOS is higher than the on-priority of the first NMOS. Even if the first signal is an intermediate value satisfying the on-condition of the PMOS and the first NMOS, the PMOS will be turned on preferentially, and the level value of the second signal is pulled up to the VDD voltage by the PMOS.

[0048] The embodiments of the present application do not limit the first resistor, which can be any type of resistor. However, if the resistance of the first resistor is too small, it will not have much effect on suppressing the resistance of the first NMOS, and the resistance is too small, for example, much smaller than the on-resistance of the first NMOS. If the resistance of the first resistor is too large, it will affect the discharge rate of the first NMOS, causing the electrostatic protection circuit to be unable to turn off in time after completing the ESD discharge function, which may slow down the speed of the integrated circuit to resume normal operation.

[0049] Next, taking the resistance of 100MΩ as an example, the process of being unable to turn off in time is described. When the ESD discharge function is completed, the ESD surge on the VDD ends and the circuit returns to the normal DC state, the impedance of the first capacitor in the detection module 01 becomes infinite, and returns to the insulating state. In this case, Figure 4 The level value of the net1 signal shown becomes the VDD voltage connected through the second resistor, and the driving module 02 will invert the input net1 signal to the net2 signal, and the level value of the net2 signal is the VSS voltage.

[0050] Since the first NMOS is turned on, the first end of the first resistor and the VSS are short-circuited through the first NMOS, so the first end of the first resistor will be discharged to the VSS. However, if the resistance of the first resistor is too large, the large resistance of the first resistor will slow down the discharge rate, and thus the first end of the first resistor needs a certain time to be pulled down to the VSS voltage. The level value of the net2 signal needs a period of time to drop to the VSS voltage. The discharge module 03 will remain in the on-state if the level value of the net2 signal does not drop, thereby turning on the leakage current and causing side effects.

[0051] For example, before the net2 signal level reaches the VSS voltage, the Vgs of the third NMOS of the discharge module 03 remains above 0.7V. Therefore, the third NMOS remains in the conducting state and continues to discharge current to VSS until the net2 signal level drops completely to the VSS voltage, at which point the third NMOS and power supply clamping can finally be turned off.

[0052] Therefore, the resistance value of the first resistor can be determined based on at least one of the on-resistance of the first NMOS or the discharge rate of the first NMOS, to avoid setting the resistance value of the first resistor too high or too low. In some cases, the resistance value of the first resistor can be determined through simulation. For example, by simulating the circuit. Figure 4 The structure shown is used, and the resistance value of the first resistor is adjusted. Based on the simulation circuit, the level value of the net2 signal output by the drive module 02 is checked when an ESD surge flows into the positive terminal of the power supply. It is determined whether the level value of the net2 signal rises to close to the VDD voltage. If the level value of the net2 signal is close to the VDD voltage, it means that the level value of the net2 signal has reached the saturation point. Even if the resistance value of the first resistor is further increased, it will not change the trigger voltage and will not turn on the PMOS. The speed at which net2 is pulled up to the VDD voltage will affect the recovery after the ESD event. Therefore, this resistor value can be selected as the resistance value of the first resistor. Here, the trigger voltage refers to the voltage at which the PMOS turns on.

[0053] For example, for every 100 ohms increase in the value of the first resistor, the trigger voltage decreases by 1V. When the value of the first resistor reaches 500 ohms, the trigger voltage stops decreasing and enters the saturation region. The value of the first resistor can be set to 500 ohms.

[0054] In some cases, the range of values ​​for the first resistor can be determined through simulation, and then the resistance value can be selected from that range. For example, the simulation process involves statistically analyzing the release voltage under different resistance values, and then selecting the range based on the resistance values ​​corresponding to those release voltages. See Table 1 for the resistance values ​​corresponding to each release voltage.

[0055] Table 1

[0056] Among them, AVDD indicates the voltage of the positive terminal of the power supply at the current moment, based on the ESD surge rising to 7.6V, Rdrain refers to the resistance value of the first resistor, and Vt1 is the trigger voltage. According to Table 1, starting from about 40kΩ, the drop in release voltage is small and the decrease is not significant, while the release voltage will rebound from 20kΩ. Based on this, the value range of the first resistor is determined to be 30kΩ~40kΩ.

[0057] After the driving module 02 provides the second signal to the discharging module 03, the discharging module 03 can discharge the electrostatic current if the second signal meets the turn-on condition. It is continued to be seen from Figure 4 , Figure 4 The net2 signal in the figure corresponds to the second signal, and the discharging module 03 includes a third NMOS, the gate of the third NMOS is connected to the input end of the discharging module 03 and the output end of the driving module 02, for receiving the second signal, the drain of the third NMOS is connected to the positive electrode of the power supply, and the source of the third NMOS is connected to the negative electrode of the power supply. In this connection relationship, the discharging module 03 can discharge the electrostatic current to the negative electrode of the power supply.

[0058] Figure 4 The third NMOS of the discharging module 03 in the figure is a BIG NMOS, where BIG refers to that the physical size of the NMOS is large, for example, the channel width is designed to be particularly large. In some cases, the channel width of the third NMOS is larger than that of the first NMOS in the driving module 02. Moreover, the turn-on resistance of the BIG NMOS is low, and the large channel width is equivalent to providing multiple parallel current paths. Even if the current carrying capacity of a single path is limited, thousands of parallel paths can safely and evenly distribute the current of several amperes to the entire device structure, avoiding local overheating and melting, so the BIG NMOS can be used to discharge the electrostatic current.

[0059] Figure 4 The turn-on condition of the discharging module 03 in the figure is that the voltage difference between the gate and the source is greater than the threshold voltage. In the case that the source is connected to the negative electrode of the power supply, the voltage at the source is 0V, and the voltage difference between the gate and the source is the level value of the second signal received at the gate. It can be understood that the discharging module 03 meets the turn-on condition when the level value of the second signal is greater than the threshold voltage, and when the level value of the second signal is the voltage of the positive electrode of the power supply, the voltage of the positive electrode of the power supply is much greater than the threshold voltage due to the influence of the electrostatic current, that is, the discharging module 03 will be turned on based on the second signal after receiving the second signal. By turning on the discharging module 03, a low-impedance channel is established between the positive electrode of the power supply and the negative electrode of the power supply, so the positive electrode of the power supply can transmit the electrostatic current to the negative electrode of the power supply based on the channel.

[0060] Figure 5 A discharge statistical diagram of the electrostatic protection circuit provided by the embodiment of the present application is shown in the figure, Figure 5 The abscissa in the figure is the voltage between the source and the drain of the third NMOS, and the ordinate is the current from the source to the drain in the third NMOS. It can be known from Figure 5 that the higher the voltage, the more the current conducted.

[0061] Figure 5The discharge conditions corresponding to three power supply voltages are also shown in the figure, the three power supply voltages are 0V, 5V and 10V respectively, and the third NMOS starts to discharge the static current when the VDD voltage suddenly changes by about 1V. Since the principle of starting to discharge the static current under different power supply voltages is similar, next, take 0V as an example to explain the reason why the third NMOS starts to conduct and discharge from 1V.

[0062] If the VDD voltage suddenly changes from 0V to 1V, the second NMOS in the detection module 01 will change from an insulating state to a low-impedance state close to short circuit, so the level value of the net1 signal (the first signal) will not remain at the VDD voltage, but will change to the VSS voltage. When the level value of the net1 signal changes to the VSS voltage, the level value of the net2 signal output by the driving module 02 changes to the VDD voltage, and when the net2 signal is input to the third NMOS, the Vgs of the third NMOS changes to VDD voltage-VSS voltage, even if the VDD voltage is at the level of 1V, the channel will be opened and allow current to flow.

[0063] Figure 5 In the figure, the reason why the discharge does not start from 1V is that during the process of the VDD voltage rising from 0V, the detection module 01 cannot be activated immediately, and it takes some time for the level value of the net1 signal to drop to near the VSS voltage. Therefore, statistically speaking, if the VDD voltage rises from 0V to about 1V, the level value of the net1 signal will usually drop to near the VSS voltage during this interval, so that the PMOS in the driving module 02 is turned on, and the driving module 02 can output the net2 signal with a level value close to the VDD voltage based on the turned-on PMOS, and the third NMOS realizes conduction and discharge.

[0064] Figure 5 In the figure, the curve slope refers to the rate of change of the discharged static current relative to the voltage of the positive electrode of the power supply, which reflects the conduction capability of the third NMOS. The rate of change of the discharged static current under different power supply voltages is different because when the gate voltage of the BIG MOS changes rapidly, the conduction capability of the BIG NMOS is positively correlated with the gate voltage, and the gate voltage is the level value of the net2 signal, and the level value of the net2 signal is equivalent to the VDD voltage. Therefore, the higher the VDD voltage, the stronger the conduction capability of the BIG NMOS, and the greater the discharged static current.

[0065] When the VDD voltage starts to rise from 0V, based on the above analysis, the net1 signal will change from the VDD voltage to the VSS voltage, and the net2 signal will change from the VSS voltage to the VDD voltage, so that the third NMOS is turned on and starts to discharge the static current. Figure 5It can be seen that the BGI NMOS starts to conduct at about 1V, and the BIG NMOS discharges a current corresponding to 1V. If the VDD voltage starts to rise from 10V due to static electricity, the level of the second signal is close to 10V at the beginning, and the BIG NMOS tries to conduct a current corresponding to the VDD voltage after being turned on. The channel of the BIG NMOS is wide open and releases a large current, resulting in an initially steep slope, but eventually the slope converges to the slope under the condition of VDD=0V after a certain point.

[0066] In a possible implementation, when the static current flows into the VDD, the channel of the third NMOS discharges the static current to the VSS. During the discharging process, although the channel of the third NMOS can conduct a large amount of ESD current, this does not mean that the resistance of the third NMOS is zero, on the contrary, the third NMOS has some resistance. Therefore, the greater the current conducted by the third NMOS, the greater the voltage applied across the third NMOS, which will generate Figure 5 As shown, the voltage across the third NMOS increases with the increase of the current.

[0067] In some cases, after the ESD surge ends, the VDD voltage gradually returns to the normal level, the frequency component on the VDD disappears, all the voltages in the static protection circuit return to the direct current level, the impedance of the first capacitor at the detection module 01 returns to infinity, and the net1 signal output by the detection module 01 rises rapidly to the same level as the VDD voltage. When the net1 signal reaches the VDD voltage, the PMOS in the driving module 02 is turned off, the first NMOS is turned on, and the net2 signal is pulled down to the VSS voltage by the first NMOS. The Vgs of the third NMOS as the discharging module 03 is VSS-VSS, that is, 0V, and the third NMOS is turned off.

[0068] The static protection circuit provided by the embodiment of the present application can realize the rapid conduction of the discharging module 03 by setting the first resistor in the driving module 02. For example, when the first signal is an intermediate value that satisfies the conduction condition of the first NMOS and the PMOS, the PMOS will also be preferentially turned on, and the second signal output by the driving module 02 can conduct the discharging module 03. Compared with the driving module without the first resistor, the static protection capability is stronger.

[0069] Among them, the static protection capability refers to the amount of static current discharged, Figure 5 In the static protection circuit, once the VDD voltage rises to 12V, the static protection circuit will inevitably fail, for example, 12V is the damage threshold voltage of the detection module 01 in the static protection circuit, and if the VDD voltage exceeds 12V, the detection module 01 will be damaged. Therefore, before reaching 12V, the static protection circuit needs to discharge the static current as much as possible, andFigure 3 In the above-mentioned three cases, no matter 0V, 5V or 10V, the electrostatic current released by the electrostatic protection circuit is close to 2.25A, and the electrostatic current discharged is more, and the electrostatic protection capability is stronger.

[0070] If the driving module is a common CMOS inverter without the first resistor, the structure of the CMOS inverter is similar to Figure 6 , wherein the turn-on priority of the PMOS is not greater than the turn-on priority of the first NMOS, when the level value of the net1 signal is the middle level, the PMOS and the first NMOS both meet the turn-on condition, and the PMOS cannot be turned on in time, and the level value of the net2 signal cannot be quickly raised with the rise of the VDD voltage, but slowly changes.

[0071] In this case, the turn-on capability of the third NMOS is stable, the change rate of the electrostatic current discharged under different supply voltages is the same, and the electrostatic current that can be released is limited. For example, when the supply voltage is 0V, the electrostatic protection circuit can handle an electrostatic current of about 2.25A. However, when the supply voltage is 10V, the electrostatic protection circuit can only release an electrostatic current of 0.25V, and more current will cause a large voltage drop, and then the VDD voltage reaches 12V. Therefore, by controlling the turn-on priority of the PMOS to be higher than the turn-on priority of the first NMOS, more current can be discharged, and the electrostatic protection capability is strong.

[0072] In summary, the electrostatic protection circuit provided by the embodiment of the present application can turn on the discharging module 03 in time through the second signal when static electricity occurs, so as to release the electrostatic current by using the discharging module 03, and avoid the voltage value of the positive electrode of the power supply being too high to cause static damage. The change rate of the electrostatic current discharged under different supply voltages is different, which indicates that when the voltage of the positive electrode of the power supply starts to rise because of the appearance of the electrostatic current, the discharging module 03 will discharge the electrostatic current matching the voltage of the positive electrode of the power supply after being turned on, and the size of the electrostatic current tried to be discharged after being turned on under different supply voltages is different, and the change rate of the electrostatic current is different. By quickly releasing the electrostatic current matching the voltage of the positive electrode of the power supply, more electrostatic current is released, and the electrostatic protection performance is good. By setting the first resistor in the driving module 02, the resistance of the electrostatic protection circuit to static electricity can be improved, the circuit structure is simple, and the operation complexity is low.

[0073] The embodiment of the present application also provides a chip, which is shown in Figure 1 , and the chip is configured with Figure 3 or Figure 7 any one of the electrostatic protection circuits shown.

[0074] The embodiment of the present application also provides an electronic device, which is shown in Figure 6 , and the electronic device is configured with Figure 6The chip shown.

[0075] In some cases, the electronic device is also configured with an IC chip, ​ The chip shown and the IC chip are connected, for releasing static current in the case that the IC chip occurs static electricity.

[0076] Exemplarily, the electronic device can be any device, and can be any terminal. Optionally, the terminal can be any electronic product that can interact with a user through one or more of a keyboard, a touchpad, a touch screen, a remote controller, voice interaction, a handwriting device, etc., such as a PC (Personal Computer), a mobile phone, a smart phone, a PDA (Personal Digital Assistant), a wearable device, a PPC (Pocket PC), a tablet computer, a smart car, a smart television, etc. Optionally, the electronic device can also be a server, a switch, a router, etc.

[0077] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the first signal involved in the present application is obtained under full authorization.

[0078] It should be understood that "multiple" referred to in the present text refers to two or more. "And / or" describes the association between the associated objects, indicating that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0079] The above only describes exemplary embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. An electrostatic protection circuit, characterized by comprising: The circuit comprises a detection module, a driving module and a discharging module; The detection module is configured to output a first signal when detecting that the positive electrode of the power supply of the electrostatic protection circuit has electrostatic current. The driving module is configured to output a second signal to the discharging module based on the first signal, and the level value of the second signal is greater than the level value of the first signal. The discharging module is configured to discharge the electrostatic current when the second signal meets a conduction condition, and the change rate of the discharged electrostatic current is different under different power supply voltages, wherein the power supply voltage refers to the voltage of the positive electrode of the power supply in the absence of electrostatic current, and the change rate refers to the change rate of the electrostatic current relative to the voltage of the positive electrode of the power supply.

2. The circuit of claim 1, wherein, The driving module comprises a PMOS and a first NMOS. The output end of the detection module is connected to the gate of the PMOS and the gate of the first NMOS. The source of the PMOS is connected to the positive electrode of the power supply, the drain of the PMOS is connected to the drain of the first NMOS, and the source of the first NMOS is connected to the negative electrode of the power supply. When the first signal meets the conduction condition of the PMOS and the conduction condition of the first NMOS, the conduction priority of the PMOS is higher than that of the first NMOS, and the level value of the second signal is the same as the voltage of the positive electrode of the power supply.

3. The circuit of claim 2, wherein, The driving module further comprises a first resistor, and the drain of the PMOS is connected to the first end of the first resistor, and the drain of the first NMOS is connected to the second end of the first resistor. The level value of the second signal indicates the voltage at the first end of the first resistor.

4. The circuit of claim 3, wherein, The resistance value of the first resistor is determined based on at least one of the conduction resistance of the first NMOS or the discharge rate of the first NMOS, wherein the discharge rate of the first NMOS indicates the rate at which the first NMOS pulls down the voltage at the first end of the first resistor to the negative electrode of the power supply when it is turned on.

5. The circuit according to any of claims 1-4, characterized in that, The detection module comprises a second resistor and a first capacitor. The first end of the second resistor is connected to the positive electrode of the power supply, the second end of the second resistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the negative electrode of the power supply. The first signal is used to describe the voltage at the second end of the second resistor.

6. The circuit of claim 5, wherein, The first capacitor is a second NMOS, the gate of the second NMOS is connected to the second end of the second resistor, and the source and drain of the second NMOS are connected to the negative electrode of the power supply.

7. The circuit according to any of claims 1-4, characterized in that The discharging module comprises a third NMOS, the gate of the third NMOS is configured to receive the second signal, the drain of the third NMOS is connected to the positive electrode of the power supply, and the source of the third NMOS is connected to the negative electrode of the power supply. The discharging module is configured to discharge the electrostatic current to the negative electrode of the power supply based on the voltage of the positive electrode of the power supply at the current time.

8. The circuit of claim 7, wherein, The channel width of the third NMOS is greater than the channel width of the first NMOS in the driving module.

9. A chip, characterized by The chip is configured with the electrostatic protection circuit of any one of claims 1-8.

10. An electronic device, comprising: The electronic device comprises the chip of claim 9.

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