Semiconductor package and method of manufacturing the same

Abstract

The invention provides a semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes: a substrate; a semiconductor chip disposed on the substrate; a molding layer covering the semiconductor chip on the substrate, the molding layer including a main body portion and a mark pattern disposed on the main body portion; and a mark frame disposed on the main body portion, a portion of the mark frame being removed to form a mark region. The mark pattern includes a plurality of protrusions. The plurality of protrusions are spaced apart from each other in a horizontal direction when viewed in a cross-sectional view, and extend from the main body portion in a vertical direction beyond an upper surface of the mark frame to fill the mark region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more particularly to semiconductor packages and methods for manufacturing semiconductor packages. Background Technology

[0002] With the rapid development of the electronics industry and the growth of user demands, electronic devices are becoming increasingly miniaturized and multifunctional. As electronic devices become smaller and lighter, semiconductor packages are also becoming smaller and lighter. Furthermore, high performance, improved integration, and high reliability are expected in semiconductor packages.

[0003] Typically, it is desirable to form marking information on semiconductor packages to identify the product type and performance parameters of the semiconductor package. To improve the integration of semiconductor packages, it is desirable to achieve semiconductor packages that include small-sized marking information. However, conventional marking processes such as laser ablation are difficult to reduce the size of the marking information and can easily degrade the reliability of the semiconductor package. Summary of the Invention

[0004] To address the aforementioned technical problems, exemplary embodiments of this disclosure provide a semiconductor package and a method for manufacturing the semiconductor package, which can reduce the size of the semiconductor package.

[0005] Furthermore, exemplary embodiments of this disclosure also provide a semiconductor package and a method for manufacturing the semiconductor package, which can reduce or prevent warping of the semiconductor package.

[0006] Furthermore, exemplary embodiments of this disclosure also provide a semiconductor package and a method for manufacturing the semiconductor package, which may have electromagnetic interference (EMI) shielding capabilities.

[0007] However, the inventive concept is not limited thereto, and the exemplary embodiments of this disclosure may not solve the above-mentioned technical problems or achieve the above-mentioned advantages.

[0008] According to one aspect of an exemplary embodiment of the present disclosure, a semiconductor package is provided, the semiconductor package comprising: a substrate; a semiconductor chip disposed on the substrate; a molding layer covering the semiconductor chip on the substrate, the molding layer including a body portion and a marking pattern disposed on the body portion; and a marking frame disposed on the body portion, a portion of the marking frame being removed to form a marking area; wherein the marking pattern includes a plurality of protrusions, and wherein, when viewed in a cross-sectional view, the plurality of protrusions are horizontally spaced apart from each other and extend vertically from the body portion beyond the upper surface of the marking frame to fill the marking area.

[0009] The thickness of the marking frame in the vertical direction can be less than or equal to 10 μm.

[0010] The marking frame can include a metal material.

[0011] The marking frame can include copper.

[0012] The marking pattern can be a text or graphic that identifies the semiconductor package.

[0013] The plurality of protrusions can include a first protrusion and a second protrusion, and a height of the first protrusion can be different from a height of the second protrusion in a vertical direction.

[0014] The height of the first protrusion can be less than the height of the second protrusion, and a coefficient of thermal expansion of the semiconductor package at a location where the first protrusion is located can be less than a coefficient of thermal expansion of the semiconductor package at a location where the second protrusion is located.

[0015] The first protrusion can overlap the semiconductor chip when viewed in the vertical direction.

[0016] At least a portion of the second protrusion can not overlap the semiconductor chip when viewed in the vertical direction.

[0017] The at least a portion of the second protrusion can be located at an edge of the body portion when viewed in a cross-sectional view, and an outer side surface of the marking frame and an outer side surface of the body portion can be aligned in the vertical direction.

[0018] A remaining portion of the marking frame can be a text or graphic that identifies the semiconductor package.

[0019] Each of the plurality of protrusions can have a same height as each other.

[0020] The plurality of protrusions can include peripheral protrusions and internal protrusions. The peripheral protrusions can be located at an edge of the body portion in a horizontal direction when viewed in a cross-sectional view, and an outer side surface of the peripheral protrusions and an outer side surface of the body portion can be aligned in the vertical direction when viewed in the cross-sectional view. The internal protrusions can be arranged between the peripheral protrusions in the horizontal direction.

[0021] The peripheral protrusions can each have a first width in the horizontal direction, the internal protrusions can each have a second width in the horizontal direction, and the first width can be less than the second width.

[0022] A remaining portion of the marking frame can include a plurality of sub-portions spaced apart from each other in the horizontal direction when viewed in a cross-sectional view, and each of the plurality of sub-portions can have a third width in the horizontal direction, the third width can be less than the first width and less than the second width.

[0023] The plurality of protrusions can have a height in a vertical direction of 10 µm to 50 µm.

[0024] The marking pattern can have a flat upper surface.

[0025] The body portion and the marking pattern can be integrally formed via a molding process in a mold.

[0026] An upper surface of the marking frame and an upper surface of the marking pattern can be exposed after removal of a separation carrier, the separation carrier can be located below the marking frame when the marking region is formed and on a release film in the mold when the molding process is performed, a portion of the separation carrier is removed when the marking region is formed, and a shape of the marking pattern corresponds to a shape of the portion of the separation carrier that is removed when the marking region is formed.

[0027] A height of the marking pattern can correspond to a depth of the portion of the separation carrier that is removed when the marking region is formed.

[0028] According to another aspect of example embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor package, the method including: forming a preliminary marking structure, wherein the preliminary marking structure includes a separation carrier and a marking frame on the separation carrier; forming a recessed pattern on the preliminary marking structure to form a marking structure, the recessed pattern including a plurality of recessed portions spaced apart from each other in a horizontal direction when viewed in a cross-sectional view, wherein a lower surface of each of the plurality of recessed portions is located below an upper surface of the separation carrier, wherein a portion of the marking frame is removed to form a marking region; forming a base structure including a base and a semiconductor chip on the base; positioning the marking structure and the base structure to face each other within a mold during a molding process; performing the molding process on the marking structure and the base structure to form a molded layer including a body portion and a marking pattern disposed on the body portion, wherein the marking pattern includes a plurality of protrusions formed by filling the plurality of recessed portions, respectively; and removing the separation carrier to expose an upper surface of the marking frame and an upper surface of the marking pattern.

[0029] The step of forming the recessed pattern can include penetrating the marking frame in a vertical direction by performing an etching process until an upper portion of the separation carrier is removed.

[0030] The marking pattern can be a character identification or a graphic identification that identifies the semiconductor package.

[0031] The plurality of recessed portions can include first recessed portions and second recessed portions, and a depth of the first recessed portions can be different from a depth of the second recessed portions.

[0032] A depth of the first recesses can be less than a depth of the second recesses. The first recesses can be formed at a location of the semiconductor package having a first coefficient of thermal expansion, and the second recesses can be formed at a location of the semiconductor package having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion.

[0033] A remaining portion of the marking frame can be a textual or graphical identification that identifies the semiconductor package.

[0034] Each of the plurality of recesses can have a same depth as each other.

[0035] The plurality of recesses can include peripheral recesses and internal recesses. When viewed in a cross-sectional view, the peripheral recesses can be located at edges of the separation carrier in a horizontal direction, and an outer side surface of each of the peripheral recesses can be aligned with an outer side surface of the separation carrier in a vertical direction. The internal recesses can be arranged between the peripheral recesses in the horizontal direction.

[0036] The internal recesses can be formed to have a first width in the horizontal direction, and the peripheral recesses can be formed to have a second width in the horizontal direction, and the first width can be greater than the second width.

[0037] When viewed in a cross-sectional view, a remaining portion of the marking frame can include a plurality of sub-portions spaced apart from each other in a horizontal direction. Each of the plurality of sub-portions can have a third width in the horizontal direction, the third width can be less than the first width and less than the second width.

[0038] The forming of the molding layer can include placing the marking structure in the lower cavity of the mold with the marking frame facing upward, and placing the base structure in the upper cavity of the mold with the semiconductor chip facing downward; closing the mold and injecting the encapsulation material; and cooling and solidifying the encapsulation material to form the molding layer. After the mold is closed, an upper surface of the semiconductor chip can be spaced apart from an upper surface of the marking frame by a first distance in a vertical direction.

[0039] The separation carrier of the marking structure can be placed on a release film in the lower cavity of the mold. BRIEF DESCRIPTION OF DRAWINGS

[0040] Some example embodiments of the disclosure will be described in detail below with reference to the attached drawings. In the drawings, the same reference numerals will be used to indicate the same elements.

[0041] Figure 1 is a cross-sectional view illustrating a semiconductor package according to the related art.

[0042] Figure 2This is a plan view illustrating a semiconductor package according to an example embodiment of the present disclosure.

[0043] Figure 3 The illustration is based on an example embodiment of this disclosure. Figure 2 A cross-sectional view of the semiconductor package taken from line II.

[0044] Figure 4 This is a plan view illustrating a semiconductor package according to another exemplary embodiment of the present disclosure.

[0045] Figure 5 This is an illustration along another example embodiment of the present disclosure. Figure 4 A cross-sectional view of the semiconductor package taken from line II-II.

[0046] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an example embodiment of the present disclosure.

[0047] Figures 7 to 12 It shows the manufacturing process. Figure 2 and Figure 3 A cross-sectional view of a method for a semiconductor package according to an example embodiment.

[0048] Figures 13 to 16 It shows the manufacturing process. Figure 4 and Figure 5 A cross-sectional view of a method for a semiconductor package according to an example embodiment. Detailed Implementation

[0049] The semiconductor package according to this disclosure is described with reference to the accompanying drawings.

[0050] It will be understood that when the terms “comprises” and / or “comprising” or “includes” and / or “including” are used in this specification, they specify the presence of the stated features, regions, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0051] For ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "top", "bottom", and the like, can be used herein for the purpose of illustrating one element or feature's relationship to another element or feature, as depicted in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if a device is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0052] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. By the term "directly connected" or "directly coupled" it is meant that the element is connected or coupled to the other element without any intervening elements.

[0053] Figure 1 is a schematic diagram of a semiconductor package according to the related art.

[0054] Referring to Figure 1 The semiconductor package 1 can include a substrate A, a semiconductor chip B disposed on the substrate A, and a molding layer C encapsulating the semiconductor chip B.

[0055] The semiconductor chip B can be electrically connected to the substrate A via a bonding wire D. The substrate A can be a printed circuit board (PCB), but is not limited thereto. The semiconductor package B can further include an external connection terminal E disposed on a lower surface of the substrate A.

[0056] In a conventional semiconductor packaging process, a marking process can be performed after a molding process of forming the molding layer C. Specifically, the marking process can include forming a marking pattern by performing engraving on the molding layer C using a laser burning method. The marking pattern can include a character or a pattern representing information of a trademark, a model number, a performance parameter, etc. of the semiconductor package 1.

[0057] When a conventional marking process is used, the marking depth is relatively deep, for example, about 10 pm to about 50 pm, due to the use of a laser burning method, and the marking pattern is unstable, for example, there is a large burning penetration depth, rough edges, etc. When the thickness of the molding layer C is thin, the relatively deep marking pattern formed by the laser burning method can easily contact the bonding lead D in the molding layer C, which can cause the bonding lead D to be unable to be tightly encapsulated, exposed to the outside, and cause short circuit or corrosion. In addition, when the thickness of the molding layer C is thin, the marking pattern can easily extend downward along the vertical direction to form a crack, causing the reliability of the semiconductor package 1 to be reduced. Therefore, the overall thickness of the semiconductor package 1 must be ensured to be large enough, which cannot achieve thinness.

[0058] In addition, the coefficient of thermal expansion (CTE) mismatch between the epoxy resin (EMC) forming the molding layer C and the PCB forming the substrate A can cause warping of the semiconductor package 1, affecting the product yield and reliability of the semiconductor package.

[0059] Hereinafter, a semiconductor package according to example embodiments of the present disclosure will be described in detail with reference to different embodiments shown in the accompanying drawings.

[0060] Figure 2 is a plan view showing a semiconductor package 1000 according to example embodiments of the present disclosure. Figure 3 is a plan view showing Figure 2 a cross-sectional view of the semiconductor package 1000 of example embodiments of

[0061] Referring to Figure 2 and Figure 3 , the semiconductor package 1000 according to example embodiments of the present disclosure can include a substrate 110, a semiconductor chip 100, a molding layer 200, and a marking frame 300.

[0062] In some example embodiments, the substrate 110 can include a package substrate such as a printed circuit board (PCB), a ceramic substrate, an interposer, a redistribution layer, etc. In some embodiments, the substrate 110 can include a multi-layer PCB. The multi-layer PCB can be a multi-layer circuit board having a plurality of wiring layers and a plurality of vias therein.

[0063] In some example embodiments, the substrate 110 can have a first surface 110a and a second surface 110b opposite to each other. The first surface 110a of the substrate 110 can be an active surface on which the semiconductor chip 100 is disposed, and the second surface 110b can be an inactive surface (e.g., a non-active surface). In the following description, the first surface 110a of the substrate 110 can also be referred to as a front side of the substrate 110, and the second surface 110b of the substrate 110 can also be referred to as a back side of the substrate 110. For example, the active surface can be a surface on which active elements such as transistors are formed, and the non-active surface or inactive surface can be a surface on which active elements are not formed.

[0064] The semiconductor chip 100 can be disposed (e.g., stacked in a vertical direction D3) on the substrate 110 (e.g., the first surface 110a of the substrate 110). In some example embodiments, the vertical direction D3 can be a direction intersecting (e.g., perpendicular to) the first surface 110a of the substrate 110, and the first horizontal direction D1 and the second horizontal direction D2 can each be a direction parallel to the first surface 110a of the substrate 110. The first horizontal direction D1 and the second horizontal direction D2 can intersect (e.g., be perpendicular to) each other. The semiconductor chip 100 can be electrically connected to the substrate 110. In some example embodiments, the semiconductor chip 100 can be mounted on the substrate 110 by a die attaching method, a wire bonding method, or a flip chip bonding method, etc., but is not limited thereto.

[0065] In example embodiments, the semiconductor chip 100 can be an integrated circuit (IC) chip in which a plurality of ICs are formed on a wafer. The semiconductor chip 100 can also include, for example, a logic chip or a memory chip.

[0066] Although one semiconductor chip 100 is shown as being disposed on the substrate 110 in Figure 3 example embodiments, the number and structure of the semiconductor chip 100 disposed on the substrate 110 can be variously modified.

[0067] The molding layer 200 can be disposed on the substrate 110 to cover (e.g., encapsulate) the semiconductor chip 100. In some example embodiments, the molding layer 200 can surround and contact the side surface and the upper surface of the semiconductor chip 100. The upper surface of the molding layer 200 can be located at a vertical height higher than the vertical height of the upper surface of the semiconductor chip 100 in the vertical direction D3.

[0068] In some example embodiments, the molding layer 200 can include an insulating material. For example, the molding layer 200 can include an insulating polymer such as an epoxy molding compound (EMC).

[0069] The molding layer 200 can include a main body portion 200a and a marking pattern disposed on the main body portion 200a. The marking pattern can include a plurality of protrusions 200b. A marking frame 300 can be disposed on the main body portion 200a. A portion of the marking frame 300 can be removed to form a marking region R1. As shown in FIG. 1A, the marking frame 300 can be disposed on the main body portion 200a to cover a portion of the main body portion 200a on which the plurality of protrusions 200b are not formed. The marking frame 300 can have a thickness (or marking depth) T0 that is less than or equal to about 10 pm, for example, about 5 pm. The thickness T0 of the marking frame 300 can be less than a height of the plurality of protrusions 200b. Figure 3 As shown in FIG. 1B, the plurality of protrusions 200b can be spaced apart from each other in a first horizontal direction D1 in a cross-sectional view and extend from the main body portion 200a beyond an upper surface of the marking frame 300 in a vertical direction D3 to fill the marking region R1. Figure 2 As shown in FIG. 1C, the marking pattern can include a character or a pattern representing information of a trademark, a model number, a performance parameter, etc. of the semiconductor package 1000.

[0070] The semiconductor package according to an embodiment of the disclosure forms a marking pattern using a marking frame instead of a conventional laser burning process, which can avoid cracks in the semiconductor package without a need for a sufficiently thick molding layer, thereby reducing an overall thickness of the semiconductor package.

[0071] One or more portions of the marking frame 300 can be removed (e.g., by an etching process) to form one or more marking regions R1. The marking region R1 can be a region of the marking frame 300 in which the plurality of protrusions 200b are formed. For example, the plurality of protrusions 200b can be formed in the marking region R1. As shown in FIG. 2A, the marking frame 300 can be disposed on the main body portion 200a to cover a portion of the main body portion 200a on which the plurality of protrusions 200b are not formed. The marking frame 300 can have a thickness (or marking depth) T0 that is less than or equal to about 10 pm, for example, about 5 pm. The thickness T0 of the marking frame 300 can be less than a height of the plurality of protrusions 200b. Figure 3 As shown in FIG. 2B, the plurality of protrusions 200b can extend from the main body portion 200a beyond an upper surface of the marking frame 300 in a vertical direction D3 to fill the marking region R1.

[0072] The marking frame 300 can be disposed on the main body portion 200a of the molding layer 200. In some example embodiments, the marking frame 300 can be disposed on the main body portion 200a of the molding layer 200 to cover a portion of an upper surface of the main body portion 200a on which the plurality of protrusions 200b are not formed. The thickness (or marking depth) T0 of the marking frame 300 can be less than or equal to about 10 pm, for example, about 5 pm. The thickness T0 of the marking frame 300 can be less than a height of the plurality of protrusions 200b.

[0073] In some example embodiments, the marking frame 300 can include a metallic material. The metallic material can be, for example, copper. When the marking frame 300 includes the metallic material, it can function as an EMI shield, thereby improving performance of the semiconductor package.

[0074] In some example embodiments, the mark pattern can be configured as a character mark or a graphic mark for identifying the semiconductor package. In this case, the area of the removed portion of the mark frame can be smaller than the area of the remaining portion of the mark frame. Hereinafter, features of the example embodiments will be described in detail. Figures 2 to 3 Features of the example embodiments are described in detail.

[0075] As Figure 3 As shown in FIG. 2B, the plurality of protrusions 200b can include a first protrusion 200b1 and a second protrusion 200b2.

[0076] In some example embodiments, the first protrusion 200b1 and the second protrusion 200b2 can have different shapes and sizes from each other. For example, the first protrusion 200b1 can have a first width W1 in the first horizontal direction D1, and the second protrusion 200b2 can have a second width W2 in the first horizontal direction D1. The first width W1 and the second width W2 can be different from each other, for example, the first width W1 can be smaller than the second width W2. However, the example embodiments are not limited thereto, and the first width W1 and the second width can be substantially the same as each other.

[0077] In some example embodiments, the plurality of protrusions 200b can have a height of about 10 µm to about 50 µm in the vertical direction D3. For example, the first protrusion 200b1 can have a first height H1 in the vertical direction D3, and the second protrusion 200b2 can have a second height H2 in the vertical direction D3. Here, the first height H1 and the second height H2 can be the height difference in the vertical direction D3 from the upper surface of the body portion 200a to the upper surface of the first protrusion 200b1 and to the upper surface of the second protrusion 200b2, respectively. As shown in FIG. 2B, the first height H1 and the second height H2 can be different from each other, for example, the first height H1 can be smaller than the second height H2. Figure 3

[0078] ​The coefficient of thermal expansion (CTE) at the location of the first protrusion 200b1 and the CTE at the location of the second protrusion 200b2 of the semiconductor package 1000 may differ from each other, which may lead to warping of the semiconductor package 1000. According to an example embodiment, the first height H1 of the first protrusion 200b1 and the second height H2 of the second protrusion 200b2 may be formed to be different from each other. For example, by controlling the difference between the first height H1 of the first protrusion 200b1 and the second height H2 of the second protrusion 200b2, the difference between the CTE at the location of the first protrusion 200b1 and the CTE at the location of the second protrusion 200b2 can be compensated, thereby effectively controlling the warping of the semiconductor package 1000 (e.g., warping caused by the difference between the CTE of the molding layer and the CTE of the substrate and / or the semiconductor chip). For example, by forming protrusions with different heights at different locations of the semiconductor package, the warping of the semiconductor package can be controlled. For example, if the CTE at the location of the first protrusion 200b1 is less than the CTE at the location of the second protrusion 200b2, then the first height H1 of the first protrusion 200b1 can be formed to be less than the second height H2 of the second protrusion 200b2.

[0079] like Figure 3 As shown, when viewed along the vertical direction D3 (e.g., when viewed in a plan view), the first protrusion 200b1 and the second protrusion 200b2 can be stacked with the semiconductor chip 100. For example, the first protrusion 200b1 and the second protrusion 200b2 can be positioned above the semiconductor chip 100 in the vertical direction D3. Furthermore, the plurality of protrusions 200b may also include a third protrusion and a fourth protrusion. The height of the third protrusion and the fourth protrusion may be the same as the height H2 of the second protrusion 200b2 and may be greater than the height H1 of the first protrusion 200b1. When viewed along the vertical direction D3, the third protrusion and the fourth protrusion may not be stacked with the semiconductor chip 100. The third protrusion and the fourth protrusion may be located at the edge of the body portion 200a in the horizontal direction (e.g., the first horizontal direction D1). For example, when viewed along, for example... Figure 3 When viewed in the cross-sectional view along the second horizontal direction D2, the third and fourth protrusions can be positioned at the left and right edges of the main body 200a, respectively, or near the left and right edges of the main body 200a. In this case, the outer surface of the marking frame 300 and the outer surface of the main body 200a can be aligned in the vertical direction D3. Although in Figure 3The number of the protrusions 200b is four as shown in FIG. 2, but the number of the protrusions 200b is not limited thereto, and for example, the number of the protrusions 200b can be three or less or four or more.

[0080] When the semiconductor package 1000 is manufactured, the body portion 200a and the marking pattern can be integrally formed in a mold via a molding process. For example, the body portion 200a and the plurality of protrusions 200b can be formed as an integral structure without an interface therebetween. In other words, the body portion 200a and the plurality of protrusions 200b can be portions of a single structure formed simultaneously from the same material. Thus, there can be no distinct boundary between the body portion 200a and the plurality of protrusions 200b. For example, the body portion 200a and the plurality of protrusions 200b can be formed together as a continuous, homogeneous layer (e.g., formed throughout from the same base material). For example, the body portion 200a and the plurality of protrusions 200b can be formed in a single process (e.g., in-situ - in the cavity without vacuum break of the cavity).

[0081] In some example embodiments, the semiconductor package 1000 can include at least one bonding pad 120. As shown in FIG. 1, Figure 3 As shown in FIG. 1, the bonding pad 120 can be disposed under the substrate 110. For example, the bonding pad 120 can be disposed on the second surface 110b of the substrate 110, and can be in contact with the second surface 110b of the substrate 110. The bonding pad 120 can include a conductive material such as a metal or an alloy.

[0082] At least one external terminal 130 can be disposed under the substrate 110. For example, the external terminal 130 can be disposed on the bonding pad 120. The external terminal 130 can be electrically connected to the semiconductor chip 100 through the bonding pad 120. Thus, the number of the external terminal 130 can be appropriately determined according to the type and capacity of the semiconductor chip 100. The external terminal 130 can include a solder ball or a solder bump.

[0083] In some example embodiments, a remaining portion of the marking frame can be configured as a character mark or a graphic mark for identifying the semiconductor package. In this case, the area of the removed portion of the marking frame can be greater than the area of the remaining portion of the marking frame. Hereinafter, the features of this example embodiment will be described in detail. Figures 4 to 5 The features of this example embodiment will be described in detail.

[0084] Figure 4 is a plan view illustrating a semiconductor package 2000 according to an example embodiment of the present disclosure. Figure 5 is a plan view illustrating a semiconductor package 2000 according to an example embodiment of the present disclosure. Figure 4 is a sectional view of the semiconductor package 2000 of the example embodiment of FIG. 2. Hereinafter, the differences from the semiconductor package 1000 will be set forth, and redundant descriptions can be omitted.

[0085] Referring to Figure 4 and Figure 5 , the semiconductor package 2000 according to example embodiments can include a substrate 110, a semiconductor chip 100, a molding layer 210, and a marking frame 310.

[0086] The molding layer 210 can include a main body portion 210a and a marking pattern disposed on the main body portion 210a. The marking pattern can include a plurality of protrusions 210b. Unlike the plurality of protrusions 200b of the semiconductor package 1000, the plurality of protrusions 210b can be formed to have substantially the same height as each other in the vertical direction D3. In some example embodiments, the height H0 of the plurality of protrusions 210b in the vertical direction D3 can be in the range of about 10 µm to about 50 µm.

[0087] In some example embodiments, the plurality of protrusions 210b can include peripheral protrusions 210b1 and internal protrusions 210b2. As shown in Figure 5 , (e.g., when viewed in a cross-sectional view along the second horizontal direction D2) the peripheral protrusions 210b1 can be located at edges of the main body portion 210a in the first horizontal direction D1, and the outer side surfaces of the peripheral protrusions 210b1 and the outer side surface of the main body portion 210a can be aligned in the vertical direction D3. In this case, the internal protrusions 210b2 can be arranged between the peripheral protrusions 210b1 in the first horizontal direction D1.

[0088] In some example embodiments, the peripheral protrusions 210b1 and the internal protrusions 210b2 can be formed to have different shapes and sizes from each other. For example, the peripheral protrusions 210b1 can have a first width W3 in the first horizontal direction D1, and the internal protrusions 210b2 can have a second width W4 in the first horizontal direction D1. The first width W3 of the peripheral protrusions 210b1 can be smaller than the second width W4 of the internal protrusions 210b2, but is not limited thereto.

[0089] The marking frame 310 can be disposed on the main body portion 210a of the molding layer 210, and one or more portions of the marking frame 310 can be removed (e.g., by an etching process) to form one or more marking regions R2. The marking regions R2 can be regions of the marking frame 310 in which the plurality of protrusions 210b are formed. For example, the plurality of protrusions 210b can be formed on and fill the marking regions R2.

[0090] Unlike the semiconductor package 1000, a relatively large portion (e.g., a main body) of the marking frame 310 of the semiconductor package 2000 is removed by etching. For example, the removed area of the marking frame 310 of the semiconductor package 2000 is larger than that of the semiconductor package 1000. As shown in FIG. 10B, the removed area of the marking frame 310 of the semiconductor package 2000 is larger than that of the semiconductor package 1000. Figure 4 and Figure 5 As shown in FIG. 10B, the remaining portion of the marking frame 310 of the semiconductor package 2000, which is not removed, is configured as a text or graphic identification for identifying the semiconductor package 2000. In this case, since the thickness (or marking depth) T0 of the marking frame 310 can be less than or equal to about 10 µm (e.g., about 5 µm), the marking depth can be significantly reduced compared to the marking depth (e.g., about 10 µm to about 50 µm) formed by a laser burning method, thereby allowing a thinner molding layer to be formed and contributing to the formation of a thinner semiconductor package.

[0091] In some example embodiments, the remaining portion of the marking frame 310, which is not removed, can include a plurality of sub-portions 311 spaced apart from each other in a horizontal direction (e.g., a first horizontal direction D1) in a cross-sectional view. Each of the plurality of sub-portions 311 can have a third width W5 in the first horizontal direction D1, which can be smaller than each of the first width W3 and the second width W4. However, example embodiments of the present disclosure are not limited thereto, and the plurality of sub-portions 311 can have different widths from each other in the horizontal direction.

[0092] In the semiconductor package 2000, since the horizontal width of the marking frame 310 is small, the marking frame 310 (e.g., the plurality of sub-portions 311) can be relatively deeply embedded into the molding layer 210, so that a gap can be formed between the plurality of protrusions 210b. Such a gap can provide a space for thermal expansion of epoxy resin (EMC) forming the molding layer 210 to mitigate stress in the semiconductor package due to thermal expansion. Accordingly, the marking frame 310 (e.g., the plurality of sub-portions 311) can act as a CTE blocking structure to improve the problem of stress concentration in the semiconductor package due to excessive CTE, thereby reducing or preventing warpage of the semiconductor package.

[0093] Hereinafter, a method of manufacturing a semiconductor package according to an example embodiment will be described with reference to the accompanying drawings. The same reference numerals can denote the same components.

[0094] Figure 6 is a flowchart illustrating a method of manufacturing a semiconductor package according to an example embodiment of the present disclosure. Figures 7 to 12 is a cross-sectional view illustrating an intermediate stage of a method of manufacturing a semiconductor package 1000 according to an example embodiment. Figure 2 and Figure 3 Hereinafter, the method of manufacturing a semiconductor package according to an example embodiment will be described with reference to FIGS. 11A to 11C.Figure 2 and Figure 3 described Figures 6 to 12 , and redundant descriptions can be omitted.

[0095] Referring to Figure 6 and Figure 7 , a method of manufacturing the semiconductor package 1000 according to an example embodiment of the disclosure includes performing step S100 to form a preliminary mark structure PMS. The preliminary mark structure PMS includes a separation carrier DC and a mark frame 300 on the separation carrier DC.

[0096] In some example embodiments, the separation carrier DC can be a photosensitive material or a thermosensitive material having tackiness. For example, when ultraviolet light irradiation or heating is performed on the separation carrier DC, the separation carrier DC can be cured to lose tackiness so as to be easily peeled off from the mark frame 300. However, example embodiments of the disclosure are not limited thereto, and the separation carrier DC can be formed of other materials.

[0097] In some example embodiments, the mark frame 300 can be formed using at least one of a chemical vapor deposition (CVD) process, a low-pressure CVD process, a plasma-enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition process. However, example embodiments of the disclosure are not limited thereto, and the mark frame 300 can also be formed by other different processes. In some example embodiments, the mark frame 300 can include a metal material. In some example embodiments, the mark frame 300 can include a metal material having an EMI shielding function. For example, the mark frame 300 can include copper (Cu).

[0098] Next, referring to Figure 6 and Figure 8 , step S200 is performed to form a recess pattern RS on the preliminary mark structure PMS to form a mark structure MS. The recess pattern RS includes a plurality of recesses RP spaced apart from each other in a horizontal direction in a cross-sectional view. Lower surfaces of the plurality of recesses RP are located below an upper surface of the separation carrier DC in a vertical direction. The removed portion of the mark frame 300 forms a mark region R1 (see, for example, Figure 3 ).

[0099] In some example embodiments, the recessed pattern RS can be formed by a selective etching process (e.g., a laser etching process, a plasma etching process, and / or a wet etching process) to remove portions of the marking frame 300 and portions of the separation carrier DC. For example, by performing the etching process, portions of the marking frame 300 can be etched and penetrated in the vertical direction D3 until the upper portion of the separation carrier DC is removed. For example, the etching process can be such that the entire depth of the marking frame 300 is etched to form the recessed pattern RS, and can be such that only a partial depth of the separation carrier DC is etched to form the recessed pattern RS. The upper portion of the separation carrier DC can be etched, and the lower portion of the separation carrier DC can remain.

[0100] Figures 7 to 12 The method shown in Figure 8 may form the marking pattern as a text identification or a graphic identification for identifying the semiconductor package. As shown in Figure 8 , the plurality of recesses RP can include a first recess RP1 and a second recess RP2. The etching process can be performed such that lower surfaces of the plurality of recesses RP (e.g., the first recess RP1 and the second recess RP2) are located below an upper surface of the separation carrier DC in the vertical direction D3. The first recess RP1 can have a first depth d1, and the second recess RP2 can have a second depth d2. Each of the first depth d1 and the second depth d2 can be greater than the thickness T0 of the marking frame 300. As shown in , the first depth d1 and the second depth d2 can be different from each other, for example, the first depth d1 can be smaller than the second depth d2. However, example embodiments of the present disclosure are not limited thereto.

[0101] In example embodiments, the selective etching process can be performed to selectively form the plurality of recesses RP at different locations. For example, the first recess RP1 having the smaller first depth d1 can be formed at a location where the CTE is relatively small, and the second recess RP2 having the larger second depth d2 can be formed at a location where the CTE is relatively large.

[0102] Figure 6 Next, referring to Figure 9 , Figure 10 , step S300 is performed to form a substrate structure SS. The substrate structure SS includes the substrate 110 and the semiconductor chip 100 on the substrate 110. The substrate structure SS can be formed by any prior art means in the relevant art, which is not described here again. The substrate structure SS can be formed separately from and / or independently of the marking structure MS. As described below with reference to Figure 11 and Figure 12The marking structure MS can be joined to the base structure SS by flipping the marking structure MS or the base structure SS such that the upper surface of the marking frame 300 faces the upper surface of the semiconductor chip 100.

[0103] Next, referring to Figure 6 and Figure 11 , a step S400 is performed to perform a molding process on the marking structure MS and the base structure SS to form a molding layer 200. The molding layer 200 includes a main body portion 200a and a marking pattern disposed on the main body portion 200a, wherein the marking pattern includes a plurality of protruding portions 200b formed by filling a plurality of recessed portions RP, respectively.

[0104] In some example embodiments, the step of forming the molding layer 200 can include, first, referring to Figure 11 , the base structure SS shown in Figure 10 can be inverted such that the semiconductor chip 100 faces downward. Then, referring to Figure 11 , the marking structure MS can be placed in a lower cavity of a mold (not shown) with the marking frame 300 facing upward, and the base structure SS can be placed in an upper cavity of the mold with the semiconductor chip 100 facing downward. In some example embodiments, a release film RL can be disposed in the lower cavity of the mold. At this time, the separation carrier DC of the marking structure MS can be located on the release film RL in the lower cavity of the mold. The release film RL can include a carbon-based material layer. For example, the release film RL can include an amorphous carbon layer (ACL).

[0105] Then, after the marking structure MS and the base structure SS are placed in the mold, the mold can be closed and an encapsulation material can be injected into the mold. For example, in the closed mold, the upper surface of the semiconductor chip 100 and the upper surface of the marking frame 300 can face each other and can be spaced apart by a certain distance in the vertical direction D3. For example, in the closed mold, the upper surface of the semiconductor chip 100 and the upper surface of the marking frame 300 can not be in contact with each other. In some example embodiments, the encapsulation material can include, for example, an epoxy resin (EMC), but is not limited thereto. After the mold is closed and the encapsulation material is injected, the encapsulation material can be cooled and solidified to form the molding layer 200.

[0106] As shown in Figure 3 and Figure 11 , the molding layer 200 includes a main body portion 200a and a marking pattern disposed on the main body portion 200a, and the marking pattern can be or can include a plurality of protruding portions 200b formed by filling a plurality of recessed portions RP, respectively. Through the molding process, the main body portion 200a and the marking pattern of the molding layer 200 are formed in one piece. Figure 3Multiple protrusions 200b) can be integrally formed, and the marking pattern can be formed as a text or graphic identifier for identifying the semiconductor package.

[0107] Next, refer to Figure 6 and Figure 12 Step S500 is performed to remove the separation carrier DC to expose the upper surface of the marker frame 300 and the upper surface of the marker pattern. In the etching process described above, due to the marker pattern (i.e., Figure 3 The upper surface of the multiple protrusions 200b is covered by the separation carrier DC, so that after the separation carrier DC is removed, the exposed upper surface of the marking pattern is smooth (e.g., flat).

[0108] In some exemplary embodiments, the separation carrier DC can be directly separated from the upper structure by, for example, the application of external force. However, the exemplary embodiments of this disclosure are not limited thereto.

[0109] After that, return to the reference. Figure 3 External terminals 130 can be provided on the bottom surface of the substrate structure SS. For example, external terminals 130 can be provided on a bonding pad 120 provided on the bottom surface of the substrate structure SS. External terminals 130 may include solder balls or solder bumps.

[0110] Next, by inverting the overall structure described above, it is possible to manufacture something like... Figure 2 and Figure 3 The semiconductor package 1000 shown is illustrated. In the method of manufacturing a semiconductor package according to this disclosure, the marking process can be completed simultaneously with the molding process, thus eliminating the need for a separate marking process, thereby saving production costs and improving production efficiency.

[0111] Figures 13 to 16 It shows the manufacturing process. Figure 4 and Figure 5 A cross-sectional view of an intermediate stage of a method for a semiconductor package 2000 according to an example embodiment. Hereinafter, reference is made to… Figure 4 and Figure 5 describe Figure 6 , Figures 13 to 16 The description will focus on... Figures 7 to 12 The manufacturing method of the semiconductor package 1000 shown is different, and redundant descriptions can be omitted.

[0112] Reference Figure 6 and Figure 13 A method for manufacturing a semiconductor package 2000 according to an example embodiment of the present disclosure includes performing step S100 to form a pre-marking structure PMS. The pre-marking structure PMS includes a discrete carrier DC and a marking frame 310 on the discrete carrier DC.

[0113] Next, referring to Figure 6 and Figure 14 , step S200 is performed to form a recessed pattern RS on the preliminary mark structure PMS to form a mark structure MS. The recessed pattern RS includes a plurality of recessed portions RP’ spaced apart from each other in a horizontal direction in a cross-sectional view. Lower surfaces of the plurality of recessed portions RP’ are located below an upper surface of the separation carrier DC in a vertical direction. The removed portions of the mark frame 310 form a mark area R2 (see, for example, Figure 5 ).

[0114] Figures 13 to 16 The method shown in Figure 8 may form the remaining portions of the mark frame as a textual identification or a graphical identification for identifying the semiconductor package. In some example embodiments, unlike the first recessed portions RP1 and the second recessed portions RP2 having different depths shown in Figure 14 , the plurality of recessed portions RP’ shown in may be formed to have the same depth.

[0115] In some example embodiments, as shown in Figure 14 , the etching process can be performed at a different location than the location shown in Figure 8 , such that the plurality of recessed portions RP’ includes peripheral recessed portions RPO and inner recessed portions RPI. For example, when viewed in a cross-sectional view along the horizontal direction, the peripheral recessed portions RPO can be located at edges of the separation carrier DC in the horizontal direction, and outer side surfaces of the peripheral recessed portions RPO and outer side surfaces of the separation carrier DC can be aligned in the vertical direction D3. The inner recessed portions RPI can be arranged between the peripheral recessed portions RPO in the horizontal direction. The etching process can be performed such that lower surfaces of the plurality of recessed portions RP’ (e.g., the peripheral recessed portions RPO and the inner recessed portions RPI) are located below the upper surface of the separation carrier DC in the vertical direction D3. The peripheral recessed portions RPO and the inner recessed portions RPI can be formed to have substantially the same depth as each other. Further, the etching process can be performed such that a width of the inner recessed portions RPI in the horizontal direction (e.g., the first horizontal direction D1 and / or the second horizontal direction D2) is greater than a width of the peripheral recessed portions RPO in the horizontal direction.

[0116] In some example embodiments, one or more portions of the mark frame 310 can be removed by an etching process. As shown in Figure 4 and Figure 14 , by the etching process, a main portion (e.g., a majority, a substantial portion, a major portion, and / or a plurality of portions) of the mark frame 310 is removed. Thus, the remaining portions of the mark frame 310 that are not removed can be configured as a textual identification or a graphical identification for identifying the semiconductor package 2000. In some example embodiments, as shown in Figure 5and Figure 14 As shown in FIG. 10, the remaining portion of the marking frame 310 that is not removed can include, in a cross-sectional view, a plurality of sub-portions 311 spaced apart from each other in a horizontal direction (e.g., the first horizontal direction D1 and / or the second horizontal direction D2). A horizontal width of each of the plurality of sub-portions 311 can be smaller than a horizontal width of each of the peripheral recess RPO and the inner recess RPI.

[0117] Next, step S300 can be performed by the same method as that shown in Figure 9 and Figure 10 Step S300 can be performed by the same method as that shown in

[0118] Next, referring to Figure 15 Step S400 can be performed by the same method as that shown in Figure 11 In some example embodiments, since the plurality of recesses RP’ formed by the etching process have substantially the same depth as each other, the plurality of protrusions 210b of the molding layer 210 formed by the molding process can have substantially the same height as each other. Further, by the peripheral recess PRO and the inner recess RPI, the peripheral protrusion 210b1 and the inner protrusion 210b2 can be correspondingly formed.

[0119] Next, referring to Figure 16 Step S500 can be performed by the same method as that shown in Figure 12 In some example embodiments, referring to Figure 16 The separation carrier DC can be removed to expose the upper surfaces of the marking frame 310 and the plurality of protrusions 210b by the same method as that shown in Figure 12 Since the upper surfaces of the plurality of protrusions 200b are covered by the separation carrier DC in the aforementioned etching process, the exposed upper surfaces of the plurality of protrusions 200b are smooth.

[0120] Thereafter, the same or similar processes as those described with respect to the semiconductor package 1000 can be performed, and a semiconductor package 2000 as shown in Figure 4 and Figure 5 FIG. 11 can be manufactured.

[0121] By way of summary and review, in the semiconductor package and the method of manufacturing the semiconductor package according to example embodiments of the present disclosure, a marking pattern having a relatively small thickness can be achieved, such that the overall thickness of the semiconductor package can be thinned compared to that of a conventional semiconductor package.

[0122] In addition, the semiconductor package according to an example embodiment of the present disclosure can balance CTE differences at different locations of the semiconductor package by forming a plurality of protrusions having different heights to reduce or prevent warping of the semiconductor package.

[0123] In addition, the marking frame of the semiconductor package according to an example embodiment of the present disclosure can be formed to have a CTE blocking structure to improve a problem of stress concentration in the semiconductor package due to excessive CTE, thereby reducing or preventing warping of the semiconductor package.

[0124] In addition, the marking frame of the semiconductor package according to an example embodiment of the present disclosure can also function as an EMI shield to improve performance of the semiconductor package.

[0125] In addition, the manufacturing method of the semiconductor package according to an example embodiment of the present disclosure is capable of forming a marking pattern while performing a molding process, and thus a separate process for forming the marking pattern is no longer required, thereby simplifying the manufacturing process and reducing production costs.

[0126] Although the present disclosure has been described with respect to certain example embodiments thereof, it will be apparent to those having ordinary skill in the art that changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure. Thus, the example embodiments disclosed above should be considered illustrative and not restrictive, and the example embodiments should be considered to include all changes and modifications that come within the scope of the present disclosure.

Claims

1. A semiconductor package, comprising: Base; Semiconductor chips are mounted on a substrate; A molding layer covers a semiconductor chip on a substrate. The molding layer includes a main body and a marking pattern disposed on the main body. as well as A marking frame, set on the main body, is partially removed to form the marking area. The marking pattern includes multiple protrusions, and When viewed in a sectional view, the plurality of protrusions are spaced apart from each other in the horizontal direction and extend from the main body beyond the upper surface of the marking frame in the vertical direction to fill the marking area.

2. The semiconductor package according to claim 1, wherein, The thickness of the marking frame in the vertical direction is less than or equal to 10 μm.

3. The semiconductor package according to claim 1, wherein, The marking frame is made of metal.

4. The semiconductor package according to claim 3, wherein, The marker frame consists of copper.

5. The semiconductor package according to claim 1, wherein, The marking pattern is a textual or graphic identifier used to identify the semiconductor package.

6. A method for manufacturing a semiconductor package, comprising: A preliminary labeling structure is formed, wherein the preliminary labeling structure includes a separation carrier and a labeling frame on the separation carrier; A recessed pattern is formed on the pre-marking structure to form the marking structure. When viewed in a cross-sectional view, the recessed pattern includes a plurality of recesses spaced apart from each other in the horizontal direction, wherein the lower surface of each of the plurality of recesses is located below the upper surface of the separation carrier in the vertical direction, wherein a portion of the marking frame is removed to form the marking area. Forming a substrate structure, which includes a substrate and a semiconductor chip on the substrate; During the molding process, the marking structure and the base structure are positioned so that they face each other within the mold; A molding process is performed on the marking structure and the base structure to form a molding layer. The molding layer includes a main body and a marking pattern disposed on the main body, wherein the marking pattern includes a plurality of protrusions formed by respectively filling the plurality of recesses; and Remove the separation carrier to expose the upper surface of the marker frame and the upper surface of the marker pattern.

7. The method according to claim 6, wherein, The steps to form the recessed pattern include: performing an etching process to penetrate the marking frame in the vertical direction until the upper part of the separation carrier is removed.

8. The method according to claim 7, wherein, The marking pattern is a textual or graphic identifier used to identify the semiconductor package.

9. The method according to claim 8, wherein, The plurality of recesses include a first recess and a second recess, and The depth of the first recess is different from the depth of the second recess.

10. The method according to claim 9, wherein, The depth of the first recess is less than the depth of the second recess, and Specifically, a first recess is formed at a location in the semiconductor package having a first coefficient of thermal expansion, and a second recess is formed at a location in the semiconductor package having a second coefficient of thermal expansion that is greater than the first coefficient of thermal expansion.

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