Stress decoupling type sensor packaging structure based on glass interposer and packaging method thereof

Abstract

The invention provides a stress decoupling type sensor packaging structure based on a glass intermediate layer and a packaging method thereof, and the method comprises the steps: preparing a glass-based carrier plate with a TGV through hole, and carrying out the metallization filling, and forming the glass intermediate layer; manufacturing a piezoresistive reference sensor in a preset area through SOI wafer bonding, silicon film transfer and a semiconductor process, and then mounting a main sensor with an upward bonding pad on the surface of the glass intermediate layer; performing plastic packaging on the main sensor and the reference sensor to form a plastic packaging layer, positioning the positions of the main sensor and the reference sensor, performing laser drilling to prepare an interconnection hole, and performing metallization to form a matrix hole interconnection structure which penetrates through the plastic packaging layer and is connected with the chip and the TGV through hole; finally, packaging is completed through ball mounting and surface treatment, two-dimensional / three-dimensional heterogeneous integration of the main sensor and the ASIC signal processing chip can be achieved through the TGV through hole, and the problems that in existing main sensor packaging, local stress interference exists, the measurement precision is insufficient, and low-cost mass production is difficult are solved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, and more specifically to a stress-decoupling sensor packaging structure and packaging method based on a glass interposer. Background Technology

[0002] In existing technologies, the packaging processes for main sensors are mainly divided into two categories: one is the traditional wire bonding molding process, which uses a copper frame or organic carrier boards such as FR4 and BT as the mounting carrier. Electrical interconnection between the chip pads and the carrier is achieved through wire bonding, and then the chip is encapsulated and protected by molding. The core principle is to use metal leads to transmit electrical signals and the molding layer to provide mechanical protection. The other is the 2.5D advanced packaging process based on silicon interposers, which uses silicon interposers as the connection carrier between the chip and the PCB. High-density vertical interconnection is achieved through through silicon vias (TSVs), and the matching thermal expansion coefficients of silicon and the chip are used to isolate the bending stress of the PCB, making it suitable for high-end precision sensor applications.

[0003] However, both of these packaging processes have unresolved key problems. The reasons are as follows: Traditional wire bonding molding technology generates extremely high local stress at the wire bonding points on the chip surface, directly interfering with sensitive piezoresistive components. Furthermore, the thermal expansion coefficients of traditional packaging materials (frame, organic substrate) and silicon chips differ greatly. When the temperature changes, unpredictable tensile or compressive stresses are generated on the chip. At the same time, it is impossible to distinguish between target stress and non-target stress, leading to measurement inaccuracies. This method is only suitable for consumer product applications with extremely low requirements for accuracy and stability. On the other hand, although 2.5D advanced packaging technology based on silicon interposers can effectively isolate PCB stress, the manufacturing cost of silicon interposers is high, making it only suitable for high-end product applications.

[0004] It is evident that in existing main sensor packaging technologies, traditional wire bonding molding processes suffer from localized stress interference, thermal expansion coefficient mismatch leading to insufficient measurement accuracy, and the 2.5D packaging process based on silicon interposers is costly and difficult to mass-produce. These issues severely affect the development of high-precision and high-stability main sensors and fail to meet the demands for high-precision and high-stability stress sensing in fields such as Industry 4.0, intelligent manufacturing, advanced robotics, aerospace, and precision medicine. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the stress decoupling sensor packaging structure and packaging method based on glass interlayer provided by the present invention solves the problems of local stress interference, insufficient measurement accuracy and difficulty in low-cost mass production in the prior art.

[0006] To achieve the above objectives, the present invention provides a stress-decoupling sensor packaging method based on a glass interposer, the method comprising the following steps: S1, preparing a glass substrate; S2, processing through-hole TGV vias on the glass substrate, and metallizing and filling the TGV vias to form a glass interposer with the glass substrate as the bearing substrate and the TGV vias as vertical interconnecting channels; S3, fabricating a piezoresistive reference sensor in a predetermined area on the surface of the glass interposer that is not covered by the subsequent main sensor; S4. Apply conductive adhesive to the preset chip mounting area on the surface of the glass interposer, and bond the main sensor with the pad facing upwards to the conductive adhesive to form a bonding structure including the glass interposer, TGV vias, a piezoresistive reference sensor, and the main sensor; S5. Moldulate the bonding structure to obtain a molded structure that completely covers the main sensor and the piezoresistive reference sensor and is tightly bonded to the surface of the glass interposer; S6. Use laser drilling technology to process interconnect holes at the electrical interconnection positions of the main sensor and the piezoresistive reference sensor in the molded structure; S7. Metallize the hole walls of the interconnect holes and the areas on the surface of the glass interposer not covered by the molded layer, the main sensor, and the piezoresistive reference sensor to form a matrix hole interconnection structure penetrating the molded layer.

[0007] The present invention further provides the above-mentioned packaging method, characterized in that the formation of the piezoresistive reference sensor in step S3 specifically includes: S01, providing an SOI wafer, and bonding the active surface (top silicon surface) of the SOI wafer to a glass interposer layer with completed TGV via fabrication; S02, sequentially removing the substrate silicon and buried oxide layer of the SOI wafer, so that the remaining top single-crystal silicon film is attached to a predetermined area on the surface of the glass interposer layer; S03, fabricating a piezoresistor on the top single-crystal silicon film by ion implantation and high-temperature annealing; S04, photolithography and dry etching of the top single-crystal silicon film, retaining the portion forming the piezoresistive strip, and removing the remaining area; S05, etching contact windows at both ends of the piezoresistive strip, and depositing a metal layer on the surface of the glass interposer layer; S06, photolithography to delineate lead paths on the metal layer, etching to remove excess metal to form metal leads, and connecting the endpoints of the piezoresistive strip through the metal leads to form a Wheatstone bridge, thereby obtaining the piezoresistive reference sensor.

[0008] Preferably, in step S05, the contact window adopts a size-differentiated design. The size of the contact window used to connect the Wheatstone bridge is 2μmx2μm-5μmx5μm, and the size of the contact window used to connect the TGV via is 20μmx20μm-50μmx50μm. The position of the contact window corresponds to the pre-positioning of the metal circuit subsequently fabricated on the surface of the glass interposer to ensure the reliability of the electrical connection between the piezoresistive reference sensor and the TGV via.

[0009] Preferably, in step S4, the distance between the piezoresistive reference sensor and the main sensor on the surface of the glass interlayer is set to 400um-2mm, and the direction of the center line connecting the two is perpendicular to the distribution direction of the TGV vias in the glass interlayer.

[0010] Preferably, in step S7, the matrix via interconnect structure includes metallized vias filling the interconnect holes, and metal lines disposed on the surface of the glass interposer, connecting the metallized vias and TGV vias. One end of the metallized via is connected to the chip pad of the main sensor or the signal lead of the piezoresistive reference sensor, and the other end is connected to one end of the metal line; the other end of the metal line is connected to the metallized filling portion of the TGV via that penetrates the glass interposer, thereby achieving electrical connection between the main sensor, the piezoresistive reference sensor, and the TGV via.

[0011] This invention also provides a stress-decoupling sensor packaging structure based on a glass interposer. The structure includes: a glass interposer, a main sensor, a piezoresistive reference sensor, a molding compound, a matrix via interconnect structure, and TGV vias. The TGV vias penetrate the glass interposer and are metallized to form vertical interconnect channels. The piezoresistive reference sensor is fabricated on the surface of the glass interposer, and the main sensor is mounted on the surface of the glass interposer via a conductive adhesive layer, with the two spaced 400µm-2mm apart. The molding compound encapsulates the main sensor and the piezoresistive reference sensor, and its bottom surface is attached to the glass interposer. The matrix via interconnect structure is embedded in the molding compound and includes metallized vias that penetrate the molding compound and connect the main sensor pads and the signal output terminals of the piezoresistive reference sensor, as well as metal lines arranged on the surface of the glass interposer to connect the metallized vias and the TGV vias, thereby achieving electrical conductivity between the three.

[0012] The present invention further provides the above-mentioned packaging structure, characterized in that it further includes an ASIC signal processing chip, wherein the ASIC signal processing chip forms a two-dimensional planar heterogeneous integration or a three-dimensional vertical heterogeneous integration with the main sensor and the piezoresistive reference sensor through a TGV via, thereby realizing the integration of "sensing-processing".

[0013] Compared with the prior art, the present invention has the following beneficial effects: In the technical solution provided by this invention, a glass interlayer is used to provide mechanical support for the chip to be packaged. Compared with the existing technology where the CTE mismatch between the frame / organic substrate and silicon can reach 20ppm / °C, the CTE mismatch between glass and silicon can be controlled within 1-3ppm / °C. This reduces thermal stress interference at the material level. At the same time, the Young's modulus of the glass interlayer is between that of the copper frame and the organic substrate, which can effectively absorb and disperse the bending or torsional stress from the PCB, avoiding the direct transfer of PCB stress to the chip in traditional packaging. Combined with a piezoresistive reference sensor fabricated using the same process, differential signal transmission is achieved. The time-compensated common-mode stress drift of the package reduces the zero-point drift and sensitivity temperature drift of the sensor by more than an order of magnitude compared to traditional wire bonding packaging. The use of matrix via interconnect technology to replace traditional wire bonding eliminates the random and local high stress points caused by wire bonding, improves the consistency of the stress environment of the sensitive elements inside the chip, and reduces the complexity of product screening and calibration. At the same time, the vertical interconnect characteristics of TGV vias support two-dimensional or three-dimensional heterogeneous integration of the main sensor and ASIC signal processing chip, reducing the overall package size, achieving high integration, and realizing "sensing-processing" integration. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the application scenario of the main sensor product of the present invention, showing the correspondence between the printed circuit board (PCB), the main sensor and the external force. Figure 2 This is a schematic diagram of the main sensor structure for traditional wire bonding (WB) technology, showing the use of a frame as the chip mounting carrier. Figure 3 This is a schematic diagram of the main sensor structure for traditional wire bonding (WB) technology, showing the use of a traditional organic substrate as the chip mounting carrier. Figure 4 A schematic diagram of an electrical interconnect structure that replaces wire bonding with matrix via interconnect technology shows the structural form of achieving chip electrical connection through matrix via interconnect on an organic substrate. Figure 5 A schematic diagram of the structure where the main sensor is mounted on an organic substrate; Figure 6 A schematic diagram of the structure for encapsulating and protecting the main sensor with molding compound; Figure 7 A schematic diagram of a structure for processing through holes using laser drilling technology; Figure 8 A schematic diagram of a laser-cut hole structure that leaves a 4-6 μm thick layer of molding compound residue above the chip pads; Figure 9 for Figure 8 A partially enlarged schematic diagram showing the relationship between residual plastic sealant and the position of the main sensor pads; Figure 10 This is a schematic diagram of a laser-hole interconnect structure using a glass interlayer, showing the combined structure of a glass substrate, TGV vias, and laser-hole interconnects. Figure 11 A schematic diagram of a piezoresistive reference sensor mounted on a glass interlayer; Figure 12 This is a partial structural diagram of a piezoresistive reference sensor; Figure 13 A schematic diagram of a structure in which a TGV through-hole is provided through a glass substrate. Figure 14 A schematic diagram of the bonding structure between an SOI wafer and a glass interlayer with a completed TGV via; Figure 15 This is a schematic diagram of the layered structure of an SOI wafer, showing that the SOI wafer consists of a substrate silicon, a buried oxide layer (SiO2), and a top silicon layer (monocrystalline silicon). Figure 16 This is a schematic diagram of the structure after removing the silicon substrate from the SOI wafer; Figure 17 This is a schematic diagram of the structure after removing the buried oxide layer from the SOI wafer; Figure 18 This is a schematic diagram of the formation of a varistor doped structure on a single-crystal silicon thin film by ion implantation. Figure 19 This is a schematic diagram of the stable resistance region and oxide layer formed after high-temperature annealing. Figure 20 This is a schematic diagram of the cross-sectional structure of the piezoresistive strip formed after photolithography and dry etching. Figure 21 This is a schematic diagram showing the planar distribution of the piezoresistive strips and TGV vias on the glass substrate interlayer. Figure 22 A schematic diagram of the cross-sectional structure of the etched contact windows at both ends of the piezoresistive strip; Figure 23 A schematic diagram of the planar structure for etching windows in a piezoresistive strip; Figure 24 A schematic diagram of the cross-sectional structure of the piezoresistive strip connected to the metal leads; Figure 25 This is a schematic diagram of the planar structure of a Wheatstone bridge and a TGV via, showing that the metal leads are connected to the piezoresistive strip to form the Wheatstone bridge; Figure 26 This is a schematic diagram of the structure of metal circuits on a glass interposer, showing the distribution of metal circuits in other areas of the glass interposer except for the piezoresistive reference sensor; Figure 27 A schematic diagram of the signal transmission path structure between the main sensor, the piezoresistive reference sensor, and the TGV via. Figure 28 A schematic diagram of the bonding structure forming the encapsulation structure; Figure 29 A schematic diagram showing the machining of interconnect holes on a plastic-encapsulated structure; Figure 30 A schematic diagram of the pretreatment structure for interconnect metallization shows the pretreatment structure for desmearing and seed layer deposition of interconnects; Figure 31 A schematic diagram of the matrix hole interconnect structure. Figure 32 A schematic diagram of the structure for secondary plastic encapsulation reinforcement of the package; Figure 33 A schematic diagram of a two-dimensional planar heterogeneous integration structure of the main sensor and the ASIC signal processing chip; Figure 34 A schematic diagram of a three-dimensional vertical heterogeneous integration structure of the main sensor and the ASIC signal processing chip. Detailed Implementation

[0015] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following embodiments. For those skilled in the art, any modifications, equivalent substitutions, and improvements made without departing from the inventive concept are all within the scope of protection of the present invention.

[0016] In a first aspect, the present invention provides a stress-decoupling sensor packaging structure and packaging method based on a glass interlayer, specifically including the following embodiments: Figure 1 This is a schematic diagram of the application scenario of the main sensor product. An external force is applied to the PCB surface, and the main sensor is attached to the force-bearing area of ​​the PCB to detect mechanical quantities such as force, torque, and pressure.

[0017] Figure 2 Schematic diagram of the main sensor structure for traditional wire bonding (WB) technology Figure 1 The structure uses a frame 22 as the chip mounting carrier. The structure includes, from bottom to top, solder balls 17, frame 22, molding compound 51, and main sensor 4 covered by the molding compound. WB bonding wires 18 are embedded in the molding compound 51. The chip 4 is electrically connected through the WB bonding wires 18. The frame 22 is made of copper with a coefficient of thermal expansion (CTE) of 17ppm / °C. The CTE mismatch with the silicon chip can reach about 14ppm / °C. When the PCB is bent, the copper frame will completely transfer the bending stress to the chip, resulting in severe signal interference of the sensitive piezoresistive components on the chip.

[0018] Figure 3 The diagram shows the main sensor structure of traditional wire bonding (WB) technology. Figure 2The main sensor 4 is electrically connected to the organic carrier plate 16 through a conventional WB bonding wire 18. The structure uses the organic carrier plate 16 as a carrier. The conventional organic carrier plate has the lowest stiffness and is easy to bend. Although it can buffer some stress, it has creep characteristics and cannot meet the stability requirements of the sensor.

[0019] Figure 4 The diagram shows a matrix hole interconnect structure 9 formed on an organic carrier plate 16, replacing the structure of WB wire bonding 18. This structure can avoid the local stress generated in the main sensor 4 region by the pressure and ultrasonic energy applied during WB wire bonding 18.

[0020] Figure 5 The diagram shows the structure in which the main sensor 4 is mounted on the organic carrier board 16 at a preset position using traditional chip mounting technology. The main sensor 4 and the organic carrier board 16 are initially fixed together by conductive adhesive.

[0021] Figure 6 The image shows a state where the main sensor 4 is encapsulated and protected by a plastic layer 51 using traditional plastic encapsulation technology, forming a plastic encapsulation structure 5.

[0022] Figure 7 The diagram shows the structure of interconnecting holes 6 fabricated at locations where electrical interconnection is required using laser drilling technology.

[0023] Figure 8 As shown, to ensure that the pad 19 of the main sensor 4 is not affected by mechanical stress or laser thermal stress, the laser parameters are adjusted to leave a 4-6 μm thick plastic residue 21 above the chip pad 19.

[0024] Figure 9 As shown Figure 8 The enlarged schematic diagram of the positional relationship between the plastic encapsulation residue 21 and the pad 19 of the main sensor 4 shows that a 4-6 μm thick plastic encapsulation residue 21 is retained above the chip pad 19, clarifying the precise processing range for subsequently immersing the package in alkaline solutions such as potassium permanganate to remove the plastic encapsulation residue 21.

[0025] Figure 10 The diagram shows the structure in which a glass interlayer 1 is used as the mounting carrier for the main sensor 4. The glass substrate is made of borosilicate glass, and the CTE mismatch between borosilicate glass and silicon can be controlled within 1-3 ppm / °C. It can serve as an ideal "stress buffer platform" to reduce the sensitivity of the main sensor 4 to installation conditions and external mechanical noise.

[0026] Figure 11The diagram shows a reserved area for fabricating a piezoresistive reference sensor 3 in the region of the glass interlayer 1 not covered by the main sensor 4. This fabrication area needs to be far away from the TGV via 2 to avoid electromagnetic interference, and the distance from the main sensor 4 should be controlled between 400um and 2mm to ensure that both sense the same package common mode stress.

[0027] It should be noted that the two different types of stress acting on the entire package are global stress and local stress. Global stress originates from temperature changes and the overall bending or warping of the PCB. Its characteristic is that it acts simultaneously, in the same direction, and in approximately the same amount on the entire glass interposer 1. Both the main sensor 4 and the piezoresistive reference sensor 3 will consistently feel this stress. Local stress, on the other hand, originates from externally applied target mechanical loads. Its characteristic is that it is highly concentrated in the sensitive area of ​​the main sensor 4 chip, and the resulting stress field decays rapidly with distance. Therefore, the piezoresistive reference sensor 3 hardly feels this local stress. When the main sensor 4 and the piezoresistive reference sensor 3 are connected in the same Wheatstone bridge, differential calculations can be used to offset the drift caused by package stress in real time, structurally achieving in-situ, real-time stress compensation, improving measurement accuracy and temperature drift performance.

[0028] In this embodiment, the preset position of the piezoresistive reference sensor 3 is determined by simulating the stress distribution on the glass interposer 1 under temperature cycling or PCB bending conditions. The stress of the piezoresistive reference sensor 3 in this region (especially the temperature-sensitive axial stress) is consistent in magnitude and direction with the stress in the region where the main sensor 4 chip is located, and the stress gradient is gentle, ensuring that the main sensor 4 and the piezoresistive reference sensor 3 are in the same common-mode stress region. In this embodiment, the distance is controlled between 400um and 2mm within the temperature range of -65℃ to 150℃.

[0029] Figure 12 The diagram shows the structural state in which the piezoresistive reference sensor 3 and the TGV via 2 are positioned relative to each other on the glass interlayer 1. The signal lead of the piezoresistive reference sensor 3 is positioned close to the TGV via 2, which can shorten the signal transmission path and reduce parasitic resistance.

[0030] Figure 13 The diagram shows the TGV through-hole 2 for preparing the glass interposer 1: a glass substrate with high surface smoothness and flatness is selected, and a through-hole 2 is processed through the glass substrate at the planned position using a laser ablation process; then, a Ti / Cu metal layer is deposited on the inner wall of the through-hole by a sputtering process to form the glass interposer 1; finally, the surface of the glass substrate is chemically and mechanically polished to reduce the surface roughness.

[0031] In a preferred embodiment, Figure 13The glass substrate used to prepare the TGV through-hole 2 shown can be either a borosilicate glass substrate or Corning glass. Both glass materials can meet the stress decoupling requirements of controlling the CTE mismatch with silicon within 1-3 ppm / °C. In another preferred embodiment, Figure 13 When preparing the TGV through-hole 2 of the glass substrate shown, the through-hole can be prepared by dry or wet etching process instead of laser ablation process.

[0032] Figure 14 The diagram shows an SOI wafer with a structure consisting of a top silicon layer (device layer, approximately 1 μm thick, i.e., top single-crystal silicon thin film 113), a buried oxide layer 112, and a substrate silicon layer 111 (approximately 500 μm thick). The active surface (top silicon surface) of the SOI wafer is bonded to the glass interposer layer 1, which has undergone TGV via 2 and chemical mechanical polishing, through direct bonding or anodic bonding.

[0033] Figure 15 The diagram shows the layered structure of SOI wafer 10, clearly illustrating the positional relationship between the substrate silicon 111, the buried oxide layer 112, and the top monocrystalline silicon thin film 113.

[0034] Figure 16 The diagram shows the substrate silicon 111 of the SOI wafer thinned by mechanical polishing, and then the remaining substrate silicon 111 is selectively removed by KOH wet etching. The etchant in this etching process automatically stops at the buried oxide layer 112 to avoid damaging the top monocrystalline silicon film 113.

[0035] In another preferred embodiment, Figure 16 The process for selectively removing the remaining substrate silicon 111 shown can be replaced by TMAH wet etching to selectively remove the remaining substrate silicon 111 instead of KOH wet etching.

[0036] Figure 17 The diagram shows the selective removal of the buried oxide layer 112 using a buffer oxide etching method, which completely transfers the top monocrystalline silicon thin film 113 of the SOI wafer 10 to the surface of the glass interposer 1. The thickness of the top monocrystalline silicon thin film 113 is controlled within the range of 0.1-5 μm to ensure the fabrication accuracy of the subsequent varistor 12.

[0037] In another preferred embodiment, Figure 17 The process for selectively removing the buried oxide layer 112 shown can be replaced by a hydrofluoric acid-based vapor etching process to selectively remove the buried oxide layer 112 instead of a buffer oxide etching process.

[0038] Figure 18 The diagram shows the doped region 120 of the varistor 12 defined on the transferred single-crystal silicon thin film 113 by a boron ion B⁺ implantation process.

[0039] Figure 19 The image shows the high-temperature annealing treatment performed on the top single-crystal silicon thin film 113 after boron ion (B⁺) implantation to activate the dopant and repair lattice damage, forming a stable resistance region, namely the core region of the varistor 12. At the same time, a high-temperature annealed oxide layer is formed on the surface to provide protection.

[0040] Figure 20 The diagram shows the patterning of the top monocrystalline silicon thin film 113 using photolithography and dry etching processes. The area retained after etching forms the final piezoresistive strip 121. Its cross-sectional view clearly shows the positional relationship between the piezoresistive strip 121 and the glass interposer 1, ensuring that there is no structural interference between the piezoresistive strip 121 and the glass interposer 1.

[0041] Figure 21 The diagram shows a planar structure of the piezoresistive strip 121 and the TGV through hole 2, clarifying the arrangement of the piezoresistive strip 121 and the positional correspondence of the TGV through hole 2, ensuring that the signal lead-out end of the piezoresistive strip 121 can be electrically connected to the TGV through hole 2 through subsequent processes.

[0042] Figure 22 The diagram shows contact windows 13 etched at both ends of the piezoresistive strip 121. The contact windows 13 need to fully expose the metal contact area of ​​the piezoresistive strip 121 to lay the foundation for the subsequent connection of the metal leads 141.

[0043] Figure 23 The diagram shows the differentiated design of the contact window 13 of the piezoresistive strip 121. The small contact window at position 131 is for connecting to the Wheatstone bridge, while the large contact window at position 132 is for connecting to the TGV via 2. By differentiating the window sizes, the signal transmission accuracy of the Wheatstone bridge is taken into account, while the stability of the interconnection with the TGV via 2 is improved. Here, the circular and square shapes are used to simply distinguish the two types of contact window structures.

[0044] It should be noted that the differences in contact windows 13 for different connections are mainly determined by current density and process reliability. The small contact window 131 used for the Wheatstone bridge connection mainly functions to connect the piezoresistive strip to form the four arms of the bridge. The sensing signal current carried by these connection points is in the microampere range, with low current density. On the other hand, the large contact window 132 used for the connection with the TGV via 2 mainly functions as the "interface" between the RDL redistribution layer and the TGV. It is the channel for power current and output signal, and the contact resistance needs to be reduced and the current carrying capacity increased by opening the window area.

[0045] In this embodiment, the contact windows are designed with different sizes. The contact windows for connecting the Wheatstone bridge are 2μm x 2μm to 5μm x 5μm in size, and the contact windows for connecting the TGV vias are 20μm x 20μm to 50μm x 50μm in size. The positions of the contact windows correspond to the pre-positioning of the metal lines subsequently fabricated on the surface of the glass interposer to ensure the reliability of the electrical connection between the piezoresistive reference sensor and the TGV via.

[0046] Figure 24 The diagram shows the structure of an Al / TiN metal layer deposited by sputtering, with metal leads 141 formed by photolithography and etching of the metal layer 14. The endpoints of the piezoresistive strip 121 are connected by the metal leads 141 to form a Wheatstone bridge structure.

[0047] Figure 25 The diagram shows a planar structure of the Wheatstone bridge and the TGV via 2. The metal lead 141 connects the endpoints of the piezoresistive strip 121 to form a complete bridge circuit. At the same time, the Wheatstone bridge leads are electrically connected to the TGV via 2 to ensure that the bridge signal can be transmitted outward through the TGV via 2.

[0048] Figure 26 As shown, on the surface of the glass interposer 1 of the pre-fabricated piezoresistive reference sensor 3, metal lines 8 are fabricated in other areas not covered by the piezoresistive reference sensor 3 using sputtering electroplating, photolithography and metal etching processes. One end of the metal line 8 is precisely connected to the signal lead-out terminal of the piezoresistive reference sensor 3, and the other end is connected to the metallized filling portion of the TGV via 2 on the glass interposer 1, thus constructing an independent and stable signal transmission path between the piezoresistive reference sensor 3 and the TGV via 2.

[0049] Figure 27 The image shown is in Figure 26 Based on this, the layout of the metal circuit 8 was expanded, and a new branch was added to connect with the pad 19 of the main sensor 4, thus finally constructing a signal transmission path between the main sensor 4, the piezoresistive reference sensor 3 and the TGV via 2.

[0050] Figure 28 The diagram shows the overall encapsulation process performed on the bonding structure after the sensor mounting and metal circuit layout are completed, forming an encapsulated structure 5 that covers the main sensor 4 and the piezoresistive reference sensor 3.

[0051] Figure 29The diagram shows the precise processing of the encapsulated structure 5 using laser drilling technology. The drilling path is preset according to the positions of the main sensor 4 and the piezoresistive reference sensor 3. Interconnect holes 6 are processed in the encapsulated layer 51 corresponding to the areas where the two need to be electrically interconnected. During the drilling process, the laser parameters are precisely controlled to ensure that the bottom of the interconnect hole 6 corresponds to the preset area of ​​the sensor pad and to avoid damaging the internal sensitive structure of the sensor.

[0052] Figure 30 and Figure 31 The diagram shows the sequential metallization process performed on the interconnect hole 6 and the glass interposer. First, the residual molding compound debris on the wall of the interconnect hole 6 is removed by a descaling process. Then, a seed layer is deposited by sputtering. After electroplating and surface smoothing, a matrix hole interconnect structure 9 that penetrates the molding layer 51 is finally formed. The matrix hole interconnect structure 9 includes metallized holes 7 filled in the interconnect hole 6, and metal lines 8 in other areas of the glass interposer connecting the metallized holes 7 and the TGV via 2, so as to achieve efficient electrical conduction between the main sensor 4, the piezoresistive reference sensor 3 and the TGV via 2.

[0053] Figure 32 The diagram shows a secondary molding and reinforcement process for the package. A molding compound is applied again to the outside of the already formed molding structure 5 and cured, resulting in a uniform increase in the thickness of the molding layer 51. This further enhances the protection of the internal matrix via interconnect structure 9, the sensor, and the metal wiring 8. Figure 33 The diagram illustrates the two-dimensional planar heterogeneous integration of the main sensor 4 and the ASIC signal processing chip 15. Following the aforementioned steps, a glass interposer 1 with a piezoresistive reference sensor 3 and metal circuitry 8 is fabricated. The ASIC signal processing chip 15 is then mounted on a predetermined area of ​​the glass interposer. The pins of the ASIC signal processing chip 15 are precisely aligned with and soldered to the metal circuitry 8 on the glass interposer 1, achieving electrical connection between the main sensor 4, the piezoresistive reference sensor 3, and the ASIC signal processing chip 15.

[0054] Figure 34 The diagram illustrates the three-dimensional heterogeneous integration of the main sensor 4 and the ASIC signal processing chip 15. During the fabrication of the glass interposer, a vertical interconnect channel, TGV via 2, is reserved. The ASIC signal processing chip 15 is bonded to the lower surface of the glass interposer 1 using a bonding process. Electrical connections are achieved between the TGV via 2 and the main sensor 4 chip and the piezoresistive reference sensor 3 on the upper surface. This structure fully utilizes vertical space, significantly improves integration density, reduces parasitic effects, and is suitable for the high-density and miniaturization requirements of precision equipment.

[0055] The above embodiments propose an integrated packaging solution centered on a glass interposer, combining matrix via interconnect technology, a piezoresistive reference sensor, and heterogeneous integration. This solution effectively decouples and isolates target stress from non-target stress, achieves real-time stress compensation through the reference sensor, and enhances product integration through heterogeneous integration. This solution can meet the high-precision main sensor requirements of Industry 4.0, smart manufacturing, advanced robotics, aerospace, and precision medical equipment, and its production cost is lower than that of 2.5D advanced packaging technology based on silicon interposers, demonstrating significant practical value and industrialization prospects.

Claims

1. A stress decoupling sensor packaging method based on a glass interlayer, characterized in that, include: S1, Prepare the glass substrate; S2, through-hole TGV via (2) is processed on the glass substrate, and the TGV via (2) is metallized and filled to form a glass interlayer (1) with the glass substrate as the bearing substrate and the TGV via (2) as the vertical interconnection channel. S3, a piezoresistive reference sensor (3) is fabricated in a preset area on the surface of the glass interlayer (1) that is not covered by the subsequent main sensor (4). S4, apply conductive adhesive to the preset chip mounting area on the surface of the glass interposer (1), and bond the main sensor (4) pad (19) upward to the conductive adhesive to form a bonding structure including the glass interposer (1), TGV via (2), piezoresistive reference sensor (3) and main sensor (4). S5, the bonding structure is encapsulated to obtain a plastic-encapsulated structure (5) that completely covers the main sensor (4) and the piezoresistive reference sensor (3) and is tightly attached to the surface of the glass interlayer (1). S6, using laser drilling technology to process interconnection holes (6) at the electrical interconnection positions of the main sensor (4) and the piezoresistive reference sensor (3) in the encapsulated structure (5). S7, the area of ​​the interconnect hole (6) and the surface of the glass interlayer (1) not covered by the encapsulation layer (51), the main sensor (4) and the piezoresistive reference sensor (3) is metallized to form a matrix hole interconnect structure (9) that penetrates the encapsulation layer (51).

2. The stress decoupling sensor packaging method based on a glass interposer layer according to claim 1, characterized in that, In step S4, the distance between the piezoresistive reference sensor (3) and the main sensor (4) on the surface of the glass interlayer (1) is set to 400um-2mm, and the direction of the center line connecting the two is perpendicular to the distribution direction of the TGV through hole (2) in the glass interlayer (1).

3. The stress decoupling sensor packaging method based on a glass interposer layer according to claim 1, characterized in that, In step S7, the matrix via interconnect structure (9) includes a metallized via (7) filled in the interconnect via (6), and a metal line (8) disposed on the surface of the glass interposer (1) and connecting the metallized via (7) and the TGV via (2). One end of the metallized via (7) is connected to the chip pad (19) of the main sensor (4) or the signal lead of the piezoresistive reference sensor (3), and the other end is connected to one end of the metal line (8); the other end of the metal line (8) is connected to the metallized filling portion of the TGV via (2) that is disposed through the glass interposer (1), thereby realizing the electrical conduction between the main sensor (4), the piezoresistive reference sensor (3) and the TGV via (2).

4. The stress decoupling sensor packaging method based on a glass interposer layer according to claim 2, characterized in that, In step S3, the formation of the piezoresistive reference sensor (3) specifically includes the following steps: S01, provide an SOI wafer (10), and bond the active surface (top silicon surface) of the SOI wafer (10) to the glass interposer (1) that has completed the fabrication of the TGV via (2); S02, the substrate silicon (111) and buried oxide layer (112) of the SOI wafer (10) are removed in sequence, so that the remaining top monocrystalline silicon thin film (113) is attached to a preset area on the surface of the glass interposer (1); S03, a varistor (12) is prepared on the top single crystal silicon thin film (113) by ion implantation and high-temperature annealing; S04, the top single-crystal silicon thin film is etched by photolithography and dry etching (113), retaining the part that forms the piezoresistive strip (121), and removing the rest of the area; S05, etch contact windows (13) at both ends of the piezoresistive strip (121) and deposit a metal layer (14) on the surface of the glass interlayer (1). S06, the lead path is marked on the metal layer (14) by photolithography, and excess metal is etched away to form metal leads (141). The endpoints of the piezoresistive strip (121) are connected through the metal leads (141) to form a Wheatstone bridge, thus obtaining the piezoresistive reference sensor (3).

5. The stress decoupling sensor packaging method based on a glass interposer as described in claim 4, characterized in that, The SOI wafer (10) includes, from bottom to top, a substrate silicon (111), a buried oxide layer (112, silicon dioxide), and a top monocrystalline silicon thin film (113). The substrate silicon (111) is first thinned to a preset thickness by mechanical polishing, and then selectively removed by KOH or TMAH wet etching. The etching process uses the buried oxide layer (112) as the stop layer. The buried oxide layer (112) is selectively removed by buffer oxide etching or hydrofluoric acid vapor etching. The etching process uses the top monocrystalline silicon thin film (113) as the stop layer.

6. The stress decoupling sensor packaging method based on a glass interposer as described in claim 4, characterized in that, In step S05, the contact window (13) adopts a size differentiation design. The contact window (131) used to connect the Wheatstone bridge and the contact window (132) used to connect the TGV through hole (2) meet the preset size relationship. The size of the contact window (131) is 2μmx2μm-5μmx5μm, and the side length of the contact window (132) is 20μmx20μm-50μmx50μm. The position of the contact window (132) corresponds to the pre-positioned metal line (8) subsequently fabricated on the surface of the glass interposer (1) to ensure the reliability of the electrical connection between the piezoresistive reference sensor (3) and the TGV through hole (2).

7. The stress decoupling sensor packaging method based on a glass interposer layer according to claim 2, characterized in that, Both the main sensor (4) and the piezoresistive reference sensor (3) are constructed using a piezoresistive resistor (12) to form a Wheatstone bridge. The piezoresistive resistor (12) is prepared by transferring the top single-crystal silicon thin film (113) of the SOI wafer (10) to the surface of the glass interlayer (1).

8. The stress decoupling sensor packaging method based on a glass interposer as described in claim 7, characterized in that, The glass interlayer (1) is made of borosilicate glass or Corning glass, and the mismatch between the glass interlayer (1) and silicon in terms of coefficient of thermal expansion (CTE) is controlled within 1-3 ppm / °C.

9. The stress decoupling sensor packaging method based on a glass interposer as described in claim 1, characterized in that, During laser drilling in step S6, by adjusting the laser power and drilling depth, a 4-6 μm thick plastic sealant residue (21) is left above the pad (19) of the main sensor (4).

10. A stress-decoupling sensor packaging structure based on a glass interlayer, comprising: The structure comprises a glass interposer (1), a main sensor (4), a piezoresistive reference sensor (3), a molding compound (51), a matrix via interconnect (9), and TGV vias (2). The TGV vias (2) penetrate the glass interposer (1) and are metallized to form vertical interconnect channels. The piezoresistive reference sensor (3) is fabricated on the surface of the glass interposer (1), and the main sensor (4) is attached to the surface of the glass interposer (1) via a conductive adhesive layer, with the two spaced 400µm-2mm apart. The molding compound... The structure (5) covers the main sensor (4) and the piezoresistive reference sensor (3), and the bottom surface is attached to the glass interlayer (1); the matrix hole interconnection structure (9) is embedded in the molding layer (51), including the metallized hole (7) that penetrates the molding layer (51) and connects the pad (19) of the main sensor (4) and the signal lead of the piezoresistive reference sensor (3), and the metal line (8) arranged on the surface of the glass interlayer (1) and connecting the metallized hole (7) and the TGV through hole (2) to realize the electrical conduction of the three.

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