Semiconductor packaging structure and packaging method
The semiconductor packaging structure, which uses a glass substrate and bump bonding, solves the problems of low connection density and poor reliability in the prior art, and realizes high-density, high-reliability chip packaging, while reducing packaging height and warpage stress.
Patent Information
- Application Number
- CN202511799360.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-02
- Publication Date
- 2026-02-27
AI Technical Summary
In existing chip packaging processes, the connection density of organic substrates and forward mounting is low, resulting in poor reliability. Furthermore, the sealant can cause stress on the chip, leading to connection failure.
By using glass substrates and bump bonding to eliminate wire bonding, multi-dimensional chip packaging is achieved through through-hole design of the first and second substrates, and the connection density and reliability are improved by combining the RDL layer.
It improves chip integration and connection reliability, reduces package height, avoids warping stress caused by sealant, and improves package yield and space utilization.
Smart Images
Figure CN121586503A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a packaging method. BACKGROUND
[0002] In the existing chip packaging process or structure, an organic substrate is mostly used, the chip is mounted in a forward direction, and is connected to the organic substrate through wire bonding. The connection density of the wire bonding is low, and the reliability is low. After wire bonding, sealing glue is used to protect the wire bonding, and the sealing glue will generate a large stress on the chip, which can easily cause the connection between the wire bonding and the chip to fail. SUMMARY
[0003] The purpose of the present application is to provide a semiconductor packaging structure and a packaging method, which have high chip integration and compact structure, and reliable connection.
[0004] In a first aspect, the present application provides a semiconductor packaging structure, comprising: a first substrate, two sides of the first substrate are respectively provided with a first connecting part and a second connecting part; the first substrate is provided with a first conductive column penetrating through the first substrate, one end of the first conductive column is electrically connected with the first connecting part, and the other end is electrically connected with the second connecting part; the first connecting part comprises a first bump and a second bump located at the periphery of the first bump; a second substrate, two sides of the second substrate are respectively provided with a third bump and a fourth bump; the second substrate is provided with a second conductive column penetrating through the second substrate, one end of the second conductive column is electrically connected with the third bump, and the other end is electrically connected with the fourth bump; the second substrate is provided with a through hole penetrating through the second substrate, the second substrate is stacked on the first substrate, the second bump and the third bump are electrically connected, and the through hole exposes the first bump; a first chip, the first chip is arranged in the through hole, and the first chip is electrically connected with the first bump; a second chip, the second chip is arranged on a side of the second substrate away from the first substrate, the second chip is electrically connected with the fourth bump, and the second chip covers the through hole.
[0005] In an optional embodiment, the first substrate and the second substrate are respectively made of a glass substrate.
[0006] In an optional embodiment, one side of the first substrate is provided with a first RDL layer, the first RDL layer is electrically connected with the first connecting part; the other side of the first substrate is provided with a second RDL layer, the second RDL layer is electrically connected with the second connecting part; and the two ends of the first conductive column are respectively electrically connected with the first RDL layer and the second RDL layer.
[0007] In an optional embodiment, a third RDL layer is provided on one side of the second substrate, and the third RDL layer is electrically connected to the third bump; a fourth RDL layer is provided on the other side of the second substrate, and the fourth RDL layer is electrically connected to the fourth bump; the two ends of the second conductive post are respectively electrically connected to the third RDL layer and the fourth RDL layer.
[0008] In an optional embodiment, the first chip includes a plurality of chips arranged side by side in the through hole, and each first chip is electrically connected to the first bump.
[0009] In an optional embodiment, a third chip is further included, which is stacked on the side of the first chip away from the first substrate and located within the through-hole; the third chip is electrically connected to the first chip or the second chip.
[0010] In an optional embodiment, the second chip has a third connection portion on the side facing the first chip, the third chip is electrically connected to the third connection portion, and the first chip and the third chip are mounted back to back. Alternatively, the first chip may have a through-hole first conductive via, and the third chip may have a through-hole second conductive via, with the first conductive via and the second conductive via electrically connected; the first conductive via is electrically connected to the first bump.
[0011] In an optional embodiment, a fourth chip is further included, which is stacked on the side of the second chip away from the first substrate, and the fourth chip is electrically connected to the second chip, or the fourth chip is electrically connected to the first substrate or the second substrate.
[0012] In an optional embodiment, a fifth bump is provided on the first substrate, located around the second bump, and the fourth chip is electrically connected to the fifth bump.
[0013] In an optional embodiment, a protective adhesive is also included, with the protective adhesive provided at the solder joints of the first substrate and the first chip, and at the solder joints of the first substrate and the second substrate.
[0014] Secondly, the present invention provides a packaging method, comprising: A first substrate is provided, and a first connecting portion and a second connecting portion are respectively provided on both sides of the first substrate; the first substrate is provided with a through first conductive post, one end of the first conductive post is electrically connected to the first connecting portion, and the other end is electrically connected to the second connecting portion; the first connecting portion includes a first protrusion and a second protrusion located around the first protrusion. A second substrate is provided, wherein a third protrusion and a fourth protrusion are respectively provided on both sides of the second substrate; a second conductive post is provided through the second substrate, one end of the second conductive post is electrically connected to the third protrusion, and the other end is electrically connected to the fourth protrusion; and a through hole is provided in the second substrate. The second substrate is bonded to the first substrate; the second bump and the third bump are electrically connected; the through hole exposes the first bump; A first chip is mounted to the first substrate, the first chip is disposed in the through hole, and the first chip is electrically connected to the first bump. A second chip is mounted to the second substrate. The second chip is located on the side of the second substrate away from the first substrate. The second chip is electrically connected to the fourth bump and the second chip is covered by the through hole.
[0015] In an optional embodiment, the first substrate and the second substrate are both glass substrates; in the step of bonding the second substrate to the first substrate, a wafer-level or panel-level bonding process is used.
[0016] The semiconductor packaging structure and packaging method provided in this invention have the following beneficial effects: The first and second substrates are connected by bump bonding, which offers high reliability, eliminates the need for wire bonding, and results in a compact structure. It also avoids the use of sealant to protect wire bonding structures in traditional processes, mitigating warpage stress. Furthermore, the first chip is located within a through-hole in the second substrate, contributing to a compact structure, reduced overall package thickness, and higher connection density. The second chip is positioned on the side of the second substrate furthest from the first substrate, improving chip integration. Attached Figure Description
[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a first type of semiconductor packaging structure provided in an embodiment of the present invention; Figure 2 A schematic diagram of a first substrate of a semiconductor packaging structure provided in an embodiment of the present invention; Figure 3 A schematic diagram of the first substrate of the semiconductor packaging structure provided in an embodiment of the present invention from another perspective; Figure 4A schematic diagram of a second substrate of a semiconductor packaging structure provided in an embodiment of the present invention; Figure 5 A schematic diagram of the second substrate of the semiconductor packaging structure provided in an embodiment of the present invention from another perspective; Figure 6 This is a schematic diagram of a second semiconductor packaging structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a third type of semiconductor packaging structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of a fourth semiconductor packaging structure provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the fifth type of semiconductor packaging structure provided in the embodiments of the present invention; Figure 10 This is one of the process schematic diagrams of a semiconductor packaging structure provided in an embodiment of the present invention; Figure 11 This is a second schematic diagram of the manufacturing process of a semiconductor packaging structure provided in an embodiment of the present invention.
[0019] Icons: 100 - Semiconductor package structure; 110 - First substrate; 111 - First connector; 112 - First bump; 113 - Second bump; 114 - Second connector; 115 - First conductive pillar; 116 - First RDL layer; 117 - Second RDL layer; 118 - Fifth bump; 120 - Second substrate; 121 - Third bump; 122 - Fourth bump; 123 - Second conductive pillar; 124 - Third RDL layer; 125 - Fourth RDL layer; 126 - Through-hole; 131 - First chip; 132 - Protective adhesive; 133 - Second chip; 1331 - RDL layer; 134 - Third connector; 135 - Third chip; 136 - First conductive via; 137 - Second conductive via; 138 - Fourth chip. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0023] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0024] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0025] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0026] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0027] The semiconductor packaging structure proposed in this invention can realize multi-dimensional packaging of chips, improve packaging integration, reduce packaging height, alleviate warpage stress, and improve packaging reliability.
[0028] Please combine Figures 1 to 5The semiconductor package structure 100 includes a first substrate 110, a second substrate 120, a first chip 131, and a second chip 133. A first connecting portion 111 and a second connecting portion 114 are respectively provided on both sides of the first substrate 110. A through-hole first conductive post 115 is provided on the first substrate 110, with one end electrically connected to the first connecting portion 111 and the other end electrically connected to the second connecting portion 114. The first connecting portion 111 includes a first bump 112 and a second bump 113 located around the first bump 112. A third bump 121 and a fourth bump 122 are respectively provided on both sides of the second substrate 120; a through-hole second conductive post 123 is provided on the second substrate 120, with one end electrically connected to the third bump 121 and the other end electrically connected to the fourth bump 122. The second substrate 120 has a through hole 126 and is stacked on the first substrate 110. The second bump 113 and the third bump 121 are electrically connected. The through hole 126 exposes the first bump 112. The first chip 131 is disposed in the through hole 126 and is electrically connected to the first bump 112. The second chip 133 is disposed on the side of the second substrate 120 away from the first substrate 110 and is electrically connected to the fourth bump 122. The second chip 133 covers the through hole 126.
[0029] The first substrate 110 and the second substrate 120 are bonded together, employing wafer-level or panel-level packaging processes, resulting in high connection efficiency. Electrical connection is achieved through bump soldering, ensuring reliable connection and a compact structure, which helps reduce package height. Furthermore, the elimination of wire bonding and the sealing adhesive protecting the wires mitigates warpage stress and avoids connection failures caused by adhesive stress tension, thus improving packaging yield. The second substrate 120 has a through-hole 126, facilitating the installation of the first chip 131 and providing protection for it. This also reduces the mounting height of the first chip 131, saving space, lowering the overall package height, resulting in a more compact structure and higher space utilization.
[0030] Optionally, the first substrate 110 and the second substrate 120 are both made of glass substrates. Glass substrates have high structural strength and rigidity, and are not easily warped or deformed. Furthermore, the coefficients of thermal expansion between glass and the chip are more closely matched, resulting in lower stress and higher reliability. Glass substrates allow for a smaller overall package thickness and can reduce the overall package height, enabling miniaturized, high-density packaging. The relatively flat surface of the glass substrate provides a natural advantage for the fabrication of high-density redistribution layers, which helps to reduce the overall package size and improve interconnect density and chip integration.
[0031] Optionally, a first RDL (ReDistributed Layer) is provided on one side of the first substrate 110, and the first RDL layer 116 is electrically connected to the first connection portion 111; a second RDL layer 117 is provided on the other side of the first substrate 110, and the second RDL layer 117 is electrically connected to the second connection portion 114; the two ends of the first conductive post 115 are respectively electrically connected to the first RDL layer 116 and the second RDL layer 117. By setting the first RDL layer 116 and the second RDL layer 117, the position and number of bumps can be redistributed, which is beneficial to improving the connection density and connection reliability. The glass substrate surface is flat, not prone to warping, and has low stress, which is beneficial to improving the RDL wiring accuracy and increasing the packaging yield.
[0032] Optionally, a third RDL layer 124 is provided on one side of the second substrate 120, and the third RDL layer 124 is electrically connected to the third bump 121; a fourth RDL layer 125 is provided on the other side of the second substrate 120, and the fourth RDL layer 125 is electrically connected to the fourth bump 122; the two ends of the second conductive post 123 are electrically connected to the third RDL layer 124 and the fourth RDL layer 125, respectively. Similarly, the third RDL layer 124 and the fourth RDL layer 125 can redistribute the position and number of bumps on the second substrate 120, which is beneficial to improving the connection density and connection reliability.
[0033] Of course, in some implementations, one or more of the first RDL layer 116, the second RDL layer 117, the third RDL layer 124, and the fourth RDL layer 125 may be selectively omitted according to actual mounting needs.
[0034] Optionally, the first bumps 112 and the second bumps 113 on the first substrate 110 are arranged in an array. The first conductive pillars 115 and the second conductive pillars 123 are fabricated using a TGV (Through Glass Via) process. In this embodiment, the second bumps 113 and the third bumps 121 are arranged in a one-to-one correspondence and are bonded together, facilitating panel-level or wafer-level bonding, improving bonding efficiency, and reducing costs. It should be noted that the second bumps 113 and the third bumps 121 fuse together after welding to form a solder joint. In the overall illustration of the package structure, only one structure of the second bumps 113 and the third bumps 121 is shown.
[0035] In this embodiment, the through-hole 126 on the second substrate 120 is laser-cut to reduce damage to the second substrate 120 and improve cutting efficiency and packaging yield. It can be understood that the third bump 121 is located around the through-hole 126. After the first substrate 110 and the second substrate 120 are bonded together, the first bump 112 is exposed from the through-hole 126.
[0036] The first chip 131 is mounted on the first substrate 110 and located within the through-hole 126. The first chip 131 and the first bump 112 are electrically connected. In this embodiment, the first bump 112 and the pads on the first chip 131 are bonded by bump bonding, that is, the first chip 131 is flip-chip.
[0037] Optionally, when mounting the first chip 131, an adhesive or a mixture of adhesive and organic acid can be used. The adhesive will cure at the bonding high temperature to protect the solder joints at the bonding point between the first chip 131 and the first bump 112. If non-conductive adhesive is not used to protect the solder joints during the mounting of the first chip 131, additional protective adhesive 132 can be applied after mounting for underfilling to protect the solder joints.
[0038] Of course, in some implementations, the first chip 131 can also be mounted upright and electrically connected to the first bump 112 via wire bonding, which is not specifically limited here.
[0039] It's easy to understand that the number and type of the first chip 131 are unlimited; there can be one or more. Please refer to... Figure 1 The image shows a first chip 131 inside a through-hole. The first chip 131 and the first bump 112 are flip-chip bonded together.
[0040] If there are multiple first chips 131, they can be arranged side by side or stacked. Please refer to... Figure 6 Multiple first chips 131 are arranged side by side within the through hole 126, and each first chip 131 is electrically connected to a first bump 112. The gaps between the multiple first chips 131 can be filled with thermally conductive adhesive to improve heat dissipation performance.
[0041] Please combine Figure 7 Multiple chips are stacked within the through-hole 126. Optionally, the semiconductor package structure 100 further includes a third chip 135, which is stacked on the side of the first chip 131 away from the first substrate 110, and both the third chip 135 and the first chip 131 are located within the through-hole 126. The third chip 135 is electrically connected to either the first chip 131 or the second chip 133.
[0042] Optionally, the second chip 133 has a third connecting portion 134 on the side facing the first chip 131, and the third chip 135 is electrically connected to the third connecting portion 134. The first chip 131 and the third chip 135 are mounted back-to-back. The first chip 131 and the third chip 135 can be bonded and fixed together using an adhesive such as DAF glue. The third connecting portion 134 can be a solder pad or a bump.
[0043] Please combine Figure 8The first chip 131 has a through-hole first conductive via 136, and the third chip 135 has a through-hole second conductive via 137. The first conductive via 136 and the second conductive via 137 are electrically connected; the first conductive via 136 is electrically connected to the first bump 112. That is, the third chip 135 is electrically connected to the first chip 131 through the conductive via. By setting the third chip 135, it is beneficial to improve the chip integration and enrich the functionality of the package structure.
[0044] In some implementations, the third chip 135 is stacked on multiple first chips 131. For example, two first chips 131 are respectively connected to the first bump 112, and the third chip 135 is stacked on the two first chips 131 respectively, i.e., in-place stacking. Alternatively, one third chip 135 can be simultaneously connected to two first chips 131, i.e., staggered stacking. Both can improve integration and have similar technical effects, and no specific limitation is made here.
[0045] Please combine Figure 9 Optionally, the semiconductor package structure 100 further includes a fourth chip 138, which is stacked on the side of the second chip 133 away from the first substrate 110. The fourth chip 138 and the second chip 133 are electrically connected, or the fourth chip 138 is electrically connected to either the first substrate 110 or the second substrate 120. It is understood that if the fourth chip 138 and the second chip 133 are electrically connected, the electrical connection between the first chip 131 and the third chip 135 can be achieved through conductive vias.
[0046] Optionally, if the fourth chip 138 and the first substrate 110 are electrically connected, the first substrate 110 is provided with a fifth bump 118 located around the second bump 113, and the fourth chip 138 and the fifth bump 118 are electrically connected by wire bonding.
[0047] Similarly, if the fourth chip 138 is electrically connected to the second substrate 120, and the second substrate 120 has a sixth bump located around the third bump 121, the fourth chip 138 and the sixth bump are electrically connected by wire bonding. The inclusion of the fourth chip 138 further enhances chip integration and increases packaging density.
[0048] It should be noted that the quantity and type of the third chip 135 and the fourth chip 138 are not limited, and their mounting quantity and position can be flexibly adjusted according to actual needs.
[0049] Optionally, protective adhesive 132 is provided at the solder joints of the first substrate 110 and the first chip 131, as well as at the solder joints of the first substrate 110 and the second substrate 120. This can protect the solder joint structure, improve insulation performance, and prevent short circuits caused by bump bridging.
[0050] In this embodiment, the second connection part 114 forms solder balls through a ball-planting process, which can be used for electrical connection with external modules such as circuit boards or other modules.
[0051] Optionally, the second chip 133 is provided with an RDL layer 1331. It should be noted that providing an RDL layer on the chip can better match and connect with other chips or substrates. In this embodiment, the first chip 131 is provided with an RDL layer, and the third chip 135 and the fourth chip 138 may also selectively be provided with RDL layers, which is not specifically limited here.
[0052] Please combine Figures 10 to 11 The present invention also provides a packaging method, which mainly includes the following steps: Step S1: Provide a first substrate 110. The first substrate 110 is a glass substrate. A first connecting portion 111 and a second connecting portion 114 are respectively provided on both sides of the first substrate 110; the first substrate 110 has a through-hole first conductive post 115, one end of which is electrically connected to the first connecting portion 111, and the other end is electrically connected to the second connecting portion 114; the first connecting portion 111 includes a first bump 112 and a second bump 113 located around the first bump 112. Optionally, a first RDL layer 116 and a second RDL layer 117 are respectively provided on both sides of the first substrate 110, and the two ends of the first conductive post 115 are electrically connected to the first RDL layer 116 and the second RDL layer 117 respectively, to improve connection density and integration. The first bump 112 and the second bump 113 are respectively connected to the first RDL layer 116.
[0053] Step S2: Provide a second substrate 120, which is a glass substrate. The second substrate 120 has a third bump 121 and a fourth bump 122 on both sides. The second substrate 120 has a through-hole second conductive post 123, one end of which is electrically connected to the third bump 121, and the other end is electrically connected to the fourth bump 122. The second substrate 120 has a through-hole 126. Optionally, the second substrate 120 has a third RDL layer 124 and a fourth RDL layer 125 on both sides. The two ends of the second conductive post 123 are electrically connected to the third RDL layer 124 and the fourth RDL layer 125 respectively, to improve connection density and integration. The third bump 121 is connected to the third RDL layer 124, and the fourth bump 122 is connected to the fourth RDL layer 125.
[0054] Step S3: Bond the second substrate 120 to the first substrate 110. Optionally, the side of the second substrate 120 with the third bump 121 is bonded to the side of the first substrate 110 with the first bump 112 and the second bump 113. The second bump 113 and the third bump 121 are electrically connected, and the first bump 112 is exposed through a through-hole 126. This bonding step uses wafer-level or panel-level bonding processes, which helps improve packaging efficiency and reduce costs. It also facilitates alignment and improves packaging accuracy.
[0055] Step S4: Mount the first chip 131 onto the first substrate 110. The first chip 131 is disposed within the through-hole 126, and the first chip 131 is electrically connected to the first bump 112. The bump bonding connection is reliable, compact, and helps reduce package height. Furthermore, bump bonding shortens the electrical path, improves transmission efficiency, and reduces transmission loss.
[0056] Optionally, a protective adhesive 132 is formed on one side of the first substrate 110 having the first bump 112 and the second bump 113 to protect the bonded solder joint structure and improve connection reliability.
[0057] Step S5: Mount the second chip 133 onto the second substrate 120. The second chip 133 is located on the side of the second substrate 120 away from the first substrate 110. The second chip 133 is electrically connected to the fourth bump 122, and the second chip 133 is covered by a through-hole 126. The stacking design of the second chip 133 further improves the chip integration.
[0058] Optionally, a ball-mounting process is performed on the side of the first substrate 110 away from the second substrate 120 to prepare the second connection portion 114 of the first substrate 110, i.e., the solder ball structure. Of course, this step can also be performed in step S1, and is not specifically limited here.
[0059] Because wafer-level or panel-level processes are used, the final packaging structure is cut into individual products to complete the manufacturing process.
[0060] In summary, the semiconductor packaging structure 100 and packaging method provided by the embodiments of the present invention have the following beneficial effects, including: The first substrate 110 and the second substrate 120 are connected by bump bonding, which offers high reliability, eliminates the need for wire bonding, and results in a compact structure. This also avoids the use of sealant to protect wire bonding structures in traditional processes, mitigating warpage stress. Secondly, the first chip 131 is located within the through-hole 126 of the second substrate 120, contributing to a compact structure, reducing the overall package height, and increasing connection density. The second chip 133 is located on the side of the second substrate 120 away from the first substrate 110, improving chip integration. Both the first substrate 110 and the second substrate 120 are made of glass substrates, which offer high rigidity and are less prone to warpage. Furthermore, the thermal expansion coefficients of the glass material and the chip are more closely matched, resulting in lower stress and higher reliability. In addition, the glass substrate has a relatively flat surface, allowing for the fabrication of high-density RDLs and reducing the size of the package structure. The integration of the third chip 135, the fourth chip 138, and others further enhances chip integration and makes the structure even more compact.
[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.
Claims
1. A semiconductor package structure, comprising: The application relates to a chip structure, which comprises the following parts: a first substrate (110) provided with a first connecting part (111) and a second connecting part (114) on two sides respectively; the first substrate (110) is provided with a first conductive column (115) penetrating through the first substrate (110), one end of the first conductive column (115) is electrically connected with the first connecting part (111), and the other end is electrically connected with the second connecting part (114); the first connecting part (111) comprises a first bump (112) and a second bump (113) located at the periphery of the first bump (112); a second substrate (120) provided with a third bump (121) and a fourth bump (122) on two sides respectively; the second substrate (120) is provided with a second conductive column (123) penetrating through the second substrate (120), one end of the second conductive column (123) is electrically connected with the third bump (121), and the other end is electrically connected with the fourth bump (122); the second substrate (120) is provided with a through hole (126) penetrating through the second substrate (120), the second substrate (120) is stacked on the first substrate (110), the second bump (113) and the third bump (121) are electrically connected, and the through hole (126) exposes the first bump (112); a first chip (131) arranged in the through hole (126), and the first chip (131) is electrically connected with the first bump (112); a second chip (133) arranged on the side, away from the first substrate (110), of the second substrate (120), the second chip (133) is electrically connected with the fourth bump (122), and the second chip (133) covers the through hole (126).
2. The semiconductor package structure of claim 1, wherein, The first substrate (110) and the second substrate (120) are respectively made of a glass substrate.
3. The semiconductor package structure of claim 1, wherein, One side of the first substrate (110) is provided with a first RDL layer (116), the first RDL layer (116) is electrically connected with the first connecting part (111); the other side of the first substrate (110) is provided with a second RDL layer (117), the second RDL layer (117) is electrically connected with the second connecting part (114); and the two ends of the first conductive column (115) are respectively electrically connected with the first RDL layer (116) and the second RDL layer (117).
4. The semiconductor package structure of claim 1, wherein, One side of the second substrate (120) is provided with a third RDL layer (124), the third RDL layer (124) is electrically connected with the third bump (121); the other side of the second substrate (120) is provided with a fourth RDL layer (125), the fourth RDL layer (125) is electrically connected with the fourth bump (122); and the two ends of the second conductive column (123) are respectively electrically connected with the third RDL layer (124) and the fourth RDL layer (125).
5. The semiconductor package structure of claim 1, wherein, The first chip (131) includes a plurality of first chips (131) arranged side by side in the through hole (126), and each first chip (131) is electrically connected with the first bump (112) respectively.
6. The semiconductor package structure of claim 1, wherein, A third chip (135) is further included, which is arranged in a stack on a side of the first chip (131) away from the first substrate (110) and located in the through hole (126); the third chip (135) is electrically connected with the first chip (131) or the second chip (133).
7. The semiconductor package structure of claim 6, wherein, A third connecting portion (134) is arranged on a side of the second chip (133) facing the first chip (131), the third chip (135) is electrically connected with the third connecting portion (134), and the first chip (131) and the third chip (135) are attached back to back; Alternatively, the first chip (131) is provided with a first conductive via (136) penetrating through, the third chip (135) is provided with a second conductive via (137) penetrating through, and the first conductive via (136) and the second conductive via (137) are electrically connected; the first conductive via (136) is electrically connected with the first bump (112).
8. The semiconductor package structure of claim 1, wherein, A fourth chip (138) is further included, which is arranged in a stack on a side of the second chip (133) away from the first substrate (110), and the fourth chip (138) is electrically connected with the second chip (133), or the fourth chip (138) is electrically connected with the first substrate (110) or the second substrate (120).
9. The semiconductor package structure of claim 8, wherein, The first substrate (110) is provided with a fifth bump (118) located at the periphery of the second bump (113), and the fourth chip (138) is electrically connected with the fifth bump (118).
10. The semiconductor package structure of any one of claims 1 to 9, wherein, A protective glue (132) is further included, and the protective glue (132) is arranged at the welding position of the first substrate (110) and the first chip (131) and the welding position of the first substrate (110) and the second substrate (120) respectively.
11. A packaging method, characterized by, It includes: A first substrate (110) is provided, and the two sides of the first substrate (110) are respectively provided with a first connecting portion (111) and a second connecting portion (114); the first substrate (110) is provided with a first conductive column (115) penetrating through, one end of the first conductive column (115) is electrically connected with the first connecting portion (111), and the other end is electrically connected with the second connecting portion (114); the first connecting portion (111) includes a first bump (112) and a second bump (113) located at the periphery of the first bump (112); A second substrate (120) is provided, two sides of the second substrate (120) are respectively provided with a third bump (121) and a fourth bump (122); the second substrate (120) is provided with a second conductive column (123) penetrating through, one end of the second conductive column (123) is electrically connected with the third bump (121), and the other end is electrically connected with the fourth bump (122); the second substrate (120) is provided with a through hole (126) penetrating through; The second substrate (120) is bonded with the first substrate (110); the second bump (113) and the third bump (121) are electrically connected; and the through hole (126) exposes the first bump (112); A first chip (131) is attached to the first substrate (110), the first chip (131) is arranged in the through hole (126), and the first chip (131) is electrically connected with the first bump (112); A second chip (133) is attached to the second substrate (120), the second chip (133) is arranged on a side of the second substrate (120) away from the first substrate (110), the second chip (133) is electrically connected with the fourth bump (122), and the second chip (133) covers the through hole (126).
12. The packaging method according to claim 11, characterized in that, The first substrate (110) and the second substrate (120) are respectively made of a glass substrate; and in the step of bonding the second substrate (120) with the first substrate (110), wafer-level or panel-level bonding is adopted.