Chip packaging interconnection structure with metal bonding and manufacturing method thereof

Abstract

The invention discloses a chip packaging interconnection structure with metal bonding and a chip packaging interconnection method.The chip packaging structure comprises a first circuit structure and a second circuit structure, the first circuit structure is provided with a first surface and first bonding areas, the first bonding areas are arranged on the first surface at intervals, and the second bonding areas are arranged on the second surface at intervals; the second circuit structure is provided with a second surface and second bonding areas, the second bonding areas are arranged on the second surface at intervals, and the first bonding areas and the second bonding areas are connected in a one-to-one correspondence mode; the first bonding area is provided with a first bonding surface facing the second bonding area, the second bonding area is provided with a second bonding surface facing the first bonding area, and the chip packaging structure comprises a nano metal layer which is in bonding connection with the first bonding surface and the second bonding surface; by optimizing materials and processes, the packaging interconnection structure and method can realize high-density interconnection of chip packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and testing, and more particularly to a chip packaging interconnect structure with metal bonding and its fabrication method. Background Technology

[0002] In existing technologies, wire bonding is used to achieve electrical connections between chips and circuit boards, which does not align with the trend towards miniaturization and thinning of chip packaging structures. To address the increasing functionality, integration, and speed of chip packaging structures, vertical connections between semiconductor chips and substrates using methods such as metal solder pillars, metal pads, and metal solder balls are widely adopted.

[0003] Direct metal bonding between metal pillars, metal pillars and metal pads, or metal pads and metal pads requires high-quality bonding surfaces. In actual processes, bonding temperature, bonding pressure, and polishing all have high requirements, resulting in high process costs. Existing technologies also typically use metal solder balls, such as solder balls electrically connecting two metal pads. However, solder balls also require high temperatures, resulting in high process costs. Furthermore, solder balls have a certain height, making it impossible to achieve ultra-small pitch connections between chips and circuit boards. Summary of the Invention

[0004] One of the objectives of this invention is to provide a chip package interconnect structure with metal bonding, so as to at least solve the technical problem of high cost of chip and substrate bonding connection process in the prior art.

[0005] One of the objectives of this invention is to provide a method for fabricating a chip package interconnect structure with metal bonding.

[0006] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip package interconnect structure with metal bonding, comprising: a first circuit structure and a second circuit structure, wherein the first circuit structure has a first surface and a first bonding region, and a plurality of the first bonding regions are arranged at intervals on the first surface; the second circuit structure has a second surface and a second bonding region, and a plurality of the second bonding regions are arranged at intervals on the second surface; the first bonding region and the second bonding region are connected in a one-to-one correspondence.

[0007] The first bonding region has a first bonding surface facing the second bonding region, and the second bonding region has a second bonding surface facing the first bonding region. The chip package interconnect structure includes a nano-metal layer, which bonds the first bonding surface and the second bonding surface together.

[0008] As a further improvement of one embodiment of the present invention, the nano-metal layer is formed by hot-pressing a nano-metal particle layer covering the first bonding surface and / or the second bonding surface, wherein the nano-metal particle layer has nanoparticles and the melting point of the nanoparticles is below 250 degrees Celsius.

[0009] As a further improvement of one embodiment of the present invention, the first bonding area is a metal sink, the first bonding surface is lower than the first surface, and the second bonding area is a metal protrusion, the second bonding surface is higher than the second surface.

[0010] Alternatively, the second bonding region is a metal sink, with the second bonding surface lower than the second surface, and the first bonding region is a metal protrusion, with the first bonding surface higher than the first surface.

[0011] As a further improvement of one embodiment of the present invention, the first bonding area is a metal flat plate, the first bonding surface is flush with the first surface, the second bonding area is a metal flat plate or a metal protrusion, and the second bonding surface is not lower than the second surface.

[0012] Alternatively, the second bonding region is a metal disc, with the second bonding surface flush with the second surface; the first bonding region is a metal disc or a metal protrusion, with the first bonding surface not lower than the first surface.

[0013] As a further improvement of one embodiment of the present invention, when the first bonding region and / or the second bonding region is a metal disk, the nano-metal layer at least covers the entire surface of the metal disk.

[0014] As a further improvement of one embodiment of the present invention, the first bonding region is a metal disk, the first surface is the surface of the dielectric layer, the second bonding region is a metal disk, the second surface is the surface of the dielectric layer, and the first surface and the second surface are bonded together.

[0015] As a further improvement of one embodiment of the present invention, the first bonding region is a metal protrusion, the first bonding surface is higher than the first surface, and / or, the second bonding region is a metal protrusion, the second bonding surface is higher than the second surface.

[0016] As a further improvement of one embodiment of the present invention, the first bonding region includes a first side surface located between the first bonding surface and the first surface, and the nano-metal layer extends from the first bonding surface to at least a portion of the first side surface; and / or, the second bonding region includes a second side surface located between the second bonding surface and the second surface, and the nano-metal layer extends from the second bonding surface to at least a portion of the second side surface.

[0017] As a further improvement of one embodiment of the present invention, a filling layer is included, the filling layer at least filling the space between the first surface and the second surface.

[0018] As a further improvement of one embodiment of the present invention, the second circuit structure includes a third bonding area disposed on a side opposite to the first circuit structure, or the first circuit structure includes a third bonding area disposed on a side opposite to the second circuit structure; the third bonding area is used for electrical connection to a circuit board.

[0019] To achieve one of the above-mentioned objectives, an embodiment of the present invention provides a method for fabricating a chip package interconnect structure with metal bonding, comprising the steps of: providing a first circuit structure having a first surface and a first bonding region, the first bonding regions being spaced apart on the first surface, and the first bonding region having a first bonding surface exposed to the first surface;

[0020] A second circuit structure is provided, having a second surface and a second bonding region, the second bonding regions being spaced apart on the second surface, and each second bonding region having a second bonding surface exposed on the second surface; the second bonding region and the first bonding region are connected in a one-to-one correspondence;

[0021] A layer of nano-metal particles is fabricated, the layer of nano-metal particles covering the first bonding surface and / or the second bonding surface;

[0022] The first bonding surface and the second bonding surface are bonded together.

[0023] As a further improvement of one embodiment of the present invention, the fabrication of the nano-metal layer includes: the fabrication of the nano-metal particle layer includes: forming the nano-metal particle layer by chemical plating or surface adsorption on the first bonding surface and / or the second bonding surface.

[0024] As a further improvement of one embodiment of the present invention, the bonding connection between the first bonding surface and the second bonding surface includes: hot-press bonding the nano-metal particle layer to the first bonding surface or the second bonding surface to form a nano-metal layer; or hot-press bonding the nano-metal particle layer on the first bonding surface and the nano-metal particle layer on the second bonding surface to form a nano-metal layer.

[0025] As a further improvement of one embodiment of the present invention, the method includes the steps of: fabricating a filling layer between the first surface and the second surface; after the first bonding region and the second bonding region are aligned and hot-pressed by fabricating the nano-metal particle layer, filling the gap between the first surface and the second surface with a bottom filler material, and heating and curing the bottom filler material to form the filling layer; wherein, one of the first bonding region and the second bonding region is a metal protrusion.

[0026] As a further improvement of one embodiment of the present invention, the method includes the steps of: fabricating a filling layer located between the first surface and the second surface, wherein one of the first bonding region and the second bonding region is a metal protrusion; firstly, covering the first surface or the second surface with a non-conductive organic layer, the thickness of the non-conductive organic layer being not less than the height of the metal protrusion; after the metal nanoparticle layer is aligned and hot-pressed to bond the first bonding region and the second bonding region, the non-conductive organic layer is at least connected between the first surface and the second surface to form the filling layer.

[0027] As a further improvement of one embodiment of the present invention, the first circuit structure includes a first dielectric layer, the surface of the first dielectric layer being a first surface; the second circuit structure includes a second dielectric layer, the surface of the second dielectric layer being a second surface; the first surface is flush with the first bonding surface, and the second surface is flush with the second bonding surface; the first bonding surface and the second bonding surface are connected through a layer of nano-metal particles, and the first surface and the second surface are bonded together.

[0028] As a further improvement to one embodiment of the present invention, the method includes the steps of: forming a third bonding region on the side of the second circuit structure opposite to the first circuit structure, the third bonding region being used for electrical connection to a circuit board; or, forming a third bonding region on the side of the first circuit structure opposite to the second circuit structure, the third bonding region being used for electrical connection to a circuit board.

[0029] Compared with the prior art, the present invention provides a chip packaging structure in which the first bonding surface and the second bonding surface are bonded together by a nano-metal layer. The bonding process is simple and low cost. The nano-metal layer bonding connection between the first bonding surface and the second bonding surface has better electrical performance. The nano-metal layer can realize the bonding connection between the first bonding surface and the second bonding surface with ultra-small pitch, realizing high-density interconnection. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the chip packaging interconnection structure in the first embodiment of the present invention.

[0031] Figure 2 This is a schematic diagram of the chip packaging interconnection structure in the second embodiment of the present invention.

[0032] Figure 3-4 This is a schematic diagram of the chip packaging interconnection structure in the third embodiment of the present invention.

[0033] Figure 5-6 This is a schematic diagram of the chip packaging interconnection structure in the fourth embodiment of the present invention.

[0034] Figure 7This is a schematic diagram of the chip packaging interconnection structure in the fifth embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of the chip packaging interconnection structure in the sixth embodiment of the present invention.

[0036] Figure 9-10 This is a schematic diagram of the chip packaging interconnection structure in the seventh embodiment of the present invention.

[0037] Figure 11-12 These are schematic diagrams illustrating various embodiments of the first and second circuit structures of the present invention.

[0038] Figure 13-14 This is a schematic diagram showing that the first circuit structure and the second circuit structure of the present invention are respectively provided with nano-metal particle layers.

[0039] Figure 15-16 This is a schematic diagram of the first circuit structure provided by the present invention.

[0040] Figure 17 This is a schematic diagram of the second circuit structure provided by the present invention.

[0041] Figure 18 This is a schematic diagram of the bonding connection between the first circuit structure and the second circuit structure of the present invention.

[0042] Figure 19 This is a schematic diagram of the first circuit structure provided in the seventh embodiment of the present invention.

[0043] Figure 20 yes Figure 19 Enlarged view of the structure inside the middle circle.

[0044] Figure 21 This is a schematic diagram of the second circuit structure provided in the seventh embodiment of the present invention. Detailed Implementation

[0045] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0046] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0047] The terms “connection,” “connected to,” or any other variations are intended to encompass various relative positions where a connection exists, including both direct and indirect connections. A direct connection can be formed through a pneumatic conduit, while an indirect connection can be formed through devices such as valves or sensors, through pneumatic components such as brake control units, or through any other medium such as air.

[0048] Please see Figure 1 This is a schematic diagram of a chip packaging structure 100 provided in the first embodiment of the present invention.

[0049] The chip packaging structure 100 includes a first circuit structure 10 and a second circuit structure 30. The first circuit structure 10 has a first surface 11 and a first bonding region 12, and a plurality of the first bonding regions 12 are arranged at intervals on the first surface 11. The second circuit structure 30 has a second surface 31 and a second bonding region 32, and a plurality of the second bonding regions 32 are arranged at intervals on the second surface 31. The first bonding region 12 and the second bonding region 32 are connected in a one-to-one correspondence.

[0050] The first bonding region 12 has a first bonding surface 121 facing the second bonding region 32, and the second bonding region 32 has a second bonding surface 321 facing the first bonding region 12. The chip package interconnect structure includes a nano metal layer 40, which bonds the first bonding surface 121 and the second bonding surface 321 together.

[0051] The first bonding surface 121 and the second bonding surface 321 are bonded together by a nano-metal layer 40. The bonding process is simple and low-cost. The nano-metal layer 40 bonded together the first bonding surface 121 and the second bonding surface 321, resulting in better electrical performance and thermal management efficiency. The nano-metal layer 40 can achieve ultra-small pitch bonding between the first bonding surface 121 and the second bonding surface 321, realizing high-density interconnection.

[0052] More specifically, using the nano-metal layer 40 for bonding reduces the stringent requirements on the flatness, roughness, and cleanliness of the first bonding surface 121 and the second bonding surface 321, thus lowering grinding and polishing costs. The bonding process between the first bonding surface 121, the second bonding surface 321, and the nano-metal layer 40 operates at a low temperature, below 250 degrees Celsius, which reduces process costs compared to bonding temperatures above 300 degrees Celsius. Furthermore, the bonding pitch between the first bonding surface 121 and the second bonding surface 321 can be less than or equal to 100 nanometers, enabling ultra-high density solder joint interconnection and achieving higher, faster, and lower power consumption data bandwidth communication required for AI training and other high-performance computing.

[0053] The metal materials of the first bonding region 12 and the second bonding region 32 can be copper, silver, or gold. When the first bonding region 12, the second bonding region 32, and the nano metal layer 40 are metal bonded, they are bonded by hot pressing, which is equivalent to bonding and connecting under high temperature and high pressure.

[0054] One of the first circuit structure 10 and the second circuit structure 30 is a chip, and the other is a circuit board, to realize the electrical connection between the chip and the circuit board. In other embodiments, the first circuit structure 10 and the second circuit structure 30 can both be chips to realize the integration of at least two chips; or, the first circuit structure 10 and the second circuit structure 30 can both be circuit boards, such as adapter boards and circuit boards, to realize the connection of the chip to an external circuit.

[0055] The thickness of the nano-metal layer 40 is less than 1 micrometer, achieving an ultra-thin bonding spacing.

[0056] The nano-metal layer 40 is formed by hot-pressing a nano-metal particle layer 40a covering the first bonding surface 121 and / or the second bonding surface 321. The nano-metal particle layer 40a can be optionally disposed on the first bonding surface 121 and / or the second bonding surface 321, as described below. Figure 13-14 It is described in detail.

[0057] The nano-metal particle layer 40a has nanoparticles with a melting point below 250 degrees Celsius, which optimizes process costs and does not affect the electrical performance of the chip packaging interconnect structure.

[0058] The nano-metal particle layer 40a contains nanoscale metal particles, which may be copper nanoparticles, silver nanoparticles, or gold nanoparticles, to ensure the electrical properties of the nano-metal particle layer 40a. Copper nanoparticles, silver nanoparticles, or gold nanoparticles have a relatively low melting point below 250 degrees Celsius.

[0059] The first bonding region 12 is a metal sink, and the first bonding surface 121 is lower than the first surface 11. The second bonding region 32 is a metal protrusion, and the second bonding surface 321 is higher than the second surface 31. The nano-metal layer 40 at least fills a portion of the space between the first bonding surface 121 and the second bonding surface 321.

[0060] Alternatively, the second bonding region 32 is a metal sink, the second bonding surface 321 is lower than the second surface 31, the first bonding region 12 is a metal protrusion, and the first bonding surface 121 is higher than the first surface 11; the nano metal layer 40 at least fills a portion of the space of the second bonding surface 321 facing the first bonding surface 121.

[0061] In other words, in the first embodiment of this application, one of the first bonding region 12 and the second bonding region 32 is formed as a metal sink, and the other is formed as a metal protrusion.

[0062] Combination Figure 1 As shown, in the first embodiment of this application, the first circuit structure 10 is a circuit board, and the second circuit structure 30 is a chip. The first circuit structure 10 has a first insulating layer 111, a first surface 11 is formed on the surface of the first insulating layer 111, a first bonding region 12 is exposed to the first insulating layer 111, and the first bonding surface 121 is lower than the first surface 11 to form a metal recessed surface.

[0063] It is understandable that when the first bonding region 12 is formed as a metal sink, since the nano metal layer 40 is relatively thin, the second bonding region 32 bonded to the first bonding region 12 should be a metal protrusion structure. The second bonding region 32 protrudes into the first insulating layer 111, thereby electrically connecting the first bonding region 12 through the nano metal layer 40.

[0064] In the first embodiment of this application, during the fabrication process, the nano-metal layer 40 can be formed separately on the first bonding surface 121 and then bonded to the second bonding surface 321; alternatively, it can be formed separately on the second bonding surface 321 and then bonded to the first bonding surface 121. Specifically, one bonding surface forms a nano-metal particle layer 40a, while the other bonding surface can form flux, which is beneficial to the stability of the connection between the two. Alternatively, the nano-metal particle layer 40a can be simultaneously formed on the first bonding surface 121 and the second bonding surface 321, and then thermo-pressed to form the nano-metal layer 40.

[0065] In the first embodiment of this application, the second bonding region 32 may be formed as a metal sink, while the first bonding region 12 may be formed as a metal protrusion, which will not be described in detail here.

[0066] The first bonding area 12 is a metal flat plate, and the first bonding surface 121 is flush with the first surface 11. The second bonding area 32 is a metal flat plate or a metal protrusion, and the second bonding surface 321 is not lower than the second surface 31.

[0067] Alternatively, the second bonding region 32 is a metal disc, and the second bonding surface 321 is flush with the second surface 31; the first bonding region 12 is a metal disc or a metal protrusion, and the first bonding surface 121 is not lower than the first surface 11.

[0068] In other words, in the second embodiment of this application, when one of the first bonding region 12 and the second bonding region 32 is a metal flat plate, the other can be a metal flat plate or a metal protrusion.

[0069] When the first bonding region 12 and / or the second bonding region 32 is a metal disk, the nano-metal layer 40 at least covers the entire surface of the metal disk to fully contact the first bonding region 12 and / or the second bonding region 32.

[0070] Combination Figure 2 As shown, the first bonding region 12 is a metal disc, the first bonding surface 121 is flush with the first surface 11, and the nano-metal layer 40 covers the entire surface of the first bonding surface 121. The second bonding region 32 is a metal protrusion, the second bonding surface 321 extends beyond the second surface 31, and the nano-metal layer 40 covers the entire surface of the second bonding surface 321. The large contact area between the nano-metal layer 40 and the first and second bonding surfaces 121 improves the electrical connection performance.

[0071] Alternatively, in the second embodiment of this application, the first bonding region 12 may be formed as a metal protrusion, while the second bonding region 32 may be formed as a metal flat plate, which will not be described in detail here.

[0072] Combination Figure 3 As shown in the third embodiment of this application, the first bonding region 12 is a metal disc, the first bonding surface 121 is flush with the first surface 11, and the nano-metal layer 40 covers the entire surface of the first bonding surface 121. The second bonding region 32 is a metal disc, the second bonding surface 321 is flush with the second surface 31, and the nano-metal layer 40 covers the entire surface of the second bonding surface 321. The large contact area between the nano-metal layer 40 and the first and second bonding surfaces 121 improves the electrical connection performance.

[0073] The first bonding region 12 is a metal protrusion, and the first bonding surface 121 is higher than the first surface 11; and / or, the second bonding region 32 is a metal protrusion, and the second bonding surface 321 is higher than the second surface 31. In other words, when one of the first bonding region 12 and the second bonding region 32 is a metal protrusion, the other can be a metal sink, a metal flat plate, or a metal protrusion.

[0074] Combination Figure 1-2 As shown, in the first and second embodiments of this application, when the second bonding region 32 is a metal protrusion, it can be bonded to the metal sink disk and the metal flat disk respectively through the nano-metal layer 40. Combined with... Figure 4 As shown, in the fourth embodiment of this application, the first bonding region 12 and the second bonding region 32 are both metal protrusions and are bonded together by the nano-metal layer 40.

[0075] It is understood that in the second, third, and fourth embodiments of this application, during the fabrication process, the nano-metal particle layer 40a can be formed separately on the first bonding surface 121 and then hot-pressed bonded to the second bonding surface 321; it can also be formed separately on the second bonding surface 321 and then hot-pressed bonded to the first bonding surface 121; or the nano-metal particle layer 40a can be simultaneously provided on the first bonding surface 121 and the second bonding surface 321 and then hot-pressed bonded together.

[0076] The first bonding region 12 includes a first side surface 122 located between the first bonding surface 121 and the first surface 11, and the nano metal layer 40 extends from the first bonding surface 121 to at least a portion of the first side surface 122; and / or, the second bonding region 32 includes a second side surface 322 located between the second bonding surface 321 and the second surface 31, and the nano metal layer 40 extends from the second bonding surface 321 to at least a portion of the second side surface 322.

[0077] In other words, when either the first bonding region 12 or the second bonding region 32 is a metal protrusion, the nano-metal layer 40 can extend to the side of the metal protrusion, increasing the area of ​​the metal protrusion and improving electrical performance. The nano-metal layer 40 can be formed before hot-press bonding, where the nano-metal particle layer 40a already coats the bonding surface and side of the metal protrusion; or it can be formed during hot-press bonding when the nano-metal particle layer 40a extends from the bonding surface of the metal protrusion to the side.

[0078] Combination Figure 5-6 As shown, in the fifth embodiment of this application, the first bonding region 12 is a metal flat plate, the second bonding region 32 is a metal protrusion, the nano metal layer 40 covers the first bonding surface 121 and extends beyond the outer periphery of the first bonding surface 121, the nano metal layer 40 covers the second bonding surface 321 and extends to the second side surface 322 of the second bonding region 32, the second side surface 322 extends beyond the second surface 31 and is adjacent to the second bonding surface 321.

[0079] Combination Figure 5-6 As shown, in the fifth embodiment of this application, the outer diameter of the second bonding region 32 is smaller than the outer diameter of the first bonding region 12, and the outer diameter of the nanoparticle layer 40 gradually increases from the second bonding region 32 toward the first bonding region 12. The outer surface of the nano metal layer 40 is inclined, which better wraps the second bonding region 32 and does not waste the nano metal layer 40.

[0080] In the fifth embodiment of this application, the chip packaging structure 100 includes a single first line structure 10 and a second line structure 30, the spacing between the first bonding regions 11 is relatively large, and the nano metal layer 40 completely covers the first bonding surface 121 and extends beyond the first bonding surface 121.

[0081] In the sixth embodiment of this application, in conjunction with Figure 7-8 As shown, the chip package structure 100 includes a single first circuit structure 10 and multiple second circuit structures 30. The first bonding region 12 is a metal flat disk, with the first bonding surface 121 flush with the first surface 11. The second bonding region 32 is a metal protrusion, with the second bonding surface 321 protruding from the second surface 31. It is understood that the other structures of the first circuit structure 10 and the second circuit structure 30 are the same as in other embodiments.

[0082] In the sixth embodiment: when a single first circuit structure 10 and multiple second circuit structures 30 are combined, the spacing between the multiple first bonding regions 12 is small and the density of the multiple first bonding regions 12 is high. When the nano metal layer 40 extends to the outer periphery of the first bonding surface 121, it may cause electrical contact between adjacent nano metal layers 40, resulting in a short circuit between adjacent first bonding regions 12. Therefore, the nano metal layer 40 may optionally cover part or the entire surface of the first bonding surface 121, but will not extend beyond the first bonding surface 121 to avoid short circuit.

[0083] It is understood that in the sixth embodiment of this application, since the surface covered by the nano metal layer 40 is smaller, the horizontal dimension is reduced. In order to ensure better electrical performance, the thickness of the nano metal layer 40 in the vertical direction is increased, which can also ensure the stability of the electrical connection.

[0084] It is understood that in the first to sixth embodiments described above, the basic structures of the first circuit structure 10 and the second circuit structure 30 are the same, with the only difference being the coordination structure between the first bonding region 12, the second bonding region 32, and the nano-metal particle layer 40.

[0085] In the first to sixth embodiments of this application, after the first bonding surface 121 and the second bonding surface 321 are bonded together by the nano-metal layer 40, there is a gap between the first surface 11 and the second surface 31. The chip package interconnect structure 100 includes a filling layer 60, which at least fills the space between the first surface 11 and the second surface 31 to encapsulate and protect the first bonding region 11, the second bonding region 32, and the nano-metal layer 40.

[0086] The filler layer 60 can also further encapsulate and protect the second circuit structure 30, as well as cover the side of the first circuit structure 10 facing the second circuit structure 30. The material of the filler layer 60 can be: underfill material (CUF), non-conductive film (NCP / NCF), or molding filler material (MUF).

[0087] The filler layer 60 can also be formed as a non-conductive organic layer, and the material can be selected from polyimide (PI), polyphenylene benzoxazole (PBO), epoxy resin (EMC), or silicon oxide and other silicon compounds.

[0088] The first circuit structure 10 includes a third bonding area disposed on a side opposite to the second circuit structure 30, or the second circuit structure 30 includes a third bonding area disposed on a side opposite to the first circuit structure 10; the third bonding area is used to electrically connect to the circuit board 50 to connect the first circuit structure 10 and the second circuit structure 30 to an external circuit.

[0089] In the first to sixth embodiments, the first circuit structure 10 is a circuit board, the second circuit structure 30 is a chip, the chip and the circuit board are electrically connected, the first circuit structure 10 is used to make the third bonding area 15, and is connected to the external circuit through the circuit board 50.

[0090] It is understood that other basic structures of the first circuit structure 10 can have multiple embodiments, and other basic structures of the second circuit structure 30 can also have multiple embodiments, as long as the first circuit structure 10 and the second circuit structure 30 satisfy the technical feature that the first bonding region 11 and the second bonding region 32 are connected by the above-mentioned nano metal layer 40.

[0091] In a first embodiment of the first circuit structure 10: the first circuit structure 10 is a circuit board with a first board 13. A first redistribution layer 14 is provided on one side of the first substrate 13. The first surface 11 is the surface of the first redistribution layer 14 that is away from the first substrate 13. The first bonding area 12 is electrically connected to the first redistribution layer 14 and is arranged at intervals on the first surface.

[0092] The first circuit structure 10 has a third bonding region 15, which is disposed on the side of the first substrate 13 away from the first redistribution layer 14. The third bonding region 15 is electrically connected to the first redistribution layer 14, thereby electrically connecting to the first bonding region 11 to achieve electrical connection with the second circuit structure 30.

[0093] The first circuit structure 10 includes a conductive post 16, which is disposed on the first substrate 13. The two ends of the conductive post 16 are respectively connected to the first redistribution layer 14 and the third bonding region 15.

[0094] In a second embodiment of the first circuit structure 10: the first circuit structure 10 further includes a second redistribution layer 17, the second redistribution layer 17 and the first redistribution layer 14 are located on opposite sides of the first substrate 13, and a third bonding region 15 is formed on the side of the second redistribution layer 17 away from the first substrate 13.

[0095] The second circuit structure 30 is a chip, combined with Figure 15As shown, the second circuit structure 30 includes a second surface 31 and a second bonding region 32; or the second circuit structure 30 includes a second surface 31, a second bonding region 32 and a third rewiring layer 33, in which case the second surface 31 is formed on the surface of the third rewiring layer 33 and the second bonding region 32 is electrically connected to the third rewiring layer 33.

[0096] The first bonding region 12 is a metal disk, the first surface 11 is the surface of the organic dielectric layer, the second bonding region 32 is a metal disk, the second surface 31 is the surface of the organic dielectric layer, and the first surface 11 and the second surface 31 are bonded together, which reduces the process cost of hybrid bonding.

[0097] In the seventh embodiment of this application, in conjunction with Figure 9 , 11 As shown in Figure 12, the first bonding region 12 is a metal flat disk, the first bonding surface 121 is flush with the first surface 11, and the second bonding region 32 is a metal flat disk, the second bonding surface 321 is flush with the second surface 31.

[0098] The outer diameter of the first bonding surface 121 is equal to the outer diameter of the second bonding surface 321, and the outer diameter of the nano metal layer 40 is equal to the outer diameter of the first bonding surface 121. This is used to realize electrical connection between two metal disks through the nano metal layer 40, thereby reducing process costs and achieving ultra-thin bonding pitch.

[0099] Combination Figure 9 As shown, the first circuit structure 10 is a circuit board, and the second circuit structure 30 is a chip. The chip and the circuit board are electrically connected and connected to an external circuit through the circuit board 50.

[0100] The first circuit structure 10 is a circuit board with a first substrate 13. A first redistribution layer 14 is provided on one side of the first substrate 13. The first surface 11 is the surface of the first redistribution layer 14 that is away from the first substrate 13. The first bonding area 12 is electrically connected to the first redistribution layer 14 and is arranged at intervals on the first surface.

[0101] The first circuit structure 10 has a third bonding region 15, which is disposed on the side of the first substrate 13 away from the first redistribution layer 14. The third bonding region 15 is electrically connected to the first redistribution layer 14, thereby electrically connecting to the first bonding region 11 to achieve electrical connection with the second circuit structure 30.

[0102] The first circuit structure 10 includes a conductive post 16, which is disposed on the first substrate 13. The two ends of the conductive post 16 are respectively connected to the first redistribution layer 14 and the third bonding region 15.

[0103] The first circuit structure 10 also has a second wiring layer 17, the second wiring layer 17 and the first wiring layer 14 are located on opposite sides of the first substrate 13, and the third bonding region 15 is formed on the side of the second wiring layer 17 away from the first substrate 13; or in other embodiments, the second wiring layer 17 may not be provided.

[0104] The second circuit structure 30 is a chip, including a second surface 31, a second bonding region 32 and a third wiring layer 33. The second surface 31 is formed on the surface of the third wiring layer 33, and the second bonding region 32 is electrically connected to the third wiring layer 33.

[0105] Although both the seventh and third embodiments of this application involve metal disks being bonded together by a nano-metal layer 40, in the third embodiment, the first bonding surface 121 is first bonded together with the second bonding surface 321, a gap is formed between the first surface 11 and the second surface 31, and then the gap is filled by a filling layer 60.

[0106] The seventh embodiment has the following differences: the first circuit structure 10 includes a first dielectric layer 18, the surface of the first dielectric layer 18 being a first surface 11; the second circuit structure 30 includes a second dielectric layer 34, the surface of the second dielectric layer 34 being a second surface 31; the first surface 11 is flush with the first bonding surface 121; the second surface 31 is flush with the second bonding surface 321; the first bonding surface 121 and the second bonding surface 321 are connected by a nano-metal layer 40; the first surface 11 and the second surface 31 are bonded together; the first dielectric layer 18 and the second dielectric layer 34 are preferably made of organic materials, thus having elasticity and being able to compensate for the gaps formed by the provision of the nano-metal layer 40.

[0107] In other embodiments, the first dielectric layer and the second dielectric layer may also be optionally formed as an organic-inorganic composite layer or an inorganic layer. By first forming an organic-inorganic composite layer or an inorganic layer with a certain height, the height can ensure that the first dielectric layer and the second dielectric layer are bonded together during subsequent metal bonding.

[0108] The materials for the organic dielectric layer can be selected from: polyimide (PI), polyphenylene benzoxazole (PBO), epoxy resin (EMC), or silicon oxide and other silicon compounds.

[0109] In the seventh embodiment of this application, a hybrid bonding process is involved. Organic materials are selected for hybrid bonding. Organic dielectric layers can tolerate higher surface roughness, reducing the stringent requirements for surface coplanarity compared to inorganic materials, and are cost-effective. During the bonding process, the organic dielectric layer undergoes local elastic or plastic deformation, filling the tiny gaps between the bonding interfaces and compensating for surface roughness, unevenness, and other phenomena.

[0110] Combination Figure 9-10 As shown, a nano-metal layer 40 is present between the first bonding surface 121 and the second bonding surface 321, while the first organic dielectric layer 18 and the second organic dielectric layer 34 are bonded together, and the bonding surfaces of the first dielectric layer 18 and the second dielectric layer 34 are fused.

[0111] Combination Figure 11-12 As shown, the first organic dielectric layer 18 is flush with the first bonding surface 121 before bonding, and the second organic dielectric layer 34 is also flush with the second bonding surface 321 before bonding. In this application, a nano-metal layer 40 is used to bond the first bonding surface 121 and the second bonding surface 321. Because of the presence of the nano-metal layer 40, the first bonding surface 121 and the second bonding surface 321 do not meet the coplanarity requirement for mixed bonding and cannot be mixed bonded. However, when the first organic dielectric layer 18 and the second organic dielectric layer 34 in this application are made of organic materials, the elasticity of the organic dielectric layer can adaptively deform to compensate for the gap caused by the setting of the nano-metal layer 40, making mixed bonding feasible. Moreover, this mixed bonding method has good electrical performance and low process cost.

[0112] More specifically, conventional hybrid bonding requires that the surfaces of the first organic dielectric layer 18 and the first bonding surface 121 be coplanar and both be clean and flat, and that the surfaces of the second organic dielectric layer 34 and the second bonding surface 321 be coplanar and both be clean and flat, requiring a stringent grinding and polishing process; then the surfaces of the first organic dielectric layer 18 and the second organic dielectric layer 34 are bonded together, and the first bonding surface 121 and the second bonding surface 321 are bonded together. During bonding, high bonding temperatures and bonding pressures are required, making the conventional hybrid bonding process extremely costly.

[0113] In this application, the first bonding surface 121 and the second bonding surface 321 are hot-pressed together using a nano-metal particle layer 40a. The surface requirements of the first bonding surface 121 and the second bonding surface 321 are not stringent. The coplanarity requirements between the first bonding surface 121 and the surface of the first organic dielectric layer 18, the surface of the second organic dielectric layer 34, and the second bonding surface 321 are also reduced. This is because the first organic dielectric layer 18 and the second organic dielectric layer 34 are made of organic materials, which can compensate for surface unevenness and surface gaps, and the grinding and polishing process has low cost. The use of a nano-metal particle layer 40a and an organic dielectric layer for mixed bonding results in a lower bonding temperature requirement and a lower bonding process cost.

[0114] In summary, combining Figure 11 As shown, the first circuit structure 10 of this application has at least four implementation methods, see reference. Figure 11 a-11c, the first bonding region 12 is below, level with, and above the first surface 11, and is filled after bonding with the applicable nano-metal layer 40. (Refer to...) Figure 11d. When the first bonding surface 121 and the first surface 11 are flush, the first bonding region 12 and the first surface 11 can be used for hybrid bonding based on the material properties of the special organic dielectric layer of the first surface 11.

[0115] In summary, combining Figure 12 As shown, the second circuit structure 30 of this application has at least four implementation methods, see reference. Figure 12 a-12c, the second bonding region 32 is below, level with, and above the second surface 31, and is filled after bonding with the applicable nano-metal layer 40. (Refer to...) Figure 12 d. When the second bonding surface 321 and the second surface 31 are flush, the second bonding region 32 and the second surface 31 can be used for hybrid bonding based on the material properties of the special organic dielectric layer of the second surface 31.

[0116] The nano-metal layer 40 is formed by hot-pressing and bonding of the nano-metal particle layer 40a. The nano-metal particle layer 40a can be optionally disposed in the first bonding region 12 and / or the second bonding region 32, depending on actual needs. Figure 13-14 The diagrams shown illustrate the arrangement of nano-metal particle layers 40a in the first bonding region 12 and the second bonding region 32, respectively.

[0117] Combination Figure 13 a, 14a, When the nano-metal particle layer 40a is disposed on the metal sink, the nano-metal particle layer 40a is relatively thin and usually does not exceed the first surface 11 or the second surface 31. Therefore, when one of the first bonding region 12 and the second bonding region 32 is a metal sink, the other is a metal protrusion to ensure effective electrical connection between the first bonding region 12 and the second bonding region 32.

[0118] When the nano-metal particle layer 40a is disposed on the metal sinking plate, the nano-metal particle layer 40a covers part of the surface of the metal sinking plate, and the other part of the surface of the metal sinking plate is covered by the dielectric layer.

[0119] Combination Figure 1 As shown, the nano-metal layer 40 will not extend beyond the first surface 11. It is understandable that when one of the first bonding region 12 and the second bonding region 32 is a metal sink and the other is a metal protrusion, and both the metal sink and the metal protrusion are bonded together with nano-metal particle layers 40a, the superposition of the thicknesses of the two nano-metal particle layers 40a may result in the nano-metal layer 40 extending beyond the first surface 11 in the finished chip packaging interconnect structure 100.

[0120] Combination Figure 13b, 14b, When the nano-metal particle layer 40a is disposed on the metal disk, the nano-metal particle layer 40a covers the entire surface of the metal disk. During the bonding process to form the chip package interconnect structure 100, the nano-metal particle layer 40a may also extend outward beyond the metal disk to form the nano-metal layer 40. Combined with... Figure 5-6 As shown, the nano metal layer 40 extends from the first bonding surface 121 to the first surface 11.

[0121] Combination Figure 13 c, 14c, the nano-metal particle layer 40a is also disposed on a metal disk, the difference being that the first surface 11 and the second surface 31 are both surfaces of an organic dielectric layer, used for hybrid bonding. Figure 9-10 The nano-metal layer 40 covers the entire surface of the metal disk. During the bonding process to form the chip package interconnect structure 100, the nano-metal particle layer 40a will not extend outward to the first surface 11 or the second surface 31 because the first surface 11 and the second surface 31 need to be deformed and fused.

[0122] Combination Figure 13 d, 14d, the nano-metal particle layer 40a is disposed on the metal protrusion, which can cover the entire surface of the metal protrusion, or it can be disposed only on the first bonding surface or the second bonding surface.

[0123] This application also protects a method for fabricating a chip package interconnect structure 100, used to fabricate the chip package interconnect structure 100 in the above technical solution. The chip packaging method includes the following steps:

[0124] S1: A first circuit structure 10 is provided, having a first surface 11 and a first bonding region 12, the first bonding regions 12 being spaced apart on the first surface 11, and the first bonding region 12 having a first bonding surface 121 exposed to the first surface 11;

[0125] S2: A second circuit structure 30 is provided, having a second surface 31 and a second bonding region 32, the second bonding regions 32 being spaced apart on the second surface 31, and the second bonding region 32 having a second bonding surface 321 exposed to the second surface 31; the second bonding region 32 and the first bonding region 12 are connected in a one-to-one correspondence.

[0126] S3: Fabricate a nano-metal particle layer 40a, which covers the first bonding surface 121 and / or the second bonding surface 321; select the nano-metal particle layer 40a to bond the first bonding surface 121 and the second bonding surface 321, the nanoparticles of the nano-metal particle layer 40a have a melting point of less than 250 degrees Celsius, and the nanoparticles can be selected as copper nanoparticles, silver nanoparticles, or gold nanoparticles, to reduce process costs and ensure electrical performance.

[0127] S4: The first bonding surface 121 and the second bonding surface 321 are bonded together. After the nano metal particle layer 40a is hot-pressed and bonded, it forms a nano metal layer 40. The nano metal layer 40 is bonded together with the first bonding region 12 and the second bonding region 32 to realize the electrical connection between the first circuit structure 10 and the second circuit structure 30.

[0128] Combination Figure 15-21 As shown, this application will select the fifth, sixth and seventh embodiments to describe the manufacturing process in detail. It can be understood that the manufacturing methods of the first to fourth embodiments are basically the same as those of the fifth embodiment, and will not be described again.

[0129] Reference Figure 15-16 This is a schematic diagram of different structures of the first circuit structure 10 in the fifth embodiment of this application. In other embodiments, the first circuit structure 10 can also be configured with different structures. The first circuit structure 10 is a circuit board, and the first bonding area 12 is a metal plate. It can be understood that providing the first circuit structure 10 means providing a fabricated first substrate 13, a first redistribution layer 14, a first surface 11, and a first bonding area 12; or, it means providing a fabricated first substrate 13, conductive pillars 16, a first redistribution layer 14, a first surface 11, and a first bonding area 12.

[0130] Reference Figure 9 This is a schematic diagram illustrating different structures of the second circuit structure 30 in the fifth embodiment of this application. In other embodiments, the second circuit structure 30 can also be configured with different structures. The second circuit structure 30 is a chip, and the second bonding region 32 is a metal bump. It can be understood that providing the first circuit structure 10 means providing a chip with a second surface 31 and a second bonding region 32; or, it means providing a chip with a third wiring layer 33, a second surface 31, and a second bonding region 32.

[0131] Fabricating the nano-metal particle layer 40a includes: chemically depositing or surface adsorption onto the first bonding surface 121 and / or the second bonding surface 321 to form the nano-metal particle layer 40a. The nanoparticles have a melting point below 250°C, reducing processing costs.

[0132] In other embodiments, the nano-metal particle layer 40 can also be formed by patterning. The photoresist 400 containing nano-metal particles is coated on the first surface 11 and the first bonding region 12. The photoresist 400 is patterned, and at least the photoresist on the complete surface of the first bonding region 12 is retained to form the nano-metal particle layer 40. When patterning the photoresist 400, the range of polishing and development can be adjusted so that the nano-metal particle layer 40 completely covers the first bonding region 12 or extends beyond the outer periphery of the first bonding region 12.

[0133] The bonding connection between the first bonding surface 121 and the second bonding surface 321 includes: hot-press bonding the nano-metal particle layer 40a to the first bonding surface 121 or the second bonding surface 321 to form a nano-metal layer 40; or hot-press bonding the nano-metal particle layer 40a on the first bonding surface and the nano-metal particle layer 40a on the second bonding surface to form a nano-metal layer 40.

[0134] The nano-metal particle layer 40a is initially formed in one of the first bonding region 12 or the second bonding region 32, and then formed by hot-press bonding with the other of the first bonding region 12 or the second bonding region 32; or, the nano-metal particle layer 40a is initially formed in both the first bonding region 12 and the second bonding region 32, and the nano-metal particle layers 40a are formed by hot-press bonding with each other.

[0135] In one embodiment, a nano-metal particle layer 40a is fabricated in the first bonding region 12, and a flux 300 is fabricated in the second bonding region 32; the nano-metal particle layer 40 and the flux 300 are bonded together; wherein, the second bonding surface 321 is higher than the second surface 31, and the first bonding surface 121 is not higher than the first surface 11.

[0136] Alternatively, a nano-metal particle layer 40a may be formed in the second bonding region 32, and flux 300 may be formed in the first bonding region 12; the nano-metal particle layer 40a and the flux 300 may be bonded together; wherein the first bonding surface 121 is higher than the first surface 11, and the second bonding surface 321 is not higher than the second surface 31; the flux contributes to the stability of the electrical connection.

[0137] Reference Figure 17-18 The first bonding region 12 is a metal disk, and the second bonding region 32 is a metal protrusion. A nano-metal particle layer 40a is formed on the metal disk, and a flux is formed on the metal protrusion. After the two are bonded together, the flux undergoes a chemical reaction and becomes other substances. The nano-metal particle layer 40a wraps from the first bonding region 12 to the second bonding region 32 to form a nano-metal layer 40.

[0138] It is understandable that, since the amount of nano-metal particle layer 40a at each bonding site is fixed, after bonding, as part of the nano-metal particle layer 40a wraps around the second bonding side 322 of the second bonding region 32, the thickness of the nano-metal layer 40 on the surface of the first bonding surface 121 is reduced, which is beneficial to achieving an ultra-thin bonding gap between the first bonding surface 121 and the second bonding surface 321.

[0139] It is understood that in the fifth embodiment of this application, the second bonding region 32 is a metal protrusion extending beyond the second surface 31. During bonding, there is a gap between the first surface 11 and the second surface 31, thus allowing the nano-metal particle layer 40a to extend outward from the second bonding region 32, thereby extending to the second side surface 322. Alternatively, nano-metal particle layers 40a can be formed on both the second bonding surface 321 and the second side surface 322 of the second bonding region 32, which is formed as a metal protrusion, and then flux can be formed on the surface of the nano-metal particle layer 40a.

[0140] The method for fabricating the chip package interconnect structure 100 includes the steps of: fabricating a filling layer 60, wherein the filling layer 60 is located at least between the first surface 11 and the second surface 31.

[0141] In the first to sixth embodiments of this application, after the first bonding region 12 and the second bonding region 32 are bonded, the filling layer 60 is then filled, which allows the nano-metal particle layer 40a to extend outward during hot-press bonding.

[0142] The process of fabricating the filler layer 60 includes the following steps: after the first bonding region 12 and the second bonding region 32 are aligned and hot-pressed by fabricating the nano-metal particle layer 40a, the gap between the first surface 11 and the second surface 31 is filled with a bottom filler material, and the bottom filler material is heated and cured to form the filler layer 60; wherein, one of the first bonding region 12 and the second bonding region 32 is a metal protrusion.

[0143] It is understandable that a gap needs to be formed between the first surface 11 and the second surface 31 in order to fill the gap. Therefore, when the first bonding area 12 and the second bonding area 32 are metal protrusions, a process of filling after bonding is adopted.

[0144] In further embodiments of this application, the fabrication of the filling layer 60 includes the following steps: one of the first bonding region 12 and the second bonding region 32 is a metal protrusion; a non-conductive organic layer is first covered on the first surface 11 or the second surface 31, the thickness of the non-conductive organic layer being not less than the height of the metal protrusion; after the metal nanoparticle layer 40a is hot-pressed to bond the first bonding region 12 and the second bonding region 32, the non-conductive organic layer is at least connected between the first surface and the second surface to form the filling layer 60.

[0145] Understandably, the non-conductive organic layer can preferentially be formed on the first surface 11 or the second surface 31. After the thermo-bonded metal nanoparticle layer 40a is completed, the non-conductive organic layer extends and is fixed between the first surface 11 and the second surface 31 to form a filling layer 60. The thickness of the non-conductive organic layer cannot be less than the height of the metal protrusion; otherwise, it may result in the inability to completely fill the space between the first surface 11 and the second surface 31.

[0146] After creating a fill layer of 60, refer to Figure 5 , 18 A second overlay layer 17 and a third bonding region 15 are fabricated on the side of the first substrate 13 opposite to the first overlay layer 14, and then the third bonding region 15 is bonded to the circuit board 50.

[0147] In the sixth embodiment of this application, when the chip packaging structure 100 includes a plurality of second line structures 30 and a single first line structure 10, the chip packaging method is basically the same as that in the fifth embodiment, except that: a plurality of second line structures 30 are provided; when fabricating the nano-metal particle layer 40a, care is taken to ensure that the nano-metal particle layer 40 does not cover the outer periphery of the first bonding surface 121; the second bonding regions 32 of the plurality of second line structures 30 are all bonded together through the nano-metal particle layer 40a and the first bonding region 12.

[0148] Combination Figure 19-21 As shown, the difference between the seventh embodiment and the fifth embodiment of this application is that: a first circuit structure 10 is provided, the first bonding area 12 is a metal flat plate, and a second circuit structure 30 is provided, the second bonding area 32 is a metal flat plate.

[0149] In the seventh embodiment of this application, the first circuit structure 10 includes: fabricating a first dielectric layer 18 on the first surface 11, the first dielectric layer 18 being flush with the first bonding surface 121; the second circuit structure 30 includes: fabricating a second dielectric layer 34 on the second surface 31, the second dielectric layer 34 being flush with the second bonding surface 321; the first dielectric layer 18 and the second dielectric layer 34 are organic materials; the first bonding surface 121 and the second bonding surface 321 are connected by a nano-metal particle layer 40, and the first dielectric layer 18 and the second dielectric layer 34 are bonded together.

[0150] In other embodiments, the first dielectric layer and the second dielectric layer may also be optionally formed as an organic-inorganic composite layer or an inorganic layer. By first forming an organic-inorganic composite layer or an inorganic layer with a certain height, the height can ensure that the first dielectric layer and the second dielectric layer are bonded together during subsequent metal bonding.

[0151] Combination Figure 19 As shown, when fabricating the first dielectric layer 18 on the first surface, the height of the first dielectric layer 18 is first made to exceed the first bonding region 12, and then the first dielectric layer 18 is ground to make it flush with the first bonding surface 121. When fabricating the nano-metal particle layer 40a, it is ensured that the nano-metal particle layer 40a does not cover the first dielectric layer 18, so as to avoid the nano-metal particle layer 40a affecting the bonding between the first dielectric layer 18 and the second dielectric layer 34.

[0152] Combination Figure 20-21As shown, similarly, when fabricating the second dielectric layer 34 on the second surface 31, the height of the second dielectric layer 34 is first made to exceed the second bonding region 32, and then the second dielectric layer 34 is ground to make it flush with the second bonding surface 321. When fabricating the nano-metal particle layer 40a, it is ensured that the nano-metal particle layer 40a does not cover the second dielectric layer 34, so as to avoid the nano-metal particle layer 40a affecting the bonding between the first dielectric layer 18 and the second dielectric layer 34.

[0153] As can be seen, in the seventh embodiment, the method of fabricating the chip packaging interconnect structure involves hybrid bonding. Before fabricating the nano-metal particle layer 40a, the first dielectric layer 18 and the second dielectric layer 34 are also fabricated. When fabricating the nano-metal particle layer 40a, it is necessary to avoid the nano-metal particle layer 40a covering the first dielectric layer 18 or the second dielectric layer 34. During hybrid bonding, the nano-metal particle layer 40a of the first bonding surface 121 and the second bonding surface 321 are thermo-pressed together to form the nano-metal layer 40. The first dielectric layer 18 and the second dielectric layer 34 are also bonded together. The nano-metal particle layer 40a cannot extend to the outer periphery. The outer diameter of the nano-metal layer 40 should be equal to the outer diameter of the first bonding surface 121 and the second bonding surface 321.

[0154] After bonding is complete, refer to Figure 9-10 As shown, the surfaces of the first dielectric layer 18 and the second dielectric layer 34 are fused together. It can be understood that before bonding, the first dielectric layer 18 is flush with the first surface 11, and the second dielectric layer 34 is also flush with the second surface 31. After bonding, a nano-metal layer 40 exists between the first bonding surface 121 and the second bonding surface 321. Since the first dielectric layer 18 and the second dielectric layer 34 are organic dielectric layers, they extend towards each other, meaning the surfaces of the first dielectric layer 18 and the second dielectric layer 34 will convex relative to each other, thus fusing together.

[0155] After the hybrid bonding is completed, a third bonding region is formed on the side of the first circuit structure 10 opposite to the second circuit structure 30. Specifically, a second redistribution layer 17 and a third bonding region 15 are formed on the side of the first substrate 13 opposite to the first redistribution layer 14, and then the third bonding region 15 is bonded to the circuit board 50.

[0156] The beneficial effects of this invention are as follows: the first bonding surface 121 and the second bonding surface 321 are bonded together by the nano-metal layer 40, and the bonding process is simple and low-cost; the nano-metal layer 40 bonded together with the first bonding surface 121 and the second bonding surface 321 has better electrical performance and thermal management efficiency; the nano-metal layer 40 can achieve ultra-small pitch bonding between the first bonding surface 121 and the second bonding surface 321, realizing high-density interconnection; the nano-metal particle layer 40a has nano-sized metal particles with a melting point below 250°, reducing process costs while ensuring conductivity; the nano-metal layer 40 has a nano-sized thickness, preferably less than or equal to 100 nm, to achieve ultra-thin bonding pitch.

[0157] This can be formed by referring to any of the technical solutions provided above, and will not be elaborated here.

[0158] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0159] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip package interconnect structure with metal bonding, characterized in that, include: A first circuit structure and a second circuit structure, wherein the first circuit structure has a first surface and a first bonding region, and a plurality of the first bonding regions are arranged at intervals on the first surface; the second circuit structure has a second surface and a second bonding region, and a plurality of the second bonding regions are arranged at intervals on the second surface; the first bonding region and the second bonding region are connected in a one-to-one correspondence. The first bonding region has a first bonding surface facing the second bonding region, and the second bonding region has a second bonding surface facing the first bonding region. The chip package interconnect structure includes a nano-metal layer, which bonds the first bonding surface and the second bonding surface together.

2. The chip package interconnect structure with metal bonding according to claim 1, characterized in that, The nano-metal layer is formed by hot-pressing a layer of nano-metal particles covering the first bonding surface and / or the second bonding surface; the nano-metal particle layer has nanoparticles with a melting point below 250 degrees Celsius.

3. The chip package interconnect structure with metal bonding according to claim 1, characterized in that, The first bonding area is a metal sink, and the first bonding surface is lower than the first surface; the second bonding area is a metal protrusion, and the second bonding surface is higher than the second surface. Alternatively, the second bonding region is a metal sink, with the second bonding surface lower than the second surface, and the first bonding region is a metal protrusion, with the first bonding surface higher than the first surface.

4. The chip package interconnect structure with metal bonding according to claim 1, characterized in that, The first bonding area is a metal flat plate, and the first bonding surface is flush with the first surface; the second bonding area is a metal flat plate or a metal protrusion, and the second bonding surface is not lower than the second surface. Alternatively, the second bonding region is a metal disc, with the second bonding surface flush with the second surface; the first bonding region is a metal disc or a metal protrusion, with the first bonding surface not lower than the first surface.

5. The chip package interconnect structure with metal bonding according to claim 4, characterized in that, When the first bonding region and / or the second bonding region is a metal disk, the nano-metal layer at least covers the entire surface of the metal disk.

6. The chip package interconnect structure with metal bonding according to claim 4, characterized in that, The first bonding region is a metal disc, the first surface is the surface of the dielectric layer, the second bonding region is a metal disc, the second surface is the surface of the dielectric layer, and the first surface and the second surface are bonded together.

7. The chip package interconnect structure with metal bonding according to claim 1, characterized in that, The first bonding region is a metal protrusion, and the first bonding surface is higher than the first surface, and / or the second bonding region is a metal protrusion, and the second bonding surface is higher than the second surface.

8. The chip package interconnect structure with metal bonding according to claim 7, characterized in that, The first bonding region includes a first side surface located between the first bonding surface and the first surface, and the nanometal layer extends from the first bonding surface to at least a portion of the first side surface; and / or, the second bonding region includes a second side surface located between the second bonding surface and the second surface, and the nanometal layer extends from the second bonding surface to at least a portion of the second side surface.

9. The chip package interconnect structure with metal bonding according to claim 1, characterized in that, It includes a filling layer that at least fills the space between the first surface and the second surface.

10. The chip package interconnect structure with metal bonding according to claim 1, characterized in that, The second circuit structure includes a third bonding area disposed on a side opposite to the first circuit structure, or the first circuit structure includes a third bonding area disposed on a side opposite to the second circuit structure; the third bonding area is used for electrical connection to the circuit board.

11. A method for fabricating a chip package interconnect structure with metal bonding, including the following steps: A first circuit structure is provided, having a first surface and a first bonding region, the first bonding regions being spaced apart on the first surface, and the first bonding region having a first bonding surface exposed on the first surface; A second circuit structure is provided, having a second surface and a second bonding region, the second bonding regions being spaced apart on the second surface, and each second bonding region having a second bonding surface exposed on the second surface; the second bonding region and the first bonding region are connected in a one-to-one correspondence; A layer of nano-metal particles is fabricated, the layer of nano-metal particles covering the first bonding surface and / or the second bonding surface; The first bonding surface and the second bonding surface are bonded together.

12. The manufacturing method according to claim 11, characterized in that, Fabricating the nano-metal particle layer includes: forming the nano-metal particle layer by chemical plating or surface adsorption on the first bonding surface and / or the second bonding surface.

13. The manufacturing method according to claim 11, characterized in that, The bonding connection between the first bonding surface and the second bonding surface includes: hot-press bonding the nano-metal particle layer to the first bonding surface or the second bonding surface to form a nano-metal layer; or hot-press bonding the nano-metal particle layer on the first bonding surface and the nano-metal particle layer on the second bonding surface to form a nano-metal layer.

14. The manufacturing method according to claim 11, characterized in that, The process includes the following steps: fabricating a filling layer between the first surface and the second surface; after the first bonding region and the second bonding region are aligned and hot-pressed by fabricating the nano-metal particle layer, filling the gap between the first surface and the second surface with a bottom filler material, and heating and curing the bottom filler material to form the filling layer; wherein, one of the first bonding region and the second bonding region is a metal protrusion.

15. The manufacturing method according to claim 11, characterized in that, The steps include: fabricating a filling layer between the first surface and the second surface, wherein one of the first bonding region and the second bonding region is a metal protrusion; firstly, covering the first surface or the second surface with a non-conductive organic layer, the thickness of the non-conductive organic layer being not less than the height of the metal protrusion; after the metal nanoparticle layer is aligned and hot-pressed to bond the first bonding region and the second bonding region, the non-conductive organic layer is at least connected between the first surface and the second surface to form the filling layer.

16. The manufacturing method according to claim 11, characterized in that, The first circuit structure includes a first dielectric layer, the surface of which is a first surface; the second circuit structure includes a second dielectric layer, the surface of which is a second surface; the first surface is flush with the first bonding surface, and the second surface is flush with the second bonding surface; the first bonding surface and the second bonding surface are hot-pressed together by a layer of nano-metal particles, and the first surface and the second surface are bonded together.

17. The manufacturing method according to claim 11, characterized in that, The steps include: fabricating a third bonding area on the side of the second circuit structure opposite to the first circuit structure, the third bonding area being used for electrical connection to a circuit board; or, fabricating a third bonding area on the side of the first circuit structure opposite to the second circuit structure, the third bonding area being used for electrical connection to a circuit board.

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