Design method of PCB interlayer voltage withstanding test module

Abstract

The invention discloses a design method of a PCB (Printed Circuit Board) interlayer voltage withstanding test module, which is applied to a PCB, the number of layers of the PCB is n, and n is an even number greater than or equal to 4. The method relates to the technical field of circuit board preparation, and comprises the following steps: S10, arranging a rectangular copper sheet in a side rail area of each layer of a PCB; s20, taking the first vertex of the rectangular copper sheet of each layer as a base point from the first layer to the n / 2 layer of the PCB, determining the position of the test hole of each layer according to a preset offset distance, and arranging each layer of circuit between the second vertex of the rectangular copper sheet of each layer and the bottom of the test hole of each layer; and S30, taking the second vertex of the rectangular copper sheet of each layer from the (n / 2) + 1th layer to the nth layer of the PCB as a base point, determining the position of the test hole of each layer according to a preset offset distance, and arranging each layer of circuit between the first vertex of the rectangular copper sheet of each layer and the top of the test hole of each layer. The method has the beneficial effect that the test efficiency and accuracy can be optimized.

Description

Technical Field

[0001] This invention relates to the field of circuit board manufacturing technology, and more specifically, to a design method for an interlayer withstand voltage test module for PCB boards. Background Technology

[0002] Interlayer insulation performance of printed circuit boards (PCBs) is one of the core indicators for evaluating their reliability and safety. With the development of modern electronic products towards high voltage and high density, especially in fields such as new energy vehicles, 5G communications, and industrial control, PCBs must be able to operate stably for extended periods under high voltage environments to avoid failures such as interlayer breakdown or arcing. Interlayer withstand voltage testing verifies whether the insulating medium between different circuit layers can withstand specific voltages, ensuring that the product meets safety standards and extends its service life.

[0003] The interlayer withstand voltage testing methods commonly used in the industry have significant shortcomings. The layout of test points (usually metallized vias) in the PCB edge area lacks systematic planning, often being randomly distributed or arranged in a simple order. This disordered arrangement forces testers to frequently adjust probe positions when continuously measuring multilayer boards, thus affecting testing efficiency and the accuracy of test results due to probe movement errors. For example, when measuring a 10-layer board, testers may need to repeatedly switch between the upper and lower parts of the module, easily leading to probe misalignment or missed tests.

[0004] Therefore, this invention provides a design method for an interlayer withstand voltage test module for PCB boards, which can optimize test efficiency and accuracy. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention provides a design method for a PCB board interlayer withstand voltage test module, which can optimize test efficiency and accuracy.

[0006] The technical solution adopted by this invention to solve its technical problem is: a design method for an interlayer withstand voltage test module for a PCB board, applied to a PCB board having n layers, where n is an even number greater than or equal to 4; the improvement lies in that the design method for the interlayer withstand voltage test module for the PCB board includes the following steps:

[0007] S10, rectangular copper foil is set in the edge rail area of ​​each layer of the PCB board;

[0008] S20, the first vertex of the rectangular copper skin of each layer of the PCB board is used as the base point, and the position of the test hole of each layer is determined according to the preset offset distance. The circuit of each layer is set between the second vertex of the rectangular copper skin of each layer and the bottom of the test hole of each layer.

[0009] S30, for the (n / 2)+1 to nth layers of the PCB board, the second vertex of the rectangular copper skin of each layer is used as the base point, and the position of the test hole of each layer is determined according to the preset offset distance. The circuit of each layer is set between the first vertex of the rectangular copper skin of each layer and the top of the test hole of each layer.

[0010] Furthermore, the rectangular copper sheet has dimensions of 450mil × 300mil.

[0011] Furthermore, the preset vertical distance between the test holes on the PCB layer 1 to n / 2 and the rectangular copper foil is 326.78 mil.

[0012] Furthermore, the preset horizontal distance between the test hole on the first layer of the PCB board and the rectangular copper foil is 400 mil, and the horizontal distance between adjacent test holes on the first layer to the n / 2 layers of the PCB board is 420 mil.

[0013] Furthermore, the preset vertical distance between the test holes on the (n / 2)+1th layer to the nth layer of the PCB board and the rectangular copper foil is 313.22 mil.

[0014] Furthermore, the preset horizontal distance between the test hole on the (n / 2)+1th layer of the PCB board and the rectangular copper foil is 610mil, and the horizontal distance between adjacent test holes on the (n / 2)+1th layer to the nth layer of the PCB board is 420mil.

[0015] Furthermore, the test holes on layers 1 to n of the PCB are all annular, with an inner diameter of 80 mil and an outer diameter of 140 mil for each test hole.

[0016] Furthermore, the traces between the rectangular copper traces and the test holes on the PCB layer 1 to n / 2 are all composed of upper horizontal segments and upper vertical segments. The length of the upper horizontal segment on the PCB layer 1 is 412.5 mil, and the length difference between adjacent upper horizontal segments on the PCB layer 1 to n / 2 is 420 mil. The length of the vertical segments on the PCB layer 1 to n / 2 is 231.78 mil.

[0017] Furthermore, the traces between the rectangular copper traces and the test holes on layers (n / 2)+1 to n of the PCB are all composed of lower horizontal segments and lower vertical segments. The length of the lower horizontal segment on layer (n / 2)+1 of the PCB is 622.5 mil, and the length difference between the adjacent upper horizontal segments on layers 1 to n / 2 of the PCB is 420 mil. The length of the vertical and horizontal segments on layers 1 to n / 2 of the PCB is 217.22 mil.

[0018] Furthermore, the line width from layer 1 to layer n on the PCB is 25mil.

[0019] The beneficial effects of this invention are as follows: By setting a rectangular copper strip in each layer of the PCB board, the test holes of each layer from layer 1 to n / 2 are determined by using the first vertex of the rectangular copper strip as the base point and a preset offset distance. The test holes of each layer from layer (n / 2)+1 to n are determined by using the second vertex of the rectangular copper strip as the base point and a preset offset distance. This results in the test holes of layers 1 to n of the PCB board being staggered, and the test holes of adjacent layers are determined based on the same vertex of the rectangular copper strip. This facilitates subsequent identification and measurement by testers, and eliminates the need for frequent adjustment of probe positions to confirm the test holes of each layer. Therefore, this invention can optimize testing efficiency and accuracy. Attached Figure Description

[0020] Figure 1 A flowchart illustrating the design method of a PCB board interlayer withstand voltage test module according to the present invention;

[0021] Figure 2 This is a schematic diagram of the overall structure of a PCB board shown in an exemplary embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the L1 layer structure of a PCB board, as shown in an exemplary embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram of the L2 layer structure of a PCB board, as shown in an exemplary embodiment of the present invention.

[0024] Figure 5 This is a schematic diagram of the L3 layer structure of a PCB board, as shown in an exemplary embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of the L4 layer structure of a PCB board, as shown in an exemplary embodiment of the present invention. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0028] Reference Figure 1 As shown, this invention discloses a design method for an interlayer withstand voltage test module for a PCB board, applicable to a PCB board having n layers, where n is an even number greater than or equal to 4; the design method for the interlayer withstand voltage test module includes the following steps:

[0029] S10, rectangular copper strips are provided in the edge rail areas of each layer of the PCB board; specifically, the dimensions of the rectangular copper strips are 450mil×300mil;

[0030] S20, for each layer of the PCB from layer 1 to layer n / 2, the position of the test hole for each layer is determined according to a preset offset distance, with the first vertex of the rectangular copper strip of each layer as the base point. The traces for each layer are set between the second vertex of the rectangular copper strip and the bottom of the test hole. Specifically, the preset vertical distance between the test hole and the rectangular copper strip for layers 1 to n / 2 is 326.78 mil; the preset horizontal distance between the test hole and the rectangular copper strip for layer 1 is 400 mil; and the horizontal distance between adjacent test holes for layers 1 to n / 2 is 420 mil. The test holes on layers 1 to n of the PCB are all annular, with an inner diameter of 80 mil and an outer diameter of 140 mil. The traces between the rectangular copper traces on layers 1 to n / 2 and the test holes consist of upper horizontal and upper vertical segments. The length of the upper horizontal segment on layer 1 is 412.5 mil, and the length difference between adjacent upper horizontal segments on layers 1 to n / 2 is 420 mil. The length of the vertical segments on layers 1 to n / 2 is 231.78 mil. The trace width on layers 1 to n / 2 is 25 mil.

[0031] S30, for layers (n / 2)+1 to n of the PCB, the second vertex of the rectangular copper strip of each layer is used as the base point, and the position of the test hole of each layer is determined according to a preset offset distance. The circuitry of each layer is set between the first vertex of the rectangular copper strip of each layer and the top of the test hole of each layer. Specifically, the preset vertical distance between the test hole and the rectangular copper strip of layers (n / 2)+1 to n of the PCB is 313.22 mil; the preset horizontal distance between the test hole and the rectangular copper strip of layer (n / 2)+1 of the PCB is 610 mil, and the distance between the test hole and the top of the test hole of layers (n / 2)+1 to n of the PCB is... The horizontal distance between adjacent test holes is 420 mil. The traces between the rectangular copper traces and test holes on layers (n / 2)+1 to n of the PCB are all composed of lower-layer horizontal and vertical segments. The length of the lower-layer horizontal segment on layer (n / 2)+1 is 622.5 mil, and the length difference between adjacent upper-layer horizontal segments on layers 1 to n / 2 is 420 mil. The length of the vertical and horizontal segments on layers 1 to n / 2 is 217.22 mil each. The trace width on layers (n / 2)+1 to n is 25 mil. Furthermore, the test holes on layers 1 to n of the PCB are all annular, with an inner diameter of 80 mil and an outer diameter of 140 mil for each test hole.

[0032] It should be noted that, in this embodiment, the design method of the PCB interlayer withstand voltage test module creates a standardized test access point for each layer by setting a rectangular copper strip in the edge area of ​​each layer of the PCB structure. The selection of the edge area avoids occupying the core circuit area, and the rectangular copper strip provides a stable and reliable test contact surface. Furthermore, by grouping layers 1 to n / 2 into one group and layers (n / 2)+1 to n into another group, and using different vertices of the rectangular copper strip as base points, the test hole positions are determined by a preset offset and the circuit is connected, so that the test holes of layers 1 to n of the PCB are staggered, and the test holes of adjacent layers are determined based on the same vertex of the rectangular copper strip. This makes it easier for testers to identify and measure in subsequent tests, and eliminates the need to frequently adjust the probe position to confirm the test holes of each layer. Therefore, this embodiment can optimize test efficiency and accuracy.

[0033] As a preferred embodiment, the test procedure of the PCB interlayer withstand voltage test module is as follows: First, prepare a PCB sample. The PCB usually needs to be baked at a specific temperature before testing to eliminate the influence of moisture, and then cooled to room temperature. Then, the high voltage output terminal and return current terminal probes of the withstand voltage tester are respectively contacted with the test holes corresponding to the two layers to be tested. Next, a specified test voltage is applied to the test hole (for example, from 0V to 500V DC or higher at a rate not exceeding 100V / s) and maintained for a period of time (e.g., 30 seconds), while monitoring the leakage current. Finally, the result is determined. If the leakage current does not exceed the set limit throughout the entire test process, and no breakdown, arcing, or other phenomena occur, the insulation performance between the two layers is judged to be qualified.

[0034] As a preferred embodiment, refer to Figure 2-6 As shown, the PCB board in this embodiment has layers L1, L2, L3, and L4 from top to bottom. Specifically, in designing the interlayer withstand voltage module of this PCB board, firstly, a first rectangular copper strip 1 needs to be set in the edge area of ​​the L1 layer. Taking the first vertex of the first rectangular copper strip 1 as the base point, the position of the first test hole 3 is determined by offsetting a first preset distance (i.e., 400 mil horizontally and 326.78 mil vertically from the first vertex of the first rectangular copper strip 1). A first line 2 is then set between the second vertex of the first rectangular copper strip 1 and the bottom of the first test hole 3. Next, a second rectangular copper strip 4 is set in the edge area of ​​the L2 layer. Taking the first vertex of the second rectangular copper strip 4 as the base point, the position of the second test hole 6 is determined by offsetting a second preset distance (i.e., 820 mil horizontally and 326.78 mil vertically from the first vertex of the second rectangular copper strip 4). A second line 5 is set between the second vertex of the rectangular copper sheet 4 and the bottom of the second test hole 6; next, a third rectangular copper sheet 7 is set in the edge rail area of ​​the L3 layer. Taking the second vertex of the third rectangular copper sheet 7 as the base point, the position of the third test hole 9 is determined by offsetting a third preset distance (i.e., 610 mil horizontally and 313.22 mil vertically from the second vertex of the third rectangular copper sheet 7) and a third line 8 is set between the first vertex of the third rectangular copper sheet 7 and the top of the third test hole 9; finally, a fourth rectangular copper sheet 10 is set in the edge cabinet area of ​​the L4 layer. Taking the second vertex of the fourth rectangular copper sheet 10 as the base point, the position of the fourth test hole 12 is determined by offsetting a fourth preset distance (i.e., 1030 mil horizontally and 313.22 mil vertically from the second vertex of the fourth rectangular copper sheet 10) and a fourth line 11 is set between the first vertex of the fourth rectangular copper sheet 10 and the top of the fourth test hole 12.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] 1. Solved the problem of being unable to measure interlayer withstand voltage when there is no measurement location inside the PCB circuit board and there are requirements for interlayer dielectric thickness and withstand voltage;

[0037] 2. The rectangular copper sheet is 450mil wide and is far from the effective area of ​​the graphic. The length extends in the long direction according to the number of layers. There is no need to delete Pcs when adding modules, thus maximizing the utilization of the board material.

[0038] 3. It can meet the requirements of all lamination withstand voltage tests for multilayer (≥30 layers) circuit boards. When facing high-layer boards, this design can extend the horizontal length of the module without changing the vertical length, which helps to save board material.

[0039] 4. The measuring aperture is 80 mil, which is relatively large and can meet the requirements of different voltage-resistant probe equipment, making it universally applicable.

[0040] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A design method for an interlayer withstand voltage test module for a PCB board, applied to a PCB board having n layers, wherein, n is an even number greater than or equal to 4; characterized in that the design method of the PCB interlayer withstand voltage test module includes the following steps: S10, rectangular copper foil is set in the edge rail area of ​​each layer of the PCB board; S20, the first vertex of the rectangular copper skin of each layer of the PCB board is used as the base point, and the position of the test hole of each layer is determined according to the preset offset distance. The circuit of each layer is set between the second vertex of the rectangular copper skin of each layer and the bottom of the test hole of each layer. S30, for the (n / 2)+1 to nth layers of the PCB board, the second vertex of the rectangular copper skin of each layer is used as the base point, and the position of the test hole of each layer is determined according to the preset offset distance. The circuit of each layer is set between the first vertex of the rectangular copper skin of each layer and the top of the test hole of each layer.

2. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, In step S10, the rectangular copper sheet has dimensions of 450mil × 300mil.

3. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The preset vertical distance between the test holes on layers 1 to n / 2 of the PCB board and the rectangular copper foil is 326.78 mil.

4. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The preset horizontal distance between the test hole on the first layer of the PCB board and the rectangular copper foil is 400 mil, and the horizontal distance between adjacent test holes on the first layer to the n / 2 layers of the PCB board is 420 mil.

5. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The preset vertical distance between the test holes on the (n / 2)+1th layer to the nth layer of the PCB board and the rectangular copper foil is 313.22 mil.

6. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The preset horizontal distance between the test hole on the (n / 2)+1th layer of the PCB board and the rectangular copper foil is 610mil, and the horizontal distance between adjacent test holes from the (n / 2)+1th layer to the nth layer of the PCB board is 420mil.

7. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The test holes on layers 1 to n of the PCB are all annular, with an inner diameter of 80 mil and an outer diameter of 140 mil.

8. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The traces between the rectangular copper traces and the test holes on the PCB layer 1 to n / 2 are all composed of upper horizontal segments and upper vertical segments. The length of the upper horizontal segment on the PCB layer 1 is 412.5 mil, and the length difference between adjacent upper horizontal segments on the PCB layer 1 to n / 2 is 420 mil. The length of the vertical segments on the PCB layer 1 to n / 2 is 231.78 mil.

9. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The traces between the rectangular copper traces and the test holes on layers (n / 2)+1 to n of the PCB board are all composed of lower horizontal segments and lower vertical segments. The length of the lower horizontal segment on layer (n / 2)+1 of the PCB board is 622.5 mil, and the length difference between the adjacent upper horizontal segments on layers 1 to n / 2 of the PCB board is 420 mil. The length of the vertical and horizontal segments on layers 1 to n / 2 of the PCB board is 217.22 mil.

10. The design method of a PCB board interlayer withstand voltage test module according to claim 1, characterized in that, The trace width from layer 1 to layer n on the PCB board is 25mil.

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