High-swing PAM3 electro-optical modulator driving circuit
By using a high-swing output stage with series PMOS and NMOS transistors and a digitally adjustable module, the problems of intermediate level compensation and transistor safety in the PAM3 modulator are solved, achieving high-swing output and improved optical linearity, and simplifying circuit design.
Patent Information
- Application Number
- CN202511693880.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-03-03
AI Technical Summary
Existing technologies struggle to achieve digitally adjustable compensation of the intermediate level of a PAM3 modulator without reducing the maximum swing, and high-swing output is difficult to achieve under conventional CMOS processes. Furthermore, there are issues related to transistor safety and nonlinear compensation.
The main output stage achieves stacked high-slew output by connecting PMOS and NMOS transistors in series, and performs short-pulse pre-charging and discharging of internal nodes at the moment of switching. Combined with a digitally adjustable adjustment module and pulse generator, the intermediate level is adjusted to compensate for micro-ring nonlinearity.
Without sacrificing maximum swing, optical linearity and receiver BER were improved, transistor breakdown risk was reduced, circuit structure was simplified, and system performance was enhanced.
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Figure CN121596592A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optical communication technology, and in particular to a high-swing PAM3 electro-optic modulator driving circuit. Background Technology
[0002] Micro-ring modulators shift the resonant peak by altering the effective refractive index of the ring waveguide, thereby achieving intensity modulation at a fixed laser wavelength. In silicon photonics, the refractive index change per volt is limited; to obtain sufficient modulation depth or resist temperature drift and process variations, a larger voltage swing is typically required. PAM3 modulation has advantages over PAM4 in terms of voltage margin and signal distortion sensitivity. Designing a driver capable of generating a large swing while compensating for micro-ring nonlinearity is crucial for system performance (e.g., eye diagram opening, bit error rate). Currently, a practical circuit scheme is lacking that can digitally adjust compensation (predistortion) for the intermediate level without reducing the maximum swing.
[0003] Existing methods for increasing swing amplitude include thick-gate processes, special process components, and transistor stacking, but these methods involve trade-offs in process compatibility, speed, or reliability. Existing nonlinear compensation (such as de-emphasis) often comes at the cost of sacrificing maximum swing amplitude. PAM4-encoded micro-ring modulation schemes require additional opto-electrical DAC structures, increasing complexity and power consumption.
[0004] Under conventional CMOS processes, especially with low VDD (e.g., VDD≈0.8V or lower), it is difficult to achieve a high swing output of ±2×VDD at the single end and 4×VDD at the differential synthesis end while ensuring transistor safety. The inherent nonlinearity of the microring resonator causes the intermediate level (the intermediate level of PAM3) to deviate from the ideal linear model, affecting optical linearity and system bit error rate. Summary of the Invention
[0005] In view of this, the present invention proposes a high-swing PAM3 electro-optic modulator driving circuit, which realizes high-swing output of the main output stage by connecting PMOS transistors and NMOS transistors in series, and adds transistors in the series path to perform short pulse pre-charging and discharging of internal nodes at the moment of switching, thereby reducing the risk of breakdown caused by exceeding the process limit and improving the safety of transistors.
[0006] In a first aspect, the present invention provides a high-swing PAM3 electro-optic modulator driving circuit, comprising a P-differential structure, an N-differential structure, an adjustment module, a calibration control module, and a pulse generator, wherein... The P-differential structure is used to input a first signal and output a first level. The N-differential structure is used to input a second signal and output a second level; The adjustment module is used to adjust the level of the intermediate level when the output is at the intermediate level, and the intermediate level is an intermediate state between high level and low level; The calibration control module is used to generate PAM3 code when the output intermediate level is reached, and to calibrate the intermediate level based on the PAM3 code. The PAM3 code includes SW_P and SW_N codes. The pulse generator is used to precharge and pre-discharge the internal nodes at the instant of the switching between the first and second output levels. By adjusting the level of the intermediate output level, nonlinear adjustment of the micro-ring electro-optic modulation can be achieved without changing the output swing.
[0007] Based on the above technical solutions, preferably, the P differential structure includes a first output branch, a second output branch, a first inverter INV1, a second inverter INV4, a third inverter INV3, a fourth inverter INV2, a first pulse drive PULSE1, a second pulse drive PULSE4, a third pulse drive PULSE3, and a fourth pulse drive PULSE2.
[0008] Based on the above technical solutions, preferably, the N-differential structure includes a third output branch, a fourth output branch, a fifth inverter INV5, a sixth inverter INV8, a seventh inverter INV7, an eighth inverter INV6, a fifth pulse driver PULSE5, a sixth pulse driver PULSE8, a seventh pulse driver PULSE7, and an eighth pulse driver PULSE6.
[0009] Based on the above technical solutions, preferably, the first inverter INV1, the second inverter INV4, the first pulse drive PULSE1, and the second pulse drive PULSE4 are driven and controlled by the L input, and the fifth inverter INV5, the sixth inverter INV8, the fifth pulse drive PULSE5, and the sixth pulse drive PULSE8 are driven and controlled by the LB input.
[0010] Based on the above technical solutions, preferably, the third inverter INV3, the fourth inverter INV2, the third pulse drive PULSE3, and the fourth pulse drive PULSE2 are driven and controlled by the HB input, and the seventh inverter INV7, the eighth inverter INV6, the seventh pulse drive PULSE7, and the eighth pulse drive PULSE6 are driven and controlled by the H input.
[0011] Based on the above technical solutions, preferably, the first output branch includes a first PMOS transistor MP5, a first NMOS transistor MN6, a second PMOS transistor MP7, and a second NMOS transistor MN8, wherein the first PMOS transistor MP5 and the first NMOS transistor MN6 are connected in series, and the second PMOS transistor MP7 and the second NMOS transistor MN8 are connected in series.
[0012] Based on the above technical solution, preferably, the second output branch includes a third PMOS transistor MP17, a third NMOS transistor MN18, a fourth PMOS transistor MP15, and a fourth NMOS transistor MN16, wherein the third PMOS transistor MP17 and the third NMOS transistor MN18 are connected in series, and the fourth PMOS transistor MP15 and the fourth NMOS transistor MN16 are connected in series.
[0013] Based on the above technical solutions, preferably, the adjustment module includes a first PMOS drive adjustment unit, a second PMOS drive adjustment unit, a first NMOS drive adjustment unit, and a second NMOS drive adjustment unit.
[0014] Based on the above technical solutions, preferably, the pulse generator includes a down-thrust logic drive generator and an up-thrust logic drive generator, wherein the down-thrust logic drive generator is used to pre-charge the PMOS transistor, and the up-thrust logic drive generator is used to pre-charge the NMOS transistor.
[0015] Based on the above technical solution, preferably, when the first PMOS transistor MP5, the second PMOS transistor MP7, the third NMOS transistor MN18 and the fourth NMOS transistor MN16 are turned on, and the first NMOS transistor MN6, the second NMOS transistor MN8, the third PMOS transistor MP17 and the fourth PMOS transistor MP15 are turned off, the output level of the first output branch and the second output branch is high.
[0016] Based on the above technical solution, preferably, when the first NMOS transistor MN6, the second NMOS transistor MN8, the third PMOS transistor MP17 and the fourth PMOS transistor MP15 are turned on, and the first PMOS transistor MP5, the second PMOS transistor MP7, the third NMOS transistor MN18 and the fourth NMOS transistor MN16 are turned off, the output level of the first output branch and the second output branch is low.
[0017] Based on the above technical solutions, preferably, when the second PMOS transistor MP7, the second NMOS transistor MN8, the third PMOS transistor MP17 and the third NMOS transistor MN18 are turned on, and the first PMOS transistor MP5, the first NMOS transistor MN6, the fourth PMOS transistor MP15 and the fourth NMOS transistor MN16 are turned off, the differential output level of the first output branch and the second output branch is the intermediate level.
[0018] The high-swing PAM3 electro-optic modulator driving circuit provided by this invention has the following advantages over the prior art: (1) By connecting PMOS and NMOS transistors in series, the main output stage is stacked high-swing output. A transistor is added in the series path to perform short pulse pre-charge and discharge on the internal node at the moment of switching, avoiding the risk of voltage breakdown caused by exceeding the process limit, improving the safety of the transistor and the output swing. The intermediate level of the driving voltage is dynamically changed by the digitally adjustable adjustment module, which can adjust the equivalent impedance of the output branch and change the voltage difference of the intermediate node to achieve pre-distortion compensation. Thus, the optical linearity is improved without sacrificing the maximum swing, and the nonlinear characteristics of the micro-ring modulator are compensated without reducing the output swing.
[0019] (2) By introducing high-swing drive logic into the PAM3 structure, the output swing is increased while ensuring the safe breakdown of the transistor. When the output is at the intermediate level, the equivalent resistance of the pull-up and pull-down resistors is changed by adjusting the module, thereby changing the position of the intermediate level and compensating for the nonlinearity of the micro-ring. This invention does not affect the conduction capability of the pull-up or pull-down resistors in the maximum swing state. It can compensate for the nonlinear response of the micro-ring without reducing the maximum swing, significantly reducing eye diagram distortion, improving the receiver BER and eye diagram opening, improving the linearity of the PAM3 optical signal, and reducing eye diagram distortion.
[0020] (3) The electro-optic modulation driving scheme is directly implemented through PAM3 encoding, eliminating the need for multi-segment optical DAC or electrical DAC, retaining the original logic of PAM3, and reducing the complexity of system design. While ensuring high modulation swing, it has better voltage margin and receiving sensitivity. By adopting a digitally controlled thermometer encoding method, it is compatible with conventional CMOS processes, has better process compatibility, and simplifies the circuit structure. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 A schematic diagram of the high swing PAM3 electro-optic modulator driving circuit provided by the present invention; Figure 2 This is a schematic diagram of the P-difference structure provided in the embodiments of this application; Figure 3 This is a schematic diagram of the N-difference structure provided in the embodiments of this application; Figure 4 This is a schematic diagram of the PN differential structure provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the PMOS drive adjustment unit and the NMOS drive adjustment unit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the pulse generator provided in the embodiments of this application; Figure 7 This is a schematic diagram of the electro-optical conversion process provided in the embodiments of this application; Figure 8 This is a circuit diagram of a conventional driving scheme provided in the embodiments of this application; Figure 9 This is a comparison diagram between the conventional driving scheme provided in this application embodiment and the present scheme; Figure 10 This is a schematic diagram illustrating the simplified principle of PAM3 high swing output provided in the embodiments of this application; Figure 11 This is a schematic diagram of the PAM3 high swing circuit structure at the intermediate level provided in the embodiments of this application; Figure 12 This is a schematic diagram of the PAM3 high-swing circuit structure at a high level provided in the embodiments of this application; Figure 13 This is a schematic diagram of the PAM3 high swing circuit structure at low level provided in the embodiments of this application; Figure 14 This is a schematic diagram of a traditional PAM3 de-emphasis predistortion scheme provided in an embodiment of this application; Figure 15 These are simulation experiment comparison diagrams provided in the embodiments of this application; Figure 16 This is a comparison table of adjusted optical PAM3 and electrical PAM3 eye diagrams provided in the embodiments of this application; Figure 17 This is an example diagram of the key input and output voltage waveforms of the circuit provided in the embodiments of this application.
[0023] Explanation of reference numerals in the attached diagram: 1. P-differential structure; 2. N-differential structure; 3. Adjustment module; 4. Calibration control module; 5. Pulse generator. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0025] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.
[0026] like Figure 1 As shown, this invention provides a high-swing PAM3 electro-optic modulator driving circuit, including a P-differential structure 1, an N-differential structure 2, an adjustment module 3, a calibration control module 4, and a pulse generator 5, wherein... The P-differential structure 1 is used to input a first signal and output a first level; The N-differential structure 2 is used to input the second signal and output the second level; The adjustment module 3 is used to adjust the level of the intermediate level when the output is at the intermediate level, and the intermediate level is an intermediate state between high level and low level; The calibration control module 4 is used to generate PAM3 code when the output intermediate level is reached, and to calibrate the intermediate level based on the PAM3 code. The PAM3 code includes SW_P and SW_N codes. For example, the calibration control module 4 includes a lookup table (LUT) or closed-loop calibration logic, which can be an MCU, FPGA, digital controller, and A / D converter, used to generate SW_P / SW_N codes and perform runtime or factory calibration.
[0027] The pulse generator 5 is used to precharge and pre-discharge the internal nodes at the instant of the switching between the first and second output levels. For example, the high-swing PAM3 electro-optic modulator driving circuit also includes an auxiliary transistor, which may be MP8, MN8, MP18, MN18 or equivalent devices, used to precharge and pre-discharge the internal nodes at the moment of output switching, limit the burst overvoltage of the main transistor, protect the transistor and achieve high swing capability.
[0028] The triggering of pulse generator 5 can be optimized for switching losses and transient stress using pulses with different pulse widths or sequential transistor gate pulses.
[0029] By adjusting the level of the intermediate output level, nonlinear adjustment of the micro-ring electro-optic modulation can be achieved without changing the output swing.
[0030] In some embodiments, a high-speed ADC+DSP can be added for online digital predistortion.
[0031] In some embodiments, the P differential structure 1 includes a first output branch OUTP, a first inverter INV1, a second inverter INV4, a third inverter INV3, a fourth inverter INV2, a first pulse drive PULSE1, a second pulse drive PULSE4, a third pulse drive PULSE3, and a fourth pulse drive PULSE2.
[0032] Figure 2 This is a schematic diagram of the P-differential structure provided in the embodiments of this application, as shown below. Figure 2 As shown, the first output branch OUTP includes a first PMOS transistor MP5, a first NMOS transistor MN6, a second PMOS transistor MP7, and a second NMOS transistor MN8. The first PMOS transistor MP5 and the first NMOS transistor MN6 are connected in series, and the second PMOS transistor MP7 and the second NMOS transistor MN8 are connected in series.
[0033] The first inverter INV1, the second inverter INV4, the first pulse drive PULSE1, and the second pulse drive PULSE4 are driven and controlled by the L input, while the fifth inverter INV5, the sixth inverter INV8, the fifth pulse drive PULSE5, and the sixth pulse drive PULSE8 are driven and controlled by the LB input.
[0034] Each path consists of a PMOS transistor on the upper end and an NMOS transistor on the lower end, with the series connection node being an internal node. The two differential paths are combined in parallel to form differential outputs OUTP and OUTN, thereby enabling differential synthesized swing.
[0035] In some embodiments, the N-differential structure 2 includes a second output branch OUTN, a fifth inverter INV5, a sixth inverter INV8, a seventh inverter INV7, an eighth inverter INV6, a fifth pulse drive PULSE5, a sixth pulse drive PULSE8, a seventh pulse drive PULSE7, and an eighth pulse drive PULSE6.
[0036] Figure 3 This is a schematic diagram of the N-difference structure provided in the embodiments of this application, as shown below. Figure 3 As shown, the second output branch OUTN includes a third PMOS transistor MP17, a third NMOS transistor MN18, a fourth PMOS transistor MP15, and a fourth NMOS transistor MN16. The third PMOS transistor MP17 and the third NMOS transistor MN18 are connected in series, and the fourth PMOS transistor MP15 and the fourth NMOS transistor MN16 are connected in series.
[0037] The third inverter INV3, the fourth inverter INV2, the third pulse drive PULSE3, and the fourth pulse drive PULSE2 are driven and controlled by the HB input, while the seventh inverter INV7, the eighth inverter INV6, the seventh pulse drive PULSE7, and the eighth pulse drive PULSE6 are driven and controlled by the H input.
[0038] It should be noted that L, H, LB, and HB are four high-swing input control signals after PAM3 encoding, and LB and HB are the inverted signals of L and H, respectively.
[0039] Figure 4 This is a schematic diagram of the PN differential structure provided in the embodiments of this application, as shown below. Figure 4As shown, the PN differential structure includes L input, HB input, LB input, and H input, a first output branch OUTP, and a second output branch OUTN, used to complete differential logic control. The P-differential and N-differential structures are symmetrical, differing only in their control logic. The P-differential structure is controlled by L and HB, while the N-differential structure is controlled by LB and H. Both the P-differential and N-differential structures have two stacked MOS transistor branches. Each branch consists of a series-connected PMOS and NMOS transistors forming the main output stage. For example, the main output stage of the second output branch of the P-differential structure is an MP7-MP8-MN7-MN8 structure. The intermediate node between MP8 and MN7 is connected to the intermediate node between MP6 and MN5, serving as the output node of this branch. MP6 and MN5 are high-swing stacked driver auxiliary transistors. The intermediate node between MP6 and MN5 is the output node of the left branch of the P-differential structure. Pulse generators PULSE1 and PULSE3 are used to pre-charge and discharge the gates of MP6 and MN5 during high-level or low-level output transitions to prevent MP6 and MN5 from being damaged by excessive voltage. MP8 and MN7 are both high-swing stacked drive auxiliary transistors. Pulse generators PULSE2 and PULSE4 are used to pre-charge and discharge the gates of MP8 and MN7 during high-level or low-level output transitions to prevent MP7 and MN8 from being damaged by excessive voltage.
[0040] It is worth noting that the output terminals of each output branch are connected via... Figure 4 The connection shown is to the load and the optical modulator. The high, medium, and low output levels correspond to the optical eye diagram required for PAM-3 modulation. Ideally, the highest output drive level is 2VDD, the lowest output drive level is -2VDD, and the intermediate output level is adjustable near 0V, with a total output swing of 4VDD.
[0041] In some embodiments, the adjustment module 3 includes a first PMOS drive adjustment unit, a second PMOS drive adjustment unit, a first NMOS drive adjustment unit, and a second NMOS drive adjustment unit.
[0042] It's easy to understand that the main control MOSFET in the middle branch of the PAM3 high-swing differential drive is controlled by a drive adjustment unit, which is divided into a PMOS drive adjustment unit and an NMOS drive adjustment unit. Figure 5 This is a schematic diagram of the structure of the PMOS drive adjustment unit and the NMOS drive adjustment unit provided in the embodiments of this application, as shown below. Figure 5 As shown, the drive adjustment unit is responsible for adjusting the level of the intermediate level when the circuit outputs an intermediate level without changing the output swing, thereby realizing the nonlinear adjustment of the micro-loop.
[0043] Specifically, based on the thermometer encoding signals SW_P_P<0:3> / SW_N_P<0:3> (controlling the upper branch conduction impedance) or SW_N_P<0:3> / SW_N_N<0:3> (controlling the lower branch conduction impedance) and the main data signals H, HB, L, LB, when linearity adjustment is required, the logic gates turn on multiple sets of switching transistors. By adjusting the number of turned-on transistors, the path resistance is controlled, thus changing the output level of that branch. When the encoding signal is set, the corresponding NAND gate operates, changing the pull-up or pull-down resistors and altering the intermediate swing of the P-differential and N-differential structures. When the encoding is reset, the corresponding NAND gate deactivates, and the differential intermediate level of the high-swing drive module returns to 0. The output intermediate level can be finely adjusted via digital control. For example, different swing compensations can be applied to different output eye diagram levels based on test or calibration results to achieve uniform eye height in the optical output.
[0044] For example, a digitally adjustable drive adjustment unit is introduced into the pull-up and pull-down networks of each output branch. A thermometer encoding structure, composed of logic gates, NAND gates, inverters, and a set of parallel switching transistors, is jointly controlled by the thermometer encoding signals SW_P_P<0:3>, SW_P_N<0:3> / SW_N_P<0:3>, SW_N_N<0:3>, and the main data signals HB, LB, H, and L. The amplitude adjustment unit changes the equivalent resistance of the main circuit only when the output is at the intermediate level, thereby adjusting the voltage of that intermediate level and achieving pre-distortion compensation for optical nonlinearity.
[0045] The drive adjustment unit can be extended by multi-bit thermometer encoding, such as 4-bit or 6-bit, to improve adjustment resolution.
[0046] The amplitude adjustment control codes SW_P_P<0:3>, SW_P_N<0:3> / SW_N_P<0:3>, and SW_N_N<0:3> can be generated from the pre-measured LUT or the closed-loop feedback during operation, such as measuring the optical power of the photodiode or the receiver BER index, supporting one-time factory calibration or periodic online calibration.
[0047] Each branch's driving PMOS and NMOS transistors incorporates a drive adjustment unit to dynamically adjust the output swing and improve optical linearity. When the output is at the intermediate level, the right branch of the stacked P-differential MOS transistors is turned on, and the left branch of the stacked N-differential MOS transistors is turned on. At this time, the number of turned-on MOS transistors is changed by digital circuitry, thereby adjusting the resistance of the pull-up MOS transistors and pull-down MOS transistors of the P-differential and N-differential structures respectively. This achieves the adjustment of the intermediate level of the P-differential structure and the N-differential structure, resulting in a predistortion effect. Although the digital control mode starts working at any output level, the adjustment module has almost no effect when adjusting the turned-off MOS transistors, which remain approximately infinite. Therefore, the predistortion only changes the intermediate logic level and never reduces the output swing.
[0048] Figure 6 This is a schematic diagram of the pulse generator provided in the embodiments of this application, as shown below. Figure 6 As shown, two types of PULSE pulse generators are used to pre-charge and discharge the gate of the stacked auxiliary MOS transistor when the output level changes from high to low, so as to avoid the main control MOS transistor being subjected to excessive voltage and breaking down. Figure 6 Figure (a) shows the undershoot logic driver generator for NAND gate logic, which is responsible for pre-charging the stacked PMOS. Figure 6 Figure (b) shows an overshoot logic driver generator for NOR logic, which is responsible for pre-charging the stacked NMOS.
[0049] Figure 7 This is a schematic diagram of the electro-optical conversion process provided in the embodiments of this application, such as... Figure 7 As shown, the electrical mid-level of PAM3 changes after pre-distortion, resulting in an electrical eye diagram that is narrower at the top and wider at the bottom. The high-swing output branches OUTP and OUTN are connected to the two poles of the microring, respectively. After the microring modulates the PAM3 electrical signal into an optical signal, it results in an optical eye diagram with the upper and lower eye levels being consistent.
[0050] During circuit operation, the PAM3 high-swing driver first receives the main data signals HB and LB from the upper-level MUX. Based on the input combination, the upper and lower branches generate corresponding high, medium, and low output levels, which are synthesized into a complete 4VDD PAM3 differential signal through a differential structure. The initial swing of the driver output reaches ±2VDD. If simulation or testing results show optical output eye diagram distortion or low linearity, the control logic changes the thermometer encoding SW_P_P<0:3> / SW_N_P<0:3> to control the upper branch or SW_P_N<0:3> / SW_N_N<0:3> to control the lower branch, compensating for the intermediate level output. The adjustment method can be achieved through a pre-set lookup table or closed-loop feedback calibration, with the controller generating PWM code or digital code. The feedforward equalization parameters can also be preset or dynamically adjusted according to channel conditions.
[0051] The compensation of the intermediate level only changes the equivalent impedance of the intermediate state and does not affect the maximum pull-up and pull-down conduction capabilities, so the maximum swing remains unchanged.
[0052] Figure 8 This is a circuit diagram of a conventional driving scheme provided in the embodiments of this application, such as... Figure 8 As shown, traditional driving schemes employ N over N control logic, offering high speed and good layout symmetry. However, the weak-1 characteristic of NMOS further degrades the swing amplitude. Traditional driving schemes offer no advantage in micro-ring applications. Furthermore, the single-ended output of traditional driving schemes provides weak noise immunity and lacks pre-distortion control, making them unsuitable for direct application to micro-ring structures.
[0053] Figure 9 This is a comparison diagram between the traditional driving scheme provided in this application embodiment and the scheme presented herein. Figure 9 Figure (a) illustrates the limitations of traditional driving schemes. Low-swing PAM3 drivers and high-swing PAM3 drivers without predistortion have limitations in micro-ring applications. Micro-ring modulators shift the resonant peak by changing the effective refractive index of the ring waveguide, thereby achieving intensity modulation at a fixed laser wavelength. This places high demands on the voltage swing. The refractive index change per volt in silicon photonics is limited, and low-swing structures often lead to eye diagram deterioration. In addition, high-swing structures without nonlinear predistortion can also cause inconsistent optical eye diagram opening, worsening the bit error rate and failing to achieve the best optical eye diagram output effect.
[0054] Figure 9 Figure (b) in the figure is a demonstration diagram of this scheme. By introducing a stacked high swing drive scheme and digital level adjustment, the intermediate level of PAM3 is preprocessed in the electrical module, and a high swing PAM3 optical uniform eye diagram is obtained by micro-ring modulation. Furthermore, the pre-distortion does not reduce the output swing of the original optical eye diagram, thus achieving the optimal output scheme of the eye diagram.
[0055] In some embodiments, the auxiliary transistors include P-type auxiliary transistors and N-type auxiliary transistors. The P-type auxiliary transistors include a first transistor MP6, a second transistor MP18, a third transistor MP8, and a fourth transistor MP16. The N-type auxiliary transistors include a fifth transistor MN7, a sixth transistor MN5, a seventh transistor MN17, and an eighth transistor MN15.
[0056] In some embodiments, when the first PMOS transistor MP5, the second PMOS transistor MP7, the third NMOS transistor MN18, and the fourth NMOS transistor MN16 are turned on, and the first NMOS transistor MN6, the second NMOS transistor MN8, the third PMOS transistor MP17, and the fourth PMOS transistor MP15 are turned off, the output levels of the first output branch and the second output branch are high.
[0057] Figure 10 This is a schematic diagram illustrating the simplified principle of the PAM3 high swing output provided in the embodiments of this application, as shown below. Figure 10 As shown, the digital circuit changes the driving logic, adjusting the number of pull-up MOS and pull-down MOS that are turned on in the P-differential and N-differential structures respectively. This, in turn, changes the resistance of the pull-up MOS and pull-down MOS, thereby raising and lowering the intermediate level of the P-differential structure and the N-differential structure respectively. This changes the output intermediate level and achieves the effect of predistortion. Furthermore, since only the intermediate level of the differential structure is changed, without changing the high and low level positions of the output, the predistortion will not reduce the output swing from beginning to end.
[0058] exist Figure 10 In Figure (b), when the output is at the intermediate level, the input signals L=1 and H=1. The circuit structure can be simplified to two open switch branches and two impedance voltage adjustment branches with outputs OUTP and OUTN, respectively. The output intermediate level is controlled by SW_P_P<0:3> / SW_N_P<0:3> and SW_P_N<0:3> / SW_N_N<0:3>.
[0059] Specifically, MP1~4 are selectively turned on by the digital logic SW_P_P<0:3> and then connected in parallel with MP7. MN1~4 are selectively turned on by the digital logic SW_P_N<0:3> and then connected in parallel with MN8. The resistance values of the upper and lower branches of the P differential structure are adjustable within a certain range, thereby changing the voltage of the OUTP node.
[0060] MP11~14 are selectively turned on by the digital logic SW_N_P<0:3> and then connected in parallel with MP17. MN11~14 are selectively turned on by the digital logic SW_N_N<0:3> and then connected in parallel with MN8. The resistance values of the upper and lower branches of the N differential structure are adjustable within a certain range, thereby changing the voltage of the OUTN node.
[0061] By controlling the amplitude adjustment code, the OUTP node voltage can fluctuate around VDD when the output is at the intermediate level, and the OUTN node voltage can also fluctuate around VDD when the output is at the intermediate level. When the voltage division of the upper branch in the P structure is higher than that of the lower branch, and the voltage division of the lower branch in the N structure is higher than that of the upper branch, the OUTN node voltage is greater than the OUTP node voltage. At this time, the intermediate level shifts downward, and the output electrical eye diagram is adjustable within a certain range of width at the top and narrowness at the bottom, thereby correcting the optical eye diagram distortion.
[0062] Figure 11 This is a schematic diagram of the PAM3 high swing circuit structure at the intermediate level provided in the embodiments of this application, as shown below. Figure 11 As shown, when the output is at the intermediate level, the right branch of the stacked MOS of the P-differential structure is turned on, and the left branch of the stacked MOS of the N-differential structure is turned on. The gate of the auxiliary transistor is controlled by a pulse signal, which stabilizes the internal node potential at the moment of output switching, preventing overvoltage between the drain and source of the main transistor. The driving PMOS and driving NMOS transistors of the corresponding branches are equipped with driving adjustment units to dynamically adjust the output swing to improve optical linearity. When the output is at the intermediate level, the right branch of the stacked MOS in the P-differential structure is turned on, and the left branch of the stacked MOS in the N-differential structure is turned on. At this time, by changing the number of turned-on MOS transistors through digital circuitry, the resistance of the pull-up MOS and pull-down MOS of the P / N differential structure are adjusted respectively, thereby adjusting the intermediate level of the P-differential structure and the intermediate level of the N-differential structure, achieving the effect of predistortion. Although the digital control mode will start working at any output level, since the adjustment module has almost no effect when adjusting the turned-off MOS transistors, the turned-off MOS transistors are still approximately infinite. Therefore, predistortion only changes the intermediate logic level and will not reduce the output swing from beginning to end.
[0063] exist Figure 10 In Figure (a), when the output is high, the input signals L=0 and H=1. The circuit structure can be simplified to eight sets of switches connected in series or parallel. At this time, all parallel switches of the differential P structure connected to the high level are closed, and all parallel switches connected to the high level are open, resulting in an output signal of 2VDD. At this time, all parallel switches of the differential N structure connected to the high level are open, and all parallel switches connected to the high level are closed, resulting in an output signal of -2VDD. The differential output level is 4VDD at this time. Figure 12 This is a schematic diagram of the PAM3 high-swing circuit structure at high level provided in the embodiments of this application, as shown below. Figure 12 As shown, when a high level output is required, the upper PMOS on the two branches of the differential PMOS structure is turned on, and the corresponding lower NMOS is turned off; the lower NMOS on the two branches of the differential NMOS structure is turned on, and the upper PMOS on the corresponding branch is turned off; the gates of auxiliary transistors MP6, MP8, MN17, and MN15 are controlled by pulse signals, so that the internal node potential is stabilized at the moment of output flipping, preventing overvoltage between the drain and source of the main transistor.
[0064] In some embodiments, when the first NMOS transistor MN6, the second NMOS transistor MN8, the third PMOS transistor MP17, and the fourth PMOS transistor MP15 are turned on, and the first PMOS transistor MP5, the second PMOS transistor MP7, the third NMOS transistor MN18, and the fourth NMOS transistor MN16 are turned off, the output levels of the first output branch and the second output branch are low.
[0065] exist Figure 10 In diagram (c), when the output is low, the input signals L=1 and H=0. The circuit structure can be simplified to eight sets of switches connected in series or parallel. At this time, all parallel switches connected to the high level in the differential P structure are open, and all parallel switches connected to the high level are closed, resulting in an output signal of -2VDD. At this time, all parallel switches connected to the high level in the differential N structure are closed, and all parallel switches connected to the high level are open, resulting in an output signal of 2VDD. The differential output level is -4VDD.
[0066] Figure 13 This is a schematic diagram of the PAM3 high swing circuit structure at low level provided in the embodiments of this application, as shown below. Figure 13 As shown, when a low level output is required, the upper PMOS on both branches of the differential NMOS structure is turned on, and the corresponding lower NMOS is turned off; the lower NMOS on both branches of the differential PMOS structure is turned on, and the upper PMOS on the corresponding branch is turned off; the gates of auxiliary transistors MP6, MP8, MN17, and MN15 are controlled by pulse signals, so that the internal node potential is stabilized at the moment of output flip, preventing overvoltage between the drain and source of the main transistor.
[0067] In some embodiments, when the second PMOS transistor MP7, the second NMOS transistor MN8, the third PMOS transistor MP17, and the third NMOS transistor MN18 are turned on, and the first PMOS transistor MP5, the first NMOS transistor MN6, the fourth PMOS transistor MP15, and the fourth NMOS transistor MN16 are turned off, the output levels of the first output branch and the second output branch are intermediate levels.
[0068] Figure 14This is a schematic diagram of a traditional PAM3 de-emphasis predistortion scheme provided in an embodiment of this application, as shown below. Figure 14 As shown, traditional nonlinear adjustment schemes mainly address micro-loop nonlinearity by de-emphasis. This approach leads to a decrease in swing amplitude for both PAM-4 encoding with optical and electrical DACs and PAM3 encoding, failing to achieve a true four-fold power supply voltage swing. While pre-emphasis schemes can improve the original swing amplitude, the existing high-swing drive structure requires a higher power supply voltage and interface than 2VDD, inevitably increasing cost and power consumption.
[0069] Figure 15 These are simulation experiment comparison diagrams provided in the embodiments of this application. Figure 15 Figure (a) in the diagram is a simulation diagram of the traditional drive scheme. Figure 15 Figure (b) in the figure is a simulation diagram based on the PAM3 high swing drive scheme. Figure 16 This is a comparison table of adjusted optical PAM3 and electrical PAM3 eye diagrams provided in the embodiments of this application, such as... Figure 16 As shown in the simulation and experiments, the PAM3 high-swing drive circuit can achieve an output swing of up to 4 × 1V = 4Vpp under typical VDD = 1V, which is a significant improvement compared to the traditional drive's approximately 0.3Vpp. Simultaneously, by utilizing nonlinear predistortion, the optical power difference between different output levels can be made more uniform, reducing the inherent nonlinear distortion of the micro-ring modulator and improving the signal's eye diagram opening and bit error rate performance. Furthermore, the predistortion method does not reduce the output swing. The drive circuit outputs a modified PAM-3 waveform input to the micro-ring modulator, achieving greater modulation depth and better optical signal linearity.
[0070] Figure 17 This is an example diagram of the key input and output voltage waveforms of the circuit provided in the embodiments of this application, such as... Figure 17 As shown in the waveform, the process of inputting PAM3 encoded signals L, H, LB, and HB into differential signals OUTP and OUTN to form a high-swing differential output OUT signal is illustrated.
[0071] It is worth emphasizing that the predistortion method based on PAM3 high swing drive does not reduce the output swing. By inputting the modified PAM3 waveform into the micro-ring modulator, a greater modulation depth and better optical signal linearity can be achieved.
[0072] In this embodiment, a stacked high-swing output of the main output stage is achieved by connecting PMOS and NMOS transistors in series. A transistor is added to the series path to pre-charge and discharge the internal nodes with short pulses during switching, avoiding the risk of voltage breakdown caused by exceeding the process limits and improving the safety and output swing of the transistors. The intermediate level of the driving voltage is dynamically changed by a digitally adjustable adjustment module, thereby compensating for the nonlinear characteristics of the micro-ring modulator without changing the output swing.
[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A high-swing PAM3 electro-optic modulator driving circuit, characterized in that, It includes a P-differential structure (1), an N-differential structure (2), an adjustment module (3), a calibration control module (4), and a pulse generator (5), among which, The P differential structure (1) is used to input a first signal and output a first level; The N-differential structure (2) is used to input the second signal and output the second level; The adjustment module (3) is used to adjust the level of the intermediate level when the output is at the intermediate level, wherein the intermediate level is an intermediate state between the high level and the low level; The calibration control module (4) is used to generate PAM3 code when the output intermediate level is reached, and to calibrate the intermediate level based on the PAM3 code. The PAM3 code includes SW_P and SW_N codes. The pulse generator (5) is used to precharge and pre-discharge the internal nodes at the instant of the switching of the first and second output levels; By adjusting the level of the intermediate output level, nonlinear adjustment of the micro-ring electro-optic modulation can be achieved without changing the output swing.
2. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 1, characterized in that, The P differential structure (1) includes a first output branch, a first inverter INV1, a second inverter INV4, a third inverter INV3, a fourth inverter INV2, a first pulse drive PULSE1, a second pulse drive PULSE4, a third pulse drive PULSE3, and a fourth pulse drive PULSE2.
3. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 2, characterized in that, The N-differential structure (2) includes a second output branch, a fifth inverter INV5, a sixth inverter INV8, a seventh inverter INV7, an eighth inverter INV6, a fifth pulse drive PULSE5, a sixth pulse drive PULSE8, a seventh pulse drive PULSE7, and an eighth pulse drive PULSE6.
4. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 3, characterized in that, The first inverter INV1, the second inverter INV4, the first pulse drive PULSE1, and the second pulse drive PULSE4 are driven and controlled by the L input, while the fifth inverter INV5, the sixth inverter INV8, the fifth pulse drive PULSE5, and the sixth pulse drive PULSE8 are driven and controlled by the LB input.
5. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 4, characterized in that, The third inverter INV3, the fourth inverter INV2, the third pulse drive PULSE3, and the fourth pulse drive PULSE2 are driven and controlled by the HB input, while the seventh inverter INV7, the eighth inverter INV6, the seventh pulse drive PULSE7, and the eighth pulse drive PULSE6 are driven and controlled by the H input.
6. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 5, characterized in that, The first output branch includes a first PMOS transistor MP5, a first NMOS transistor MN6, a second PMOS transistor MP7, and a second NMOS transistor MN8. The first PMOS transistor MP5 and the first NMOS transistor MN6 are connected in series, and the second PMOS transistor MP7 and the second NMOS transistor MN8 are connected in series.
7. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 6, characterized in that, The second output branch includes a third PMOS transistor MP17, a third NMOS transistor MN18, a fourth PMOS transistor MP15, and a fourth NMOS transistor MN16. The third PMOS transistor MP17 and the third NMOS transistor MN18 are connected in series, and the fourth PMOS transistor MP15 and the fourth NMOS transistor MN16 are connected in series.
8. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 7, characterized in that, The adjustment module (3) includes a first PMOS drive adjustment unit, a second PMOS drive adjustment unit, a first NMOS drive adjustment unit, and a second NMOS drive adjustment unit.
9. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 8, characterized in that, The pulse generator (5) includes a down-thrust logic drive generator and an up-thrust logic drive generator. The down-thrust logic drive generator is used to pre-charge the PMOS transistor, and the up-thrust logic drive generator is used to pre-charge the NMOS transistor.
10. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 9, characterized in that, When the first PMOS transistor MP5, the second PMOS transistor MP7, the third NMOS transistor MN18, and the fourth NMOS transistor MN16 are turned on, and the first NMOS transistor MN6, the second NMOS transistor MN8, the third PMOS transistor MP17, and the fourth PMOS transistor MP15 are turned off, the output levels of the first output branch and the second output branch are high.
11. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 10, characterized in that, When the first NMOS transistor MN6, the second NMOS transistor MN8, the third PMOS transistor MP17, and the fourth PMOS transistor MP15 are turned on, and the first PMOS transistor MP5, the second PMOS transistor MP7, the third NMOS transistor MN18, and the fourth NMOS transistor MN16 are turned off, the output levels of the first output branch and the second output branch are low.
12. The high-swing PAM3 electro-optic modulator driving circuit as described in claim 11, characterized in that, When the second PMOS transistor MP7, the second NMOS transistor MN8, the third PMOS transistor MP17, and the third NMOS transistor MN18 are turned on, and the first PMOS transistor MP5, the first NMOS transistor MN6, the fourth PMOS transistor MP15, and the fourth NMOS transistor MN16 are turned off, the differential output level of the first output branch and the second output branch is the intermediate level.