Integrated circuit performing dynamic voltage and frequency scaling operation and method of operation thereof

Abstract

An integrated circuit performing dynamic voltage and frequency scaling operations and a method of operating the same are provided. In one aspect, an integrated circuit includes: a plurality of intellectual property (IP) blocks; a memory configured to store a dynamic voltage and frequency scaling (DVFS) table in which operating voltages and operating frequencies are classified into a plurality of groups based on power characteristics of the plurality of IP blocks, where the operating voltages and operating frequencies correspond to utilization rates; and a DVFS controller configured to calculate a workload of each of the plurality of IP blocks, and control an operation frequency provided to each of the plurality of IP blocks based on the calculated workload and the DVFS table. The DVFS controller is configured to change an operating frequency of the IP block based on a power characteristic of the IP block of the plurality of IP blocks before the utilization reaches a threshold utilization.

Description

[0001] Cross-reference to related applications

[0002] Related Application This application is based on and claims priority to Korean Patent Application No. 10-2024-0110586 filed on August 19, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to integrated circuits. Specifically, this disclosure relates to integrated circuits that perform dynamic voltage and frequency scaling operations and methods of operating thereof. Background Technology

[0004] With advancements in integrated circuit technology and increased integration, the importance of power management for integrated circuits or devices containing integrated circuits is growing. Specifically, power consumption can affect the temperature of integrated circuits, and performance degradation due to heat generation can be fatal.

[0005] Meanwhile, as the number of intellectual property (IP) blocks (e.g., chips) included in integrated circuits increases, so does the complexity of power management. Therefore, techniques that can efficiently manage the power of various IP blocks are desired. For power management, dynamic voltage and frequency scaling (DVFS) operations that control the operating voltage and frequency can be performed. Summary of the Invention

[0006] This disclosure provides an integrated circuit that performs DVFS operations more efficiently by taking into account the characteristics of IP blocks (or chips), and a method for operating the integrated circuit.

[0007] According to one aspect of the present invention, an integrated circuit is provided, comprising: a plurality of IP blocks; a memory configured to store a DVFS table, in which operating voltages and operating frequencies are categorized into multiple groups based on the power characteristics of the plurality of IP blocks, wherein the operating voltages and operating frequencies correspond to workloads; and a DVFS controller configured to calculate the workload of each of the plurality of IP blocks and to control the operating frequency supplied to each of the plurality of IP blocks based on the DVFS table and the calculated workload, wherein the DVFS controller is configured to change the operating frequency based on power characteristics before utilization reaches a threshold utilization, wherein utilization is the ratio of the IP block using a clock signal having an operating frequency.

[0008] According to another aspect of the present invention, a method for operating an integrated circuit is provided, comprising: calculating the workload of each of a plurality of IP blocks; providing an operating frequency to each of the plurality of IP blocks based on the calculated workload and a DVFS table, wherein the operating voltage and operating frequency are classified into a plurality of groups based on the power characteristics of the plurality of IP blocks in the DVFS table; and changing the operating frequency based on the power characteristics before the utilization reaches a threshold utilization, wherein the utilization is the ratio of the IP blocks using a clock signal having the operating frequency.

[0009] According to another aspect of the present invention, an integrated circuit is provided, comprising: a plurality of IP blocks; a memory configured to store a DVFS table, in which operating voltages and operating frequencies are categorized into multiple groups based on the power characteristics of the plurality of IP blocks, wherein the operating voltages and operating frequencies correspond to workloads; a DVFS controller configured to calculate the workload of each IP block among the IP blocks, and based on the calculated workload and the DVFS table, generate a voltage control signal and a frequency control signal for controlling the operating voltage and operating frequency supplied to each IP block among the IP blocks, respectively; a power management unit (PMU) configured to adjust the amplitude of a power supply voltage supplied to each IP block among the plurality of IP blocks in response to the voltage control signal; and a clock management unit (CMU) configured to adjust the frequency of a clock signal supplied to each IP block among the plurality of IP blocks in response to the frequency control signal; wherein the DVFS controller is configured to change the operating frequency based on power characteristics before the utilization reaches a threshold utilization, wherein the utilization is the ratio of the IP blocks using a clock signal having an operating frequency. Attached Figure Description

[0010] The embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This is a block diagram illustrating an example of an integrated circuit according to an embodiment;

[0012] Figure 2 This is a block diagram used to describe an example of dynamic voltage and frequency scaling (DVFS) operation according to an implementation method;

[0013] Figure 3 This is a diagram used to describe an example of a DVFS table according to an implementation method;

[0014] Figure 4 This is a diagram used to illustrate an example of DVFS operation according to an implementation method;

[0015] Figure 5 This is a diagram used to illustrate an example of DVFS operation according to an implementation method;

[0016] Figure 6 This is a diagram used to illustrate an example of DVFS operation according to an implementation method;

[0017] Figure 7 This is a block diagram used to describe an example of updating a DVFS table according to an implementation method;

[0018] Figure 8 This is a flowchart illustrating an example of a method for operating an integrated circuit according to an embodiment;

[0019] Figure 9 This is a flowchart illustrating an example of a method for operating an integrated circuit according to an embodiment;

[0020] Figure 10 This is a flowchart illustrating an example of a method for updating a DVFS table according to an implementation method;

[0021] Figure 11 This is a block diagram illustrating an example of a system according to an implementation method; and

[0022] Figure 12 This is a block diagram illustrating an example of a communication device including an application processor (AP) according to an embodiment. Detailed Implementation

[0023] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 This is a block diagram illustrating an integrated circuit 10 according to an embodiment.

[0025] refer to Figure 1Integrated circuit 10 may include device 100, clock management unit (CMU) 210, power management unit (PMU) 220, and memory 300. In some embodiments, at least some of device 100, CMU 210, PMU 220, and memory 300 may be included in a single semiconductor package. In some embodiments, device 100, CMU 210, PMU 220, and memory 300 may be included in a single chip, i.e., a system-on-a-chip (SoC), and integrated circuit 10 may be referred to as an application processor (AP). Integrated circuit 10 may include a system bus (not shown) to which a protocol with a predetermined standard bus specification is applied, and may include various intellectual property (IP) connected to the system bus. As a standard specification for the system bus, the Advanced Microcontroller Bus Architecture (AMBA) protocol from Advanced RISC Machines (ARM) Ltd. may be applied. The AMBA protocol can support bus types including Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4, and AXI Coherency Extensions (ACE). In addition, other protocols can be used, such as Sonics Inc.'s uNetwork, IBM's CoreConnect, and the OCP-IP open core protocol.

[0026] Integrated circuit 10 can be a fixed computing system such as a desktop personal computer (PC), a server, etc., and can correspond to a laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, digital multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console, mobile internet device (MID), wearable computer, Internet of Things (IoT) device, Internet of Everything (IoE) device, or e-book.

[0027] Device 100 may include multiple IP blocks 110 and a Dynamic Voltage and Frequency Scaling (DVFS) controller 120. Device 100 can control integrated circuit 10 and may be referred to as a processor, host processor, host device, etc. In some embodiments, device 100 may include multiple IP blocks 110 that execute a series of instructions and can execute a program composed of instructions. The program may include multiple subroutines, and subroutines may be referred to as subroutines, routines, procedures, functions, etc. In some embodiments, device 100 may be designed as an integrated circuit implemented as multiple transistors. Device 100 may include, for example, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), or an Image Signal Processor (ISP). Meanwhile, Figure 1 A device 100 is illustrated, but the type and number of devices 100 included in the integrated circuit 10 are not limited thereto. In some embodiments, the DVFS controller 120 may be located external to the device 100.

[0028] Each of the multiple IP blocks 110 can process instructions independently. Each IP block 110 can be a CPU core, GPU core, NPU core, or ISP core. Because the device 100 includes multiple cores, the integrated circuit 10 can be referred to as a multi-core processor. The IP blocks 110 can be referred to as sub-functional blocks.

[0029] Each of the multiple IP blocks 110 can process instructions based on a clock signal CLK and a power supply voltage VDD (or voltage-frequency level). The performance of each IP block 110 can depend on the clock signal CLK and the power supply voltage VDD. As the amplitude of the power supply voltage VDD supplied to the IP block 110 and the frequency of the clock signal CLK increase, the performance of the device 100 can be improved, and power consumption can increase.

[0030] However, in some embodiments, some of the IP blocks 110 can reduce power consumption even when the frequency of the clock signal CLK increases according to power characteristics (or chip characteristics) (e.g., dynamic power and / or static power). The integrated circuit 10 according to the embodiment can perform DVFS operation based on power characteristics. DVFS operation control based on the power characteristics of IP block 110 (or chip) will be described in detail below with reference to the accompanying drawings. For ease of description, the frequency of the clock signal CLK may be referred to as the operating frequency, and the amplitude of the supply voltage VDD may be referred to as the operating voltage.

[0031] The DVFS controller 120 can provide control signals CTRL_CLK and CTRL_VDD to the CMU 210 and / or PMU 220 to adjust the operating frequency and / or operating voltage of each of the various functional blocks (e.g., IP blocks 110) in the integrated circuit 10 according to the operating state of each of them. In some embodiments, the DVFS controller 120 can adjust the operating frequency and operating voltage supplied to each of the plurality of IP blocks 110. In some embodiments, the DVFS controller 120 can control the CMU 210 and / or PMU 220 to provide the operating voltage and operating frequency supplied to each of the plurality of IP blocks 110 based on the power characteristics (e.g., dynamic power and / or static power) of each of the plurality of IP blocks 110. For example, the DVFS controller 120 can output control signals CTRL_CLK and CTRL_VDD every predetermined sampling period to control the operating conditions of each of the plurality of IP blocks 110.

[0032] The CMU 210 can generate a clock signal CLK based on the clock control signal CTRL_CLK and adjust the frequency of the clock signal CLK. For example, the CMU 210 may include an oscillator that generates the clock signal CLK based on the clock control signal CTRL_CLK. The CMU 210 may be referred to as a clock generator or clock generation circuit. The operating frequency may refer to the fundamental frequency of the system clock provided by the CMU 210 to IP block 110.

[0033] PMU 220 can generate and adjust the power supply voltage VDD based on the power supply voltage control signal CTRL_VDD. In an embodiment, PMU 220 may include a switching regulator that generates the power supply voltage VDD based on the power supply voltage control signal CTRL_VDD, and may include a power management integrated circuit (PMIC).

[0034] The memory 300 can be accessed by the device 100, and the device 100 can store data in the memory 300 or read data stored in the memory 300. The memory 300 may include volatile memory devices, such as static random access memory (SRAM), dynamic random access memory (DRAM), etc., and may include non-volatile memory devices, such as flash memory, resistive random access memory (RRAM), etc.

[0035] In some implementations, when the DVFS controller 120 performs a DVFS operation, the memory 300 may store a DVFS table for reference. More specifically, the DVFS controller 120 may calculate the workload of the work performed by the integrated circuit 10 and / or multiple IP blocks 110, and may refer to the DVFS table stored in the memory 300 to perform DVFS operations in response to the calculated workload. The DVFS controller 120 may obtain from the DVFS table the operating voltage and / or operating frequency to be supplied to the IP blocks 110 in the corresponding workload.

[0036] In some embodiments, the DVFS table may include multiple groups categorized according to the power characteristics of IP block 110 (or chip). That is, the DVFS controller 120 can perform more efficient DVFS operations by referencing the DVFS table to which the power characteristics (e.g., dynamic or static power consumption) of IP block 110 are reflected. In some embodiments, the DVFS controller 120 may provide operating frequencies to IP block 110 based on the DVFS table, and some of the IP blocks 110 may reduce power consumption even as the operating frequency increases according to the power characteristics. In some embodiments, utilization may fluctuate as the workload of IP block 110 increases or decreases, and even when the changed utilization does not reach the threshold utilization for changing the operating frequency, a margin can be ensured in the timing for previously changed operating frequencies, thereby reducing power consumption. As described above, the integrated circuit 10 according to the embodiments can manage power more effectively by performing DVFS operations according to the corresponding power characteristics of each IP block 110, thereby reducing heat generation of the integrated circuit 10 and / or device 100 and improving its performance. Reference will be made below. Figures 2 to 6 Provide a detailed description of this point.

[0037] Integrated circuit 10 may also include, in addition to Figure 1 Components other than those shown. For example, integrated circuit 10 may also include other types of functional blocks, such as input / output (I / O) interface blocks, universal serial bus (USB) master blocks, USB slave blocks, etc.

[0038] Figure 2 This is a block diagram used to describe the DVFS operation according to an implementation method.

[0039] refer to Figure 2The DVFS controller 120 may include a DVFS governor module 121, a CMU driver 122, and a PMU driver 123. Hereinafter, "module" may refer to hardware capable of performing functions and operations according to a given name, or computer program code capable of performing specific functions and operations. However, this disclosure is not limited thereto, and may also refer to an electronic recording medium equipped with computer program code capable of performing specific functions and operations, such as a processor. That is, "module" may refer to a combination of functions and / or structures that execute the hardware and / or drive the hardware of this disclosure.

[0040] DVFS controller module 121 controls overall DVFS operation. DVFS controller module 121 can control CMU driver 122 and PMU driver 123 based on determined operating voltages and / or operating frequencies. In some embodiments, DVFS controller module 121 can refer to a DVFS table 350 stored in memory 300 and categorized according to the power characteristics of the IP block, and can control CMU driver 122 and PMU driver 123 to adjust the operating voltage and operating frequency (e.g., voltage-frequency level) supplied to the IP block based on the referenced DVFS table 350.

[0041] CMU driver 122 can output a clock control signal CTRL_CLK to CMU 210 under the control of DVFS controller module 121. CMU 210 can provide a clock signal CLK with an operating frequency determined according to the clock control signal CTRL_CLK to device 100 and / or multiple IP blocks 110. PMU driver 123 can output a power supply voltage control signal CTRL_VDD to PMU 220 under the control of DVFS controller module 121. PMU 220 can provide a power supply voltage VDD with an amplitude determined according to the power supply voltage control signal CTRL_VDD to device 100 and / or multiple IP blocks 110.

[0042] The memory 300 may include a DVFS table 350. The DVFS table 350 may include multiple operating voltages and operating frequencies (multiple voltage-frequency levels). The multiple operating voltages and operating frequencies included in the DVFS table 350 can be categorized into multiple groups based on the power characteristics of the IP block. In some embodiments, Figure 2 A single DVFS table 350 is shown, but multiple DVFS tables 350 may be included. For example, multiple DVFS tables 350 may be generated based on changes in the environment of the integrated circuit 10 (e.g., changes in the characteristics of IP blocks). In this regard, the DVFS controller module 121 can perform DVFS operations according to the implementation by selecting any one of the multiple DVFS tables 350 generated according to the environment.

[0043] Figure 3 This is a diagram used to describe the DVFS table according to the implementation method.

[0044] refer to Figure 3 The multiple groups included in DVFS table 350 may include the first group GROUP_1 and the second group GROUP_2. Figure 3 The image shows only some of the multiple operating frequencies.

[0045] In some implementations, the first group GROUP_1 and the second group GROUP_2 can be grouped according to power characteristics, and these power characteristics can include information about the dynamic power consumption and / or static power consumption of the IP blocks. That is, as shown, the first group GROUP_1 and the second group GROUP_2 can be classified according to the power consumed in response to the operating frequency. More specifically, the first group GROUP_1 may be a group exhibiting relatively high dynamic power consumption and relatively low static power consumption, while the second group GROUP_2 may be a group exhibiting relatively low dynamic power consumption and relatively high static power consumption. Some of the multiple IP blocks 110 can belong to the first group GROUP_1 based on power characteristics (e.g., having low static power consumption), and other IP blocks 110 can belong to the second group GROUP_2 based on power characteristics (e.g., having low dynamic power consumption).

[0046] The DVFS table 350 may include a larger number of groups. That is, the classification based on dynamic power consumption and / or static power consumption can be further refined. For example, the DVFS table 350 may consist of multiple groups (e.g., nine groups) including a first group GROUP_1 and a second group GROUP_2, and each IP block in the plurality of IP blocks 110 may belong to any of the multiple groups. In some implementations, the first group GROUP_1 may exhibit the characteristic of having the lowest static power consumption, and the second group GROUP_2 may exhibit the characteristic of having the lowest dynamic power consumption.

[0047] Figure 4 This is a diagram used to describe an example of DVFS operation according to an implementation method.

[0048] refer to Figure 4For example, the first group GROUP_1 included in DVFS table 350 can show power consumption based on operating frequency and utilization (or workload), as shown in the figure. Utilization can refer to the ratio of the total cycle count of the clock signal CLK to the cycle count of the clock signal CLK provided when the IP block is active. That is, utilization can refer to the ratio of the total cycle count of the clock signal CLK generated by CMU210 (with a clock signal having an operating frequency according to DVFS table 350) to the cycle count actually used by the IP block. As the workload of the IP block increases, the actual cycle count used by the IP block in the total cycle count of the clock signal CLK may increase, and therefore the utilization may increase.

[0049] As described above, the first group GROUP_1 can exhibit characteristics of relatively large dynamic power consumption and relatively small static power consumption, or it can be a group representing the lowest static power consumption. (On the other hand, the second group GROUP_2 can exhibit characteristics of relatively small dynamic power consumption and relatively large static power consumption). The integrated circuit 10 according to the embodiment can perform efficient DVFS operation by first changing the operating frequency based on the power characteristics of the IP blocks before the utilization rate increases or decreases according to the increase or decrease of the workload and reaches a threshold utilization rate.

[0050] In some implementations, power consumption can be reduced in groups exhibiting low static power consumption characteristics (e.g., the first group GROUP_1) by ensuring more idle periods. In other words, the first group GROUP_1 consumes relatively low power during idle periods, and therefore the overall power consumption can be reduced by increasing the operating frequency earlier and ensuring more idle periods. More specifically, IP blocks with lower static power consumption can generate more operating frequency change periods that can reduce the overall power consumption through an early increase in operating frequency. Therefore, when the utilization of any IP block included in the first group GROUP_1 increases (e.g., when the workload increases), power consumption can be reduced by preemptively increasing the operating frequency currently provided to any IP block before the utilization increases to a threshold utilization for increasing the operating frequency. In some implementations, power consumption can be further reduced by performing power gating operations during protected idle periods.

[0051] In one implementation, the first IP block included in the first group GROUP_1 may receive a sixteenth operating frequency (or a sixteenth voltage-frequency level) L15, and its utilization may be 60% depending on the workload. As the workload of the first IP block increases, the utilization may increase, and the first threshold utilization cu_1 at the sixteenth operating frequency level L15 for providing a higher operating frequency as the workload increases may be, for example, 90%. In this regard, the DVFS controller 120 can reduce power consumption by providing a higher operating frequency preemptively (e.g., at a faster time) without waiting until the utilization of the first IP block increases to the first threshold utilization cu_1. For example, the DVFS controller 120 may provide the fifteenth operating frequency L14 to the first IP block before its utilization increases to the first threshold utilization cu_1. As mentioned above, operating at a lower utilization by providing a higher operating frequency may be more advantageous in terms of power consumption (as mentioned above, this is due to the low static power consumption of the IP block). In another implementation, the second IP block included in the first group GROUP_1 may receive the fifteenth operating frequency L14, and its utilization may be 50% depending on the workload. As the workload of the second IP block increases, the utilization can increase, and the second threshold utilization cu_2 used to provide a higher operating frequency can be, for example, 80%. In this regard, the DVFS controller 120 can reduce power consumption by providing a higher operating frequency (e.g., a fourteenth operating frequency L13) before the utilization of the second IP block increases to the second threshold utilization cu_2.

[0052] In some implementations, the DVFS controller 120 may maintain the current operating frequency without increasing it, even if the operating frequency increases at a faster pace (e.g., before the IP block utilization increases to the corresponding threshold utilization). In one implementation, the third IP block included in the first group GROUP_1 may receive a seventeenth operating frequency L16, and its utilization may be 70% depending on the workload. The third threshold utilization cu_3 used to provide a higher operating frequency due to the increased utilization of the third IP block may be, for example, 90%. In this respect, increasing the operating frequency before the utilization of the third IP block increases to the third threshold utilization cu_3 may increase power consumption, and therefore the DVFS controller 120 may maintain the current operating frequency (seventeenth operating frequency L16) without increasing it.

[0053] In other words, the DVFS controller 120 can determine whether to increase the operating frequency based on the power characteristics reflected in its DVFS table 350. The DVFS controller 120 can predict the power consumption when increasing the operating frequency by referring to the DVFS table 350, and can compare the predicted power consumption with the current power consumption to determine whether to increase the operating frequency. Therefore, when the predicted power consumption based on the increase in operating frequency is less than or equal to the power consumption at the current operating frequency, i.e., when the power consumption decreases, the DVFS controller 120 can increase the operating frequency. The DVFS controller 120 can preemptively increase the operating frequency of the IP block to a new operating frequency, wherein the new operating frequency is within a frequency range in which the predicted power consumption based on the new operating frequency is less than or equal to the power consumption based on the current operating frequency and utilization of the IP block.

[0054] In some implementations, the DVFS controller 120 can provide the highest possible operating frequency within a range where the predicted power consumption decreases as the operating frequency increases. For example, the current utilization at the sixteenth operating frequency L15 of the IP blocks included in the first group GROUP_1 could be 60%, and the DVFS controller 120 could provide an operating frequency higher than the fifteenth operating frequency L14 (e.g., the thirteenth operating frequency L12 or the fourteenth operating frequency L13) to reduce power consumption as utilization increases. By directly increasing the operating frequency to a higher frequency rather than increasing it in stages, power consumption can be reduced while performance can be further improved, and fast responsiveness can be ensured by reducing the overhead of frequency-dependent changes. This DVFS operation may be more advantageous under increasing workloads.

[0055] Conversely, in some implementations, even when utilization decreases due to a decrease in the workload of the IP block, the DVFS controller 120 may maintain the current operating frequency without directly reducing it. As described above, providing a higher operating frequency for low utilization operation may be more advantageous in terms of power consumption, and therefore the DVFS controller 120 may maintain the current operating frequency. That is, the DVFS controller 120 can predict the power consumption when reducing the operating frequency by referring to the DVFS table 350, and can compare the predicted power consumption with the current power consumption to determine whether to reduce the operating frequency. The DVFS controller 120 may maintain the current operating frequency until the predicted power consumption due to the reduction in operating frequency is less than the current power consumption at the current operating frequency. In response to the predicted power consumption associated with a lower operating frequency being less than the current power consumption, the DVFS controller 120 may reduce the operating frequency of the corresponding IP block.

[0056] On the other hand, in some implementations, power consumption can be reduced in groups exhibiting low dynamic power consumption characteristics (e.g., the second group GROUP_2) by ensuring more active periods. In other words, the second group GROUP_2 consumes relatively low power during its operating period, so the total power consumption can be reduced by increasing the operating frequency as late as possible and ensuring more operating periods. Therefore, when the utilization of any IP block included in the second group (GROUP_2) increases (e.g., when the workload increases), power consumption can be reduced by increasing the operating frequency currently provided to the IP block as late as possible.

[0057] Figure 5 This is a diagram used to describe an example of DVFS operation according to an implementation method.

[0058] refer to Figure 5 The DVFS controller 120 can provide the IP block with a higher operating frequency among a plurality of operating frequencies having the same power consumption. For example, the power consumption of the operating frequency provided to the IP block under any workload (e.g., when processing the same workload) can appear as shown. Even when processing the same workload, the first operating frequencies L0 to the fourth operating frequencies L3 can have the same power consumption (this phenomenon may be more pronounced in groups with low quiescent power consumption (e.g., the first group GROUP_1)). When the operating frequency increases with utilization at the fifth operating frequency L4, the DVFS controller 120 can directly increase the operating frequency to the first operating frequency L0 instead of increasing the operating frequency to the fourth operating frequency L3.

[0059] In other words, the DVFS controller 120 can provide the IP block with the higher (or highest) operating frequency among multiple operating frequencies consuming the same power. This allows the integrated circuit 10 and / or device 100 to benefit in terms of performance by integrating and simplifying operating frequency changes without the need for unnecessary staged changes. The integrated circuit 10 and / or device 100 can reduce the overhead incurred when changing operating frequencies and also alleviate the timing conditions required for frequency changes (switching), ensuring timing margins. Furthermore, faster responsiveness can be ensured when workloads increase rapidly.

[0060] In addition, the integrated circuit 10 and / or the device 100 can ensure more idle time by providing a higher operating frequency, and can further reduce power consumption by performing power gating operations during idle time, and thus reduce heat generation.

[0061] Figure 6 This is a diagram used to describe the DVFS operation according to an implementation method.

[0062] Figure 6An example of the change in operating frequency is shown as a comparative example of the change in operating frequency based on the increase or decrease in workload and the change in operating frequency according to an embodiment. The DVFS controller 120 according to the embodiment can reduce or minimize unnecessary frequency change operations and further reduce power consumption by directly increasing the operating frequency to a first operating frequency L0 based on the increase in workload (utilization).

[0063] More specifically, the comparative example changes the operating frequency when utilization reaches a threshold utilization, thus performing a total of six frequency change (switching) operations. In contrast, the implementation of this disclosure can quickly provide a high operating frequency even when utilization has not increased to the threshold utilization for each operating frequency level without performing unnecessary frequency change operations, and can further reduce power consumption by ensuring idle periods (e.g., increasing the percentage of idle periods). Furthermore, even when utilization decreases with decreasing workload, the comparative example performs frequency change operations that reduce the operating frequency when utilization reaches a threshold utilization. In contrast, the implementation of this disclosure can maintain a high operating frequency even when utilization decreases without performing unnecessary frequency change operations, and similarly, can reduce power consumption by ensuring idle periods.

[0064] Figure 7 This is a block diagram used to describe the updating of DVFS table 350 according to the implementation method.

[0065] refer to Figure 7 The DVFS controller 120 may include a DVFS controller module 121 and a monitoring module 125. (The details regarding...) Figure 1 and Figure 2 Those redundant components Figure 7 Description of the components.

[0066] The monitoring module 125 can collect the overall operating status (mainly the status of multiple IP blocks 110) within the integrated circuit 10, generate update information, and provide the update information to the DVFS controller module 121. In some embodiments, the monitoring module 125 can generate aging information by checking the usage time of the multiple IP blocks 110, and the monitoring module 125 can measure the degree of degradation of each IP block among the multiple IP blocks 110. For example, the monitoring module 125 can generate update information based on the amount of threshold voltage change, timing change, operating temperature, power consumption according to operating voltage and operating frequency, aging information, etc., of each IP block among the multiple IP blocks 110. The power characteristics of IP blocks 110 (or chips) may change due to degradation, etc., and the monitoring module 125 can generate update information by detecting the performance or characteristics of each IP block among the multiple IP blocks 110 that change in real time. That is, for example, the update information may include the changed static power consumption and dynamic power consumption of IP blocks 110. DVFS controller module 121 can modify DVFS table 350 stored in memory 300 based on update information.

[0067] In other words, the DVFS controller 120 can update the status of multiple IP blocks 110 through the monitoring module 125, and when the characteristics of IP blocks 110 (e.g., dynamic power consumption, static power consumption, and / or total power consumption) change due to device degradation, it can more accurately perform DVFS operations by reflecting changes and modifying the DVFS table 350.

[0068] Figure 8 This is a flowchart illustrating a method for operating integrated circuit 10 according to an embodiment.

[0069] refer to Figure 8 The method of operating integrated circuit 10 may include operations S100, S200 and S300. In operation S100, DVFS controller 120 may calculate the workload of the work performed by multiple IP blocks 110 in order to provide appropriate dynamic voltage and dynamic frequency to IP blocks 110.

[0070] In operation S200, the DVFS controller 120 can provide an operating frequency to the IP block 110 based on the DVFS table 350 stored in the memory 300 and the calculated workload. The DVFS controller 120 can obtain the operating voltage and / or operating frequency to be provided to the IP block 110 from the DVFS table 350 according to the calculated workload. The DVFS table 350 may include multiple groups categorized according to the power characteristics of the IP block (or chip). For example, multiple groups can be grouped according to the magnitude of dynamic power consumption and / or static power consumption. That is, the DVFS controller 120 can perform more efficient DVFS operations by referring to the DVFS table 350, which includes multiple groups categorized based on the dynamic power consumption and / or static power consumption characteristics of the IP block.

[0071] In operation S300, the DVFS controller 120 can change the operating frequency provided to the IP block based on the power characteristics reflected in its DVFS table 350. Utilization can fluctuate as the IP block's workload increases or decreases, and even when the changed utilization does not reach the threshold utilization for changing the operating frequency, the DVFS controller 120 can ensure a timing margin for frequency changes and reduce power consumption by pre-changing the operating frequency based on the IP block's power characteristics.

[0072] According to the implementation, the integrated circuit 10 can operate more efficiently by performing DVFS operation according to the corresponding power characteristics of each IP block, and the performance of the integrated circuit 10 and / or the device 100 can be improved.

[0073] Figure 9 This is a flowchart illustrating a method for operating an integrated circuit according to an embodiment.

[0074] refer to Figure 9 In operation S310, the utilization rate can increase according to the increase in the workload of the IP block. In operation S320, the DVFS controller 120 can determine whether the utilization rate is less than the threshold utilization rate. When the utilization rate of the IP block is greater than or equal to the threshold utilization rate (No in operation S320), because it is necessary to change the operating frequency according to the increase in workload, in operation S330, the DVFS controller 120 can change the operating frequency by referring to the DVFS table 350.

[0075] In some implementations, even when the utilization rate is less than a threshold utilization rate (Yes in operation S320), the DVFS controller 120 may preemptively increase the operating frequency provided to the IP block at a faster time before the utilization rate increases to the threshold utilization rate, thereby increasing the operating frequency. In some implementations, in operation S340, the DVFS controller 120 may determine whether to reduce power consumption based on the increase in operating frequency, based on the power characteristics reflected in its DVFS table 350. When power consumption may not decrease even if the operating frequency increases at a faster time (e.g., when the predicted power consumption due to the increase in operating frequency is greater than the current power consumption) (No in operation S340), the DVFS controller 120 may maintain the current operating frequency in operation S350 without increasing the operating frequency. On the other hand, when power consumption can be reduced by increasing the operating frequency at a faster time (e.g., when the predicted power consumption due to the increase in operating frequency is less than the current power consumption) (Yes in operation S340), the DVFS controller 120 may reduce power consumption by providing a higher operating frequency in operation S360. In some implementations, the DVFS controller 120 may provide the highest operating frequency within a range of predicted power consumption reductions based on the increase in operating frequency. Additionally, in some implementations, the DVFS controller 120 may provide the IP block with the higher (or highest) of a plurality of operating frequencies consuming the same power.

[0076] Figure 10 This is a flowchart illustrating a method for updating DVFS table 350 according to an implementation.

[0077] refer to Figure 8 The DVFS controller 120 can execute operations S400, S500, and S600 to update the DVFS table 350. In operation S400, the monitoring module 125 can detect changes in the power characteristics of the IP block 110. The power characteristics of the IP block 110 (or chip) can change due to degradation, etc., and the monitoring module 125 can detect these changes based on factors such as the amount of threshold voltage change, the amount of timing change, operating temperature, power consumption based on operating voltage and frequency, and aging information. In operation S500, the monitoring module 125 can generate updated information indicating changes in the power characteristics of the IP block 110. In operation S600, the DVFS controller module 121 can modify the DVFS table 350 based on the updated information received from the monitoring module 125.

[0078] In other words, the DVFS controller 120 can update the state of each IP block in multiple IP blocks 110 to reflect the state in the DVFS table 350, and can perform more precise DVFS operations.

[0079] Figure 11This is a block diagram illustrating a system 1000 according to an embodiment.

[0080] refer to Figure 11 System 1000 can be implemented as a mobile phone, smartphone, tablet computer, PDA, EDA, digital still camera, digital video camera, PMP, PND, handheld game console or handheld device such as an e-reader.

[0081] System 1000 may include SoC 1100 and memory device 1200. SoC 1100 may include CPU 1110, GPU 1120, NPU 1130, ISP 1140, memory interface (MIF) 1150, CMU 1160, and PMU 1170. CPU 1110, GPU 1120, NPU 1130, and ISP 1140 may be referred to as master IP devices, and MIF 1150 may be referred to as slave IP devices. At least one of CPU 1110, GPU 1120, NPU 1130, or ISP 1140 may be referenced above. Figures 1 to 10 The described device 100 or multiple IP blocks 110 are implementation examples. Therefore, at least one of the CPU 1110, GPU 1120, NPU 1130, or ISP 1140 may include a DVFS controller that performs DVFS operations according to the implementation. The DVFS controller included in at least one of the CPU 1110, GPU 1120, NPU 1130, or ISP 1140 can control CMU 1160 or PMU 1170, and the CPU 1110, GPU 1120, NPU 1130, and ISP 1140 can process instructions by receiving a clock signal CLK from CMU 1160 and a power supply voltage from PMU 1170. A DVFS controller included in at least one of CPU 1110, GPU 1120, NPU 1130 or ISP 1140 can manage power more effectively by performing DVFS operations on the corresponding unit or processor according to the corresponding power characteristics (by providing the operating frequency according to the power characteristics), and can improve the performance of the device or IP block.

[0082] CPU 1110 can process or execute instructions and / or data stored in memory device 1200 in response to a clock signal generated by CMU 1160 (i.e., according to the operating frequency controlled by the DVFS controller).

[0083] GPU 1120 can obtain image data stored in memory device 1200 in response to a clock signal generated by CMU 1160 (i.e., according to the operating frequency controlled by DVFS controller). GPU 1120 can generate data for an image to be output on a display device based on the image data provided from MIF 1150, or it can encode the image data.

[0084] NPU 1130 can refer to any device that executes machine learning models. NPU 1130 can be a hardware block designed to execute machine learning models. Machine learning models can be based on artificial neural networks, decision trees, support vector machines, regression analysis, Bayesian networks, genetic algorithms, etc. As a non-limiting example, artificial neural networks can include convolutional neural networks (CNNs), region with convolutional neural networks (R-CNNs), region proposal networks (RPNs), recurrent neural networks (RNNs), stacked deep neural networks (S-DNNs), state-space dynamic neural networks (S-SDNNs), deconvolutional networks, deep belief networks (DBNs), restricted Boltzmann machines (RBMs), fully convolutional networks, long short-term memory (LSTM) networks, and classification networks.

[0085] The ISP 1140 can perform signal processing operations on raw data received from an image sensor located outside the SoC 1100 and generate digital data with improved image quality.

[0086] The MIF 1150 can provide an interface for a memory device 1200 located outside the SoC 1100. The memory device 1200 can be DRAM, phase-change random access memory (PRAM), resistive random access memory (ReRAM), or flash memory.

[0087] The CMU 1160 generates and supplies clock signals to components of the SoC 1100. The CMU 1160 may include clock generation devices such as phase-locked loops (PLLs), delay-locked loops (DLLs), crystals, etc. The PMU 1170 converts external power to internal power and supplies that internal power to components of the SoC 1100.

[0088] Figure 12 This is a block diagram illustrating a communication device 3000 including an AP 3010 according to an embodiment.

[0089] refer to Figure 12The communication device 3000 may include an AP 3010, a memory device 3020, a display 3030, an input device 3040, and a radio transceiver 3050. The AP 3010 may be as described above. Figures 1 to 10 An example of an implementation of the described integrated circuit 10.

[0090] Radio transceiver 3050 can transmit and receive radio signals via antenna 3060. For example, radio transceiver 3050 can convert radio signals received via antenna 3060 into signals that can be processed by AP 3010.

[0091] Therefore, AP 3010 can process the radio signals output from radio transceiver 3050 and send the processed radio signals to display 3030. Furthermore, radio transceiver 3250 can convert the signals output from AP 3010 into radio signals and output the radio signals to external devices via antenna 3060.

[0092] Input device 3040 is a device capable of inputting control signals for controlling the operation of AP 3010 or data to be processed by AP 3010, and can be implemented as a pointing device such as a touchpad and computer mouse, keypad or keyboard.

[0093] In some implementations, AP 3010 may include a DVFS controller 120 according to an embodiment. (Refer to the above...) Figures 1 to 10 The DVFS controller 120 can control the operating frequency to be supplied to each IP block based on the DVFS table 350, which reflects the power characteristics of each IP block. The DVFS controller 120 can effectively manage power by changing the operating frequency in a faster time according to the power characteristics of each IP block and supplying the operating frequency to each IP block, and can improve the performance of AP 3010.

[0094] Although not in Figure 12 As shown, but may further include a CMU that provides clock signals to various components disposed in the communication device 3000 and a PMU that provides power supply voltage. The CMU may output a clock signal having a frequency regulated by the control of the DVFS controller 120, and the PMU may output a power supply voltage having an amplitude regulated by the control of the DVFS controller 120.

[0095] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims. Certain features described in this disclosure in the context of individual implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of individual implementations may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. An integrated circuit, comprising: Multiple intellectual property (IP) blocks; The memory is configured to store a dynamic voltage and frequency scaling (DVFS) table, the DVFS table including operating voltages and operating frequencies categorized into multiple groups based on the power characteristics of the plurality of IP blocks, wherein the operating voltages and operating frequencies correspond to the workload; and A DVFS controller is configured to calculate the workload of each of the plurality of IP blocks and, based on the DVFS table and the calculated workload, control the frequency of operation provided to each of the plurality of IP blocks. The DVFS controller is configured to change the operating frequency of the IP block based on the power characteristics of the IP block before the utilization of the IP block in the plurality of IP blocks reaches a threshold utilization, wherein the utilization is the ratio of the IP block using a clock signal having the operating frequency.

2. The integrated circuit of claim 1, wherein the power characteristics include information indicating at least one of dynamic power consumption or static power consumption.

3. The integrated circuit according to claim 2, wherein, The plurality of groups includes a first group and a second group, and The static power consumption of the corresponding IP block in the first group is less than the static power consumption of the corresponding IP block in the second group.

4. The integrated circuit according to claim 3, wherein the dynamic power consumption of the corresponding IP block in the second group is less than the dynamic power consumption of the corresponding IP block in the first group.

5. The integrated circuit of claim 3, wherein the DVFS controller is configured to increase the operating frequency of the IP blocks before the utilization of the IP blocks in the first group increases to the threshold utilization.

6. The integrated circuit of claim 5, wherein the DVFS controller is configured to increase the operating frequency of the IP block to a new operating frequency, wherein the new operating frequency is within a frequency range in which the predicted power consumption based on the new operating frequency is less than or equal to the power consumption based on the current operating frequency of the IP block and the utilization rate.

7. The integrated circuit of claim 3, wherein the DVFS controller is configured to maintain the current operating frequency of the IP block in response to a decrease in the utilization of the IP block in the first group until the predicted power consumption based on the decrease in the operating frequency is less than the power consumption based on the current operating frequency and the utilization.

8. The integrated circuit according to claim 1, wherein, At least one of the plurality of groups includes a first operating frequency and a second operating frequency, wherein the first operating frequency and the second operating frequency have the same power consumption, and the first operating frequency is greater than the second operating frequency. The DVFS controller is configured to increase the operating frequency to the first operating frequency in response to an increase in utilization at the current operating frequency, wherein the current operating frequency is lower than both the first operating frequency and the second operating frequency.

9. The integrated circuit of claim 8, wherein the DVFS controller is configured to maintain the operating frequency at the first operating frequency regardless of a decrease in utilization, until the predicted power consumption based on the decrease in operating frequency is less than the power consumption based on the first operating frequency and the utilization.

10. The integrated circuit of claim 5, wherein the DVFS controller is configured to perform power gating relative to idle periods ensured by the increase of the operating frequency.

11. The integrated circuit according to claim 1, wherein, The DVFS controller further includes a monitor configured to detect changes in the power characteristics of the plurality of IP blocks to generate update information, and the DVFS controller is configured to modify the DVFS table stored in the memory based on the update information.

12. A method of operating an integrated circuit, the method comprising: Calculate the workload of each IP block in a plurality of intellectual property IP blocks; The DVFS table, which is dynamically scaled based on the calculated workload and voltage and frequency, provides the operating frequency for each of the plurality of IP blocks, and the DVFS table has operating voltage and operating frequency that are categorized into multiple groups based on the power characteristics of the plurality of IP blocks. and Before the utilization rate of an IP block among the plurality of IP blocks reaches a threshold utilization rate, the operating frequency of the IP block is changed based on the power characteristics of the IP block, wherein the utilization rate is the ratio of the IP block using a clock signal having the operating frequency.

13. The method according to claim 12, wherein, The multiple groups in the DVFS table include a first group and a second group, and the static power consumption of the corresponding IP block in the first group is less than the static power consumption of the corresponding IP block in the second group.

14. The method according to claim 13, wherein, Changing the operating frequency includes: Before the utilization rate of the IP block in the first group increases to the threshold utilization rate, the operating frequency of the IP block is increased.

15. The method according to claim 14, wherein, Increasing the operating frequency includes: The operating frequency is increased to a new operating frequency within a frequency range, in which the predicted power consumption based on the new operating frequency is less than or equal to the power consumption based on the current operating frequency and the utilization rate.

16. The method according to claim 12, wherein, At least one of the plurality of groups includes a first operating frequency and a second operating frequency, wherein the first operating frequency and the second operating frequency have the same power consumption, and the first operating frequency is greater than the second operating frequency. Changing the operating frequency includes: In response to an increase in utilization at the current operating frequency, the operating frequency is increased to the first operating frequency, wherein the current operating frequency is lower than both the first operating frequency and the second operating frequency.

17. The method of claim 12, further comprising: Update information is generated by detecting changes in the power characteristics of the plurality of IP blocks; and Modify the DVFS table based on the updated information.

18. An integrated circuit, comprising: Multiple intellectual property (IP) blocks; The memory is configured to store a dynamic voltage and frequency scaling (DVFS) table, the DVFS table having operating voltages and operating frequencies categorized into multiple groups based on the power characteristics of the plurality of IP blocks, wherein the operating voltages and operating frequencies correspond to the workload; A DVFS controller is configured to compute the workload of each of the plurality of IP blocks; as well as Based on the calculated workload and the DVFS table, voltage control signals and frequency control signals are generated, which are used to control the operating voltage and operating frequency provided to each of the plurality of IP blocks, respectively. A power management unit (PMU) configured to adjust the magnitude of the power supply voltage supplied to each of the plurality of IP blocks in response to the voltage control signal; and A clock management unit (CMU) is configured to adjust the frequency of the clock signal provided to each of the plurality of IP blocks in response to the frequency control signal. The DVFS controller is configured to change the operating frequency of the IP block based on the power characteristics of the IP block before the utilization of the IP block in the plurality of IP blocks reaches a threshold utilization, wherein the utilization is the ratio of the IP block using a clock signal having the operating frequency.

19. The integrated circuit of claim 18, wherein the DVFS controller is configured to generate the voltage control signal and the frequency control signal to increase the operating frequency of the IP block to a new operating frequency before the utilization of the IP block increases to the threshold utilization, wherein the new operating frequency is within a frequency range in which the predicted power consumption based on the new operating frequency is less than or equal to the power consumption based on the current operating frequency and the utilization of the IP block.

20. The integrated circuit of claim 18, wherein the DVFS controller is configured to generate the voltage control signal and the frequency control signal in response to a decrease in the utilization of the IP block to maintain the current operating frequency of the IP block until the predicted power consumption based on the decrease in the operating frequency is less than the power consumption based on the current operating frequency and the utilization of the IP block.

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