Loading storage unit, data acquisition method, chip and computer equipment

Abstract

The embodiment of the invention discloses a loading storage unit, a data acquisition method, a chip and computer equipment, and belongs to the technical field of chips. The loading storage unit comprises a storage address pipeline, a storage data pipeline, a loading data pipeline and a storage queue; the storage address assembly line is used for storing a storage address indicated by a storage instruction to a storage queue under the condition that the storage instruction is received; the storage data assembly line is used for storing the storage data indicated by the storage instruction to the storage queue under the condition that the storage instruction is received; and the loading data assembly line is used for obtaining the storage data corresponding to the loading address from the storage data assembly line under the condition that the storage address matched with the loading address indicated by the loading instruction exists in the storage queue and the storage data corresponding to the storage address is not completely stored. According to the scheme, the execution times of the loading instruction can be effectively reduced, and the instruction execution efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a loading storage unit, a data acquisition method, a chip, and a computer device. Background Technology

[0002] In a processor, the Load Store Unit (LSU) is responsible for handling the loading and storing of data.

[0003] In related technologies, the LSU divides the storage pipeline for executing store instructions into a store address pipeline (STA) and a store data pipeline (STD), and uses a store queue to temporarily store the execution results of store instructions. However, due to the different execution speeds of the store address pipeline and the store data pipeline, the store address and store data indicated by the same store instruction often cannot be stored in the store queue simultaneously. Therefore, when executing a load instruction and querying the store queue for the data required by the load instruction, if a matching store address is found and the corresponding store data has already been stored in the store queue, the query is successful. If a matching store address is found but the corresponding store data has not been stored in the store queue (i.e., the store address has been stored in the store queue by the store address pipeline, but the store data is still in the store data pipeline), the query fails, and the load instruction needs to wait for a period of time before being re-executed.

[0004] Obviously, in the relevant technologies, if a matching storage address is found but the corresponding storage data is not stored in the storage queue, the loading instruction still needs to be re-executed, resulting in a large number of loading instruction executions and low instruction execution efficiency. Summary of the Invention

[0005] This application provides a loading storage unit, a data acquisition method, a chip, and a computer device, the technical solutions of which are as follows.

[0006] On one hand, embodiments of this application provide a loading storage unit, which includes a storage address pipeline, a storage data pipeline, a loading data pipeline, and a storage queue;

[0007] The storage address pipeline is used to store the storage address indicated by the storage instruction into the storage queue upon receiving a storage instruction;

[0008] The storage data pipeline is used to store the storage data indicated by the storage instruction into the storage queue upon receiving the storage instruction; wherein the storage data indicated by the same storage instruction and the storage address are stored in the same storage queue entry in the storage queue;

[0009] The loading data pipeline is used to retrieve the storage data corresponding to the loading address from the storage data pipeline when there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, and the storage data corresponding to the storage address has not been fully stored.

[0010] On the other hand, embodiments of this application provide a data acquisition method, which is used to load a storage unit, the loading storage unit including a storage address pipeline, a storage data pipeline, a loading data pipeline, and a storage queue;

[0011] The method includes:

[0012] Upon receiving a storage instruction, the storage address indicated by the storage instruction is stored in the storage queue through the storage address pipeline;

[0013] Upon receiving the storage instruction, the storage data indicated by the storage instruction is stored in the storage queue through the storage data pipeline; wherein the storage data indicated by the same storage instruction and the storage address are stored in the same storage queue entry in the storage queue;

[0014] If a storage address matching the load address indicated by the load instruction exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, the storage data corresponding to the load address is obtained from the storage data pipeline through the load data pipeline.

[0015] On the other hand, embodiments of this application provide a chip that includes at least one load memory unit as described above.

[0016] On the other hand, embodiments of this application provide a board card that is provided with the chip described above.

[0017] On the other hand, embodiments of this application provide a computer device, which is provided with the boards as described above.

[0018] The beneficial effects of the technical solutions provided in this application include at least the following:

[0019] In the load memory unit, by connecting the load data pipeline to the memory queue, even if there is a memory address in the memory queue that matches the load address indicated by the load instruction, and the memory data corresponding to the memory address has not been fully stored, the load data pipeline can retrieve the memory data corresponding to the load address from the memory data pipeline. This eliminates the need to wait for the memory data to be stored in the memory queue before re-executing the load instruction to obtain the required data, reducing the number of instruction executions for the load instruction and improving instruction execution efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram illustrating the execution of loading instructions via a loading data pipeline in related technologies is shown.

[0022] Figure 2 This illustration shows a schematic diagram of instruction code provided in an exemplary embodiment of this application;

[0023] Figure 3 A schematic diagram of a loading storage unit provided in an exemplary embodiment of this application is shown;

[0024] Figure 4 This illustration shows a waveform diagram of code for querying data based on index values, provided in an exemplary embodiment of this application.

[0025] Figure 5 A schematic diagram of a storage queue provided in an exemplary embodiment of this application is shown;

[0026] Figure 6 This illustration shows a schematic diagram of a storage queue when retrieving stored data from a storage queue, provided in an exemplary embodiment of this application.

[0027] Figure 7 A schematic diagram of a loading storage unit provided in another exemplary embodiment of this application is shown;

[0028] Figure 8 This illustration shows a schematic diagram of the comparison data length provided in an exemplary embodiment of this application;

[0029] Figure 9 A schematic diagram illustrating the comparison of data lengths provided in another exemplary embodiment of this application is shown;

[0030] Figure 10 A schematic diagram of a loading storage unit provided in another exemplary embodiment of this application is shown;

[0031] Figure 11 A flowchart illustrating a data processing method provided in an exemplary embodiment of this application is shown;

[0032] Figure 12 A flowchart illustrating a data processing method provided in an exemplary embodiment of this application is shown;

[0033] Figure 13 A schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0036] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0037] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0038] First, a brief introduction to the terms used in the embodiments of this application:

[0039] The Load Store Unit (LSU) is a crucial component of the processor, primarily responsible for handling data loading and storing operations. The LSU includes multiple buffers, such as the Store Queue (SQ) and the Store Buffer (SB). The SQ buffers the results of Store instructions (instructions that store data from registers to external memory (the computer system's main memory; the CPU's cache is collectively referred to as external memory) that have not yet been committed. The SB buffers the results of instructions that have been committed but not yet written to the Dcache (data cache). Load instructions (instructions that load data from external memory into the processor's registers) check the SQ and SB for the required data (if the address matches). If found, the data retrieved from the SQ is taken first, while the data retrieved from the Dcache is discarded.

[0040] The Store Address Pipeline (STA) executes the address storage operation in Store instructions, storing the memory address contained in the Store instruction into the memory queue. The Store Address Pipeline contains multiple address storage stages, and each address storage stage contains at least one hardware unit responsible for performing the address storage task for that stage. Optionally, the Store Address Pipeline may include an address generation unit (for calculating the memory address corresponding to the store instruction), an execution unit (for performing arithmetic or logical operations to calculate the memory address), address registers, a data bus, buffers, latches, etc.

[0041] Store Data Pipeline (STD): This pipeline executes the data storage operations specified in Store instructions, storing the data contained in the Store instructions into a storage queue. The STD comprises multiple data storage stages, each containing at least one hardware unit responsible for performing the data storage tasks at that stage. Optionally, the STD may include data registers, a data bus, a data transfer unit, a control logic unit, a data comparison unit, etc.

[0042] Load Pipeline: Used to perform load operations, retrieving the load data required by the Load instruction from the memory queue. The load pipeline contains multiple data loading stages, and each stage includes at least one hardware unit responsible for executing the data loading task for that stage. Optionally, the load pipeline may include an instruction decoding unit, an address generation unit, an address register, an address bus, a data register, a data transfer unit, a data comparison unit, etc.

[0043] Store Queue (SQ): An important component of the load memory unit, it is a hardware structure used to temporarily store the execution results of storage instructions. In this embodiment, the store queue is a circular queue.

[0044] In related technologies, during the execution of a load instruction, the storage queue is queried through the load data pipeline. Only if the storage queue contains a storage address that matches the load address and the storage data corresponding to that storage address has been completely stored can the data required by the load instruction be retrieved from the storage queue. Otherwise, the load instruction is deemed to have failed to execute and needs to wait for a period of time before being re-executed. This results in a large number of times the load instruction is executed, leading to low instruction execution efficiency.

[0045] Indicative, such as Figure 1 As shown, it illustrates a schematic diagram of executing load instructions via a load data pipeline in related technologies. For example... Figure 1 As shown, the storage address pipeline 104 is connected to the storage queue 102, and the storage data pipeline 103 is also connected to the storage queue 102. Both are used to process storage instructions in parallel, writing the storage data and storage address from the storage instruction into the storage queue 102. The load data pipeline 101 is connected to the storage queue 102. Upon receiving a load instruction, the load data pipeline 101 queries the storage queue 102. If the storage queue 102 contains a storage address matching the load address, and the corresponding storage data has been fully stored, the load data pipeline 101 retrieves the required data from the storage queue 102. However, if the storage queue 102 contains a storage address matching the load address, but the corresponding storage data has not been fully stored, the load instruction is deemed to have failed and needs to be re-executed after a period of time. The load data pipeline 101 cannot retrieve the required data from the storage queue during this time.

[0046] like Figure 2 As shown, in the Coremark program, 80000cb4 is a load instruction with a load address of sp+32. Its data source is a store instruction of 80000cba with a store address of sp+32. However, in an out-of-order processor, load and store instructions are executed out of order. That is, it is impossible to confirm whether the data of the store instruction has been stored before the load instruction is executed. Therefore, when executing the load instruction 80000cb4, there is a high probability that the store instruction 80000cba has not yet been executed, which will cause the load instruction to fail.

[0047] In this embodiment of the application, by connecting the loading data pipeline to the loading data pipeline, when there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, and the storage data corresponding to the storage address has not been fully stored, the loading data pipeline can retrieve the storage data corresponding to the loading address from the storage data pipeline. This eliminates the need to wait for the storage data to be stored in the storage queue before re-executing the loading instruction to obtain the required data, effectively reducing the number of times the loading instruction is executed and improving the instruction execution efficiency.

[0048] Please refer to Figure 3 The diagram illustrates a loading memory unit provided in an exemplary embodiment of this application, which includes a memory address pipeline 301, a memory data pipeline 302, a loading data pipeline 303, and a memory queue 304.

[0049] Specifically, the storage address pipeline 301 is connected to the storage queue 304, the storage data pipeline 302 is connected to the storage queue 304, the load data pipeline 303 is connected to the storage queue 304, and the load data pipeline 303 is connected to the storage data pipeline 302.

[0050] The storage address pipeline 301 is used to store the storage address indicated by the storage instruction into the storage queue 304 when a storage instruction is received.

[0051] Optionally, the Store instruction is used to write data from inside the processor (usually in registers) into memory. The Store instruction includes the data to be stored and the store address, which is the specified memory address where the data will be written.

[0052] Optionally, the storage address can be directly encoded in the storage instruction, or it can be indicated by one or more operands in the storage instruction. Optionally, the stored data can be an immediate value directly encoded in the storage instruction, or it can be indicated by one or more operands in the storage instruction; this application embodiment does not limit this.

[0053] For illustration, a store instruction can be represented as `store src dst`, meaning to load the data in register `src` into memory address `dst`; a store instruction can also be represented as `store R0,[R1,#8]`, meaning to store the data in register `R0` into the memory address 8 bytes below the base memory address stored in register `R1`; a store instruction can also be represented as `store#1,[R0]`, meaning to store the value 1 into the address pointed to by register `R0`.

[0054] Optionally, the storage queue 304 is a hardware structure in the loading storage unit used to temporarily store the execution results of storage instructions. That is, when a storage instruction is received, the storage pipeline can first temporarily store the storage address and storage data in the storage instruction into the storage queue 304.

[0055] Optionally, the storage queue 304 includes multiple storage queue entries, each used to store the stored data and storage address of a storage instruction. That is, the stored data and storage address indicated by the same storage instruction are stored in the same storage queue entry. For different storage instructions with the same storage address but different stored data, they are stored in different storage queue entries.

[0056] Optionally, to improve processor performance, the storage pipeline for executing storage instructions in the loading memory unit is usually divided into a storage address pipeline and a storage data pipeline. By coordinating the work of the two pipelines and executing storage instructions in parallel, it is possible to store both the storage address and the storage data corresponding to the storage instruction into the storage queue.

[0057] Optionally, the load memory unit includes at least one memory address pipeline, with different memory address pipelines used to process their respective allocated memory instructions. Optionally, different memory address pipelines can be used to process the same memory instruction or to process different memory instructions.

[0058] Optionally, a memory address pipeline can be divided into multiple address storage stages, and each address storage stage includes at least one hardware unit responsible for performing the address storage task of that stage. Optionally, the memory address pipeline may include an address generation unit (for calculating the memory address corresponding to a memory instruction), an execution unit (for performing arithmetic or logical operations to calculate the memory address), an address register, a data bus, a buffer, a latch, etc., which are not limited in this embodiment.

[0059] In some embodiments, upon receiving a storage instruction from a reservation station, the storage address pipeline 301 parses and calculates the storage address from the storage instruction and writes the storage address into the storage queue 304. Optionally, after parsing and obtaining the storage address, the storage address pipeline 301 may first verify the address validity of the storage address, and only write the storage address into the storage queue 304 if the address is confirmed to be valid.

[0060] The storage data pipeline 302 is used to store the storage data indicated by the storage instruction to the storage queue 304 upon receiving a storage instruction.

[0061] Optionally, the load storage unit includes at least one storage data pipeline, with different storage data pipelines used to process their respective allocated storage instructions. Optionally, different storage data pipelines can be used to process the same storage instruction or to process different storage instructions.

[0062] Optionally, a storage data pipeline can be divided into multiple data storage stages, and each data storage stage includes at least one hardware unit responsible for performing the data storage task of that stage. Optionally, the storage data pipeline may include data registers, data buses, data transmission units, control logic units, data comparison units, etc., which are not limited in this embodiment.

[0063] Optionally, the number of storage address pipelines and the number of storage data pipelines in the load storage unit can be the same or different, and this application embodiment does not limit this.

[0064] In some embodiments, upon receiving a storage instruction from a retention station, the storage data pipeline 302 parses and calculates the storage data from the storage instruction and writes the storage data into the storage queue 304. Optionally, after parsing and obtaining the storage data, the storage data pipeline 302 may first verify the validity of the storage data, and only write the storage data into the storage queue 304 if the data is confirmed to be valid.

[0065] Optionally, after a store instruction enters the load memory unit, it is first cached in a reservation station. The reservation station checks whether the operands corresponding to the store instruction are ready. If the operands are ready, the store instruction is sent to the memory address pipeline and the memory data pipeline for execution. The reservation station is responsible for storing the instruction, checking the operands for readiness, listening for instruction write-backs, and waking up waiting instructions. Once the operands are ready, the instruction in the reservation station is sent to the pipeline for execution.

[0066] The loading data pipeline 303 is used to retrieve the storage data corresponding to the loading address from the storage data pipeline 302 when there is a storage address in the storage queue 304 that matches the loading address indicated by the loading instruction, and the storage data corresponding to the storage address has not been fully stored.

[0067] Optionally, the Load instruction is used to load data from external memory into the processor's registers. During the execution of the Load instruction, the load pipeline needs to query the memory queue to determine if the required data (address match) is available. If so, the data is retrieved first.

[0068] Optionally, the load memory unit includes at least one load data pipeline, with different load data pipelines used to process their respective assigned load instructions. Optionally, different load data pipelines can be used to process the same load instruction or different load instructions.

[0069] Optionally, a data loading pipeline can be divided into multiple data loading stages, and each data loading stage includes at least one hardware unit responsible for performing the data loading task of that stage. Optionally, the data loading pipeline may include an instruction decoding unit, an address generation unit, an address register, an address bus, a data register, a data transmission unit, a data comparison unit, etc., which are not limited in this embodiment.

[0070] In some embodiments, upon receiving a load instruction, the load data pipeline 303 parses the load instruction to obtain the load address, and then queries the storage queue 304 based on the load address to determine whether there is a storage address in the storage queue 304 that matches the load address, and whether the storage address corresponds to stored data. Here, address matching means that the storage address and the load address are the same, both pointing to the same location in memory.

[0071] In out-of-order processors, for a store instruction, because the store address pipeline and the store data pipeline execute in parallel and at different times, it is very possible that the store address has already been stored in the store queue, while the store data is still in the store data pipeline and has not yet been stored in the store queue. That is, when the load instruction is executed, the required store data has not yet been stored.

[0072] Unlike related technologies, where a matching storage address is found in the storage queue but the corresponding data is not yet fully stored, the current load instruction is immediately deemed a failure and requires a waiting period before re-execution, resulting in numerous load instruction executions and low efficiency, this embodiment minimizes the number of load instruction executions. Instead, when a matching storage address is found in the storage queue but the corresponding data is not yet fully stored, the load data pipeline 303 queries the storage data pipeline to directly retrieve the storage data.

[0073] Optionally, if a storage address matching the load address of the load instruction exists in the storage queue 304, and the storage data corresponding to that address has been completely stored, the load data pipeline 303 directly retrieves the storage data corresponding to the load address from the storage queue 304. If multiple storage addresses match the load address, the load data pipeline 303 retrieves the storage data corresponding to the most recently written storage address to the storage queue 304.

[0074] Optionally, if a storage address matching the load address of a load instruction exists in the storage queue 304, but the storage data corresponding to the storage address has not been fully stored, the load data pipeline 303 queries the storage data pipeline 302. If the storage data required by the load instruction exists in the storage data pipeline 302, the storage data is retrieved from the storage data pipeline 302.

[0075] In summary, in the embodiments of this application, by connecting the loading data pipeline to the storage queue in the loading storage unit, and connecting the loading data pipeline to the storage queue, even if there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, and the storage data corresponding to the storage address has not been fully stored, the loading data pipeline can retrieve the storage data corresponding to the loading address from the storage data pipeline. This eliminates the need to wait for the storage data to be stored in the storage queue before re-executing the loading instruction to obtain the required data, reducing the number of instruction executions for the loading instruction and improving instruction execution efficiency.

[0076] In some embodiments, to improve the orderliness of data storage in a storage queue, an index value (Store Queue Index) can be set for each storage queue entry in the storage queue. This index value is used to characterize the position of the storage queue entry in the storage queue. For example, if the storage queue includes 90 storage queue entries, the index value can be set from 0 to 89 according to the order of the storage queue entries in the storage queue.

[0077] Optionally, after receiving a storage instruction but before executing it, considering that a storage instruction will be stored in a storage queue entry, when processing storage instructions in parallel through the storage address pipeline and the storage data pipeline, in order to ensure the correspondence between storage addresses and storage data, index values ​​can be set for the storage addresses and storage data in the same storage instruction according to the storage queue entry corresponding to the storage instruction.

[0078] Optionally, the loading processing unit can assign an index value to a storage instruction based on the usage of the storage queue entries contained in the storage queue. For example, if data has been stored in storage queue entries 0 to 24 when a storage instruction is started, the index value 25 can be set for the current storage instruction, thereby binding the storage address and stored data in the same storage instruction to the same index value, serving as its identity identifier that distinguishes it from other storage instructions in the pipeline.

[0079] Optionally, without considering circular storage, the loading storage unit binds index values ​​to each storage instruction in turn according to the execution order of the storage instructions. The larger the index value, the later the execution order of the storage instruction. That is, when there are multiple storage data corresponding to the same storage address, the larger the index value, the newer the storage data of the storage instruction.

[0080] In some embodiments, when a load instruction is received and the storage queue is queried according to the load address indicated by the load instruction, if there is a storage address in the storage queue that matches the load address, but the storage data corresponding to the storage address has not been completely stored, in order to ensure that the incompletely stored storage data can be found in the storage data pipeline, the load data pipeline needs to further obtain the first index value of the storage queue entry to which the storage address that matches the load address belongs in the storage queue, and then obtain the storage data corresponding to the load address from the storage data pipeline according to the first index value.

[0081] Indicative, such as Figure 4 As shown, there is a load instruction (io_forward_0 instruction) with a load address of 0x3FFFFD13B18. After querying the storage queue, it is found that there is a storage instruction with a matching address but no data yet stored. The index value of this storage instruction is the position of 1 in 0x0000080000000000, which is 0x2B in hexadecimal (43 in decimal). Therefore, the load data pipeline can query the storage data pipeline to see if the storage data corresponding to the index value exists. It is found that the data (0x3E844) with storeDataIn_1_bits_uop_sqIdx_value[5:0] = 2B is about to be written to the storage queue. Thus, the load data pipeline can directly obtain the storage data from the storage data pipeline without waiting for the load instruction to be re-executed.

[0082] In one possible implementation, the load data pipeline is used to determine the storage address in the storage queue that matches the load data of the load instruction, thereby querying whether the storage queue entry to which the storage address belongs contains storage data. If the storage queue entry does not contain storage data, it can be determined that the storage data corresponding to the storage address has not been fully stored, and the load data pipeline obtains the first index value of the storage queue entry to which the storage address belongs.

[0083] Optionally, in the case where there are multiple storage addresses that match the load address of the load instruction, and the storage data corresponding to at least two storage addresses has not been fully stored (i.e., there are at least two storage queue entries in the storage queue whose storage addresses match the load address, and at least two storage queue entries do not contain storage data), in order to ensure that the latest written storage data can be obtained, the load data pipeline can determine the index value corresponding to the storage queue entry of the latest written storage address among the at least two storage queue entries as the first index value, and then obtain the storage data corresponding to the load address from the storage data pipeline based on the first index value.

[0084] Optionally, in order to improve the data storage efficiency of the storage queue, the storage queue adopts a circular storage method to store data, that is, the storage queue is a circular queue.

[0085] Optionally, the storage queue is configured with an enqueue pointer (EnqPtr) and a dequeue pointer (DeqPtr). The enqueue pointer points to the next storage queue entry after the latest one to be written to. When data is written to this next storage queue entry, the enqueue pointer is incremented by one, pointing to the next storage queue entry after that. The dequeue pointer points to the earliest one to be written to. When data is retrieved from this storage queue entry, the dequeue pointer is incremented by one, pointing to the next storage queue entry after this one.

[0086] Optionally, the storage queue stores data cyclically, meaning that if the last storage queue entry in the storage queue has already stored data and the first storage queue entry in the storage queue is empty, the most recently written data will be stored in the first storage queue entry.

[0087] Based on this, flags can be set for the enqueue and dequeue pointers respectively. Optionally, the enqueue pointer corresponds to the first pointer flag, and the dequeue pointer corresponds to the second pointer flag. The first pointer flag indicates the pointer toggling state of the enqueue pointer in the storage queue, and the second pointer flag indicates the pointer toggling state of the dequeue pointer in the storage queue. Optionally, the pointer flag values ​​can be 0 or 1.

[0088] For example, a storage queue contains 0 to 99 entries. Before circular storage, both the first and second pointer flags are set to 0. As data is continuously stored and retrieved, the dequeue pointer points to the 67th storage queue entry, at which point the second pointer flag is 0. Furthermore, when storing data to the 99th storage queue entry, and the 0th storage queue entry is empty, the enqueue pointer is incremented, pointing to the 0th storage queue entry, and the first pointer flag is updated from 0 to 1.

[0089] Indicative, such as Figure 5 As shown, in the storage queue, the enqueue pointer points to the next storage queue entry after the storage queue entry with the latest written data, and the dequeue pointer points to the storage queue entry with the earliest written data.

[0090] In one possible implementation, if at least two storage queue entries in the storage queue contain storage addresses that match the load address, and at least two storage queue entries do not contain stored data, the load data pipeline determines the storage queue entry with the latest written storage address among the at least two storage queue entries based on the first pointer flag of the enqueue pointer, the second pointer flag of the dequeue pointer, and the index value corresponding to the at least two storage queue entries.

[0091] Optionally, if the first pointer flag of the enqueue pointer matches the second pointer flag of the dequeue pointer, it means that the flipping states of the enqueue and dequeue pointers are consistent. At this time, there are storage queue entries with consecutive data in the storage queue. Thus, the loading pipeline can directly compare the index values ​​to determine the writing order of the storage address that matches the loading address. The smaller the index value, the earlier the storage address is written to the storage queue entry. Therefore, the loading pipeline can determine the storage queue entry corresponding to the largest index value among at least two storage queue entries as the storage queue entry that was written to the latest storage address.

[0092] Indicative, such as Figure 5 As shown, when the first pointer flag of the enqueue pointer and the second pointer flag of the dequeue pointer are the same, taking the index values ​​of the storage queue entries to which the storage address matches the load address as an example, the load data pipeline can directly compare the index values. The storage queue entry with the index value of 45 is the storage queue entry of the latest written storage address.

[0093] Optionally, if the first pointer flag of the enqueue pointer is inconsistent with the second pointer flag of the dequeue pointer, it means that the flipping states of the enqueue pointer and the dequeue pointer are inconsistent. In this case, the storage queue can be divided into two index value ranges according to the index value.

[0094] The first index value range is the set of index values ​​between the head index value and the index value of the storage queue entry pointed to by the enqueue pointer. The second index value range is the set of index values ​​between the index value of the storage queue entry pointed to by the dequeue pointer and the tail index value. The writing order of the storage queue entries located in the first index value range is after the writing order of the storage queue entries located in the second index value range.

[0095] In one possible implementation, when the first pointer flag of the enqueue pointer and the second pointer flag of the dequeue pointer are inconsistent, and the index values ​​corresponding to at least two storage queue entries are in a continuous index value range (i.e., at least two storage queue entries are both in the first index value range or at least two storage queue entries are both in the second index value range), the load data pipeline can directly compare the index values ​​to determine the writing order of the storage address matching the load address. The smaller the index value, the earlier the storage address is written to the storage queue entry. Therefore, the load data pipeline can determine the storage queue entry corresponding to the largest index value among the index values ​​corresponding to at least two storage queue entries as the storage queue entry that was most recently written to the storage address.

[0096] In another possible implementation, when the first pointer flag of the enqueue pointer is inconsistent with the second pointer flag of the dequeue pointer, and the index values ​​corresponding to at least two storage queue entries are located in a non-contiguous index value range, that is, when there are storage queue entries in both the first and second index value ranges among the at least two storage queue entries, the loading data pipeline can determine the storage queue entry corresponding to the largest index value in the first index value range as the storage queue entry for the latest written storage address.

[0097] Indicative, such as Figure 5 As shown, when the first pointer flag of the enqueue pointer and the second pointer flag of the dequeue pointer are inconsistent, taking the index values ​​of the storage queue entries to which the storage address that matches the load address belongs as 6 and 15 as an example, the index values ​​are all within the first index value range (0~21). Therefore, the load data pipeline can also directly compare the index values ​​and determine the storage queue entry with the index value of 15 as the storage queue entry of the latest written storage address.

[0098] When the first pointer flag of the enqueue pointer and the second pointer flag of the dequeue pointer are inconsistent, taking the index values ​​of the storage queue entries to which the storage address matching the load address belongs as 15 and 98 as an example, the index value 15 is in the first index value range (0~21), while the index value 98 is in the second index value range (97~99). Therefore, the load data pipeline can directly determine the storage queue entry with index value 15 located in the first index value range as the storage queue entry of the latest written storage address.

[0099] It should be noted that, in this embodiment of the application, the loading data pipeline will only obtain the storage data corresponding to the loading address from the storage data pipeline if there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, the storage data corresponding to the storage address has not been fully stored, and the storage address is the latest one written, that is, if the storage queue entry corresponding to the first index value is the storage queue entry of the latest written storage address.

[0100] In one possible implementation, if the storage queue entry corresponding to the first index value is not the storage queue entry of the latest written storage address, and there is storage data corresponding to the latest written and stored storage address in the storage queue, the loading data pipeline can directly obtain the storage data corresponding to the loading address from the storage queue, without needing to obtain data from the storage data pipeline, and without needing to wait for the storage queue entry corresponding to the first index value to write storage data.

[0101] The above process determines whether the storage queue entry corresponding to the first index value is the storage queue entry with the latest written storage address in the storage queue, and whether there is a storage queue entry in the storage queue with both the latest written storage address and the stored data already stored. This allows for accurate identification of the storage queue entry corresponding to the data required by the load instruction, and direct acquisition of the required storage data.

[0102] Indicative, such as Figure 6 As shown, taking the case where the first pointer flag of the enqueue pointer and the second pointer flag of the dequeue pointer in the storage queue are the same as the example, the storage queue entries with indices 20, 23, and 25 correspond to the same storage address, and this storage address matches the load address of the currently executed load instruction. Specifically, in the storage queue entry with index 23, the storage address has been fully stored, but the storage data has not yet been fully stored; in the storage queue entries with indices 20 and 25, both the storage address and the storage data have been fully stored. That is, the first index value corresponding to the current load instruction is 23, but the storage queue entry corresponding to the first index value 23 is not the storage queue entry with the most recently written storage address. The storage queue entry corresponding to index 25 is the storage queue entry with the most recently written storage address and storage data. Therefore, the load data pipeline can directly obtain the storage data corresponding to the load address from the storage queue entry with index 25 in the storage queue, without waiting for the storage data to be written to the storage queue entry with the first index value 23.

[0103] In some embodiments, to improve instruction execution efficiency, upon receiving a load instruction, while querying the storage queue using the load data pipeline, the load data pipeline can also be used to obtain the second index value corresponding to each stored data in the storage data pipeline. Thus, if there is unstored stored data in the storage queue, the load data pipeline can obtain the storage data corresponding to the load address from the storage data pipeline based on the second index value corresponding to each stored data and the first index value obtained from the storage queue.

[0104] In one possible implementation, after determining the first index value and obtaining the second index value corresponding to each stored data in the storage data pipeline, the loading data pipeline can obtain the stored data corresponding to the loading address from the storage data pipeline corresponding to the first index value by comparing the first index value with the second index value, and if there is a second index value that is the same as the first index value.

[0105] For example, if the first index value is 25, and the second index values ​​obtained by the loading data pipeline from the storage data pipeline are 21, 24, 25, and 27, then there exists a second index value that is the same as the first index value, so the loading data pipeline can obtain the stored data from the storage data pipeline corresponding to the index value 25.

[0106] Optionally, the data loading pipeline can perform a bitwise AND operation between each second index value and the first index value, and then determine whether there is a second index value that is the same as the first index value based on the result of the bitwise AND operation.

[0107] Optionally, if there is a second index value that is the same as the first index value, the loading data pipeline directly obtains the stored data from the storage data pipeline corresponding to the second index value; if there are multiple second index values ​​that are the same as the first index value, the loading data pipeline can obtain the stored data from the storage data pipeline corresponding to any one of the multiple second index values.

[0108] Optionally, the storage data pipeline includes multiple data storage components, each performing its own corresponding data storage task. Specifically, the first n data storage components in the storage data pipeline are used to perform the task of writing stored data into a storage queue.

[0109] In one possible implementation, to improve the efficiency of obtaining the second index value, the loading data pipeline can be connected to the first n data storage components in the storage data pipeline. Then, upon receiving a load instruction, the loading data pipeline can directly obtain the second index value corresponding to each stored data from the first n data storage components of the storage data pipeline, without needing to query other data storage components.

[0110] Optionally, different data storage components execute data storage tasks corresponding to different data storage stages, and each data storage component is equipped with a data register for temporarily storing the data to be stored in that data storage stage. In one possible implementation, the loading data pipeline can directly obtain the second index value corresponding to the stored data from the data registers of the first n data storage components of the storage data pipeline.

[0111] Indicative, such as Figure 7 As shown, the storage data pipeline 701 includes two data storage components, StoreD S0 and StoreD S1, which are used to perform the task of writing storage data into the storage queue. Therefore, the loading data pipeline 702 can be connected to StoreD S0 and StoreD S1 respectively to obtain the second index value corresponding to the storage data contained therein.

[0112] Considering that the length of the stored data corresponding to the storage instruction may not be consistent with the length of the data required by the load instruction, for example, the data required by a load instruction may need to be provided by two or more storage instructions, even if the stored data corresponding to a single storage instruction is obtained from the storage data pipeline, the load instruction cannot be executed completely, and the load instruction will still fail to execute in the end.

[0113] Therefore, in some embodiments, in addition to combining index values ​​to ensure the correspondence between storage addresses and storage data, the data loading pipeline also needs to determine whether the loading instruction meets the data acquisition conditions, that is, whether the data to be loaded by the loading instruction only needs to be provided by a single storage instruction, or whether it is located in a single storage queue entry.

[0114] Optionally, if the data to be loaded by the load instruction is located in a single storage queue entry and there is a second index value that is the same as the first index value, the load data pipeline obtains the storage data corresponding to the load address from the storage data pipeline corresponding to the first index value.

[0115] Optionally, it can be determined whether the load instruction is located in a single storage queue entry based on the first data length of the data to be loaded by the load instruction, the second data length of the data stored by the storage instruction, and the third data length of the storage queue entry.

[0116] Optionally, if the first data length required by the load instruction is greater than the second data length of the stored data, it means that the stored data contained in a single store instruction cannot satisfy the load instruction's requirements. That is, if the stored data of the store instruction is not written to the storage queue, the stored data obtained solely from the storage data pipeline for that store instruction cannot satisfy the load instruction's requirements, resulting in load instruction execution failure. Therefore, only when the first data length required by the load instruction is not greater than the second data length of the stored data can the stored data obtained from the storage data pipeline satisfy the load instruction's requirements, and only then can the load instruction potentially execute successfully.

[0117] Indicative, such as Figure 8 As shown, the first data length required by the load instruction is 8 bytes, and the second data length of the stored data is 4 bytes. That is, the first data length required by the load instruction is greater than the second data length of the stored data. Therefore, even if the stored data is retrieved, the load instruction cannot be completed.

[0118] Optionally, if the first data length required by the load instruction is no greater than the second data length of the stored data, but the sum of the starting data read bit of the load instruction in the storage queue entry and the first data length is greater than the third data length of the storage queue entry, then the stored data contained in a single storage queue entry cannot satisfy the load instruction's requirements. The load instruction needs to be provided by stored data from multiple storage queue entries, and therefore the load instruction fails. Therefore, only when the first data length required by the load instruction is no greater than the second data length of the stored data, and the sum of the starting data read bit of the load instruction in the storage queue entry and the first data length is no greater than the third data length of the storage queue entry, can the load instruction's requirements be satisfied by stored data from a single storage queue entry, and only then can the load instruction potentially execute successfully.

[0119] Indicative, such as Figure 9 As shown, the first data length required by the load instruction is 8 bytes, the third data length of the storage queue entry is 16 bytes, and the starting data read bit of the load instruction in the storage queue entry is at the 13th byte. That is, the storage queue entry can only provide four bytes of storage data to the load instruction, which cannot meet the load instruction's requirements. Therefore, the load instruction is determined to have failed to execute.

[0120] In summary, the loading data pipeline obtains stored data from the storage data pipeline under three conditions: first, there exists a second index value that is identical to the first index value; second, the length of the first data to be loaded by the loading instruction is not greater than the length of the second data of the stored data; and third, the sum of the starting data read bit of the loading instruction in the storage queue entry and the first data length is not greater than the length of the third data of the storage queue entry. That is, only when the length of the first data to be loaded by the loading instruction is not greater than the length of the second data of the stored data, the sum of the starting data read bit of the loading instruction in the storage queue entry and the first data length is not greater than the length of the third data of the storage queue entry, and a second index value identical to the first index value exists, can the loading data pipeline obtain the stored data corresponding to the loading address from the storage data pipeline corresponding to the first index value.

[0121] In the above embodiments, by simultaneously obtaining index values ​​from the storage queue and the storage data pipeline through the loading data pipeline, and by comparing the first index value with the second index value, ensuring that the first data length of the data required by the loading instruction is not greater than the second data length of the stored data, and ensuring that the sum of the starting data read bit of the loading instruction in the storage queue entry and the first data length is not greater than the third data length of the storage queue entry, it is determined whether the data required by the currently executed loading instruction is located in a single storage queue entry. This ensures that the data required by the loading instruction can be obtained accurately and effectively, improves the execution efficiency of the loading instruction, and thus enhances the processor performance.

[0122] In some embodiments, the load storage unit contains multiple load data pipelines, and each load data pipeline is connected to a storage queue and a storage data pipeline. When at least two load data pipelines execute the same load instruction, the storage queue contains a storage address matching the load address included in the load instruction, and the storage data corresponding to the storage address has not been fully stored, each load data pipeline can obtain the storage data corresponding to the load address from the storage data pipeline.

[0123] Optionally, for a single data loading pipeline, the execution of load instructions can be divided into multiple instruction execution stages, including address fetch stage, data query stage, data fetch stage, and data write stage. Different instruction execution stages are executed by different data loading components, each including at least one hardware unit. Based on this, to enable querying and retrieving data from the storage queue or storage data pipeline, the data loading components used for the data query stage and the data fetch stage can be connected to the storage queue and the storage data pipeline, respectively.

[0124] Indicative, such as Figure 10As shown, there are two data loading pipelines executing the same loading instruction. For data loading pipeline 0, the data loading component Load S1 used in the data query stage is connected to the storage queue 1001, StoreD S0 and StoreD S1 in storage data pipeline 0, and StoreD S0 and StoreD S1 in storage data pipeline 1, respectively. The data loading component Load S2 used in the data acquisition stage is also connected to the storage queue 1001, StoreD S0 and StoreD S1 in storage data pipeline 0, and StoreD S0 and StoreD S1 in storage data pipeline 1, respectively.

[0125] For data loading pipeline 1, the data loading component Load S1 used in the data query stage is connected to storage queue 1001, StoreD S0 and StoreD S1 in storage data pipeline 0, and StoreD S0 and StoreD S1 in storage data pipeline 1, respectively. The data loading component Load S2 used in the data acquisition stage is also connected to storage queue 1001, StoreD S0 and StoreD S1 in storage data pipeline 0, and StoreD S0 and StoreD S1 in storage data pipeline 1, respectively.

[0126] Furthermore, during the execution of the load instruction, LoadS1 in Load Data Pipeline 0 and Load Data Pipeline 1 respectively queries Storage Queue 1001, StoreD S0 and StoreD S1 in Storage Data Pipeline 0, and StoreD S0 and StoreD S1 in Storage Data Pipeline 1. If a storage address matching the load address contained in the load instruction exists in storage queue 1001, and the storage data corresponding to the storage address has been completely stored, Load S2 directly retrieves the storage data corresponding to the load address from storage queue 1001. If a storage address matching the load address contained in the load instruction exists in storage queue 1001, and the storage data corresponding to the storage address has not been completely stored, Load S1 determines the first index value of the storage queue entry for the latest written storage address, queries for a second index value that is the same as the first index value, and compares the data lengths. If a second index value that is the same as the first index value exists, the first data length of the data to be loaded by the load instruction is not greater than the second data length of the stored data, and the sum of the starting data read bit in the storage queue entry and the first data length is not greater than the third data length of the storage queue entry, Load S2 retrieves the storage data required by the load instruction in the storage data pipeline corresponding to the first index value.

[0127] It should be noted that, Figure 10Only the component connections between the data loading pipeline, the data storage pipeline, and the storage queue are shown during the process of acquiring stored data. The connection between the storage address pipeline and the storage queue, as well as the connection between different components of the same pipeline, are not shown.

[0128] Please refer to Figure 11 This document illustrates a flowchart of a data acquisition method provided in an exemplary embodiment of this application. This embodiment uses the method applied to the loading storage unit in the above embodiments, where the loading storage unit includes a storage address pipeline, a storage data pipeline, a loading data pipeline, and a storage queue, as an example for explanation. The method includes the following steps:

[0129] Step 1110: Upon receiving a storage instruction, the storage address indicated by the storage instruction is stored in the storage queue through the storage address pipeline.

[0130] Optionally, store instructions are used to write data from inside the processor (usually in registers) into memory. A store instruction includes the data to be stored and a store address, which is the specified memory address where the data will be written.

[0131] Optionally, the storage address can be directly encoded in the storage instruction, or it can be indicated by one or more operands in the storage instruction. Optionally, the stored data can be an immediate value directly encoded in the storage instruction, or it can be indicated by one or more operands in the storage instruction; this application embodiment does not limit this.

[0132] Optionally, the storage queue is a component within the load storage unit used to temporarily store the execution results of storage instructions. That is, upon receiving a storage instruction, the load storage unit can temporarily store the storage address and storage data in the storage instruction to the storage queue through the storage pipeline.

[0133] Optionally, the storage queue includes multiple storage queue entries, each used to store the storage data and storage address indicated by a storage instruction. That is, the storage data and storage address indicated by the same storage instruction are stored in the same storage queue entry. For different storage instructions with the same storage address but different storage data, they are stored in different storage queue entries.

[0134] Optionally, to improve processor performance, the storage pipeline for executing stored instructions in the loaded memory unit is usually divided into a storage address pipeline and a storage data pipeline. By coordinating the work of the two pipelines and executing stored instructions in parallel, it is possible to store both the storage address and the storage data in the stored instructions into the storage queue.

[0135] Optionally, the load memory unit includes at least one memory address pipeline, with different memory address pipelines used to process their respective allocated memory instructions. Optionally, different memory address pipelines can be used to process the same memory instruction or to process different memory instructions.

[0136] Optionally, a memory address pipeline can be divided into multiple address storage stages, and each address storage stage includes at least one hardware unit responsible for performing the address storage task of that stage. Optionally, the memory address pipeline may include an address generation unit (for calculating the memory address corresponding to a memory instruction), an execution unit (for performing arithmetic or logical operations to calculate the memory address), an address register, a data bus, a buffer, a latch, etc., which are not limited in this embodiment.

[0137] In some embodiments, upon receiving a storage instruction, the loading storage unit can parse and calculate the storage address from the storage instruction using a storage address pipeline, and then write the storage address into a storage queue. Optionally, after parsing and obtaining the storage address, the storage address pipeline can also first verify the validity of the storage address, and only write the storage address into the storage queue if the address is confirmed to be valid.

[0138] Step 1120: Upon receiving a storage instruction, the storage data indicated by the storage instruction is stored in the storage queue through the storage data pipeline.

[0139] Optionally, the load storage unit includes at least one storage data pipeline, with different storage data pipelines used to process their respective allocated storage instructions. Optionally, different storage data pipelines can be used to process the same storage instruction or to process different storage instructions.

[0140] Optionally, a storage data pipeline can be divided into multiple data storage stages, and each data storage stage includes at least one hardware unit responsible for performing the data storage task of that stage. Optionally, the storage data pipeline may include data registers, data buses, data transmission units, control logic units, data comparison units, etc., which are not limited in this embodiment.

[0141] Optionally, the number of storage address pipelines and the number of storage data pipelines in the load storage unit can be the same or different, and this application embodiment does not limit this.

[0142] In some embodiments, upon receiving a storage instruction, the loading storage unit can parse and calculate using a storage data pipeline to obtain storage data from the storage instruction and write the storage data to a storage queue. Optionally, after parsing and obtaining the storage data, the storage data pipeline can also first verify the validity of the storage data and, if the data is confirmed to be valid, then write the storage data to the storage queue.

[0143] Step 1130: If a storage address matching the load address indicated by the load instruction exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, the storage data corresponding to the load address is obtained from the storage data pipeline through the load data pipeline.

[0144] Optionally, load instructions are used to load data from external memory into the processor's registers. During the execution of a load instruction, the load pipeline needs to query the memory queue to determine if the required data (address match) is available; if so, it retrieves the data from that queue first.

[0145] Optionally, the load memory unit includes at least one load data pipeline, with different load data pipelines used to process their respective assigned load instructions. Optionally, different load data pipelines can be used to process the same load instruction or different load instructions.

[0146] Optionally, a data loading pipeline can be divided into multiple data loading stages, and each data loading stage includes at least one hardware unit responsible for performing the data loading task of that stage. Optionally, the data loading pipeline may include an instruction decoding unit, an address generation unit, an address register, an address bus, a data register, a data transmission unit, a data comparison unit, etc., which are not limited in this embodiment.

[0147] In some embodiments, upon receiving a load instruction, the load storage unit can parse the load instruction through the load data pipeline to obtain the load address. Then, it can query the storage queue based on the load address to determine whether a storage address matching the load address exists in the queue, and whether that storage address corresponds to stored data. Here, address matching means that the storage address and the load address are the same, both pointing to the same location in memory.

[0148] In out-of-order processors, for a store instruction, because the store address pipeline and the store data pipeline execute in parallel and at different times, it is very possible that the store address has been stored in the store queue, but the store data has not yet been stored in the store queue. That is, when a load instruction is executed, the required store data has not yet been stored.

[0149] Unlike related technologies, where a matching storage address is found in the storage queue but the corresponding data is not yet fully stored, the current load instruction is immediately deemed a failure and requires a waiting period before re-execution, resulting in numerous load instruction executions and low efficiency, this embodiment minimizes the number of load instruction executions. In cases where a matching storage address is found in the storage queue but the corresponding data is not yet fully stored, the load storage unit queries the storage data pipeline through the load data pipeline to directly obtain the stored data.

[0150] Optionally, if a storage address matching the load address of the load instruction exists in the storage queue, and the storage data corresponding to that address has already been stored, the load storage unit directly retrieves the storage data corresponding to the load address from the storage queue via the load data pipeline. If multiple storage addresses matching the load address exist, the load storage unit retrieves the storage data corresponding to the most recently written storage address from the storage queue via the load data pipeline.

[0151] Optionally, if a storage address matching the load address of a load instruction exists in the storage queue, but the storage data corresponding to the storage address has not been fully stored, the load storage unit queries the storage data pipeline through the load data pipeline. If the storage data required by the load instruction exists in the storage data pipeline, the storage data is retrieved from the storage data pipeline.

[0152] In summary, in the embodiments of this application, by connecting the loading data pipeline to the storage queue in the loading storage unit, and connecting the loading data pipeline to the storage queue, even if there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, and the storage data corresponding to the storage address has not been fully stored, the loading data pipeline can retrieve the storage data corresponding to the loading address from the storage data pipeline. This eliminates the need to wait for the storage data to be stored in the storage queue before re-executing the loading instruction to obtain the required data, reducing the number of instruction executions for the loading instruction and improving instruction execution efficiency.

[0153] In some embodiments, to improve the orderliness of data storage in a storage queue, an index value (Store Queue Index) can be set for each storage queue entry in the storage queue. This index value is used to characterize the position of the storage queue entry in the storage queue. For example, if the storage queue includes 90 storage queue entries, the index value can be set from 0 to 89 according to the order of the storage queue entries in the storage queue.

[0154] Optionally, after receiving a storage instruction but before executing it, considering that a storage instruction will be stored in a storage queue entry, when processing storage instructions in parallel through the storage address pipeline and the storage data pipeline, in order to ensure the correspondence between storage addresses and storage data, index values ​​can be set for the storage addresses and storage data in the same storage instruction according to the storage queue entry corresponding to the storage instruction.

[0155] Optionally, the loading processing unit can assign an index value to a storage instruction based on the usage of the storage queue entries contained in the storage queue. For example, if data has been stored in storage queue entries 0 to 24 when a storage instruction is started, the index value 25 can be set for the current storage instruction, thereby binding the storage address and stored data in the same storage instruction to the same index value, serving as its identity identifier that distinguishes it from other storage instructions in the pipeline.

[0156] Optionally, without considering circular storage, the loading storage unit binds index values ​​to each storage instruction in turn according to the execution order of the storage instructions. The larger the index value, the later the execution order of the storage instruction. That is, when there are multiple storage data corresponding to the same storage address, the larger the index value, the newer the storage data of the storage instruction.

[0157] Please refer to Figure 12 This document illustrates a flowchart of retrieving stored data based on a first index value, provided in an exemplary embodiment of this application. This embodiment uses the method for loading storage units in the above embodiments as an example for explanation. The method includes the following steps:

[0158] Step 1131: Based on the load address indicated by the load instruction, query the storage queue through the load data pipeline.

[0159] In some embodiments, upon receiving a load instruction, the load storage unit queries the storage queue according to the load address indicated by the load instruction via the load data pipeline.

[0160] Optionally, the load instruction can be executed through a single load data pipeline or multiple load data pipelines simultaneously.

[0161] Step 1132: If a storage address matching the load address exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, obtain the first index value of the storage queue entry to which the storage address belongs through the data loading pipeline.

[0162] In some embodiments, if there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, and the storage data corresponding to the storage address has not been fully stored, in order to ensure that the incompletely stored storage data can be found in the storage data pipeline, the loading storage unit needs to further obtain the first index value of the storage queue entry to which the storage address that matches the loading address belongs in the storage queue through the loading data pipeline.

[0163] In one possible implementation, the loading storage unit determines the storage address in the storage queue that matches the loading data of the loading instruction through the loading data pipeline, and then queries whether the storage queue entry to which the storage address belongs contains the storage data. If the storage queue entry does not contain the storage data, it can be determined that the storage data corresponding to the storage address has not been fully stored, and the first index value of the storage queue entry to which the storage address belongs can be obtained through the loading data pipeline.

[0164] Optionally, when there are multiple storage addresses that match the load address of the load instruction, and the storage data corresponding to at least two storage addresses has not been fully stored (i.e., at least two storage queue entries in the storage queue contain storage addresses that match the load address, and at least two storage queue entries do not contain storage data), in order to ensure that the latest written storage data can be obtained, the load storage unit can determine the index value corresponding to the storage queue entry of the latest written storage address among the at least two storage queue entries as the first index value through the load data pipeline, and then obtain the storage data corresponding to the load address from the storage data pipeline based on the first index value.

[0165] Optionally, in order to improve the data storage efficiency of the storage queue, the storage queue adopts a circular storage method to store data, that is, the storage queue is a circular queue.

[0166] Optionally, the storage queue is configured with an enqueue pointer and a dequeue pointer. The enqueue pointer points to the next storage queue entry after the latest one to be written to. When data is written to this next storage queue entry, the enqueue pointer is incremented by one, pointing to the next storage queue entry after that. The dequeue pointer points to the earliest one to be written to. When data is retrieved from this storage queue entry, the dequeue pointer is incremented by one, pointing to the next storage queue entry after this one.

[0167] Optionally, the storage queue stores data cyclically, meaning that if the last storage queue entry in the storage queue has already stored data and the first storage queue entry in the storage queue is empty, the most recently written data will be stored in the first storage queue entry.

[0168] Based on this, flag bits can be set for the enqueue pointer and the dequeue pointer respectively. Optionally, the enqueue pointer corresponds to the first pointer flag bit, and the dequeue pointer corresponds to the second pointer flag bit. The first pointer flag bit represents the pointer toggling state of the enqueue pointer in the storage queue, and the second pointer flag bit represents the pointer toggling state of the dequeue pointer in the storage queue. Optionally, the pointer flag bit can take the value 0 or 1.

[0169] For example, a storage queue contains 0 to 99 entries. Before circular storage, both the first and second pointer flags are set to 0. As data is continuously stored and retrieved, the dequeue pointer points to the 67th storage queue entry, at which point the second pointer flag is 0. Furthermore, when storing data to the 99th storage queue entry, and the 0th storage queue entry is empty, the enqueue pointer is incremented, pointing to the 0th storage queue entry, and the first pointer flag is updated from 0 to 1.

[0170] In one possible implementation, if at least two storage queue entries in the storage queue contain storage addresses that match the load address, and at least two storage queue entries do not contain stored data, the load storage unit determines the storage queue entry with the latest written storage address among the at least two storage queue entries by using the load data pipeline, based on the first pointer flag of the enqueue pointer, the second pointer flag of the dequeue pointer, and the index values ​​corresponding to the at least two storage queue entries.

[0171] Optionally, if the first pointer flag of the enqueue pointer matches the second pointer flag of the dequeue pointer, it means that the flipping states of the enqueue and dequeue pointers are consistent. At this time, there are storage queue entries with consecutive data in the storage queue. Thus, the loading storage unit can directly compare the index values ​​through the loading data pipeline to determine the writing order of the storage address that matches the loading address. The smaller the index value, the earlier the storage address is written to the storage queue entry. Therefore, the loading data pipeline can determine the storage queue entry corresponding to the largest index value among at least two storage queue entries as the storage queue entry that was written to the latest storage address.

[0172] Optionally, if the first pointer flag of the enqueue pointer is inconsistent with the second pointer flag of the dequeue pointer, it means that the flipping states of the enqueue pointer and the dequeue pointer are inconsistent. In this case, the storage queue can be divided into two index value ranges according to the index value.

[0173] The first index value range is the set of index values ​​between the head index value and the index value of the storage queue entry pointed to by the enqueue pointer. The second index value range is the set of index values ​​between the index value of the storage queue entry pointed to by the dequeue pointer and the tail index value. The writing order of the storage queue entries located in the first index value range is after the writing order of the storage queue entries located in the second index value range.

[0174] In one possible implementation, when the first pointer flag of the enqueue pointer and the second pointer flag of the dequeue pointer are inconsistent, and the index values ​​corresponding to at least two storage queue entries are located in a continuous index value range (i.e., at least two storage queue entries are both located in the first index value range or at least two storage queue entries are both located in the second index value range), the loading storage unit can directly compare the index values ​​through the loading data pipeline to determine the writing order of the storage address matching the loading address. The smaller the index value, the earlier the storage address is written to the storage queue entry. Therefore, the loading data pipeline can determine the storage queue entry corresponding to the largest index value among the index values ​​corresponding to at least two storage queue entries as the storage queue entry that was most recently written to the storage address.

[0175] In another possible implementation, when the first pointer flag of the enqueue pointer is inconsistent with the second pointer flag of the dequeue pointer, and the index values ​​corresponding to at least two storage queue entries are located in a non-contiguous index value range, that is, when there are storage queue entries in both the first and second index value ranges among the at least two storage queue entries, the loading data pipeline can determine the storage queue entry corresponding to the largest index value in the first index value range as the storage queue entry for the latest written storage address.

[0176] It should be noted that, in this embodiment of the application, the loading data pipeline will only obtain the storage data corresponding to the loading address from the storage data pipeline if there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, the storage data corresponding to the storage address has not been fully stored, and the storage address is the latest one written, that is, if the storage queue entry corresponding to the first index value is the storage queue entry of the latest written storage address.

[0177] In one possible implementation, if the storage queue entry corresponding to the first index value is not the storage queue entry of the latest written storage address, and there is storage data corresponding to the latest written and stored storage address in the storage queue, the loading data pipeline can directly obtain the storage data corresponding to the loading address from the storage queue, without needing to obtain data from the storage data pipeline, and without needing to wait for the storage queue entry corresponding to the first index value to write storage data.

[0178] The above process determines whether the storage queue entry corresponding to the first index value is the storage queue entry with the latest written storage address in the storage queue, and whether there is a storage queue entry in the storage queue with both the latest written storage address and the stored data already stored. This allows for accurate identification of the storage queue entry corresponding to the data required by the load instruction, and direct acquisition of the required storage data.

[0179] Step 1133: Based on the first index value, obtain the storage data corresponding to the load address from the storage data pipeline through the load data pipeline.

[0180] In some embodiments, to improve instruction execution efficiency, upon receiving a load instruction, while querying the storage queue using the load data pipeline, the load storage unit can also obtain the second index value corresponding to each stored data in the storage data pipeline through the load data pipeline. Thus, if there is unstored stored data in the storage queue, the storage data corresponding to the load address can be obtained from the storage data pipeline through the load data pipeline based on the second index value corresponding to each stored data and the first index value obtained from the storage queue.

[0181] In one possible implementation, after determining the first index value and obtaining the second index value corresponding to each stored data in the storage data pipeline, the storage data corresponding to the load address can be obtained from the storage data pipeline corresponding to the first index value by comparing the first index value and the second index value, and if there is a second index value that is the same as the first index value, the storage data can be obtained from the storage data pipeline corresponding to the first index value by loading the data pipeline.

[0182] Optionally, the data loading pipeline can perform a bitwise AND operation between each second index value and the first index value, and then determine whether there is a second index value that is the same as the first index value based on the result of the bitwise AND operation.

[0183] Optionally, the storage data pipeline includes multiple data storage components, each performing its own corresponding data storage task. Specifically, the first n data storage components in the storage data pipeline are used to perform the task of writing stored data into a storage queue.

[0184] In one possible implementation, to improve the efficiency of obtaining the second index value, the loading data pipeline can be connected to the first n data storage components in the storage data pipeline. Then, upon receiving a load instruction, the loading storage unit can directly obtain the second index value corresponding to each stored data from the first n data storage components of the storage data pipeline via the loading data pipeline, without needing to query other data storage components.

[0185] Optionally, different data storage components execute data storage tasks corresponding to different data storage stages, and each data storage component is equipped with a data register for temporarily storing the data to be stored in that data storage stage. In one possible implementation, the loading data pipeline can directly obtain the second index value corresponding to the stored data from the data registers of the first n data storage components of the storage data pipeline.

[0186] Considering that the length of the stored data corresponding to the storage instruction may not be consistent with the length of the data required by the load instruction, for example, the data required by a load instruction may need to be provided by two or more storage instructions, even if the stored data corresponding to a single storage instruction is obtained from the storage data pipeline, the load instruction cannot be executed completely, and the load instruction will still fail to execute in the end.

[0187] Therefore, in some embodiments, in addition to combining the index value to ensure the correspondence between the storage address and the storage data, the loading storage unit also needs to determine whether the loading instruction meets the data acquisition conditions, that is, whether the data to be loaded by the loading instruction only needs to be provided by a single storage instruction, or whether it is located in a single storage queue entry.

[0188] Optionally, if the data to be loaded by the load instruction is located in a single storage queue entry and there is a second index value that is the same as the first index value, the load storage unit obtains the storage data corresponding to the load address from the storage data pipeline corresponding to the second index value through the load data pipeline.

[0189] Optionally, it can be determined whether the load instruction is located in a single storage queue entry based on the first data length of the data to be loaded by the load instruction, the second data length of the data stored by the storage instruction, and the third data length of the storage queue entry.

[0190] Optionally, if the first data length required by the load instruction is greater than the second data length of the stored data, it means that the stored data contained in a single store instruction cannot satisfy the load instruction's requirements. That is, if the stored data of the store instruction is not written to the storage queue, the stored data obtained solely from the storage data pipeline for that store instruction cannot satisfy the load instruction's requirements, resulting in load instruction execution failure. Therefore, only when the first data length required by the load instruction is not greater than the second data length of the stored data can the stored data obtained from the storage data pipeline satisfy the load instruction's requirements, and only then can the load instruction potentially execute successfully.

[0191] Optionally, if the first data length required by the load instruction is no greater than the second data length of the stored data, but the sum of the starting data read bit of the load instruction in the storage queue entry and the first data length is greater than the third data length of the storage queue entry, then the stored data contained in a single storage queue entry cannot satisfy the load instruction's requirements. The load instruction needs to be provided by stored data from multiple storage queue entries, and therefore the load instruction fails. Therefore, only when the first data length required by the load instruction is no greater than the second data length of the stored data, and the sum of the starting data read bit of the load instruction in the storage queue entry and the first data length is no greater than the third data length of the storage queue entry, can the load instruction's requirements be satisfied by stored data from a single storage queue entry, and only then can the load instruction potentially execute successfully.

[0192] In summary, the loading data pipeline obtains stored data from the storage data pipeline under three conditions: first, there exists a second index value that is identical to the first index value; second, the length of the first data to be loaded by the loading instruction is not greater than the length of the second data of the stored data; and third, the sum of the starting data read bit of the loading instruction in the storage queue entry and the first data length is not greater than the length of the third data of the storage queue entry. That is, only when the length of the first data to be loaded by the loading instruction is not greater than the length of the second data of the stored data, the sum of the starting data read bit of the loading instruction in the storage queue entry and the first data length is not greater than the length of the third data of the storage queue entry, and a second index value identical to the first index value exists, can the loading data pipeline obtain the stored data corresponding to the loading address from the storage data pipeline corresponding to the first index value.

[0193] In the above embodiments, by simultaneously obtaining index values ​​from the storage queue and the storage data pipeline through the loading data pipeline, and by comparing the first index value with the second index value, ensuring that the first data length of the data required by the loading instruction is not greater than the second data length of the stored data, and ensuring that the sum of the starting data read bit of the loading instruction in the storage queue entry and the first data length is not greater than the third data length of the storage queue entry, it is determined whether the data required by the currently executed loading instruction is located in a single storage queue entry. This ensures that the data required by the loading instruction can be obtained accurately and effectively, improves the execution efficiency of the loading instruction, and thus enhances the processor performance.

[0194] The solutions shown in the above embodiments of this application can be applied to chips. Specifically, this application also provides a chip that includes at least one load memory unit as shown in the various embodiments described above.

[0195] Optionally, the chip may include a processor, such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), or other processors that require access to memory units. This application embodiment does not limit this.

[0196] This application also provides a board card, which is provided with the chip described above.

[0197] This board may include a printed circuit board (PCB) whose supported interface types match the chip, which can be connected to an integrated circuit board. For example, this board can be a single-board computer, a graphics card, a sound card, etc. Alternatively, the PCB may be a motherboard, with the chip directly connected to it. This board can also be a main control board, a line card, a network card, etc.

[0198] This application also provides a computer device, which in some embodiments may be a server.

[0199] See Figure 13 , Figure 13 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application.

[0200] Specifically, the computer device 1300 includes a system bus 1301, a board 1302, and other devices 1304. The board 1302 includes a chip 1303. The chip 1303 includes a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU).

[0201] Optionally, other devices 1304 include system memory consisting of random access memory and read-only memory, a basic input / output (I / O) system that facilitates information transfer between various devices within the computer, and a mass storage device for storing the operating system, applications, and other program modules. The basic input / output system includes a display for showing information and input devices such as a mouse and keyboard for user input. Both the display and the input devices are connected to the processing unit via an input / output controller connected to the system bus 1301. The basic input / output system may also include an input / output controller for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller also provides output to a display screen, printer, or other types of output devices.

[0202] The mass storage device is connected to the processing unit via a mass storage controller connected to the system bus 1301. The mass storage device and its associated computer-readable medium provide non-volatile storage for the computer device 1300. That is, the mass storage device may include computer-readable media such as a hard disk or drive.

[0203] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage media are not limited to the above-mentioned types. The aforementioned system memories and mass storage devices can be collectively referred to as memory.

[0204] The memory stores one or more programs, which are configured to be executed by one or more processing units. The one or more programs contain instructions for implementing the methods described above, and the processing units execute the one or more programs to implement the methods provided in the various method embodiments described above.

[0205] According to various embodiments of this application, the computer device 1300 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 1300 can be connected to a network via a network interface unit connected to the system bus 1301, or it can use the network interface unit to connect to other types of networks or remote computer systems.

[0206] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0207] The above are merely optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A loading storage unit, characterized in that, The load storage unit includes a storage address pipeline, a storage data pipeline, a load data pipeline, and a storage queue; The storage address pipeline is used to store the storage address indicated by the storage instruction into the storage queue upon receiving a storage instruction; The storage data pipeline is used to store the storage data indicated by the storage instruction into the storage queue upon receiving the storage instruction; wherein the storage data indicated by the same storage instruction and the storage address are stored in the same storage queue entry in the storage queue; The loading data pipeline is used to retrieve the storage data corresponding to the loading address from the storage data pipeline when there is a storage address in the storage queue that matches the loading address indicated by the loading instruction, and the storage data corresponding to the storage address has not been fully stored.

2. The loading storage unit according to claim 1, characterized in that, Each storage queue entry in the storage queue has an index value, which is used to characterize the position of the storage queue entry in the storage queue. The data loading pipeline is used for: Based on the load address indicated by the load instruction, query the storage queue; If a storage address matching the loading address exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, obtain the first index value of the storage queue entry to which the storage address belongs; Based on the first index value, the storage data corresponding to the load address is obtained from the storage data pipeline.

3. The loading storage unit according to claim 2, characterized in that, The data loading pipeline is used for: Determine the storage address in the storage queue that matches the load address; If the storage data is not contained in the storage queue entry to which the storage address belongs, it is determined that the storage data corresponding to the storage address has not been fully stored, and the first index value of the storage queue entry to which the storage address belongs is obtained.

4. The loading storage unit according to claim 3, characterized in that, The data loading pipeline is used for: If at least two storage queue entries in the storage queue contain storage addresses that match the load address, and the at least two storage queue entries do not contain the storage data, the storage data corresponding to the load address is obtained from the storage data pipeline based on the first index value of the storage queue entry that was most recently written to the storage address among the at least two storage queue entries.

5. The loading storage unit according to claim 4, characterized in that, The storage queue is a circular queue, and the storage queue is equipped with an enqueue pointer and a dequeue pointer; The data loading pipeline is used for: If at least two storage queue entries in the storage queue contain storage addresses that match the load address, and the at least two storage queue entries do not contain the stored data, the storage queue entry that was most recently written to the storage address is determined based on the first pointer flag of the enqueue pointer, the second pointer flag of the dequeue pointer, and the index value corresponding to the at least two storage queue entries in the storage queue. Wherein, the first pointer flag bit represents the pointer flipping state of the enqueue pointer in the storage queue, and the second pointer flag bit represents the pointer flipping state of the dequeue pointer in the storage queue.

6. The loading storage unit according to claim 5, characterized in that, The data loading pipeline is used for: When the first pointer flag of the enqueue pointer is consistent with the second pointer flag of the dequeue pointer, the storage queue entry corresponding to the largest index value among the index values ​​corresponding to the at least two storage queue entries is determined as the storage queue entry that was most recently written to the storage address. If the first pointer flag of the enqueue pointer is inconsistent with the second pointer flag of the dequeue pointer, and the index values ​​corresponding to the at least two storage queue entries are in a continuous index value range, the storage queue entry corresponding to the largest index value among the at least two storage queue entries shall be determined as the storage queue entry most recently written to the storage address. If the first pointer flag of the enqueue pointer is inconsistent with the second pointer flag of the dequeue pointer, and the index values ​​corresponding to the at least two storage queue entries are in a non-contiguous index value range, the storage queue entry corresponding to the largest index value in the first index value range among the at least two storage queue entries is determined as the storage queue entry most recently written to the storage address. Wherein, the writing order of the storage queue entries located in the first index value interval is after the writing order of the storage queue entries located in the second index value interval, the first index value interval is the set of index values ​​between the head index value and the index value pointed to by the enqueue pointer, and the second index value interval is the set of index values ​​between the index value pointed to by the dequeue pointer and the tail index value.

7. The loading storage unit according to claim 2, characterized in that, The data loading pipeline is used for: If the storage queue entry corresponding to the first index value is the latest storage queue entry written to the storage address, the storage data corresponding to the load address is obtained from the storage data pipeline; The data loading pipeline is also used for: If the storage queue entry corresponding to the first index value is not the latest storage queue entry written to the storage address, and the storage queue contains the latest written and already stored storage data corresponding to the storage address, then the storage data corresponding to the load address is retrieved from the storage queue.

8. The loading storage unit according to claim 2, characterized in that, The data loading pipeline is used for: Obtain the second index value corresponding to each stored data in the storage data pipeline; If a second index value exists that is identical to the first index value, the storage data corresponding to the load address is retrieved from the storage data pipeline corresponding to the first index value.

9. The loading storage unit according to claim 8, characterized in that, The data loading pipeline is used for: If the data to be loaded by the load instruction is located in a single storage queue entry, and a second index value that is the same as the first index value exists, the storage data corresponding to the load address is obtained from the storage data pipeline corresponding to the first index value.

10. The loading storage unit according to claim 9, characterized in that, The data loading pipeline is used for: If the first data length of the data to be loaded by the loading instruction is not greater than the second data length of the stored data, and the sum of the starting data read bit of the loading instruction in the storage queue entry and the first data length is not greater than the third data length of the storage queue entry, and there exists a second index value that is the same as the first index value, the stored data corresponding to the loading address is obtained from the storage data pipeline corresponding to the first index value.

11. The loading storage unit according to claim 8, characterized in that, The storage data pipeline includes multiple data storage components, and the first n data storage components in the storage data pipeline are used to perform the task of writing the stored data into the storage queue; The data loading pipeline is used for: The second index value corresponding to each stored data is obtained from the first n data storage components of the storage data pipeline.

12. A data acquisition method, characterized in that, The method is used to load a storage unit, which includes a storage address pipeline, a storage data pipeline, a load data pipeline, and a storage queue. The method includes: Upon receiving a storage instruction, the storage address indicated by the storage instruction is stored in the storage queue through the storage address pipeline; Upon receiving the storage instruction, the storage data indicated by the storage instruction is stored in the storage queue through the storage data pipeline; wherein the storage data indicated by the same storage instruction and the storage address are stored in the same storage queue entry in the storage queue; If a storage address matching the load address indicated by the load instruction exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, the storage data corresponding to the load address is obtained from the storage data pipeline through the load data pipeline.

13. The method according to claim 12, characterized in that, When a storage address matching the load address indicated by the load instruction exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, the storage data corresponding to the load address is obtained from the storage data pipeline through the load data pipeline, including: Based on the load address in the load instruction, the storage queue is queried through the load data pipeline; If a storage address matching the loading address exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, the first index value of the storage queue entry to which the storage address belongs is obtained through the loading data pipeline. Based on the first index value, the storage data corresponding to the loading address is obtained from the storage data pipeline through the loading data pipeline.

14. The method according to claim 13, characterized in that, When a storage address matching the loading address exists in the storage queue, and the storage data corresponding to the storage address has not been fully stored, the first index value of the storage queue entry to which the storage address belongs is obtained through the loading data pipeline, including: The storage address that matches the loading address in the storage queue is determined through the loading data pipeline; If the stored data is not contained in the storage queue entry to which the storage address belongs, the data loading pipeline determines that the stored data corresponding to the storage address has not been fully stored, and obtains the first index value of the storage queue entry to which the storage address belongs.

15. The method according to claim 13, characterized in that, The step of obtaining the storage data corresponding to the load address from the storage data pipeline through the load data pipeline based on the first index value includes: The second index value corresponding to each stored data in the storage data pipeline is obtained through the loading data pipeline; If a second index value exists that is identical to the first index value, the storage data corresponding to the load address is obtained from the storage data pipeline corresponding to the first index value through the load data pipeline.

16. The method according to claim 15, characterized in that, In the case where a second index value identical to the first index value exists, retrieving the storage data corresponding to the load address from the storage data pipeline corresponding to the first index value via the load data pipeline includes: If the data to be loaded by the load instruction is located in a single storage queue entry, and a second index value that is the same as the first index value exists, the storage data corresponding to the load address is obtained from the storage data pipeline corresponding to the first index value through the load data pipeline.

17. The method according to claim 15, characterized in that, The storage data pipeline includes multiple data storage components, and the first n data storage components in the storage data pipeline are used to perform the task of writing the stored data into the storage queue; The step of obtaining the second index value corresponding to each stored data in the storage data pipeline through the loading data pipeline includes: The second index value corresponding to each stored data is obtained from the first n data storage components of the storage data pipeline through the loading data pipeline.

18. A chip, characterized in that, The chip includes at least one load memory unit as described in any one of claims 1 to 11.

19. A circuit board, characterized in that, The board is equipped with the chip as described in claim 18.

20. A computer device, characterized in that, The computer device is equipped with the board as described in claim 19.

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