Communication method and device
By allocating data transfer tasks to the less powerful first processor core in high-performance computing, the problem of data transfer consuming computing power is solved, the computing efficiency of the processor core and the flexibility of task execution are improved, and energy consumption is reduced.
Patent Information
- Application Number
- CN202411147994.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2026-03-03
AI Technical Summary
In high-performance computing, data transfer consumes the computing power of the processor cores, leading to a decrease in computing efficiency.
By setting the first processor core to perform data transfer tasks and the second processor core to perform computation tasks, the computation efficiency of the second processor core is prevented from being reduced due to data transfer tasks. The processing speed of data transfer tasks is balanced by using task queues and priority sorting, and timely completion or failure notification of tasks is ensured through inter-thread or inter-processor communication.
It improves the computing efficiency of the processor core, reduces the energy consumption of data transfer tasks, and enhances computing performance and the flexibility and rationality of task execution.
Smart Images
Figure CN121597433A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more particularly to communication methods and apparatus. Background Technology
[0002] High-performance computing (HPC), also known as large-scale computing, uses a large number of processor cores to solve complex mathematical tasks.
[0003] In high-performance computing, data movement is involved. Data movement refers to the processor core reading the data required for computation from memory and writing the data generated by the computation into memory.
[0004] Data transfer during high-performance computing consumes a portion of the processor core's computing power, thereby reducing the processor core's computing efficiency. Summary of the Invention
[0005] This application provides a communication method and apparatus to improve the computational efficiency of processor cores. To achieve the above objectives, this application adopts the following technical solutions:
[0006] In a first aspect, embodiments of this application provide a communication method, the method comprising: a first processor core receiving a first message sent by a second processor core, the first message including a first address, a second address and the size of target data, the first message being used to instruct the execution of a data transfer task, the data transfer task being to transfer the target data from the first address to the second address or to transfer the target data from the second address to the first address; in response to the first message, the first processor core executing the data transfer task.
[0007] The solution provided in this application embodiment includes a first processor core for performing data transfer tasks. When a second processor core performing a computing task generates a data transfer task, it can send a message to instruct the first processor core to perform the data transfer task. The second processor core itself does not perform the data transfer task, thereby avoiding a reduction in computing efficiency due to the second processor core performing the data transfer task, thus improving the computing efficiency of the processor core.
[0008] In one possible implementation, the target data is the data obtained by the second processor core performing the computing task or the data required by the second processor core to perform the computing task.
[0009] In one possible implementation, the first processor core includes a task queue, which includes at least one data transfer task.
[0010] In one possible implementation, the response to the first message may be made if the data transfer task indicated by the first message is the first data transfer task in the task queue.
[0011] The solution provided in this application embodiment can first place the data transfer task indicated by the first message into the task queue, and then retrieve the data transfer task indicated by the first message from the task queue for processing. This can avoid data transfer task loss and also balance the processing speed of data transfer tasks.
[0012] In one possible implementation, the task queue described above includes at least one data transfer task ordered by priority.
[0013] Understandably, priority queues can define priorities based on factors such as task time and importance, making task execution order more flexible and reasonable.
[0014] In one possible implementation, the first processor core sends a second message to the second processor core, the second message indicating that the data transfer task was successfully executed.
[0015] It is understandable that after the first processor core completes the data transfer task, it sends a second message to the second processor core that executes the computing task so that the second processor core can be informed in a timely manner that the data transfer task is completed. In this way, the second processor core can execute the computing task in a timely manner based on the target data.
[0016] In one possible implementation, the first processor core sends a third message to the second processor core, the third message indicating that the data transfer task has failed.
[0017] It is understandable that if the first processor core sends a third message to the second processor core that is executing the computing task after the data transfer task fails, the second processor core can be informed of the data transfer task failure in a timely manner, so that the second processor core can adjust the computing task in a timely manner.
[0018] In one possible implementation, when the first processor core sends a third message to the second processor core, the first processor core can receive the first message that the second processor core sends again.
[0019] Understandably, the first processor core sends a third message to the second processor core, indicating that the data transfer task executed by the first processor core has failed. Therefore, the first processor core can receive the first message sent again by the second processor core to re-execute the data transfer task until it succeeds.
[0020] In one possible implementation, the first message can be an inter-thread communication message or an inter-processor communication message.
[0021] The inter-thread communication messages mentioned above include, but are not limited to, thread (pthread) messages or parallel algorithm (openMP) messages.
[0022] The aforementioned inter-processor communication messages include, but are not limited to, peripheral component interconnect express (PCIE) messages, Ethernet messages, NVLink messages, or Infiniband (IB) messages.
[0023] In one possible implementation, the clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
[0024] It is understood that the clock frequency of a processor core is positively correlated with its computing performance, while the clock frequency of a processor core is negatively correlated with its energy consumption (power). The solution provided in this application, on the one hand, improves computing efficiency by using a second processor core with stronger computing performance to perform computing tasks; on the other hand, it reduces the energy consumption of data transfer tasks by using a first processor core with weaker computing performance to perform data transfer tasks.
[0025] In one possible implementation, the first processor core and the second processor core are located in the same processor.
[0026] For example, both the first processor core and the second processor core are located in the first processor.
[0027] In another possible implementation, the first processor core and the second processor core are not located on the same processor.
[0028] For example, the first processor core mentioned above is located in the first processor, and the second processor core mentioned above is located in the second processor core.
[0029] In one possible implementation, the second processor core described above can perform computational tasks to obtain the target data.
[0030] In one possible implementation, the second processor core performs computational tasks based on the target data.
[0031] Secondly, embodiments of this application provide another communication method, which includes: a second processor core sending a first message to a first processor core, the first message including a first address, a second address and the size of target data, the first message being used to instruct the execution of a data transfer task, the data transfer task being to transfer the target data from the first address to the second address or to transfer the target data from the second address to the first address.
[0032] In one possible implementation, the target data is the data obtained by the second processor core performing the computing task or the data required by the second processor core to perform the computing task.
[0033] In one possible implementation, the second processor core receives a second message sent by the first processor core, the second message indicating that the data transfer task was successfully executed.
[0034] In one possible implementation, the second processor core receives a third message sent by the first processor core, the third message indicating that the data transfer task has failed.
[0035] In one possible implementation, if the second processor core receives a third message sent by the first processor core, the second processor core may send the first message back to the first processor core.
[0036] In one possible implementation, the first message mentioned above is an inter-thread communication message or an inter-processor communication message.
[0037] In one possible implementation, the clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
[0038] In one possible implementation, the first processor core and the second processor core are located in the same processor.
[0039] For example, both the first processor core and the second processor core are located in the first processor.
[0040] In another possible implementation, the first processor core and the second processor core are not located on the same processor.
[0041] For example, the first processor core mentioned above is located in the first processor, and the second processor core mentioned above is located in the second processor core.
[0042] Thirdly, embodiments of this application provide a communication device. This device may be a first processor core, a module (e.g., a chip or chip system) applied to the first processor core, or a logic node, logic module, or software capable of implementing all or part of the functions of the first processor core. The device includes a first transceiver unit and a first processing unit. The first transceiver unit is used to perform the operations related to receiving and / or transmitting in the methods described in the first aspect and any possible design of the first aspect. The first processing unit is used to perform other operations besides the operations related to receiving and / or transmitting in the methods described in the first aspect and any possible design of the first aspect.
[0043] In one possible implementation, the first transceiver unit is configured to: receive a first message sent by the second processor core, the first message including a first address, a second address, and the size of target data, the first message being used to instruct the execution of a data transfer task, the data transfer task being to transfer the target data from the first address to the second address or from the second address to the first address.
[0044] In one possible implementation, the first processing unit is used to: execute the data transfer task in response to the first message.
[0045] In one possible implementation, the target data is the data obtained by the second processor core performing the computing task or the data required by the second processor core to perform the computing task.
[0046] In one possible implementation, the first processor core includes a task queue, which includes at least one data transfer task.
[0047] In one possible implementation, the first processing unit is specifically used to: respond to the first message when the data transfer task indicated by the first message is the first data transfer task in the task queue.
[0048] In one possible implementation, the task queue described above includes at least one data transfer task ordered by priority.
[0049] In one possible implementation, the first transceiver unit is further configured to: send a second message or a third message to the second processor core, wherein the second message indicates that the data transfer task was executed successfully, and the third message indicates that the data transfer task failed.
[0050] In one possible implementation, the first transceiver unit is further configured to: receive the first message resent by the second processor core when a third message is sent to the second processor core.
[0051] In one possible implementation, the first message mentioned above is an inter-thread communication message or an inter-processor communication message.
[0052] In one possible implementation, the clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
[0053] In one possible implementation, the first processor core and the second processor core are located in the same processor.
[0054] In another possible implementation, the first processor core and the second processor core described above are located in different processors.
[0055] Fourthly, embodiments of this application provide a communication device. This device may be a second processor core, a module (e.g., a chip or chip system) applied to the second processor core, or a logic node, logic module, or software capable of implementing all or part of the functions of the second processor core. The device includes a second transceiver unit and a second processing unit. The second transceiver unit is used to perform the receiving and / or transmitting operations related to the methods described in the second aspect and any possible design of the second aspect. The second processing unit is used to perform other operations besides the receiving and / or transmitting operations described in the methods described in the second aspect and any possible design of the second aspect.
[0056] In one possible implementation, the second transceiver unit is configured to: send a first message to the first processor core, the first message including a first address, a second address and the size of the target data, the first message being used to instruct the execution of a data transfer task, the data transfer task being to transfer the target data from the first address to the second address or to transfer the target data from the second address to the first address.
[0057] In one possible implementation, the target data is the data obtained by the second processor core performing the computing task or the data required by the second processor core to perform the computing task.
[0058] In one possible implementation, the second transceiver unit is further configured to: receive a second message or a third message sent by the first processor core, wherein the second message indicates that the data transfer task was executed successfully, and the third message indicates that the data transfer task failed.
[0059] In one possible implementation, the second transceiver unit is further configured to: upon receiving a third message sent by the first processor core, resend the first message to the first processor core.
[0060] In one possible implementation, the first message mentioned above is an inter-thread communication message or an inter-processor communication message.
[0061] In one possible implementation, the clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
[0062] In one possible implementation, the first processor core and the second processor core are located in the same processor.
[0063] In another possible implementation, the first processor core and the second processor core described above are located in different processors.
[0064] Fifthly, embodiments of this application also provide a communication device, the device comprising: at least one processor, which, when the at least one processor executes program code or instructions, implements the method described in the first aspect or any possible implementation thereof.
[0065] Optionally, the device may further include at least one memory for storing the program code or instructions.
[0066] Sixthly, embodiments of this application also provide a chip, including: an input interface, an output interface, at least one processor, and at least one memory. The at least one processor is used to execute code in the at least one memory, and when the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation thereof.
[0067] Alternatively, the chip described above can also be an integrated circuit.
[0068] In a seventh aspect, embodiments of this application also provide a computer-readable storage medium for storing a computer program that includes methods for implementing the first aspect or any possible implementation thereof.
[0069] Eighthly, embodiments of this application also provide a computer program product containing instructions that, when run on a computer, cause the computer to implement the method described in the first aspect or any possible implementation thereof.
[0070] In a ninth aspect, embodiments of this application also provide a processor, the processor including a first processor core and a second processor core, the first processor core being used to instruct the method described in the first aspect or any possible implementation thereof, and the second processor core being used to execute the method described in the second aspect or any possible implementation thereof.
[0071] In a tenth aspect, embodiments of this application also provide an electronic device, the electronic device including a first processor and a second processor, the first processor including a first processor core, the second processor including a second processor core, the first processor core being used to instruct the method described in the first aspect or any possible implementation thereof, and the second processor core being used to execute the method described in the second aspect or any possible implementation thereof.
[0072] The communication device, computer storage medium, computer program product, and chip provided in this embodiment are all used to execute the communication method provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the communication method provided above, and will not be repeated here. Attached Figure Description
[0073] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0074] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0075] Figure 2 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;
[0076] Figure 3 A flowchart illustrating a communication method provided in an embodiment of this application;
[0077] Figure 4 A schematic diagram illustrating a data transfer task execution flow provided in an embodiment of this application;
[0078] Figure 5 A flowchart illustrating another communication method provided in an embodiment of this application;
[0079] Figure 6 A flowchart illustrating yet another communication method provided in an embodiment of this application;
[0080] Figure 7 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;
[0081] Figure 8 This is a schematic diagram of another communication device provided in an embodiment of this application;
[0082] Figure 9 A schematic diagram of a processor provided in an embodiment of this application;
[0083] Figure 10 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. Detailed Implementation
[0084] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.
[0085] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0086] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.
[0087] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0088] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.
[0089] The technical solutions provided in the embodiments of this application can be applied to electronic devices.
[0090] Figure 1 A schematic diagram of one possible, non-limiting electronic device described above is shown. (e.g.) Figure 1 As shown, the electronic device 10 includes a processor 100 and memory 200. The processor 100 includes multiple processor cores. For example, the processor 100 may include M processor cores, where M is a positive integer.
[0091] Electronic device 10 can be a server, computer, laptop computer, mobile phone, tablet computer, mouse, remote control, stylus, set-top box, router, camera, screen, smart screen, wireless data card, personal digital assistant computer (PDA), smartwatch, smart bracelet, wireless headset, electronic whiteboard, virtual reality (VR) terminal, augmented reality (AR) terminal, smart home device (e.g., refrigerator, television, air conditioner, washing machine, rice cooker, table lamp, electricity meter, etc.), smart robot, robotic arm, workshop equipment, or other electronic device.
[0092] Processor 100 can be a heterogeneous multi-core processor, central processing unit (CPU), graphics processing unit (GPU), application processor (AP), modem processor, image signal processor (ISP), video codec, digital signal processor (DSP), baseband processor, or neural network processing unit (NPU).
[0093] In one possible implementation, the processor core mentioned above includes at least one of the following: CPU core, GPU core, AP core, modem processor core, ISP core, video codec core, DSP core, baseband processor core, and NPU core.
[0094] Memory 200 may include double data rate synchronous dynamic random access memory (DDR) (such as DDR3, DDR4, DDR5, etc.), low power DDR (LPDDR) (such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, etc.), graphics DDR (GDDR) (such as GDDR5, GDDR5X or GDDR6), synchronous dynamic random access memory (SDRAM), or high bandwidth memory (HBM).
[0095] In one possible implementation, memory 200 may include a first memory and a second memory. The bandwidth of the first memory is greater than the bandwidth of the second memory.
[0096] For example, memory 200 can include a first memory and a second memory. The first memory is HMB2 memory with a bandwidth of 256GB / s, and the second memory is DDR4 memory with a bandwidth of 23GB / s. It can be seen that the bandwidth of the first memory and the second memory can differ by a factor of 10.
[0097] Understandable, Figure 1 The structures shown do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
[0098] Combination Figure 1 ,like Figure 2 As shown, in one possible implementation, the electronic device may also include a processor 101.
[0099] In one possible implementation, processor 100 and processor 101 can be processors of the same type.
[0100] For example, processor 100 and processor 101 can both be CPUs.
[0101] In one possible implementation, processor 100 and processor 101 can be different types of processors.
[0102] For example, processor 100 is a CPU, and processor 101 is a GPU.
[0103] Understandable, Figure 2 The structures shown do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
[0104] In one possible implementation, the electronic device 10 may also include more processors.
[0105] For example, the electronic device may also include processor 102, processor 103, ..., processor N.
[0106] Figure 3 This application illustrates a communication method provided by an embodiment of the present application. This method can be executed by a first processor core and a second processor core, such as... Figure 3As shown, the method includes:
[0107] S301, the second processor core sends the first message to the first processor core.
[0108] Accordingly, the first processor core receives the first message sent by the second processor core.
[0109] For example, when the first processor core and the second processor core are located on the same processor, the second processor core can send a first message to the first processor core via inter-thread communication. Correspondingly, the first processor core can receive the first message sent by the second processor core via inter-thread communication. The inter-thread communication methods mentioned above include, but are not limited to, the pthread communication protocol or the OpenMP communication protocol.
[0110] For example, when the first processor core and the second processor core are located on the same processor, the worker thread of the second processor core can send a first message to the transport thread of the first processor core via the pthread communication protocol. Correspondingly, the worker thread of the first processor core can receive the first message sent by the transport thread of the second processor core via the pthread communication protocol.
[0111] It is understandable that when the first and second processor cores reside on the same processor, the second processor core needs to send a first message to the first processor core via inter-thread communication. Therefore, the first message can be an inter-thread communication message. This inter-thread communication message includes, but is not limited to, pthread messages or OpenMP messages.
[0112] As another example, when the first processor core and the second processor core are located on different processors, the second processor core can send a first message to the first processor core via inter-processor communication. Correspondingly, the first processor core can receive the first message sent by the second processor core via processor communication. These processor communication methods include, but are not limited to, PCIe communication protocol, Ethernet communication protocol, NVLink communication protocol, or IB communication protocol.
[0113] For example, when the first processor core and the second processor core are located on different processors, the worker thread of the second processor core can send a first message to the transport thread of the first processor core via the PCIe communication protocol. Correspondingly, the worker thread of the first processor core can receive the first message sent by the transport thread of the second processor core via PCIe.
[0114] It is understandable that when the first processor core and the second processor core are located on different processors, the second processor core needs to send a first message to the first processor core via inter-processor communication. Therefore, the first message can be an inter-processor communication message. This inter-processor communication message includes, but is not limited to, PCIe messages, Ethernet messages, NVLink messages, or IB messages.
[0115] In one possible implementation, the first message mentioned above may include detach semantics and fulfillment semantics.
[0116] Understandably, enhancing the "separation" semantic functionality essentially enables the distribution of transferred data without blocking existing computation tasks, ensuring that computation threads continue to perform calculations after the distribution is complete. The "completion" and "separation" semantics work together to ensure the execution order and correctness of the same chunk transmission and computation tasks, and to avoid data races and consistency issues.
[0117] The first message includes a first address, a second address, and the size of the target data. The first message is used to instruct the execution of a data transfer task, which is to transfer the target data from the first address to the second address or from the second address to the first address.
[0118] For example, the first processor core can be a processor core for data transfer tasks, and the second processor core can be a processor core for performing computational tasks. The first address can be the address of the target data in the processor, and the second address can be the address of the target data in memory. The address of the target data in the processor can be the address of the target data in the processor's cache.
[0119] In one possible implementation, the target data is the data obtained by the second processor core performing the computing task or the data required by the second processor core to perform the computing task.
[0120] When the target data is the data obtained by performing a computational task on the second processor core, the data moving task is to move the target data from the first address to the second address, for example, from the cache corresponding to the second processor to memory.
[0121] When the target data is the data required by the second processor core to perform the computing task, the data moving task is to move the target data from the second address to the first address, for example, from memory to the cache corresponding to the second processor.
[0122] The following describes the computational tasks performed by the second processor core.
[0123] In one possible implementation, the computational tasks performed by the second processor core may include finite element analysis (FEA), deoxyribonucleic acid (DNA) analysis, computer-aided design, computational fluid dynamics (CFD), or other computational tasks.
[0124] Finite element analysis (FEM) replaces a complex problem with a simpler one before solving it. It treats the solution domain as consisting of many small, interconnected subdomains called finite elements. For each element, a suitable (simpler) approximate solution is assumed, and then the overall conditions satisfying the domain (such as the equilibrium conditions of the structure) are derived to obtain the solution. Because the real-world problem is replaced by a simpler one, this solution is not an exact solution but an approximate one. Since most real-world problems are difficult to solve exactly, and finite element analysis offers high computational accuracy and can adapt to various complex shapes, it has become an effective engineering analysis tool.
[0125] Computational fluid dynamics (CFD) is a computer-aided engineering tool used to simulate the flow of fluids such as air, water, or any other fluid in a system and to understand the impact of fluid flow on the surrounding environment.
[0126] In some scenarios, the second processor core can perform a portion of the data transfer tasks. For example, in scenarios where the data transfer task involves both first and second memory, the second processor core can perform the data transfer tasks involving the first memory.
[0127] As mentioned earlier, the bandwidth of the first memory is greater than that of the second memory. For example, the first memory could be an HMB2 memory with a bandwidth of 256GB / s, and the second memory could be a DDR4 memory with a bandwidth of 23GB / s.
[0128] In one possible implementation, the second processor core can perform a data transfer task when the second address is an address of the first memory (i.e., when target data needs to be written to or read from the first memory); the second processor core can send a first message to the transfer thread of the first processor core when the second address is an address of the second memory (i.e., when target data needs to be written to or read from the second memory).
[0129] It is understandable that the bandwidth of the first memory is greater than that of the second memory. The second processor core, which performs the computation task, will not consume too much computing power when performing data transfer tasks involving the first memory. However, the second processor core, which performs the computation task, will consume more computing power when performing data transfer tasks involving the second memory. Therefore, the data transfer tasks involving the second memory are distributed to the first processor core. The second processor core itself does not perform data transfer tasks involving the second memory, thereby avoiding the second processor core from consuming too much computing power and reducing its computing efficiency, thus improving the computing efficiency of the processor core.
[0130] In one possible implementation, the clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
[0131] It is understood that the clock frequency of a processor core is positively correlated with its computing performance, while the clock frequency of a processor core is negatively correlated with its energy consumption (power). The solution provided in this application, on the one hand, improves computing efficiency by using a second processor core with stronger computing performance to perform computing tasks; on the other hand, it reduces the energy consumption of data transfer tasks by using a first processor core with weaker computing performance to perform data transfer tasks.
[0132] In one possible implementation, the first processor core and the second processor core described above are processor cores of the same type.
[0133] For example, both the first processor core and the second processor core mentioned above are CPU cores.
[0134] It is understandable that processor cores of the same type can execute the same type of tasks, so migrating data transfer tasks to processor cores of the same type will not cause task compatibility issues.
[0135] In another possible implementation, the first processor core and the second processor core described above are processor cores of different types.
[0136] For example, the first processor core mentioned above is a CPU core, and the second processor core mentioned above is a GPU core.
[0137] It's understandable that different types of processor cores have different application scenarios; some types of processor cores have strong computational performance, while others have strong data read / write performance. Therefore, using the processor cores with the strongest computational performance from among multiple different types of processor cores can improve computational efficiency. Similarly, using the processor cores with the strongest data read / write performance from among multiple different types of processor cores can improve the efficiency of data transfer tasks.
[0138] It is understood that in the solution provided in this application embodiment, the data transfer task is executed in the thread started by the first processor core (i.e., the transfer thread), and the data transfer task is not executed in the worker thread of the second processor core responsible for executing the computing task. The worker thread is only responsible for sending the data transfer task to the transfer thread for execution, and the overhead is very low and can be ignored (for example, the sending of the data transfer task can be completed within a few processors, and the time taken for sending the data transfer task is on the nanosecond level).
[0139] S302, the first processor core responds to the first message and executes the data transfer task.
[0140] For example, in response to the first message mentioned above, the data transfer thread of the first processor core performs the data transfer task mentioned above.
[0141] For example, in response to the first message mentioned above, the transport thread of the first processor core can transport the target data from the first address to the second address mentioned above.
[0142] For example, in response to the first message mentioned above, the transport thread of the first processor core can transport the target data from the second address to the first address.
[0143] In one possible implementation, the first processor core includes a task queue, which includes at least one data transfer task.
[0144] In one possible implementation, if the data transfer task indicated by the first message is the first data transfer task in the task queue, the first processor core may respond to the first message and execute the data transfer task.
[0145] For example, after receiving the first message, the data transfer thread of the first processor core can put the data transfer task indicated by the first message into the task queue. If the data transfer task indicated by the first message is the first task in the task queue, the data transfer task is executed based on the first message.
[0146] The solution provided in this application embodiment can first place the data transfer task indicated by the first message into the task queue, and then retrieve the data transfer task indicated by the first message from the task queue for processing. This can avoid data transfer task loss and also balance the processing speed of data transfer tasks.
[0147] In one possible implementation, the task queue described above can be a first-in, first-out (FIFO) queue.
[0148] The following section provides a detailed description of the task execution process of the first processor core 1 and the second processor core 2.
[0149] like Figure 4 As shown, worker thread 1, worker thread 2, worker thread 3, and worker thread 4 are threads running on the second processor core 1. The transport thread is a thread running on the first processor core 2.
[0150] Worker threads 1, 2, 3, and 4 can issue data transfer tasks by sending a first message to the transfer thread of the first processor core when a data transfer task needs to be performed. For example, the transfer thread of the first processor core executes the data transfer tasks indicated by the first message in order from the first-in-first-out queue according to the sending time of the first message.
[0151] For example, when the worker thread 1 of the second processor core 1 needs to perform a data transfer task 1 to move data 1 from the first address 1 in memory to the second address 1 in the processor, it can send a first message 1 to the transfer thread of the first processor core to send the data transfer task 1.
[0152] When the worker thread 2 of the second processor core 2 needs to perform a data transfer task 2 to move data 2 from the first address 2 in memory to the second address 2 in the processor, it can send a first message 2 to the transfer thread of the first processor core to send the data transfer task 2.
[0153] When the worker thread 3 of the second processor core 3 needs to perform a data transfer task 3 to move data 3 from the second address 3 in the processor to the first address 3 in memory, it can send a first message 3 to the transfer thread of the first processor core to send the data transfer task 3.
[0154] When the worker thread 4 of the second processor core 4 needs to perform a data transfer task 4 to move data 4 from the second address 4 in the processor to the first address 4 in memory, it can send a first message 4 to the transfer thread of the first processor core to send the data transfer task 4.
[0155] When the worker thread 1 of the second processor core 1 needs to perform a data transfer task 5 to move data 5 from the first address 5 in memory to the second address 5 in the processor, it can send a first message 5 to the transfer thread of the first processor core to send the data transfer task 5.
[0156] When the worker thread 2 of the second processor core 2 needs to perform a data transfer task 6 to move data 6 from the first address 5 in memory to the second address 6 in the processor, it can send a first message 6 to the transfer thread of the first processor core to send the data transfer task 6.
[0157] For example, the data transfer thread of the first processor core receives first message 1, first message 2, first message 3, first message 4, first message 5, and first message 6 sequentially, and executes the data transfer tasks indicated by the first message in order from the first-in-first-out queue according to the sending time of the first message. The process of the data transfer thread of the first processor core executing the data transfer tasks is as follows.
[0158] The first processor core's transport thread executes transport task 1, moving data 1 from the first address 1 in memory to the second address 1 in the processor;
[0159] After the first processor core's transport thread completes transport task 1, it executes transport task 2 to move data 2 from the first address 2 in memory to the second address 2 in the processor.
[0160] After the first processor core's transport thread completes transport task 2, it executes transport task 3 to transport data 3 from the second address 3 in the processor to the first address 3 in memory;
[0161] After the first processor core's transport thread completes transport task 3, it executes transport task 4 to move data 4 from the second address 4 in the processor to the first address 4 in memory.
[0162] After the first processor core's transport thread completes transport task 4, it executes transport task 5 to move data 5 from the first address 5 in memory to the second address 5 in the processor.
[0163] After the first processor core's transport thread completes transport task 5, it executes transport task 6 to move data 6 from the first address 5 in memory to the second address 6 in the processor.
[0164] In another possible implementation, the task queue described above can be a priority queue. This task queue includes at least one data transfer task ordered by priority.
[0165] In one possible implementation, the priority of a data transfer task can be determined based on its priority information. This priority information includes at least one of task priority, processor core priority, or first message sending time. The task priority or processor core priority can be pre-configured.
[0166] The task priorities mentioned above can be determined by factors such as task type and the time when the target data for the task is used. Generally speaking, read tasks (i.e., reading target data from memory) have higher priority than write tasks (i.e., writing target data to memory). The earlier the target data is used, the higher the task priority.
[0167] Understandably, priority queues can define priorities based on factors such as task time and importance, making task execution order more flexible and reasonable.
[0168] In one possible implementation, the first processor core can determine whether the data transfer task has failed based on the function's return value.
[0169] For example, the first processor core can determine that the data transfer task has been successfully executed if the function return value of the data transfer task is a first value; the second processor core can determine that the data transfer task has failed if the function return value of the data transfer task is a second value.
[0170] For example, the first processor core can determine that the data transfer task has been successfully executed if the function return value of the data transfer task is 0; the first processor core can determine that the data transfer task has been successfully executed if the function return value of the data transfer task is -1 or 1.
[0171] Understandably, the function return value of a task can reflect the execution status of the task relatively accurately. Therefore, the first processor core can determine whether the data transfer task has failed based on the function return value.
[0172] In one possible implementation, the first processor core can send a second message to the second processor core. Correspondingly, the second processor core receives the second message sent by the first processor core. This second message indicates that the data transfer task was successfully executed.
[0173] For example, the first processor core can send a second message to the second processor core upon successful execution of the data transfer task. Accordingly, the second processor core receives the second message sent by the first processor core.
[0174] For example, when the first processor core and the second processor core are located on the same processor, the first processor core can send a second message to the second processor core via inter-thread communication. Correspondingly, the second processor core can receive the second message sent by the first processor core via inter-thread communication.
[0175] It is understandable that when the first processor core and the second processor core are located on the same processor, the first processor core needs to send a second message to the second processor core through inter-thread communication. Therefore, the second message can be an inter-thread communication message.
[0176] As another example, when the first processor core and the second processor core are located on different processors, the first processor core can send a second message to the second processor core via inter-processor communication. Correspondingly, the second processor core can receive the second message sent by the first processor core via inter-processor communication.
[0177] It is understandable that when the first processor core and the second processor core are located on different processors, the first processor core needs to send a second message to the second processor core via inter-processor communication. Therefore, the second message can be an inter-processor communication message.
[0178] In one possible implementation, the first processor core can send a third message to the second processor core. Correspondingly, the second processor core receives the third message sent by the first processor core. This third message indicates that the data transfer task has failed.
[0179] For example, the data transfer thread of the first processor core can send a third message to the worker thread of the second processor core if the data transfer task fails. Accordingly, the second processor core receives the third message sent by the first processor core.
[0180] For example, when the first processor core and the second processor core are located on the same processor, the first processor core can send a third message to the second processor core via inter-thread communication. Correspondingly, the second processor core can receive the third message sent by the first processor core via inter-thread communication.
[0181] It is understandable that when the first and second processor cores reside on the same processor, the first processor core needs to send a third message to the second processor core via inter-thread communication. Therefore, the third message can be an inter-thread communication message.
[0182] As another example, when the first processor core and the second processor core are located on different processors, the first processor core can send a third message to the second processor core via inter-processor communication. Correspondingly, the second processor core can receive the third message sent by the first processor core via inter-processor communication.
[0183] It is understandable that when the first processor core and the second processor core are located on different processors, the first processor core needs to send a third message to the second processor core via inter-processor communication. Therefore, the third message can be an inter-processor communication message.
[0184] In one possible implementation, when the first processor core sends a third message to the second processor core (i.e., the second processor core receives the third message sent by the first processor core), the second processor core can resend the first message to the first processor core. Correspondingly, the first processor core can receive the resent first message from the second processor core.
[0185] For example, after data transfer task 1 fails, the first processor core sends a third message to the second processor core instructing data transfer task 1 to be executed again. Upon receiving the third message, the second processor core can then send a first message back to the first processor core, instructing it to re-execute data transfer task 1. Upon receiving the second processor core's re-sent first message, the first processor core can then re-execute data transfer task 1.
[0186] Understandably, when the second processor core receives the third message sent by the first processor core, it indicates that the data transfer task to be executed by the second processor core has failed. Therefore, the second processor core can send the first message again to make the first processor core re-execute the data transfer task until the data transfer task is successful.
[0187] The solution provided in this application embodiment can achieve true hiding of computation and data transfer. It enables control over the dependencies between multiple concurrent tasks and manages asynchronous data transfer tasks to support mutual masking of intensive computational data transfer, fully utilizing hardware resources and improving system efficiency.
[0188] The solution provided in this application embodiment includes a first processor core for performing data transfer tasks. When a second processor core for performing computation tasks generates a data transfer task, it can send a message to instruct the first processor core to perform the data transfer task. The second processor core itself does not perform the data transfer task, thereby avoiding a reduction in computational efficiency due to the second processor core performing the data transfer task, thus improving the computational efficiency of the processor core.
[0189] Figure 5 This application illustrates another communication method provided by an embodiment of the present application, which can be executed by a first processor core, such as... Figure 5 As shown, the method includes:
[0190] S501, the first processor core receives the first message sent by the second processor core.
[0191] S502, the first processor core responds to the first message and executes the data transfer task.
[0192] The specific implementation methods of S501 to S502 can be referred to S301 to S302 above, and will not be repeated here.
[0193] Figure 6 This application illustrates yet another communication method provided by an embodiment of the present application, which can be executed by a second processor core, such as... Figure 6 As shown, the method includes:
[0194] S601, the second processor core sends the first message to the first processor core.
[0195] The specific implementation of S601 can be found in S301 above, and will not be repeated here.
[0196] When dividing each function into modules according to its corresponding function. Figure 7 The diagram illustrates another possible configuration of the communication device involved in the above embodiments. This device can be a first processor core, a module (e.g., a chip or chip system) applied to the first processor core, or a logic node, logic module, or software capable of implementing all or part of the functions of the first processor core. Figure 7 As shown, the communication device 700 may include a first transceiver unit 701 and a first processing unit 702.
[0197] The first transceiver unit 701 is used to perform operations related to receiving and / or sending in any communication method provided in the embodiments of this application.
[0198] The first processing unit 702 is used to perform other operations besides those related to receiving and / or sending in any communication method provided in the embodiments of this application.
[0199] In one possible implementation, the first transceiver unit 701 is configured to: receive a first message sent by the second processor core, the first message including a first address, a second address and the size of the target data, the first message being used to instruct the execution of a data transfer task, the data transfer task being to transfer the target data from the first address to the second address or to transfer the target data from the second address to the first address.
[0200] In one possible implementation, the first processing unit 702 is used to: perform the data transfer task in response to the first message.
[0201] In one possible implementation, the target data is the data obtained by the second processor core performing the computing task or the data required by the second processor core to perform the computing task.
[0202] In one possible implementation, the first processor core includes a task queue, which includes at least one data transfer task.
[0203] In one possible implementation, the first processing unit 702 is specifically used to: respond to the first message when the data transfer task indicated by the first message is the first data transfer task in the task queue.
[0204] In one possible implementation, the task queue described above includes at least one data transfer task ordered by priority.
[0205] In one possible implementation, the first transceiver unit 701 is further configured to: send a second message or a third message to the second processor core, wherein the second message is used to indicate that the data transfer task was executed successfully, and the third message is used to indicate that the data transfer task failed.
[0206] In one possible implementation, the first transceiver unit 701 is further configured to: receive the first message resent by the second processor core when a third message is sent to the second processor core.
[0207] In one possible implementation, the first message mentioned above is an inter-thread communication message or an inter-processor communication message.
[0208] In one possible implementation, the clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
[0209] In one possible implementation, the first processor core and the second processor core are located in the same processor.
[0210] When dividing each function into modules according to its corresponding function. Figure 8 A possible configuration diagram of the communication device involved in the above embodiments is shown. The device may be a second processor core, or a module (such as a chip or chip system) applied to the second processor core, or a logic node, logic module or software that can implement all or part of the functions of the second processor core. The device includes: a second transceiver unit 801 and a second processing unit 802.
[0211] The second transceiver unit 801 is used to perform operations related to receiving and / or sending in any of the communication methods provided in the embodiments of this application.
[0212] The second processing unit 802 is used to perform other operations besides those related to receiving and / or sending in any of the communication methods provided in the embodiments of this application.
[0213] In one possible implementation, the second transceiver unit 801 is configured to: send a first message to the first processor core, the first message including a first address, a second address and the size of the target data, the first message being used to instruct the execution of a data transfer task, the data transfer task being to transfer the target data from the first address to the second address or to transfer the target data from the second address to the first address.
[0214] In one possible implementation, the target data is the data obtained by the second processor core performing the computing task or the data required by the second processor core to perform the computing task.
[0215] In one possible implementation, the second transceiver unit 801 is further configured to: receive a second message or a third message sent by the first processor core, wherein the second message is used to indicate that the data transfer task was executed successfully, and the third message is used to indicate that the data transfer task failed.
[0216] In one possible implementation, the second transceiver unit 801 is further configured to: upon receiving a third message sent by the first processor core, resend the first message to the first processor core.
[0217] In one possible implementation, the first message mentioned above is an inter-thread communication message or an inter-processor communication message.
[0218] In one possible implementation, the clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
[0219] In one possible implementation, the first processor core and the second processor core are located in the same processor.
[0220] In another possible implementation, the first processor core and the second processor core described above are located in different processors.
[0221] like Figure 9 As shown in the figure, this application embodiment also provides a processor 900, which includes a first processor core 901 and a second processor core 901.
[0222] The first processor core, 901, is used for execution. Figure 5 The communication method shown or Figure 3 The communication method shown is the part of the communication method executed by the first processor core.
[0223] The second processor core, 902, is used to execute... Figure 6 The communication method shown or Figure 3 The communication method shown is the part of the communication method executed by the second processor core.
[0224] like Figure 10 As shown in the figure, this application embodiment also provides an electronic device 1000, which includes a first processor 1100 and a second processor 1200. The first processor 1100 includes a first processor core 1101, and the second processor 1200 includes a second processor core 1201.
[0225] The first processor core, 1101, is used to execute... Figure 5 The communication method shown or Figure 3 The communication method shown is the part of the communication method executed by the first processor core.
[0226] The second processor core, 1201, is used to execute... Figure 6 The communication method shown or Figure 3 The communication method shown is the part of the communication method executed by the second processor core.
[0227] This application also provides a communication device, which includes at least one processor. When the at least one processor executes program code or instructions, it implements the aforementioned method steps to achieve the communication method in the above embodiments.
[0228] Optionally, the device may further include at least one memory for storing the program code or instructions.
[0229] This application also provides a computer storage medium storing computer instructions. When the computer instructions are executed on a communication device, the communication device performs the aforementioned related method steps to implement the communication method in the above embodiments.
[0230] This application also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the communication method described in the above embodiments.
[0231] It should be understood that in various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application.
[0232] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.
[0233] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the above method embodiments, and will not be repeated here.
[0234] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0235] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0236] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0237] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this application, essentially, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0238] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.
Claims
1. A communication method, characterized in that, include: The first processor core receives a first message sent by the second processor core. The first message includes a first address, a second address, and the size of the target data. The first message is used to instruct the execution of a data transfer task, which is to move the target data from the first address to the second address or move the target data from the second address to the first address. In response to the first message, the first processor core executes the data transfer task.
2. The method according to claim 1, characterized in that, The target data is the data obtained by the second processor core in performing the computing task or the data required by the second processor core in performing the computing task.
3. The method according to claim 1 or 2, characterized in that, The method further includes: The first processor core sends a second message or a third message to the second processor core. The second message indicates that the data transfer task was executed successfully, and the third message indicates that the data transfer task failed. When the first processor core sends the third message to the second processor core, the first processor core receives the first message again sent by the second processor core.
4. The method according to any one of claims 1 to 3, characterized in that, The clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
5. The method according to any one of claims 1 to 4, characterized in that, The first processor core and the second processor core are located in the same processor or different processors.
6. A communication method, characterized in that, include: The second processor core sends a first message to the first processor core. The first message includes a first address, a second address, and the size of the target data. The first message is used to instruct the execution of a data transfer task, which is to move the target data from the first address to the second address or move the target data from the second address to the first address.
7. The method according to claim 6, characterized in that, The target data is the data obtained by the second processor core in performing the computing task or the data required by the second processor core in performing the computing task.
8. The method according to claim 6 or 7, characterized in that, The method further includes: The second processor core receives a second message or a third message sent by the first processor core. The second message indicates that the data transfer task was executed successfully, and the third message indicates that the data transfer task failed. If the second processor core receives the third message sent by the first processor core, the second processor core sends the first message to the first processor core again.
9. The method according to any one of claims 6 to 8, characterized in that, The clock frequency of the first processor core is less than or equal to the clock frequency of the second processor core.
10. The method according to any one of claims 6 to 9, characterized in that, The first processor core and the second processor core are located in the same processor or different processors.
11. A communication device, characterized in that, include: First transceiver unit and first processing unit; The first transceiver unit is configured to perform the receiving and / or sending related operations in the method of any one of claims 1 to 5; The first processing unit is configured to perform other operations in the method of any one of claims 1 to 5, other than the receiving and / or sending related operations.
12. A communication device, characterized in that, include: Second transceiver unit and second processing unit; The second transceiver unit is configured to perform the receiving and / or transmitting related operations in the method of any one of claims 6 to 10; The second processing unit is configured to perform other operations in the method of any one of claims 6 to 10, other than the receiving and / or sending related operations.
13. A communication device comprising at least one processor and a memory, characterized in that, The at least one processor executes a program or instructions stored in a memory to cause the communication device to implement the method of any one of claims 1 to 10.
14. A computer program product, the computer program product comprising instructions, characterized in that, When the instructions are executed on a computer or processor, the computer or processor causes the computer or processor to perform the method of any one of claims 1 to 10.
15. A processor, characterized in that, The processor includes a first processor core and a second processor core, wherein the first processor core is used to execute the method of any one of claims 1 to 5, and the second processor core is used to execute the method of any one of claims 6 to 10.
16. An electronic device, characterized in that, The electronic device includes a first processor and a second processor. The first processor includes a first processor core, and the second processor includes a second processor core. The first processor core is used to perform the method of any one of claims 1 to 5, and the second processor core is used to perform the method of any one of claims 6 to 10.