Data processing method, memory and equipment

Abstract

The embodiment of the invention provides a data processing method, a memory and equipment. The data processing method comprises the following steps: in response to an instruction fetching request, searching identification information corresponding to the instruction fetching request; and when the search result is incomplete hit, determining whether a copying condition is met or not. When a copying condition is met, first target data corresponding to the instruction fetching request which is not hit is obtained from the memory, first identification information corresponding to the instruction fetching request which is not hit is copied into at least two ways in the target way group, the first target data are copied into corresponding data slices in the target data slice group, and the first target data are copied into the data slices in the target data slice group; the path group comprises at least two paths, the data slice group comprises at least two data slices, and the paths in the path group are in one-to-one correspondence with the data slices in the data slice group. The target data slice group corresponds to the target path group. The method and the device are used for solving the problem that instruction fetch conflicts are easy to occur during data instruction fetch.

Description

Technical Field

[0001] This application relates to the field of computers, and more particularly to a data processing method, memory, and device. Background Technology

[0002] CPU (Central Processing Unit) cache memory is a temporary storage device located between the CPU and main memory. It has a smaller capacity than main memory but a faster data exchange rate. The data in the cache is a small portion of the data in main memory, but this small portion is what the CPU will access in the near future. When the CPU needs to retrieve data, it can directly access it from the cache, thus speeding up the read process. Therefore, adding a cache to the CPU can effectively improve data processing speed. Thus, using a combination of cache and main memory for data storage achieves both the high speed of the cache and the efficient use of the large capacity of main memory.

[0003] Therefore, it is evident that caching has a significant impact on CPU performance. To improve cache utilization and increase data processing efficiency, researchers have proposed solutions to increase instruction fetch bandwidth, for example, by using multiple data slices. However, a data slice can only respond to one request instruction. In multi-core processors, when multiple requests simultaneously point to the same data slice, conflicts occur, affecting instruction fetch efficiency and causing performance loss. Summary of the Invention

[0004] In view of this, embodiments of this application provide a data processing method, a memory, and a device to improve the problem of instruction fetching conflicts that easily occur when fetching data.

[0005] In a first aspect, embodiments of this application provide a data processing method, including:

[0006] In response to an instruction fetch request, look up the identification information corresponding to the instruction fetch request.

[0007] If the search results are not a complete match, determine whether the copying conditions are met.

[0008] When the copying conditions are met, the first target data corresponding to the missed instruction fetch request is retrieved from memory. The first identifier information corresponding to the missed instruction fetch request is copied to at least two roads in the target road group. The first target data is copied to the corresponding data slice in the target data slice group. Each road group includes at least two roads, and each data slice group includes at least two data slices. There is a one-to-one correspondence between the roads in the road group and the data slices in the data slice group. The target data slice group corresponds to the target road group.

[0009] In one implementation of the first aspect, the replication condition includes the existence of an idle road group.

[0010] In one implementation of the first aspect, when the copying condition is met, the first target data corresponding to the missed instruction fetch request is retrieved from memory, the first identification information corresponding to the missed instruction fetch request is copied to each road in the target road group, and the first target number is copied to each data slice in the target data slice group.

[0011] In one implementation of the first aspect, the replication conditions include: there are no free road groups, but there are at least two free roads, and among the at least two free roads, at least two roads are located in the same road group.

[0012] In one implementation of the first aspect, when the copying condition is met, the first target data corresponding to the requested address is retrieved from memory, and the first identifier information corresponding to the first target data is copied to the target roads in the target road group, where the target roads are the free roads in the target road group. The first target data is then copied to the target data slices in the target data slice group, where each target data slice corresponds to a target road.

[0013] One implementation of the first aspect also includes:

[0014] If the replication conditions are not met, the data is backfilled according to the data backfilling strategy.

[0015] In one implementation of the first aspect, the data backfilling strategy includes:

[0016] If there are no available road groups but there are available roads, then select the available road for backfilling.

[0017] Otherwise, if there is a road group that is already in use, select one road from the road group to replace it.

[0018] Otherwise, select one path to replace according to the replacement strategy.

[0019] One implementation of the first aspect also includes:

[0020] Clear the aging data.

[0021] Secondly, this application provides a memory, including at least one storage cell.

[0022] The storage unit includes:

[0023] At least one TAG table is required, which stores identification information. The TAG table includes several road groups, and each road group contains at least two roads.

[0024] At least one data slice group, and each data slice group comprises at least two data slices. The data slices are used to store information corresponding to the identification information in the TGA table.

[0025] The TAG table corresponds one-to-one with the data slice group. The roads in the road group correspond one-to-one with the data slices in the data slice group. The memory operates in two modes: copy-backfill mode and copy-fill mode. When the copy conditions are met, the memory initiates copy-backfill mode. In copy-backfill mode, the memory retrieves the first target data corresponding to the missed instruction fetch request from memory, copies the first identifier information corresponding to the missed instruction fetch request to at least two roads in the target road group, and copies the first target data to the corresponding data slice in the target data slice group. The target data slice group corresponds to the target road group.

[0026] Thirdly, this application provides an apparatus configured with the data processing method provided in the first aspect, and / or the apparatus includes at least one memory provided in the second aspect.

[0027] In this embodiment, when the replication condition is met, the target data and its corresponding identification information are replicated to at least two ways. That is, at least two ways simultaneously contain the same identification information, and at least two corresponding data slices store a common target data. Therefore, when at least two ways are hit, fetch conflicts can be effectively avoided. Specifically, when at least two ways are hit by a sub-fetch request, the sub-fetch request can choose any corresponding data slice for fetching, thereby avoiding fetch conflicts. Even if at least two ways are hit by at least two sub-fetch requests simultaneously, each sub-fetch request can be independently allocated a way, i.e., each sub-fetch request can be independently allocated a data slice, thereby enabling multiple sub-fetch requests to fetch in parallel, improving fetch efficiency and effectively reducing the probability of fetch request conflicts. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This diagram illustrates the instruction fetching relationships between the CPU, cache, and memory.

[0030] Figure 2 This is a schematic diagram of the cache structure;

[0031] Figure 3 This is a schematic diagram of the TAG table;

[0032] Figure 4 This is a schematic diagram of a two-level cache structure;

[0033] Figure 5 A diagram illustrating a shared cache for network processors;

[0034] Figure 6 This is a schematic diagram of a multi-cache slice structure;

[0035] Figure 7 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0036] Figure 8 A diagram showing the correspondence between TAG tables, paths, and data slices provided in the embodiments of this application;

[0037] Figure 9 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0038] Figure 10 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0039] Figure 11 This is a schematic diagram of the structure of aging data provided in an embodiment of this application;

[0040] Figure 12 A schematic diagram of a device provided in this application. Detailed Implementation

[0041] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0043] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0045] Before providing a detailed description of the embodiments of this application, the terms used or possibly used in the embodiments of this application will first be explained.

[0046] Cache has a significant impact on CPU performance, primarily due to the order in which data is exchanged between the CPU and the cache, as well as the bandwidth between the CPU and the cache. For example... Figure 1 As shown, the working principle of caching is that when the CPU needs to read data, it first searches for it in the cache. If the data is found, it is read immediately and sent to the CPU for processing. If the data is not found, it is read from memory at a relatively slower speed and sent to the CPU for processing. At the same time, the data block containing this data is loaded into the cache, so that subsequent readings of the entire data block can be performed from the cache without having to access memory again.

[0047] This reading mechanism results in a very high cache hit rate for the CPU (around 90% for most CPUs). This means that 90% of the data the CPU needs to read next is already in the cache, and only about 10% needs to be read from main memory. This significantly reduces the time the CPU spends directly reading from main memory and means that the CPU essentially doesn't need to wait when reading data. In general, the CPU reads data in the order of cache first, then main memory.

[0048] like Figure 2 As shown, the basic structure of a cache includes a TAG table and a Cache Data table. The TAG table stores tagging information corresponding to the information stored in the Cache Data table for easy addressing, while the Cache Data table stores data or instructions.

[0049] The TAG table data structure contains multiple ways, with each way corresponding to an entry in the Cache Data table. The data structure of each way is as follows: Figure 3 As shown. Here, V is the Valid flag; a V value of 1 indicates a valid way, and a V value of 0 indicates an invalid way. TAG is PC_H, where PC_H represents the high-order bits of the PC address. PC_H and PC_L together form a complete PC (i.e., PC = {PC_H, PC_L}). For easier searching, the TAG table generally also includes an index, which is PC_L, representing the low-order bits of the address. Multiple ways within an entry of the PC_L index in the TAG table are called a group. Cache Data stores user data, which can be data or instructions. Each way is fixedly mapped to an entry in Cache Data; therefore, the address of the Cache Data table is the address of the hit way.

[0050] The cache lookup process is as follows:

[0051] 1. After receiving the instruction fetch PC, a scheduling request is sent to the scheduler S. After being scheduled, an entry is obtained by reading the TAG table using PC_L as the address.

[0052] 2. Use PC_H as the tag to match the tags of the 8 Ways of the read entry. If a match is found, use the address of the matched Way as the index to read the Cache Data. If no match is found, a refill request needs to be initiated to read the PC instruction from main memory (IMEM).

[0053] 3. Read Cache Data to obtain instructions and output them.

[0054] Multi-core shared iCloud application scenarios

[0055] In the realm of general-purpose CPUs, multi-level cache structures are typically supported to improve instruction fetch efficiency. For example... Figure 4 As shown, the four CPUs support independent L1 caches, and the four L1 caches share one L2 cache. Figure 5 As shown, in the field of Network Processors (NPs), there are also scenarios where multiple NP cores share a single cache. To meet the requirement of extremely low cost, NPs do not support independent caches; instead, multiple NPs share a single cache.

[0056] like Figure 6 As shown, when multiple processor cores share a single cache, multiple slice caches are typically used to improve instruction fetch bandwidth. For example... Figure 6 The scheme shown uses four slice caches to support instruction fetch requests from four processor cores (IF_REQ0 to IF_REQ4) to improve fetch bandwidth. This allows for simultaneous fetching of instructions for all four requests and return of instructions to the processor as much as possible.

[0057] like Figure 6 As shown, assuming the Cache Data's Instruction Word (IW) contains 4 instructions, the Slice is selected via PC[3:2]. Each slice has only one receive port, so it can only receive and process one request at a time. Therefore, if two or more fetch requests simultaneously target the same Slice, a fetch conflict will occur. Once a PC fetch conflict occurs, it will affect fetch efficiency and cause performance loss.

[0058] Therefore, a solution is needed to address the instruction fetch conflict issue when multiple pointers point to the same slice, in order to improve instruction fetch efficiency.

[0059] This application provides a data processing method to improve the problem of fetch conflict when multiple requests simultaneously point to the same slice for fetching, thereby reducing the probability of fetch conflict.

[0060] like Figure 7 As shown, a data processing method includes:

[0061] S101. In response to the instruction fetch request, look up the identification information corresponding to the instruction fetch request.

[0062] The processor sends a fetch request to the cache, which receives the fetch address from the request. In this application, "cache" refers to memory used for caching. Identification information is used to identify target information in the cache. Target information is the information to be read corresponding to the fetch request; for example, target information can be information retrieved in response to the fetch request. Target information can be target data and / or target instructions.

[0063] The cache consists of a TAG table and a cache data table. The TAG table contains multiple ways, and the data structure of each way is as follows: Figure 3 As shown. Each way stores an identifier (i.e., a TAG). In one possible implementation, finding the identifier corresponding to the fetched instruction includes:

[0064] Retrieve the request address from the instruction fetch request. Based on the request address, look up the corresponding identifier information from the TAG table. In one possible implementation, the identifier information can be a portion of the request address, specifically the high-order bits of the request address. For example, the high-order bits of the request address could be the TAG table. Therefore, the identifier information can be quickly retrieved using the low-order and high-order bits of the request address.

[0065] The lookup result is a hit if the identifier is found in the cache. The lookup result is a miss if the identifier is not found in the cache.

[0066] In one possible implementation, the instruction fetch request includes at least one sub-instruction fetch request, and the identification information includes at least one sub-identification information. The sub-instruction fetch request corresponds to the sub-identification information. The sub-instruction fetch request includes an instruction fetch address, where the high-order bits of the fetch address are the sub-identification information (i.e., TAG).

[0067] In one possible implementation, the instruction fetch request includes at least two sub-instruction fetch requests, which include a first sub-instruction fetch request and a second sub-instruction fetch request.

[0068] like Figure 8As shown, in one possible implementation, the TAG table in the cache includes multiple ways, and the data table includes data slice groups. The number of TAG tables is equal to the number of data slice groups, and there is a one-to-one correspondence between TAG tables and data slice groups. The data format of the way in the TAG table is as follows: Figure 8 As shown, where: P: Parity check bit; V: Validity flag; TAG: PC_H. The TAG can be used to identify the data block stored in the corresponding storage area (or location) within the data slice corresponding to this way.

[0069] A data slice group comprises at least two data slices. Each data slice includes several storage locations or storage areas, and each storage location or storage area stores one data block, which corresponds to one identification information. There is a fixed correspondence between multiple ways in the TAG table and data slices; that is, the data corresponding to the identification information in each way is fixedly stored in a fixed storage location or storage area within a fixed data slice. For example, the TAG table includes M (M is an even number) ways, and the data slice group includes two data slices. In these two data slices, one data slice corresponds to an even-numbered way, and the other data slice corresponds to an odd-numbered way. An even-numbered way can refer to a way whose sequence number is even, such as way0, way2, way4, ..., wayM-2; an odd-numbered way can refer to a way whose sequence number is odd, such as way1, way3, way5, ..., wayM-1. If the two data slices are slice0 and slice1, then slice0 corresponds to way0, way2, way4, ..., wayM-2, meaning the data corresponding to the identification information stored in way0, way2, way4, ..., wayM-2 are stored in slice0. Slice1 corresponds to way1, way3, way5, ..., wayM-1, meaning the data corresponding to the identification information stored in way1, way3, way5, ..., wayM-1 are stored in slice1.

[0070] It should be noted that the above implementation is based on an example with two data slices in the data slice group. The number of data slices in the data slice group can also be other numbers, such as four. For example, the four data slices would be slice0, slice1, slice2, and slice3. Slice0 corresponds to way0, way4, way8, ..., wayM-3, meaning the data corresponding to the identification information stored in way0, way4, way8, ..., wayM-3 is stored in slice0. Slice1 corresponds to way1, way5, way9, ..., wayM-2, meaning the data corresponding to the identification information stored in way1, way5, way9, ..., wayM-2 is stored in slice1. Slice2 corresponds to way2, way6, way10, ..., wayM-1, meaning the data corresponding to the identification information stored in way2, way6, way10, ..., wayM-1 is stored in slice2. Slice3 corresponds to way3, way7, way11, ..., wayM. That is, the identification information stored in way3, way7, way11, ..., wayM is stored in slice3 respectively. The aforementioned each road and its corresponding data slice is only an example and not a limitation.

[0071] The multiple paths in the TAG table are divided into multiple path groups according to a preset combination method. Each path group contains the same number of paths, and the paths in each path group correspond one-to-one with the data slices in the data slice group.

[0072] In one possible implementation, the combination of road groups can be fixed, meaning the roads within each road group are fixed. For example, adjacent road groups can be combined into one road group. That is, the cache includes multiple road groups, each containing at least two sequentially adjacent roads. "Adjacent" can refer to sequential adjacency, meaning the road numbers are adjacent. For example, if each road group contains two roads and the cache contains N roads, then the cache contains N / 2 road groups. The first road group contains way0 and way1, the second road group contains way2 and way3, and so on, with the N / 2th road group containing wayN-1 and wayN. When a road group contains two roads, this road group can be called a road pair. In one possible implementation, the two roads in a road pair are adjacent. For example, if each path group includes 4 paths, then the cache includes N / 4 path groups. The first path group includes way0, way1, way2 and way3, the second path group includes way4, way5, way6 and way7, and so on. The N / 4th path group includes wayN-3, wayN-2, wayN-1 and wayN.

[0073] In one possible implementation, the combination of road groups is flexible, but a road can only reside in one road group. The number of roads contained in each road group corresponds one-to-one with the number of data slices in a data slice group, and no two road groups are allowed to contain the same road simultaneously. For example, the cache includes N roads: way0, way1, ..., wayN, where way0 is the road group. Assuming the combination of road groups is flexible, with each road group containing two roads and each data slice group containing two data slices, then at a certain time t1, way0 and way1 belong to the same road group W1, and at time t1, way0 and way1 belong to only road group W1. At a certain time, way0 and way3 belong to the same road group W1. This flexible grouping can increase the probability of forming groups. When the number of free roads in the TAG table is greater than the number of roads contained in a road group, there is an opportunity to form a road group. For example, when the number of free roads in the TAG table is greater than or equal to the number of roads contained in a road group, and the free roads include the road corresponding to each data slice, a road group can be formed. For example, if way4, way6, and way9 in the TAG table are in an idle state, then you can choose either way4 or way6 to form a road group with way9.

[0074] S102. When the search result is not a complete match, determine whether the copying conditions are met. If the copying conditions are met, initiate the copy backfill mode. In copy backfill mode, retrieve the first target data corresponding to the missed instruction fetch request from the main memory, copy the first identifier information corresponding to the missed instruction fetch request to at least two roads in the target road group, and copy the first target data to the corresponding data slice in the target data slice group. The road group includes at least two roads, the data slice group includes at least two data slices, and the roads in the road group correspond one-to-one with the data slices in the data slice group; the target data slice group corresponds to the target road group.

[0075] In step S102, the lookup result of a sub-fetch request is either a hit or a miss. When a fetch request includes at least two sub-fetch requests, the lookup result of the fetch request will be incompletely hit, that is, among the at least two sub-fetch requests, some sub-fetch requests are hit, while the remaining sub-fetch requests are miss. Therefore, in the copy-backfill mode, the first target data corresponding to the miss fetch requests is obtained from the main memory, the first identifier information corresponding to the miss fetch requests is copied to at least two paths in the target road group, and the first target number is copied to the corresponding data slice in the target data slice group. That is: in the copy-backfill mode, the first target data corresponding to the miss sub-fetch requests is obtained from the main memory, the first identifier information corresponding to the miss sub-fetch requests is copied to at least two paths in the target road group, and the first target number is copied to the corresponding data slice in the target data slice group.

[0076] In step S102, the first target data can be a data block. To avoid instruction fetch conflicts, a copy-backfill mode is established during data processing. Furthermore, to comprehensively consider the flexibility of cache allocation, starting the copy-backfill mode requires meeting certain copying conditions. The copy-backfill mode is only activated when these conditions are met. Therefore, the copy-backfill mode is a flexible backfill mode, not a mandatory one, thereby increasing cache utilization and flexibility.

[0077] In one possible implementation, the replication condition includes the existence of an idle road group. When an idle road group exists, the replication-backfill mode will be automatically initiated during data backfilling. In replication-backfill mode, when the cache retrieves the first target data corresponding to the requested address from memory, it copies the first identifier information corresponding to the first target data into each data slice, and the corresponding first identifier information is copied to each road in the target road group. An idle road group refers to a road group in which every road is in an idle state.

[0078] For example, a request instruction might include the request address 00001110, corresponding to data block X. The TAG in a way is the high five bits, meaning the TAG for this request instruction is 00001, and the identifier for data block X is 00001. If the data block corresponding to the fetch request is not found, and the copying condition is met, the cache will initiate copy backfilling mode. In copy backfilling mode, the identifier 00001 is filled into each way of the target way group, and data block X is copied to the storage location or storage area within the data slice corresponding to each way in the target way group. For example, if the target way group includes way0 and way1, where way0 corresponds to area a1 of slice0 and way1 corresponds to area b1 of slice1, then in copy backfilling mode, 00001 (the identifier) ​​is copied into the TAGs of way0 and way1, and data block X is copied to area a1 of slice0 and area b1 of slice1, respectively.

[0079] In one possible implementation, a road group includes at least three roads. The replication conditions include: no free road group exists, but at least two free roads exist, and at least two of these free roads belong to the same road group. In this case, the two roads belonging to the same road group constitute the target road group. At this point, replication backfilling mode can be initiated. In replication backfilling mode, the cache retrieves the first target data corresponding to the requested address from memory, copies the first identification information corresponding to the first target data to the target roads in the target road group, where the target road refers to a free road in the target road group. The first target data is also copied to the target data slice in the target data slice group, where the target data slice corresponds to the target road in the target road group. That is, in replication backfilling mode, the free roads in the target road group are replicated and backfilled. For example, taking data block X and its corresponding TAG 00001 (i.e., identification information 00001) as an example, road group W1 includes way0, way1, way2, and way3. When a cache miss occurs, way2 and way3 in W1 are occupied, while way0 and way1 are idle. Way0 corresponds to area A1 of slice0, and way1 corresponds to area B1 of slice1. During copy-fill, the identifier information 00001 is copied and filled into way0 and way1. Data block X is copied to area A1 of slice0 and area B1 of slice1.

[0080] In one possible implementation, determining whether the replication condition is met includes:

[0081] Determine if there is an idle road group. If there is an idle road group, then the replication condition is met.

[0082] If there are no free road groups, determine if there are at least two free roads;

[0083] When there are at least two free paths, determine whether there are at least two paths in the same road group among the at least two free paths;

[0084] The replication condition is satisfied if at least two of the at least two free paths are in the same path group.

[0085] When the replication conditions are met, the replication backfill mode is initiated.

[0086] In one possible implementation, the replication condition is not satisfied if there are no at least two free paths. Similarly, the replication condition is not satisfied if there are no at least two paths in the same road group among the at least two free paths.

[0087] Based on the copy-and-fill model, the target data and its corresponding identification information are copied to at least two ways. That is, at least two ways simultaneously contain the same identification information, and at least two corresponding data slices store a common target data. Therefore, when at least two ways are hit, fetch conflicts can be effectively avoided. Specifically, when at least two ways are simultaneously hit by a sub-fetch request, the sub-fetch request can choose any corresponding data slice for fetching, thus avoiding fetch conflicts. Even if at least two ways are simultaneously hit by at least two sub-fetch requests, each sub-fetch request can be independently allocated a way, i.e., each sub-fetch request can be independently allocated a slice. This allows multiple sub-fetch requests to fetch in parallel, improving fetch efficiency and effectively reducing the probability of fetch request conflicts.

[0088] like Figure 9 As shown in the embodiments of this application, a data processing method is also provided, including the following steps:

[0089] S201. In response to the instruction fetch request, look up the identification information corresponding to the instruction fetch request.

[0090] The specific implementation of step S201 can be found in step S101, and will not be elaborated here.

[0091] S202. When the search result is not a complete match, determine whether the copying conditions are met. If the copying conditions are met, initiate the copy backfill mode. In copy backfill mode, retrieve the first target data corresponding to the missed instruction fetch request from the main memory, copy the first identifier information corresponding to the missed instruction fetch request to at least two roads in the target road group, and copy the first target data to the corresponding data slice in the target data slice group. The road group includes at least two roads, the data slice group includes at least two data slices, and the roads in the road group correspond one-to-one with the data slices in the data slice group; the target data slice group corresponds to the target road group.

[0092] The specific implementation of step S202 can be found in step S102, and will not be elaborated here.

[0093] S203. When the search result is not a complete match, and the copying conditions are not met, the data is backfilled according to the data backfilling strategy.

[0094] In step S203, a search result of "not a complete miss" means that the fetch request includes at least two sub-fetch requests, in which at least one sub-fetch request has a miss result and at least one sub-fetch request has a hit result. When there is a miss sub-fetch request, the cache retrieves data from memory for backfilling according to a data backfilling strategy. In one possible implementation, the data backfilling strategy includes:

[0095] If there are no available road groups but there are available roads, then the available roads should be selected for backfilling.

[0096] Otherwise, if there is a road group that is already in use, a road will be selected from the corresponding road group to replace it.

[0097] Otherwise, a replacement is performed using a chosen path based on the replacement strategy. This replacement strategy can be any existing strategy, such as First-In-First-Out (FIFO), Least Recently Used (LRU), or a random strategy.

[0098] For ease of distinction, we will define the mode in which data is backfilled according to the data backfilling strategy when the replication conditions are not met as the non-replication backfilling mode. As can be clearly seen from step S203, the replication backfilling mode has a higher priority than the non-replication backfilling mode. The execution of the backfilling mode depends on the replication conditions; when these conditions are not met, the cache performs backfilling according to the non-replication backfilling mode. Therefore, the activation of the replication backfilling mode is actually determined by the actual usage of the cache; thus, the replication backfilling mode is an adaptive and balanced working mode, a dynamic and flexible working mode.

[0099] In summary, the data processing method provided in this application can effectively reduce the probability of instruction fetch request conflicts. It also allows for flexible use of cache storage resources. When memory availability is high, a copy-and-fill mode can be used to reduce the probability of instruction fetch request conflicts and improve fetch efficiency. When cache availability is low, the probability of an idle path group is very low, so the cache can be considered to automatically exit the copy-and-fill mode. The copy-and-fill mode is restarted when cache availability is high. This achieves dynamic copying of the target data and its identification information, and achieves adaptive load balancing.

[0100] S203. When the search result in step S201 is a complete match and there is no conflict in the instruction fetch request, then the instruction fetch request is responded to and the instruction is fetched.

[0101] In step S203, during execution, the instruction fetch request fetches instructions according to its own needs. For example, the instruction fetch request includes a first sub-instruction fetch request and a second sub-instruction fetch request, and the first sub-instruction fetch request hits way0, which corresponds to slice0, and the second sub-instruction fetch request hits way5, which corresponds to slice1. In this case, the first sub-instruction fetch request and the second sub-instruction fetch request fetch instructions simultaneously.

[0102] In one possible implementation, step S203 further includes: the instruction fetch request includes at least two sub-instruction fetch requests; when the instruction fetch request performs instruction fetching, if there is a conflict between the instruction fetch requests, a number of executable sub-instruction fetch requests are randomly selected for instruction fetching, and the sub-instruction fetch requests that are not executed this time have priority in the subsequent instruction fetch requests.

[0103] To better understand step S203, the following will be combined with... Figure 10 Please provide an explanation.

[0104] like Figure 10 As shown, a fetch request corresponding to a TAG table includes two sub-fetch requests, and a data switching group includes two data slices, with the two data slices sharing a TAG table. Figure 10 In the text, yellow fill indicates that copying and backfilling have occurred, green fill indicates that it only points to slice2, and light pink fill indicates that it only points to slice3. The numbers in the fill colors of Tag Slice1 represent the instruction fetch request sequence numbers. Specifically, instruction fetch request 1 and instruction fetch request 2 are initiated simultaneously, instruction fetch request 3 and instruction fetch request 4 are initiated simultaneously, and instruction fetch request 5 and instruction fetch request 6 are initiated simultaneously.

[0105] from Figure 10As can be seen, fetch request 5 and fetch request 6 both point to slice2. In this case, only one scheduling request can be scheduled, resulting in a 50% decrease in scheduling efficiency. The buffer will randomly select one of fetch request 5 and fetch request 6 for instruction fetching. The following explanation uses the example of randomly selecting fetch request 5 and fetch request 6 being rolled back and not executed. In the next fetch cycle after fetch request 5, if there is no fetch request pointing to slice2, slice2 executes fetch request 5, while the remaining slices execute their corresponding fetch requests. In the next fetch cycle after fetch request 5, if fetch request 7 points to slice2, fetch request 6 is prioritized, and fetch request 7 is fetched in the next fetch cycle.

[0106] In one possible implementation, a conflict condition is met when there is a conflict in the instruction fetch request. The conflict condition is as follows:

[0107] Reqi.WP==0&&Reqi+1.WP==0&&Reqi.Hit_Way[0]==Reqi+1.Hit_Way[0], where i is the request sequence number, and its value range is an integer greater than or equal to zero; where Reqi.WP==0 indicates that the road group pointed to by the fetch request i has not been copied, that is, at least two roads in the road group have different identification information, Reqi+1.WP==0 indicates that the road group pointed to by the fetch request i+1 has not been copied, that is, at least two roads in the road group have different identification information, Reqi.Hit_Way[0] represents the low-order flag bit, and Reqi.Hit_Way[0]==Reqi+1.Hit_Way[0] means that request i and request i+1 point to the same slice.

[0108] In this implementation, if a fetch request does not meet the aforementioned conflict conditions, it indicates that the fetch request does not conflict. When there is no conflict, the data slice corresponding to the hit way in the cache responds to the corresponding fetch request, that is, the data slice corresponding to the hit way in the cache is fetched. For example, if the fetch request includes a first sub-fetch request and a second sub-fetch request, and the first sub-fetch request hits way0, which corresponds to slice0, and the second sub-fetch request hits way1, which corresponds to slice1, then the first sub-fetch request fetches an instruction from slice0, and the second sub-fetch request fetches an instruction from slice1, thus achieving synchronous fetching and having good fetch efficiency.

[0109] In one possible implementation, the replication condition is the existence of an idle road group. When an idle road group exists, the replication-backfill mode is automatically initiated during data backfilling. In replication-backfill mode, when the cache retrieves the first target data corresponding to the requested address from memory, it copies the first identifier information corresponding to the first target data into each data slice, and the corresponding first identifier information is copied to each road in the target road group. When exiting replication-backfill mode, after one way in the road group is replaced with new identifier information, that road group can no longer be replicated and backfilled.

[0110] In one possible implementation, the data processing method further includes: S204, clearing aging data.

[0111] In step S204, to improve the effective utilization of the cache, the cache needs to clear the aging way. The aging table data structure is as follows: Figure 11 As shown in the diagram. IN_USE is the way validity flag. An IN_USE value of 0 indicates the current way is inactive; an IN_USE value of 1 indicates the current way is in use. AGING is the aging flag. An AGING value of 0 indicates no access during the aging period; an AGING value of 1 indicates access during the aging period.

[0112] Erasing aging data includes:

[0113] Maintain an identification information table (i.e., BITMAP) based on the monitored targets. Each monitored target maintains a 2-bit flag, namely IN_USE and AGING. During refill, the IN_USE flag of the corresponding way is set, and the AGING flag is cleared.

[0114] Maintain a timer based on clock cycle (CC). When the timer reaches a configured threshold, it triggers a scan and aging process of the identification information table.

[0115] If IN_USE is valid but AGING is invalid, then the AGING flag is set;

[0116] If IN_USE and AGING are both valid, then IN_USE and AGING will be cleared to zero and aging will be performed. This means that the corresponding way in the corresponding TAG table will be set to invalid, the corresponding way will be released, and the identification information in the way will be cleared. The corresponding data in the corresponding data slice will also be cleared.

[0117] If IN_USE is invalid, no action is taken.

[0118] When a way becomes old, the corresponding way in the corresponding TAG table is set to invalid and the corresponding way is released. When all ways in the road group are released, the next data backfill will start the replication backfill mode, that is, the new backfill can replicate the backfill to the road group again.

[0119] The data processing method provided in the embodiments of this application can achieve the following technical effects:

[0120] 1. Using the data processing method provided in the embodiments of this application, in scenarios with a small amount of program volume in a single service flow or a small number of mixed service flows (such as network access comparison test), when making an instruction fetch request, the cache automatically enters the copy-fill mode, reducing the probability of instruction fetch conflict and improving instruction fetch performance;

[0121] 2. Using the data processing method provided in this application embodiment, in scenarios with a large volume of mixed business flow programs (normal operation), the cache is heavily occupied, and there are often idle paths. Therefore, the cache will exit or partially exit the replication mode during data backfilling, improving instruction density. Furthermore, whether the cache operates in replication backfilling mode or non-replication backfilling mode depends on the cache's idle state and is not mandatory. Therefore, adaptive adjustment and switching between replication backfilling mode and non-replication backfilling mode can be achieved.

[0122] 3. The data processing method provided in the embodiments of this application can achieve a dynamic balance between cache performance and capacity without increasing cache capacity.

[0123] Please see Figure 10This application embodiment also provides a memory 100, including at least one storage unit 110. The storage unit 110 includes at least one TGA table 111 and at least one data slice group 112. The TGA table 111 stores identification information. The TGA table 111 includes several road groups, and each road group includes at least two roads. The TGA table 111 stores identification information through roads. For example, the identification information is a TAG in the road. The data slice group 112 includes at least two data slices 1121. The data slices 1121 store information corresponding to the identification information in the TGA table. The TGA table 111 and the data slice group 112 correspond one-to-one. The roads in the road group correspond one-to-one with the data slices in the data slice group. In one possible implementation, the number of roads in the road group, the number of data slices in the data slice group, and the number of sub-fetch requests that the TGA table can respond to simultaneously are equal. The number of sub-fetch requests that the TAG table can respond to simultaneously can be the maximum number of sub-fetch requests that the TAG table can receive in a single fetch cycle. For example, if the TAG table can receive a maximum of m sub-fetch requests in a single fetch cycle, then the road group includes m roads, and the data slice group includes m data slices. In one possible implementation, m is 2.

[0124] The operating modes of the memory 100 include a copy-backfill mode. In the copy-backfill mode, the memory 100 retrieves the first target data corresponding to the missed instruction fetch request from memory, copies the first identification information corresponding to the missed instruction fetch request to at least two paths in the target path group, and copies the first target number to the corresponding data slice 1121 in the target data slice group. The target data slice group corresponds to the target path group.

[0125] The first target data refers to the data or instruction corresponding to the portion of the instruction fetch request that was not hit. For example, an instruction fetch request may include multiple sub-fetch requests, including a first sub-fetch request and a second sub-fetch request. The first sub-fetch request may have a hit result, while the second sub-fetch request may have a miss result, meaning the instruction fetch request was not completely hit. The first target data is the data or instruction corresponding to the second sub-fetch request.

[0126] In one embodiment of this application, the memory 100 performs data processing according to the data processing method provided in the foregoing embodiments. The memory 100 may be a cache, and the cache may be SRAM.

[0127] In one embodiment of this application, the storage unit 110 further includes: at least one scheduler group 113, the scheduler group 113 corresponding one-to-one with the TAG table 111; each scheduler group 113 includes at least two schedulers 1131, and the number of schedulers 1131 in the scheduler group 113 is the same as the number of roads in the road group.

[0128] Scheduler 1131 is used to schedule instruction fetches. In one possible implementation, a scheduler can only allow one sub-fetch request to pass. The number of sub-fetch requests that can be allowed to pass within the same scheduler group is the same as the number of schedulers 1131 in that group. Figure 10 For example, a scheduler group 113 includes two schedulers 1131. When the scheduler group 113 receives more than two sub-fetch requests, only two sub-fetch requests can be scheduled to pass within one fetch cycle.

[0129] In one embodiment of this application, the data slice 1121 further includes a data selector. In one possible implementation, the data selector is a multiple-to-one data selector used to determine the data within the data block. Using a data selector enables efficient reading of target data from the data block, ensuring the effective execution of full fetch.

[0130] In one embodiment of this application, the operating mode of the memory 100 also includes a non-copy backfill mode, in which the memory backfills data according to a data backfill strategy.

[0131] In one possible implementation, when the memory search result is a partial miss and the copying conditions are not met, the memory automatically enters a non-copying backfill mode. The memory's data backfilling strategy is as follows:

[0132] If there are no available road groups but there are available roads, then the available roads should be selected for backfilling.

[0133] Otherwise, if there is a road group that is already in use, a road will be selected from the corresponding road group to replace it.

[0134] Otherwise, a replacement is performed using a chosen path based on the replacement strategy. This replacement strategy can be any existing strategy, such as First-In-First-Out (FIFO), Least Recently Used (LRU), or a random strategy.

[0135] In one embodiment of this application, the operating mode of the memory 100 further includes an aging and clearing mode, in which the memory 100 cleans the aging data.

[0136] In one possible implementation, the memory 100 can clear the aging data by referring to the aging data clearing steps in the foregoing embodiments, which will not be repeated here.

[0137] The memory provided in this application embodiment achieves improved instruction fetch performance when there are few programs, as it has a large number of idle path groups. During data backfilling, it automatically initiates a copy-and-fill mode, thus improving fetch performance. When there are many programs, the memory usage is large, and the probability of having idle path groups is extremely low. Therefore, during data backfilling, the memory may exit the copy-and-fill mode because it cannot meet the copying conditions, thus increasing instruction density. Therefore, the memory provided in this application embodiment can effectively meet the characteristics of high program size and performance during network access testing, but large program size and low performance margin during network operation.

[0138] This application also provides a device configured with the data processing method provided in the foregoing embodiments, and / or the device includes at least one memory provided in the foregoing embodiments.

[0139] In one possible implementation, the device includes multiple memories. Multiple memories can effectively increase data processing speed.

[0140] like Figure 12 As shown, in one embodiment of this application, device 200 may include a processor 201, a memory 202, and a communication unit 203. These components communicate via one or more buses. Those skilled in the art will understand that the server structure shown in the figures does not constitute a limitation on the embodiments of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0141] The communication unit 203 is used to establish a communication channel, enabling the storage device to communicate with other devices. It can receive user data sent by other devices or send user data to other devices.

[0142] The processor 201 serves as the control center of the storage device, connecting various parts of the electronic device via various interfaces and lines. It executes software programs and / or modules stored in the memory 202, and calls data stored in the memory to perform various functions of the electronic device and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 201 may consist only of a central processing unit (CPU). In this embodiment of the invention, the CPU may have a single processing core or include multiple processing cores.

[0143] The memory 202 is used to store the execution instructions of the processor 201. The memory 202 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. It should be noted that the memory 100 provided in the foregoing embodiments can be a part of the memory 202.

[0144] When the execution instructions in memory 202 are executed by processor 201, the embedded device 200 is able to execute... Figure 6 Some or all of the steps in the illustrated embodiments.

[0145] In a specific implementation, the present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps of the various embodiments of the image annotation method provided by the present invention. The storage medium may be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0146] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0147] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A data processing method, characterized in that, include: In response to an instruction fetch request, locate the identification information corresponding to the instruction fetch request; If the search results are not a complete match, determine whether the copying conditions are met; When the copying conditions are met, the first target data corresponding to the missed instruction fetch request is retrieved from memory, the first identifier information corresponding to the missed instruction fetch request is copied to at least two paths in the target road group, and the first target data is copied to the corresponding data slice in the target data slice group. The road group includes at least two paths, the data slice group includes at least two data slices, and the paths in the road group correspond one-to-one with the data slices in the data slice group. The target data slice group corresponds to the target road group.

2. The data processing method according to claim 1, characterized in that, The replication conditions include: the existence of an idle road group.

3. The data processing method according to claim 2, characterized in that, When the copying conditions are met, the first target data corresponding to the missing instruction fetch request is retrieved from memory, the first identifier information corresponding to the missing instruction fetch request is copied to each road in the target road group, and the first target number is copied to each data slice in the target data slice group.

4. The data processing method according to claim 1, characterized in that, The replication conditions include: there are no free road groups, but there are at least two free roads, and at least two of the at least two free roads are in the same road group.

5. The data processing method according to claim 4, characterized in that, When the copying conditions are met, the first target data corresponding to the requested address is retrieved from memory, and the first identification information corresponding to the first target data is copied to the target roads in the target road group, wherein the target roads are the idle roads in the target road group. The first target data is then copied into a target data slice within the target data slice group, the target data slice corresponding to the target road.

6. The data processing method according to claim 1, characterized in that, Also includes: If the replication conditions are not met, the data is backfilled according to the data backfilling strategy.

7. The data processing method according to claim 6, characterized in that, The data backfilling strategy includes: If there are no available road groups but there are available roads, then select the available roads for backfilling; Otherwise, if there is a road group that is already in use, select one road from the road group to replace it; Otherwise, select one path to replace according to the replacement strategy.

8. The data processing method according to claim 1, characterized in that, Also includes: Clear the aging data.

9. A memory, characterized in that, include: At least one storage unit; The storage unit includes: At least one TAG table, the TAG table being used to store identification information; the TAG table including several road groups, the road group including at least two roads; At least one data slice group, the data slice group comprising at least two data slices; the data slices are used to store information corresponding to the identification information in the TGA table; The TAG table corresponds one-to-one with the data slice group; the roads in the road group correspond one-to-one with the data slices in the data slice group; the working mode of the memory includes a copy-backfill mode; when the copy condition is met, the memory starts the copy-backfill mode; in the copy-backfill mode, the memory retrieves the first target data corresponding to the missed instruction fetch request from memory, copies the first identifier information corresponding to the missed instruction fetch request to at least two roads in the target road group, and copies the first target number to the corresponding data slice in the target data slice group, wherein the target data slice group corresponds to the target road group.

10. A device, characterized in that, The device is configured with the data processing method according to any one of claims 1-8, and / or the device includes at least one memory according to claim 9.

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