Data processing method and device, electronic equipment, storage medium and program product

Abstract

The present disclosure provides a data processing method and device, electronic equipment, storage medium and program product, applied to the technical field of computer, the method comprises the steps of: determining the first slot number corresponding to the board card based on the spring ejector pin level; receiving the acquisition instruction of the baseboard management controller, if the slot number carried in the acquisition instruction is the first slot number, then the board card material number is sent to the baseboard management controller; receiving the address code of each chip in the board card sent by the baseboard management controller; wherein the address code of each chip is determined based on the material number and slot number of all board cards corresponding to the electronic equipment; based on the address code of each chip in the board card, adjust the address configuration pin level of each chip in the board card, so that the address configuration pin level of each chip after adjustment is consistent with the address code of each chip; in this way, it is not necessary to configure the address of each chip on the board card in advance, which reduces the configuration cost and is more convenient for expanding the electronic equipment configuration.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method, apparatus, electronic device, and storage medium. Background Technology

[0002] To enrich product configurations, server manufacturers use expansion cards (RISER cards, RISERs) and server backplanes (BPs) to support various network cards, redundant array of independent disks (RAID) cards, graphics processing units (GPUs), and hard drives, meeting the diverse application needs of customers. To ensure stable server operation and ease of maintenance, the Baseboard Management Controller (BMC) communicates with the BP or RISER via the Inter-Integrated Circuit Bus (I2C) to obtain information such as the temperature, model, and location of the network cards and hard drives on them. Typically, each backplane or RISER requires a dedicated I2C channel and connector. While several backplanes and RISERs can share a single I2C channel, provided there are no I2C address conflicts, this is usually limited to no more than two cards. Due to the large number of cards and limited I2C interfaces, I2C expansion chips are typically added to the motherboard to expand the I2C channels; this is a common practice among different manufacturers.

[0003] Devices such as the CPU, power chip, and temperature sensor on the motherboard require I2C channels, which means that BP or RISER can only use 3-5 I2C channels. Due to insufficient I2C resources, in order to meet configuration requirements, more than 5 part numbers of the same type of board have been iterated. Since these part numbers are not interchangeable, a single model may have less stock than demand or more stock than demand, which leads to increased material control costs. Summary of the Invention

[0004] This disclosure provides a data processing method, apparatus, electronic device, storage medium, and program product to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this disclosure, a data processing method is provided, applied to a board including a microcontroller unit (MCU), the method comprising:

[0006] The first slot number corresponding to the board is determined based on the spring pin level.

[0007] Receive an acquisition instruction from the substrate management controller. If the slot number carried in the acquisition instruction is the first slot number, then send the board part number to the substrate management controller.

[0008] The address codes of each chip in the board are sent by the baseboard management controller; wherein the address codes of each chip are determined based on the part number and slot number of all boards corresponding to the electronic device.

[0009] Based on the address codes of each chip in the board, the address configuration pin levels of each chip in the board are adjusted so that the adjusted address configuration pin levels of each chip match the address codes of each chip.

[0010] In the above solution, the chassis of the electronic device includes multiple slots, and the method further includes:

[0011] Number each slot to obtain the slot number corresponding to each slot;

[0012] In the first area corresponding to each slot on the chassis, holes are drilled based on the slot number so that after the board is inserted into the slot, multiple spring pins of the board contact the first area.

[0013] The method in the above scheme further includes:

[0014] Binary encoding is performed based on the slot number corresponding to each slot;

[0015] In the first area corresponding to each slot, a hole is punched at position 1 in the slot code, so that after the board is inserted into the slot, the level of the spring pin inserted into the hole is 1, and the level of the spring pin not inserted into the hole is 0. The level of all spring pins matches the binary code of the slot number.

[0016] In the above scheme, determining the first slot number corresponding to the board based on the spring pin level includes:

[0017] Receives the voltage level from the spring-loaded pin;

[0018] The binary code corresponding to the slot is determined based on the position and level of each spring pin;

[0019] The first slot number corresponding to the board is determined based on the binary code corresponding to the slot.

[0020] The method in the above scheme further includes:

[0021] The first general-purpose input / output interface of the microcontroller is connected to the second general-purpose input / output interface of the bus connector, and is used to receive acquisition instructions transmitted to the board by the baseboard management controller through the bus connector;

[0022] The third general-purpose input / output interface of the microcontroller is connected to the fourth general-purpose input / output interface of the bus connector, and is used to transmit the data corresponding to the acquisition command to the board management controller;

[0023] At least one fifth general-purpose input / output interface of the microcontroller is connected to the address configuration pins of other chips on the board, respectively, for configuring the address configuration pin levels of each chip.

[0024] The method in the above scheme further includes:

[0025] The board is provided with an inter-integrated circuit bus expansion chip, which is connected to a bus connector and is used to receive control commands transmitted from the baseboard controller to the board through the bus connector.

[0026] The inter-integrated circuit bus expansion chip transmits the control command to the chip corresponding to the address code based on the address code included in the control command.

[0027] In the above scheme, receiving the acquisition instruction from the substrate management controller, if the slot number carried in the acquisition instruction is the first slot number, then sending the board part number to the substrate management controller includes:

[0028] The microcontroller receives the acquisition instruction based on the first general-purpose input / output interface and determines the slot number carried in the acquisition instruction;

[0029] If the slot number carried in the acquisition command is the first slot number, the board part number and the first slot number are transmitted to the board management controller through the third general purpose input / output interface.

[0030] In the above scheme, the address codes of each chip on the board are determined based on the address code table;

[0031] The address encoding table is determined based on the board part number and slot number of all boards on the electronic device.

[0032] In the above scheme, adjusting the address configuration pin level of each chip in the board based on the address encoding of each chip in the board includes:

[0033] Based on the address codes of each chip on the board, the address configuration pin levels of each chip are adjusted through at least one fifth input / output interface in the microcontroller unit so that the address configuration pin levels of each chip on the board match the address codes of each chip.

[0034] In the above scheme, after adjusting the address configuration pin levels of each chip in the board based on the address encoding of each chip in the board, the method further includes:

[0035] The microcontroller stores the address codes of each chip on the board into the flash memory of the microcontroller so that the electronic device can load the address codes of each chip on the board from the flash memory of the microcontroller when it starts up.

[0036] In the above scheme, after adjusting the address configuration pin levels of each chip in the board based on the address encoding of each chip in the board, the method further includes:

[0037] The inter-integrated circuit bus expansion chip receives processing instructions transmitted by the substrate management controller based on the bus connector;

[0038] The address code in the processing instruction is parsed, and the processing instruction is transmitted to the corresponding chip.

[0039] In the above scheme, the electronic device connects multiple boards based on slots;

[0040] Of the plurality of circuit boards, at least two circuit boards have the same part number;

[0041] Two boards with the same part number may have different address codes for chips of the same specifications.

[0042] According to a second aspect of this disclosure, a data processing method is provided, applied to a substrate management controller, comprising:

[0043] Based on the slot numbers of multiple slots in an electronic device, multiple acquisition instructions are determined;

[0044] The multiple acquisition commands are transmitted via a bus connector to the microcontroller units of multiple boards connected to the electronic device;

[0045] Based on the slot number and board part number transmitted by the microcontroller unit of each board, the address code of each chip on each board is determined.

[0046] The address codes of each chip on each board are transmitted to the microcontroller unit of each board through the bus connector, so that the microcontroller unit can adjust the address configuration pin level of each chip on the board based on the address code of each chip, so that the adjusted address configuration pin level of each chip matches the address code of each chip.

[0047] In the above scheme, determining the address code of each chip on each board based on the slot number and board part number transmitted by the microcontroller unit of each board includes:

[0048] The location of each board is determined based on its slot number;

[0049] The address coding table is determined based on the location and part number of each board;

[0050] The address code of each chip connected to each board is determined based on the address encoding table.

[0051] In the above solution, the step of transmitting the multiple acquisition commands to the microcontroller unit of multiple boards connected to the electronic device via a bus connector includes:

[0052] The first acquisition instruction is determined based on the second slot number;

[0053] The first acquisition instruction is transmitted via a bus connector to the microcontroller unit of multiple boards connected to the electronic device;

[0054] In response to receiving the slot number and board part number transmitted by the microcontroller unit within a preset time interval, a second acquisition instruction is determined based on the third slot number, and the second acquisition instruction is sent through the bus connector;

[0055] Alternatively, in response to the failure to receive the slot number and board part number transmitted by the microcontroller unit within a preset time interval, a second acquisition command is determined based on the third slot number, and the second acquisition command is sent through the bus connector.

[0056] According to a third aspect of this disclosure, a data processing apparatus is provided for use on a board including a microcontroller unit, the apparatus comprising:

[0057] A slot determination unit is used to determine the first slot number corresponding to the board based on the spring pin level.

[0058] The first transmission unit is used to receive the acquisition instruction from the substrate management controller. If the slot number carried in the acquisition instruction is the first slot number, the board part number is sent to the substrate management controller.

[0059] The first transmission unit is further configured to receive the address codes of each chip in the board sent by the baseboard management controller; wherein the address codes of each chip are determined based on the part number and slot number of all boards corresponding to the electronic device;

[0060] The configuration unit is used to adjust the address configuration pin level of each chip in the board based on the address code of each chip in the board, so that the adjusted address configuration pin level of each chip matches the address code of each chip.

[0061] According to a fourth aspect of this disclosure, a data processing apparatus is provided for use in a substrate management controller, the apparatus comprising:

[0062] The instruction determination unit is used to determine multiple acquisition instructions based on the slot numbers of multiple slots in an electronic device.

[0063] The second transmission unit is used to transmit the multiple acquisition instructions to the microcontroller units of multiple boards connected to the electronic device via a bus connector;

[0064] The address encoding determination unit is used to determine the address encoding of each chip on each board based on the slot number and board part number transmitted by the microcontroller unit of each board.

[0065] The second transmission unit is further configured to transmit the address codes of each chip on each board to the microcontroller unit of each board through the bus connector, so that the microcontroller unit adjusts the address configuration pin level of each chip on the board based on the address codes of each chip in the board, so that the adjusted address configuration pin level of each chip matches the address code of each chip.

[0066] According to a fifth aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of this disclosure.

[0067] According to a sixth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this disclosure.

[0068] According to a seventh aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the methods described in this disclosure.

[0069] The data processing method disclosed herein involves: determining the first slot number corresponding to the board based on the spring pin level; receiving an acquisition instruction from the baseboard management controller; if the slot number carried in the acquisition instruction is the first slot number, then sending the board part number to the baseboard management controller; receiving the address codes of each chip in the board sent by the baseboard management controller; wherein the address codes of each chip are determined based on the part numbers and slot numbers of all boards corresponding to the electronic device; and adjusting the address configuration pin levels of each chip in the board based on the address codes of each chip in the board, so that the adjusted address configuration pin levels of each chip match the address codes of each chip. In this way, address codes are assigned to each chip on the board only after the board is inserted into the slot, enabling the use of different boards with the same part number on the same electronic device, reducing the need for part number expansion on the same board, and reducing board management costs; simultaneously, it eliminates the need to pre-configure I2C addresses for each chip on the board, reducing configuration costs and facilitating the expansion of electronic device configurations; furthermore, it can reduce R&D investment.

[0070] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0071] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:

[0072] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0073] Figure 1 A schematic diagram illustrating the communication between the BMC and the RISER or BP in related technologies is shown;

[0074] Figure 2 A schematic diagram of a first optional flow of the data processing method provided in this embodiment of the present disclosure is shown;

[0075] Figure 3 A schematic diagram of a second optional flow of the data processing method provided in an embodiment of this disclosure is shown;

[0076] Figure 4 A schematic diagram of the board structure provided in an embodiment of this disclosure is shown;

[0077] Figure 5 A schematic diagram of the motherboard structure provided in an embodiment of this disclosure is shown;

[0078] Figure 6 A schematic diagram of the chassis provided in an embodiment of this disclosure is shown;

[0079] Figure 7 A schematic diagram of a third optional flow of the data processing method provided in this embodiment of the present disclosure is shown;

[0080] Figure 8 A schematic diagram of the acquisition instructions provided in an embodiment of this disclosure is shown;

[0081] Figure 9 A schematic diagram of a fourth optional flow of the data processing method provided in this disclosure embodiment is shown;

[0082] Figure 10 A first schematic diagram of an electronic device chassis provided in an embodiment of this disclosure is shown;

[0083] Figure 11 A second schematic diagram of an electronic device chassis provided in an embodiment of this disclosure is shown;

[0084] Figure 12A schematic diagram of a first optional structure of the data processing apparatus provided in an embodiment of this disclosure is shown;

[0085] Figure 13 A schematic diagram of a second optional structure of the data processing apparatus provided in an embodiment of this disclosure is shown;

[0086] Figure 14 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0087] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0088] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0089] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0090] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0091] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0092] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms involved in the embodiments of this disclosure will be explained, and the nouns and terms involved in the embodiments of this disclosure shall be interpreted as follows.

[0093] In related technologies, a general-purpose server (i.e., the electronic device described in this embodiment) consists of a CPU, memory, hard disk, and external expansion card; among which the CPU, as the central processing unit of the server, is the most core component, and the BMC is a server-specific module that provides temperature, voltage, fan, and bus monitoring; it also provides a management interface to facilitate remote management of the server.

[0094] To enrich server product configurations, server manufacturers use RISER and BP to implement various network cards, RAID cards, GPUs, and hard drives to meet the application needs of different customers; BMC communicates with RISER or BP via I2C.

[0095] BMC includes more than 10 I2C channels, but devices such as the CPU, power chip, and temperature sensor on the motherboard need to occupy I2C channels. In practice, only about 3-5 channels can be used in RISER or BP. During the development phase, it is necessary to manually determine how many boards are connected to each I2C channel and which devices are connected.

[0096] Figure 1 A schematic diagram of BMC communicating with RISER or BP in related technologies is shown.

[0097] like Figure 1 As shown, when multiple RISRs are mounted to the same I2C channel, each chip on the RISR needs to occupy an independent I2C channel, and address resources will be quickly exhausted. This also causes the BMC to be unable to manage too many RISRs or chips on RISRs at the same time, and even address conflicts may occur, leading to communication identification problems.

[0098] In related technologies, for the same model of circuit board, if the I2C addresses of the chips on the board are different, there may be differences in hardware jumpers, solder joints, or material selection, resulting in different part numbers for the same model of circuit board. Similarly, circuit boards of the same model may have different part numbers simply because the I2C addresses of the chips on the board are different, but the hardware jumpers, solder joints, or material selections are the same.

[0099] In the latter case, separate inventory management will be implemented for different board part numbers, and these part numbers cannot be used interchangeably. For example, for a certain model of board, due to insufficient I2C resources, more than five board part numbers may be generated just to meet configuration requirements. Since these part numbers are not interchangeable, either less stock or more stock will be available for a single model, leading to increased material control costs.

[0100] Furthermore, address configuration of chips on the RISER is mostly done manually. This requires engineers to be familiar with all configurations and boards, which places high demands on R&D personnel. If a misjudgment leads to an address conflict, it is usually resolved by modifying the motherboard and changing the I2C address. Such changes affect new projects. Considering the need to change the BOM and re-make the board, it usually takes more than a month to delay the project. Moreover, if the problem is only discovered at the end of the project, it will directly lead to project delays or make the function impossible to implement.

[0101] In view of the deficiencies existing in the related technologies, this disclosure provides a data processing method to at least solve some or all of the above-mentioned technical problems.

[0102] Figure 2 A schematic diagram of a first alternative flow of the data processing method provided in this disclosure is shown, and the steps will be described accordingly.

[0103] In some embodiments, Figure 2 The data processing method shown, namely the data processing method described in steps S201 to S204, is executed by a board including a microcontroller unit.

[0104] Step S201: Determine the first slot number corresponding to the board based on the spring pin level.

[0105] In some embodiments, the board is provided with spring pins; after the board is inserted into the slot of the electronic device, the spring pins contact the chassis of the electronic device; if there is a hole in the part of the chassis that contacts any of the spring pins, the spring pin detects a voltage level of 1; if there is no hole in the part of the chassis that contacts the spring pins, the spring pin detects a voltage level of 0. The hole configurations for different slots on the chassis are different, and the binary representation of the hole information is the slot number.

[0106] In some embodiments, the board determines the first slot number of the slot to which it is connected based on the level of the spring pin.

[0107] Step S202: Receive an acquisition instruction from the substrate management controller. If the slot number carried in the acquisition instruction is the first slot number, then send the board part number to the substrate management controller.

[0108] In some embodiments, the microcontroller unit of the board receives and parses the acquisition instruction from the BMC. If the slot number carried in the acquisition instruction is the first slot number, the board part number and the slot number are sent to the BMC; or, if the slot number carried in the acquisition instruction is not the first slot number, the microcontroller unit does not process the acquisition instruction.

[0109] Step S203: Receive the address codes of each chip in the board sent by the board management controller.

[0110] In some embodiments, the address encoding of each chip on the board is determined based on the part number and slot number of all boards corresponding to the electronic device.

[0111] Step S204: Based on the address encoding of each chip in the board, adjust the address configuration pin level of each chip in the board.

[0112] In some embodiments, the general purpose input / output (GPIO) interface of the microcontroller on the board is respectively connected to the address configuration pins of each chip on the board; after the microcontroller obtains the address code of each chip on the board, it controls the GPIO interface to adjust the level of the address configuration pin of each chip so that the adjusted level of the address configuration pin of each chip matches the address code of each chip.

[0113] Thus, by using the data processing method provided in this embodiment, address codes are assigned to each chip on the board only after the board is inserted into the slot. This allows different boards with the same part number to be used on the same electronic device, reducing the need for part number expansion on the same board and reducing board management costs. At the same time, it eliminates the need to configure I2C addresses for each chip on the board in advance, reducing configuration costs and making it easier to expand the configuration of electronic devices. In addition, it can also reduce R&D investment.

[0114] Figure 3 A second alternative flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0115] In some embodiments, Figure 3 The data processing method shown, namely the data processing method described in steps S301 to S304, is executed by a substrate management controller.

[0116] Step S301: Based on the slot numbers of multiple slots in the electronic device, determine multiple acquisition instructions.

[0117] In some embodiments, the BMC determines the acquisition instruction corresponding to each slot based on the slot number of the slot. The acquisition instruction carries the slot number.

[0118] In some embodiments, the BMC can determine the acquisition instructions corresponding to all slots in the electronic device.

[0119] Step S302: The multiple acquisition commands are transmitted to the microcontroller units of multiple boards connected to the electronic device via the bus connector.

[0120] In some embodiments, the BMC transmits each acquisition command to the slot via a bus connector, and then to the microcontroller unit of the board connected to the slot.

[0121] The bus connector can be an I2C bus connector, located on the motherboard, used to enable communication between the BMC and the board.

[0122] Step S303: Based on the slot number and board part number transmitted by the microcontroller unit of each board, determine the address code of each chip on each board.

[0123] In some embodiments, BMC determines an address encoding table based on the part numbers and slot numbers of all boards corresponding to the electronic device; and determines the address encoding of each chip connected to each board based on the address encoding table.

[0124] In some embodiments, the address encoding tables are determined differently depending on the location of the board on the electronic device.

[0125] Step S304: The address codes of each chip on each board are transmitted to the microcontroller unit of each board through the bus connector.

[0126] In some embodiments, BMC generates address encoding instructions for different boards based on the slot number corresponding to each board, and transmits the address encoding of each chip connected to the board to the microcontroller unit included in each board based on the address encoding instructions.

[0127] Thus, by using the data processing method provided in this embodiment, address codes are assigned to each chip on the board only after the board is inserted into the slot. This allows different boards with the same part number to be used on the same electronic device, reducing the need for part number expansion on the same board and reducing board management costs. At the same time, it eliminates the need to configure I2C addresses for each chip on the board in advance, reducing configuration costs and making it easier to expand the configuration of electronic devices. In addition, it can also reduce R&D investment.

[0128] Figure 4 A schematic diagram of the board structure provided in an embodiment of this disclosure is shown.

[0129] like Figure 4 The diagram shows the board structure of any board. Each board includes at least one microcontroller unit, and the chips on the board can be configured according to the board's purpose; for example... Figure 4 The mid-board includes an MCU and multiple chips (such as CA9546, TPM112, FRU, CA9555, etc.); the bus connector (I2C CONN) can be located on the board or on the motherboard. Figure 4 The bus connector is shown to illustrate the arrangement of the connection lines between the MCU and the bus connector, and is not intended to restrict the position of the bus connector.

[0130] like Figure 4 As shown, the first general-purpose input / output interface of the microcontroller is connected to the second general-purpose input / output interface of the bus connector, and is used to receive the acquisition command transmitted to the board by the baseboard management controller through the bus connector; the third general-purpose input / output interface of the microcontroller is connected to the fourth general-purpose input / output interface of the bus connector, and is used to transmit the data corresponding to the acquisition command to the baseboard management controller; at least one fifth general-purpose input / output interface of the microcontroller is connected to the address configuration pins of other chips on the board, respectively, and is used to configure the address configuration pin levels of each chip.

[0131] The bus connector and the inter-integrated circuit bus expansion chip (CA9546) are used to transmit processing instructions sent by the BMC. The inter-integrated circuit bus expansion chip routes the processing instructions to the corresponding chips based on the address code carried in the processing instructions.

[0132] Figure 5 A schematic diagram of the motherboard structure provided in an embodiment of this disclosure is shown.

[0133] like Figure 5 As shown, the motherboard includes two central processing units (CPU0 and CPU1), a BMC, an inter-integrated circuit bus expansion chip, and a bus connector. The bus connector is usually located on the motherboard.

[0134] The sixth general purpose input / output interface on the BMC is connected to the second general purpose input / output interface of the bus connector and is used to transmit acquisition commands to the board; the seventh general purpose input / output interface on the BMC is connected to the fourth general purpose input / output interface of the bus connector and is used to receive data corresponding to the acquisition commands returned by the microcontroller unit.

[0135] The BMC has n+1 I2C interfaces (i.e., I2C[0] to I2C[n]), which are connected to the bus connector and used to transmit processing instructions to each board.

[0136] Figure 6 A schematic diagram of a chassis provided in an embodiment of this disclosure is shown.

[0137] like Figure 6 As shown, binary encoding is performed based on the slot number corresponding to each slot; in the first area corresponding to each slot, a hole is punched at the position of 1 in the slot code, while the position of 0 remains unchanged, so that after the board is inserted into the slot, the level of the spring pin inserted with the hole is 1, and the level of the spring pin not inserted with the hole is 0, and the level of all spring pins matches the binary encoding of the slot number.

[0138] Specifically, holes are drilled in the area corresponding to each slot on the chassis according to the corresponding slot number. For example, if the slot number is 5, which corresponds to binary 00101, holes are drilled for bits 0 and 2. After the board is inserted into the slot, the 0th and 2nd spring pins on the board do not contact the chassis due to the holes, and the voltage level is 1; the other spring pins contact the chassis, and the voltage level is 0. Therefore, the MCU of the board with slot number 5 reads slot number 00101.

[0139] Figure 7 A third alternative flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0140] Figure 7 The method is applicable to every board.

[0141] In step S401, the microcontroller determines the first slot number corresponding to the board based on the spring pin level.

[0142] In some embodiments, no address encoding is set for each chip on the board; after the board is inserted into the slot, the MCU on the board reads the spring pin level and determines the first slot number corresponding to the board based on the spring pin level. That is, the first slot number connected to the board.

[0143] In practice, the MCU receives the voltage level of the spring pins; based on the position and voltage level of each spring pin, it determines the binary code corresponding to the slot; based on the binary code corresponding to the slot, it determines the first slot number corresponding to the board.

[0144] In some embodiments, the electronic device chassis connected to the board is configured according to... Figure 6 The diagram shows the drilling process; the structure of the board is as follows. Figure 4 As shown.

[0145] Step S402: Receive the acquisition command from the substrate management controller.

[0146] In some embodiments, the microcontroller receives an acquisition command transmitted from the board management controller to the bus connector via a first general-purpose input / output interface, and then transmitted via a second general-purpose input / output interface of the bus connector. Specifically, the acquisition command is transmitted to the MCU via a sixth general-purpose input / output interface, a third general-purpose input / output interface, and a first general-purpose input / output interface.

[0147] In some embodiments, the microcontroller parses the acquisition instruction to determine the slot number carried in the acquisition instruction.

[0148] Figure 8 A schematic diagram of the acquisition instructions provided in an embodiment of this disclosure is shown.

[0149] like Figure 8 As shown, the acquisition instruction includes a clock calibration segment (8 bits), IDEL (empty), slot number (ID, 5 bits), instruction type identifier (R, 1 bit), data length bits (16 bits), data (N bits), and check bits (bits). The instruction type identifier includes R or W. If it is R, it indicates that the instruction is an acquisition instruction used to obtain information such as the board's part number and board identifier; if it is W, it is a processing instruction used to instruct the corresponding chip on the board to perform the operation corresponding to the processing instruction.

[0150] In some embodiments, if the slot number carried in the acquisition instruction is the first slot number, the board part number is sent to the baseboard management controller through the third general purpose input / output interface. Specifically, the returned data is transmitted to the BMC via the third general purpose input / output interface, the fourth general purpose input / output interface and the seventh general purpose input / output interface.

[0151] Step S403: Receive the address codes of each chip in the board sent by the board management controller.

[0152] In some embodiments, BMC determines an address encoding table based on the part numbers and slot numbers of all boards corresponding to the electronic device; and determines the address code of each chip connected to each board based on the address encoding table. In some embodiments, the address encoding table is determined differently depending on the distribution location of the boards on the electronic device.

[0153] In some embodiments, the MCU receives the address codes of each chip transmitted by the BMC via the sixth general purpose input / output interface, the third general purpose input / output interface and the first general purpose input / output interface.

[0154] Step S404: Based on the address encoding of each chip in the board, adjust the address configuration pin level of each chip in the board.

[0155] In some embodiments, the MCU adjusts the address configuration pin level of each chip on the board based on the address code of each chip through at least one fifth input / output interface in the microcontroller unit, so that the address configuration pin level of each chip on the board matches the address code of each chip.

[0156] In some embodiments, the MCU stores the address codes of each chip on the board into the flash memory of the microcontroller unit so that the electronic device can load the address codes of each chip on the board from the flash memory of the microcontroller unit when it starts up.

[0157] In some optional embodiments, after the address encoding of each chip on the board is configured, the inter-integrated circuit bus expansion chip on the board receives the processing instructions transmitted by the baseboard management controller based on the bus connector; parses the address encoding in the processing instructions, and transmits the processing instructions to the corresponding chip.

[0158] Thus, by using the data processing method provided in this embodiment, address codes are assigned to each chip on the board only after the board is inserted into the slot. This allows different boards with the same part number to be used on the same electronic device, reducing the need for part number expansion on the same board and reducing board management costs. At the same time, it eliminates the need to configure I2C addresses for each chip on the board in advance, reducing configuration costs and making it easier to expand the configuration of electronic devices. In addition, it can also reduce R&D investment.

[0159] Figure 9 A fourth optional flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0160] In some embodiments, the electronic device connects multiple boards via slots; among the multiple boards, at least two boards have the same part number; the two boards with the same part number have different address codes for chips of the same specification installed on them.

[0161] In step S501, the MCU of each board determines the corresponding slot number of the board based on the spring pin.

[0162] The specific steps of step S501 are the same as those of step S401, and will not be repeated here.

[0163] In step S502, the BMC determines the acquisition instruction corresponding to each board number.

[0164] In some embodiments, each acquisition instruction carries a different board number; the BMC determines the acquisition instruction corresponding to each board. For example, the first acquisition instruction is determined based on the second slot number. The second slot number is the slot number corresponding to any board.

[0165] In some embodiments, the BMC transmits any fetch command via the bus connector. Optionally, the BMC can transmit any fetch command to the MCUs of all boards via the bus connector, or it can transmit any fetch command to the MCU of the target board via the bus connector, i.e., in this case, the BMC knows the address codes of each board.

[0166] In some alternative embodiments, the BMC sends only one acquisition command at a time. In response to receiving the slot number and board part number transmitted by the microcontroller within a preset time interval, the BMC sends the next acquisition command through the bus connector.

[0167] Alternatively, if the slot number and board part number are not received from the microcontroller unit within a preset time interval, a next acquisition command is sent via the bus connector. This indicates that no board is connected to the slot corresponding to the slot number.

[0168] In step S503, the MCU of each board receives the acquisition instruction from the baseboard management controller.

[0169] In some embodiments, if the BMC transmits any of the acquisition instructions to the MCUs of all boards via the bus connector, the MCU of each board parses the acquisition instruction and determines whether the slot code carried in the acquisition instruction is consistent with the slot code corresponding to the board; if they are consistent, the board part number and slot code are transmitted to the BMC; if they are inconsistent, no processing is performed.

[0170] In step S504, the BMC determines the address code of each chip on each board based on the slot number and board part number transmitted by the microcontroller unit of each board.

[0171] In some embodiments, the BMC firmware generates a configuration table based on the board's slot number (board ID), board part number, and I2C address.

[0172] In some embodiments, the BMC receives the board part number and slot number returned by each board, determines the distribution information of each board on the chassis based on the board part number and slot number, and determines an address encoding table based on the distribution information. Different distribution information corresponds to different address encoding tables.

[0173] In some embodiments, the BMC transmits the address codes of each chip on different boards to the MCU of each board based on the address encoding table.

[0174] Step S505: Based on the address encoding of each chip in the board, adjust the address configuration pin level of each chip in the board.

[0175] In some embodiments, the general-purpose input / output (GPIO) interface of the microcontroller on the board is respectively connected to the address configuration pins of each chip on the board; after the microcontroller obtains the address code of each chip on the board, it controls the GPIO interface to adjust the level of the address configuration pin of each chip so that the adjusted level of the address configuration pin of each chip matches the address code of each chip.

[0176] Thus, by using the data processing method provided in this embodiment, address codes are assigned to each chip on the board only after the board is inserted into the slot. This allows different boards with the same part number to be used on the same electronic device, reducing the need for part number expansion on the same board and reducing board management costs. At the same time, it eliminates the need to configure I2C addresses for each chip on the board in advance, reducing configuration costs and making it easier to expand the configuration of electronic devices. In addition, it can also reduce R&D investment.

[0177] Figure 10 A first schematic diagram of an electronic device chassis provided in an embodiment of this disclosure is shown; Figure 11 A second schematic diagram of an electronic device chassis provided in an embodiment of this disclosure is shown.

[0178] like Figure 10 or Figure 11 As shown, different slots on the chassis correspond to different slot numbers, and each slot number is unique. Holes can be drilled in the area corresponding to the slot on the chassis to allow the specific slot number to be detected based on the voltage level of a spring-loaded pin.

[0179] circuit boards, such as Figure 4 As shown, each board has an MCU. The address configuration pin of each chip (I2C chip) on the board is connected to the MCU's GPIO. The address configuration pin of the chip and the MCU's GPIO are in a one-to-one relationship, that is, one address configuration pin is connected to one GPIO.

[0180] To implement this function, a 2-wire GPIO bus (hereinafter referred to as the configuration bus, with the two lines referred to as a / b) is required, corresponding to the first and third general purpose input / output (GPIO) interfaces on the MCU. The BMC connects to various boards. For simplified wiring, boards can be interconnected, meaning one board can connect to a nearby board. During connection, the first and third GPIO interfaces of the two MCUs are connected to achieve the connection between the two boards. For example, the first GPIO interface of board A is connected to the first GPIO interface of board B; the third GPIO interface of board A is connected to the third GPIO interface of board B.

[0181] In some embodiments, the MCU can use various flexible models with 32 pins or more. The MCU needs two GPIOs (i.e., a first general purpose input / output interface and a third general purpose input / output interface) to connect to the configuration bus and BMC communication.

[0182] The board is designed with spring-loaded pogo pins. The number of pogo pins, n, depends on the total number of RISERs and BPs. It is ensured that 2n ≥ the total number of RISERs and BPs, so that each slot has a unique slot number and the spring-loaded pins are sufficient to read the complete slot number.

[0183] To ensure compatibility, the rest of the design remains consistent with the original design.

[0184] like Figure 10 or Figure 11 As shown, the spring-loaded ejector pins of each type of board are pulled up at the end of the board. At different locations on the chassis, cutouts determine whether the spring-loaded ejector pins contact the board. After the board is installed in the corresponding position, the spring-loaded ejector pins confirm the slot number by contacting the chassis structure. Figure 10 As shown, for slot number 5, because the 0th and 3rd bits are cut out, the spring pin is not in contact with the chassis, so the MCU reads ID 000101.

[0185] In some embodiments, BMC such as Figure 5 As shown, the BMC sends a message containing a request to read the board location and a configuration information message via line a, i.e., a retrieval command. The retrieval command is as follows: Figure 8 As shown.

[0186] The board and BMC transmit the board's slot number and board part number via line b. After receiving the BMC's acquisition command (read command, or r command), the slot number and board part number are transmitted to the BMC via line b.

[0187] After collecting the board part numbers and locations, BMC matches them according to the configuration table in its own storage and sends the address code (or I2C address) of each board to each board. The MCU on each board confirms the address by pulling down the address configuration pin of each chip through GPIO. The MCU records this address information in the FLASH area so that it will not be lost when power is off. When the server starts, it loads the address information in FLASH first.

[0188] In some embodiments, the board can be connected to the printed circuit board and the chassis by screws; holes are drilled at the spring pin positions of the board according to the slot positions (or slot numbers) to ensure that the spring pins can obtain different values ​​according to their positions after installation.

[0189] In some embodiments, the BMC's functions include: the BMC firmware program forming an address encoding table based on the board ID, slot number, board part number, and chip I2C address (or address encoding); after the BMC starts, it first sends an acquisition command (R command) on line a, i.e., the R / W bit is 0, starting from 00000 to the maximum number of boards; the BMC listens for the reply on line b, and if it exceeds 1 second, it sends the W command for the next board number on line a; the BMC confirms the address encoding of each chip on each board based on at least two of the collected board number, board ID, and board part number, and transmits the address encoding (I2C address) to different boards through line a via the processing command (R command).

[0190] In some embodiments, the MCU on the board listens for information on line a. If it hears an R instruction and the slot number matches, it uploads the slot number and the board part number. If it hears a W instruction, it parses the address instruction that follows.

[0191] Thus, since the I2C address is confirmed after installation, the number of RISER card part numbers is greatly reduced, and it is not necessary to open a new board for each I2C address, which reduces the management cost of the board; the settings are more flexible and there are more expandable configurations; it greatly reduces the investment of R&D manpower and reduces the risk of project delays and new board openings caused by insufficient human evaluation.

[0192] Figure 12 A schematic diagram of a first alternative structure of the data processing apparatus provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0193] In some embodiments, the data processing apparatus is applied to a board including a microcontroller unit, the apparatus including a slot determination unit, a first transmission unit, and a configuration unit.

[0194] The configuration unit is used to number each slot to obtain the slot number corresponding to each slot;

[0195] In the first area corresponding to each slot on the chassis, holes are drilled based on the slot number so that after the board is inserted into the slot, multiple spring pins of the board contact the first area.

[0196] The configuration unit is used to perform binary encoding based on the slot number corresponding to each slot.

[0197] In the first area corresponding to each slot, a hole is punched at the position of 1 in the slot code, while the position of 0 remains unchanged. This ensures that after the board is inserted into the slot, the level of the spring pin with the hole inserted is 1, and the level of the spring pin without the hole inserted is 0. The level of all spring pins matches the binary code of the slot number.

[0198] The configuration unit is used to receive the voltage level of the spring pin;

[0199] The binary code corresponding to the slot is determined based on the position and level of each spring pin;

[0200] The first slot number corresponding to the board is determined based on the binary code corresponding to the slot.

[0201] In some embodiments, the first general-purpose input / output interface of the microcontroller is connected to the second general-purpose input / output interface of the bus connector, and is used to receive acquisition instructions transmitted to the board by the baseboard management controller through the bus connector;

[0202] The third general-purpose input / output interface of the microcontroller is connected to the fourth general-purpose input / output interface of the bus connector, and is used to transmit the data corresponding to the acquisition command to the board management controller;

[0203] At least one fifth general-purpose input / output interface of the microcontroller is connected to the address configuration pins of other chips on the board, respectively, for configuring the address configuration pin levels of each chip.

[0204] In some embodiments, the board is provided with an inter-integrated circuit bus expansion chip, which is connected to a bus connector and is used to receive control commands transmitted to the board through the bus connector from the baseboard controller.

[0205] The inter-integrated circuit bus expansion chip transmits the control command to the chip corresponding to the address code based on the address code included in the control command.

[0206] The first transmission unit is specifically used for the microcontroller unit to receive the acquisition instruction based on the first general-purpose input / output interface, and to determine the slot number carried in the acquisition instruction;

[0207] If the slot number carried in the acquisition command is the first slot number, the board part number and the first slot number are transmitted to the board management controller through the third general purpose input / output interface.

[0208] In some embodiments, the address codes of each chip on the board are determined based on an address code table;

[0209] The address encoding table is determined based on the board part numbers and slot numbers of all boards on the electronic device.

[0210] The configuration unit is specifically used to adjust the address configuration pin level of each chip based on the address encoding of each chip on the board through at least one fifth input / output interface in the microcontroller unit, so that the address configuration pin level of each chip on the board matches the address encoding of each chip.

[0211] In some embodiments, the configuration unit is further configured to store the address codes of each chip on the board into the flash memory of the microcontroller unit, so that the electronic device can load the address codes of each chip on the board from the flash memory of the microcontroller unit when it starts up.

[0212] In some embodiments, the on-board integrated circuit bus expansion chip receives processing instructions transmitted by the baseboard management controller via a bus connector;

[0213] The address code in the processing instruction is parsed, and the processing instruction is transmitted to the corresponding chip.

[0214] In some embodiments, the electronic device connects multiple boards via slots;

[0215] Of the plurality of circuit boards, at least two circuit boards have the same part number;

[0216] Two boards with the same part number may have different address codes for chips of the same specifications.

[0217] Figure 13 A schematic diagram of a second alternative structure of the data processing apparatus provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0218] In some embodiments, the data processing apparatus includes an instruction determination unit, a second transmission unit, and an address encoding determination unit.

[0219] The instruction determining unit is used to determine multiple acquisition instructions based on the slot numbers of multiple slots in the electronic device;

[0220] The second transmission unit is used to transmit the plurality of acquisition instructions to the microcontroller units of the plurality of boards connected to the electronic device via a bus connector;

[0221] The address encoding determination unit is used to determine the address encoding of each chip on each board based on the slot number and board part number transmitted by the microcontroller unit of each board.

[0222] The second transmission unit is further configured to transmit the address codes of each chip on each board to the microcontroller unit of each board through the bus connector, so that the microcontroller unit adjusts the address configuration pin level of each chip on the board based on the address codes of each chip in the board, so that the adjusted address configuration pin level of each chip matches the address code of each chip.

[0223] The instruction determination unit is specifically used to determine the position of each board based on the slot number; and to determine the address encoding table based on the position and part number of each board.

[0224] The address code of each chip connected to each board is determined based on the address encoding table.

[0225] The second transmission unit is specifically used to determine the first acquisition instruction based on the second slot number;

[0226] The first acquisition instruction is transmitted via a bus connector to the microcontroller unit of multiple boards connected to the electronic device;

[0227] In response to receiving the slot number and board part number transmitted by the microcontroller unit within a preset time interval, a second acquisition instruction is determined based on the third slot number, and the second acquisition instruction is sent through the bus connector;

[0228] Alternatively, in response to the failure to receive the slot number and board part number transmitted by the microcontroller unit within a preset time interval, a second acquisition command is determined based on the third slot number, and the second acquisition command is sent through the bus connector.

[0229] According to embodiments of this disclosure, this disclosure also provides an electronic device and a readable storage medium.

[0230] Figure 14 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0231] like Figure 14 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0232] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0233] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as data processing methods. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform data processing methods by any other suitable means (e.g., by means of firmware).

[0234] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0235] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0236] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0237] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0238] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0239] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0240] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this disclosure does not impose any limitations herein.

[0241] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0242] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, A method for use with circuit boards including microcontrollers, wherein the chassis of the electronic device corresponding to the circuit board includes multiple slots, each slot is numbered to obtain a slot number; in a first area corresponding to each slot on the chassis, holes are drilled based on the slot number, so that after the circuit board is inserted into the slot, multiple spring-loaded pins of the circuit board contact the first area, the method comprising: Binary encoding is performed based on the slot number corresponding to each slot; in the first area corresponding to each slot, a hole is punched at the position of 1 in the slot code, so that after the board is inserted into the slot, the level of the spring pin inserted into the hole is 1, the level of the spring pin not inserted into the hole is 0, and the level of all spring pins matches the binary encoding of the slot number. Receive the voltage level of the spring pins; determine the binary code corresponding to the slot based on the position and voltage level of each spring pin; determine the first slot number corresponding to the board based on the binary code corresponding to the slot. Receive an acquisition instruction from the substrate management controller. If the slot number carried in the acquisition instruction is the first slot number, then send the board part number to the substrate management controller. The address codes of each chip in the board are sent by the baseboard management controller; wherein the address codes of each chip are determined based on the part number and slot number of all boards corresponding to the electronic device. Based on the address codes of each chip in the board, adjust the address configuration pin levels of each chip in the board so that the adjusted address configuration pin levels of each chip match the address codes of each chip. The microcontroller stores the address codes of each chip on the board into the flash memory of the microcontroller so that the electronic device can load the address codes of each chip on the board from the flash memory of the microcontroller when it starts up.

2. The method according to claim 1, characterized in that, The method further includes: The first general-purpose input / output interface of the microcontroller is connected to the second general-purpose input / output interface of the bus connector, and is used to receive acquisition instructions transmitted to the board by the baseboard management controller through the bus connector; The third general-purpose input / output interface of the microcontroller is connected to the fourth general-purpose input / output interface of the bus connector, and is used to transmit the data corresponding to the acquisition instruction to the board management controller; At least one fifth general-purpose input / output interface of the microcontroller is connected to the address configuration pins of other chips on the board, respectively, for configuring the address configuration pin levels of each chip.

3. The method according to claim 2, characterized in that, The method further includes: The board is provided with an inter-integrated circuit bus expansion chip, which is connected to a bus connector and is used to receive control commands transmitted from the baseboard controller to the board through the bus connector. The inter-integrated circuit bus expansion chip transmits the control command to the chip corresponding to the address code based on the address code included in the control command.

4. The method according to claim 1, characterized in that, The method of receiving the acquisition instruction from the substrate management controller, if the slot number carried in the acquisition instruction is the first slot number, then sending the board part number to the substrate management controller, includes: The microcontroller receives the acquisition instruction based on the first general-purpose input / output interface and determines the slot number carried in the acquisition instruction; If the slot number carried in the acquisition command is the first slot number, the board part number and the first slot number are transmitted to the board management controller through the third general purpose input / output interface.

5. The method according to claim 1, characterized in that, The address codes of each chip on the board are determined based on the address code table; The address encoding table is determined based on the board part number and slot number of all boards on the electronic device.

6. The method according to claim 1, characterized in that, The step of adjusting the address configuration pin levels of each chip in the board based on the address encoding of each chip in the board includes: Based on the address codes of each chip on the board, the address configuration pin levels of each chip are adjusted through at least one fifth input / output interface in the microcontroller unit so that the address configuration pin levels of each chip on the board match the address codes of each chip.

7. The method according to claim 1, characterized in that, After adjusting the address configuration pin levels of each chip in the board based on the address encoding of each chip in the board, the method further includes: The inter-integrated circuit bus expansion chip receives processing instructions transmitted by the substrate management controller based on the bus connector; The address code in the processing instruction is parsed, and the processing instruction is transmitted to the corresponding chip.

8. The method according to claim 1, characterized in that, Electronic devices connect multiple boards using slots; Of the plurality of circuit boards, at least two circuit boards have the same part number; Two boards with the same part number may have different address codes for chips of the same specifications.

9. A data processing method, characterized in that, The method, applied to a baseboard management controller of an electronic device according to any one of claims 1 to 8, comprises: Based on the slot numbers of multiple slots in an electronic device, multiple acquisition instructions are determined; The multiple acquisition commands are transmitted via a bus connector to the microcontroller units of multiple boards connected to the electronic device; Based on the slot number and board part number transmitted by the microcontroller unit of each board, the address code of each chip on each board is determined. The address codes of each chip on each board are transmitted to the microcontroller unit of each board through the bus connector, so that the microcontroller unit can adjust the address configuration pin level of each chip on the board based on the address code of each chip, so that the adjusted address configuration pin level of each chip matches the address code of each chip.

10. The method according to claim 9, characterized in that, The address encoding of each chip on each board is determined based on the slot number and board part number transmitted by the microcontroller unit of each board, including: The location of each board is determined based on its slot number; The address coding table is determined based on the location and part number of each board; The address code of each chip connected to each board is determined based on the address encoding table.

11. The method according to claim 9, characterized in that, The microcontroller unit that transmits the multiple acquisition commands to multiple boards connected to the electronic device via a bus connector includes: The first acquisition instruction is determined based on the second slot number; The first acquisition instruction is transmitted via a bus connector to the microcontroller unit of multiple boards connected to the electronic device; In response to receiving the slot number and board part number transmitted by the microcontroller unit within a preset time interval, a second acquisition instruction is determined based on the third slot number, and the second acquisition instruction is sent through the bus connector; Alternatively, in response to the failure to receive the slot number and board part number transmitted by the microcontroller unit within a preset time interval, a second acquisition command is determined based on the third slot number, and the second acquisition command is sent through the bus connector.

12. A data processing apparatus, characterized in that, An application to a circuit board including a microcontroller unit, wherein the chassis of the electronic device corresponding to the circuit board includes multiple slots, each slot is numbered to obtain a slot number; in a first area corresponding to each slot on the chassis, holes are drilled based on the slot number, so that after the circuit board is inserted into the slot, multiple spring-loaded pins of the circuit board contact the first area, the device comprising: The slot determination unit is used to perform binary encoding based on the slot number corresponding to each slot; in the first area corresponding to each slot, a hole is punched at the position of 1 in the slot encoding, so that after the board is inserted into the slot, the level of the spring pin inserted into the hole is 1, and the level of the spring pin not inserted into the hole is 0, and the level of all spring pins matches the binary encoding of the slot number; the unit receives the level of the spring pins; determines the binary encoding corresponding to the slot based on the position and level of each spring pin; and determines the first slot number corresponding to the board based on the binary encoding corresponding to the slot. The first transmission unit is used to receive the acquisition instruction from the substrate management controller. If the slot number carried in the acquisition instruction is the first slot number, the board part number is sent to the substrate management controller. The first transmission unit is further configured to receive the address codes of each chip in the board sent by the baseboard management controller; wherein the address codes of each chip are determined based on the part number and slot number of all boards corresponding to the electronic device; The configuration unit is used to adjust the address configuration pin level of each chip in the board based on the address code of each chip in the board, so that the adjusted address configuration pin level of each chip matches the address code of each chip; and to store the address code of each chip on the board into the flash memory of the microcontroller unit; so that the electronic device can load the address code of each chip on the board from the flash memory of the microcontroller unit when it starts up.

13. A data processing apparatus, characterized in that, A board management controller for an electronic device according to any one of claims 1 to 8, the device comprising: The instruction determination unit is used to determine multiple acquisition instructions based on the slot numbers of multiple slots in an electronic device. The second transmission unit is used to transmit the multiple acquisition instructions to the microcontroller units of multiple boards connected to the electronic device via a bus connector; The address encoding determination unit is used to determine the address encoding of each chip on each board based on the slot number and board part number transmitted by the microcontroller unit of each board. The second transmission unit is further configured to transmit the address codes of each chip on each board to the microcontroller unit of each board through the bus connector, so that the microcontroller unit adjusts the address configuration pin level of each chip on the board based on the address codes of each chip in the board, so that the adjusted address configuration pin level of each chip matches the address code of each chip.

14. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8; Or perform the method according to any one of claims 9-11.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-8; Or perform the method according to any one of claims 9-11.

16. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-8; Or perform the method according to any one of claims 9-11.

Images