Multi-channel parallel high-speed data transmission system and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the field of multi-channel parallel high-speed data transmission, and particularly relates to a multi-channel parallel high-speed data transmission system and method based on an FPGA. The system comprises a multi-path parallel data input module, a parallel-serial conversion module, a high-speed serial sending module, an optical module, a matching optical module, a high-speed serial receiving module, a serial-parallel conversion module and a multi-path parallel data analysis module which are connected in sequence, wherein the multi-path parallel data input module, the parallel-serial conversion module and the high-speed serial sending module are integrated and embedded in an FPGA chip, and the high-speed serial receiving module, the serial-parallel conversion module and the multi-path parallel data analysis module are integrated and embedded in another FPGA chip. The method disclosed by the invention is designed based on the system disclosed by the invention, the scheduling logic complexity is greatly reduced, the signal integrity is efficiently improved, the dynamic synchronism of the data stream is ensured, and the resource utilization rate is maximized.

Description

Technical Field

[0001] This invention belongs to the field of multi-channel parallel high-speed data transmission, specifically relating to a multi-channel parallel high-speed data transmission system and method based on FPGA. Background Technology

[0002] Existing technologies for high-speed multi-channel transmission often employ three methods: Method 1: Time-division multiplexing of multiple SERDES channels to increase the total bandwidth, but this requires complex scheduling logic and has low channel utilization, resulting in significant bandwidth waste and high scheduling logic complexity; Method 2: Using a fixed arbitration strategy, but this method cannot dynamically adapt to data stream priorities; Method 3: Using cross switches to achieve multi-channel data routing, but this method results in dense cabling, poor signal integrity, and high resource occupancy.

[0003] With the explosive growth in demand for 5G communication, data center interconnection, and high-performance computing, FPGAs have become a core carrier for high-speed data transmission due to their low latency and reconfigurability. Researchers have already applied FPGAs to multi-channel data transmission; however, in traditional FPGA designs, multi-channel parallel data transmission suffers from increased bit error rates and limited transmission efficiency due to clock skew, path delay differences, and signal crosstalk. Furthermore, it is difficult to achieve efficient scheduling and maximize bandwidth utilization of multi-channel parallel data within limited FPGA resources.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and propose a multi-channel parallel high-speed data transmission system and method based on FPGA. This method utilizes a serial transmission method that rationally groups packets using a clock synchronization network and plans wiring paths in different areas, which greatly reduces the complexity of scheduling logic, efficiently improves signal integrity, ensures dynamic synchronization of data streams, and maximizes resource utilization.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: On one hand, the present invention provides a multi-channel parallel high-speed data transmission system based on FPGA, including a multi-channel parallel data input module, a parallel-to-serial conversion module, a high-speed serial transmission module, an optical module, a matching optical module, a high-speed serial receiving module, a serial-to-parallel conversion module, and a multi-channel parallel data parsing module connected in sequence. The multi-channel parallel data input module, parallel-to-serial conversion module, and high-speed serial transmission module are integrated and embedded on one FPGA chip, while the high-speed serial receiving module, serial-to-parallel conversion module, and multi-channel parallel data parsing module are integrated and embedded on another FPGA chip.

[0007] On the other hand, the present invention provides a multi-channel parallel high-speed data transmission method based on FPGA, which, based on the multi-channel parallel high-speed data transmission system described above, includes the following process: Step 1: The received original multi-channel synchronous parallel data stream is divided into packets using the multi-channel parallel data input module, and the number of packets is determined accordingly. x Number of independent sub-channels; Step 2: Convert the parallel-to-serial conversion module to... x The data streams of each packet are dynamically reordered and framed into a high-speed serial data stream with a set data rate for transmission. Step 3: The high-speed serial data stream sent in Step 2 is CRC generated, encoded, and pre-emphasized by the high-speed serial transmission module, and then serialized to the set rate by the high-speed serial transceiver inside the FPGA chip. Step 4: The optical signal is transmitted from the optical module to the matching optical module, and then the matching optical module performs photoelectric conversion to convert the received optical signal into an electrical signal for output. Step 5: The received electrical signal is deserialized, equalized, decoded, and CRC checked by the high-speed serial transceiver inside the FPGA chip through the high-speed serial receiving module, and then converted into a high-speed serial data stream corresponding to the parallel-to-serial conversion module. Step 6: The high-speed serial data stream is parsed and sorted into frames using a serial-to-parallel conversion module. x A synchronous parallel data stream; Step 7: The data is parsed using a multi-path parallel data parsing module. x The synchronous parallel data stream is unpacked into the original multi-channel synchronous parallel data stream.

[0008] Furthermore, in step 1, the number of packages... x It is based on the internal resource structure of the FPGA chip, taking a power of 2, that is, 2. ^1 ~2 ^11 .

[0009] Furthermore, in step 1, the number of multiple independent sub-channels and the number of packets... x They are identical, and each sub-channel contains a dedicated clock domain, data buffer, and routing resources.

[0010] Furthermore, the dedicated clock domain uses an asymmetric PLL architecture to generate a multi-phase clock, and the clock of each sub-channel is independently adjustable.

[0011] Furthermore, in step 2, the set data rate is matched with the operating clock frequency set by the FPGA chip.

[0012] Furthermore, in step 3, the set rate is the fiber optic transmission line rate.

[0013] Furthermore, the multi-path parallel high-speed data transmission method employs a regional planning wiring path method before transmitting data to avoid the overlap of multiple parallel data streams within the same physical area.

[0014] Furthermore, the regional planning cabling path method relies on the comprehensive tools in the Vivado design software to perform regional layout cabling planning for the parallel data of each group of packages.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The method provided by this invention is designed based on the system of this invention, and the method brings the following advantages: Improved bandwidth utilization: By rationally grouping channels to avoid idle channels, the measured bandwidth utilization rate reached 80% (the existing solution only achieves 70%). Latency reduction: Distributed clock synchronization reduces data stream latency within a group by more than 50%; Signal integrity enhancement: High-speed fiber optic transmission interference suppression technology reduces crosstalk noise by 15dB, improves the high reliability of parallel data transmission, and maximizes resource utilization. Resource utilization optimization: Regional planning cabling path method reduces cabling intersections to improve the high-speed signal integrity of parallel data and intra-group data synchronization (e.g., Figure 3 and Figure 4 (Comparison), logic resources are saved by about 30%. Attached Figure Description

[0016] The accompanying drawings are incorporated in and form part of this specification, and together with the description serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the multi-channel parallel high-speed data transmission system of the present invention; Figure 2 This is a schematic diagram illustrating the conversion between 73.728MHz*16b data and 32 192*12KHz*16b data in an embodiment of the present invention. Figure 3 This is a schematic diagram of a wiring path without regional planning in an embodiment of the present invention; Figure 4 This is a schematic diagram of the regional planning wiring path adopted in an embodiment of the present invention; Figure 5This is a schematic diagram of the transmission of 73.728MHz*16b high-speed data in the high-speed serial transmission module according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the transmission of 73.728MHz*16b high-speed data in a high-speed serial receiving module according to an embodiment of the present invention. Detailed Implementation

[0019] Exemplary embodiments will now be described in detail. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples consistent with some aspects of the invention as detailed in the appended claims.

[0020] Example 1 Please see Figure 1 This invention provides a multi-channel parallel high-speed data transmission system based on FPGA, comprising a multi-channel parallel data input module, a parallel-to-serial conversion module, a high-speed serial transmission module, an optical module (electro-optical converter), a matching optical module (photoelectric converter), a high-speed serial receiving module, a serial-to-parallel conversion module, and a multi-channel parallel data parsing module connected in sequence. The multi-channel parallel data input module, parallel-to-serial conversion module, and high-speed serial transmission module are integrated and embedded on one FPGA chip (transmitter), while the high-speed serial receiving module, serial-to-parallel conversion module, and multi-channel parallel data parsing module are integrated and embedded on another FPGA chip (receiver).

[0021] Example 2 This invention provides a multi-channel parallel high-speed data transmission method based on FPGA, which, based on the multi-channel parallel high-speed data transmission system described above, includes the following process: Step 1: The received original multi-channel synchronous parallel data stream is divided into packets by the multi-channel parallel data input module, and multiple independent sub-channels are divided according to the number of packets x (each packet is transmitted in a separate sub-channel). The number of packages x It is based on the internal resource structure of the FPGA chip, taking a power of 2, that is, 2. ^1 ~2 ^11 .

[0022] Number of independent sub-channels and number of packets x They are identical, and each sub-channel contains a dedicated clock domain, data buffer, and routing resources.

[0023] The dedicated clock domain uses an asymmetric PLL architecture to generate a multi-phase clock, with the clock of each sub-channel being independently adjustable, eliminating global clock skew.

[0024] Step 2: Dynamically reorder and frame the x data streams into a high-speed serial data stream with a set data rate using a parallel-to-serial conversion module; The set data rate is matched with the operating clock frequency set by the FPGA chip.

[0025] Step 3: The high-speed serial data stream sent in Step 2 is CRC generated, encoded, and pre-emphasized by the high-speed serial transmission module, and then serialized to the set rate by the high-speed serial transceiver inside the FPGA chip. The set rate is the fiber optic transmission line rate.

[0026] Step 4: The optical signal is transmitted from the optical module to the matching optical module, and then the matching optical module performs photoelectric conversion to convert the received optical signal into an electrical signal for output. Step 5: The received electrical signal is deserialized, equalized, decoded, and CRC checked by the high-speed serial transceiver inside the FPGA chip through the high-speed serial receiving module, and then converted into a high-speed serial data stream corresponding to the parallel-to-serial conversion module. Step 6: The high-speed serial data stream is parsed and sorted into frames using a serial-to-parallel conversion module. x A synchronous parallel data stream; Step 7: The data is parsed using a multi-path parallel data parsing module. x The synchronous parallel data stream is unpacked into the original multi-channel synchronous parallel data stream.

[0027] Furthermore, the multi-path parallel high-speed data transmission method employs a regional planning wiring path method before transmitting data to avoid the overlap of multiple parallel data streams within the same physical area.

[0028] Furthermore, the regional planning cabling path method relies on the comprehensive tools in Xilinx's Vivado design software to perform regional layout cabling planning for the parallel data of each group of packages.

[0029] To enable those skilled in the art to better understand the operation of this invention, the inventors provide the following examples: The system employs a regional planning and routing method, utilizing the synthesis tools in Xilinx's Vivado design software to plan the regional layout and routing of key modules within the FPGA.

[0030] like Figure 2 As shown, the multi-channel parallel data input module includes 6144 synchronous parallel data streams with a data rate of 12KHz*16b, and the data source is controllable. It is used to reasonably package the 6144 synchronous parallel data streams with a data rate of 12KHz*16b into 32 synchronous parallel data streams with a data rate of 192*12KHz*16b. The grouping value depends on the resource availability of the selected FPGA chip. Based on the chip's internal resource structure, the grouping value (number of groups) can be 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, or 2048. However, due to the limited distribution of resources within the chip, a larger value results in more partitions, more difficult logic routing, and more interference between signals. In this embodiment, the grouping number is set to 32.

[0031] Furthermore, the parallel-to-serial conversion module dynamically reorders and frames 32 synchronous parallel data streams with a data rate of 192*12KHz*16b into a high-speed serial data stream with a data rate of 73.728MHz*16b; where 73.728MHz is the logic clock frequency of the FPGA chip and 16b is the parallel data bit width.

[0032] like Figure 5 As shown, the high-speed serial transmission module performs a series of operations such as CRC generation, encoding, and pre-emphasis on the high-speed serial data stream, and then serializes it into 1.8432Gbps through the high-speed serial transceiver inside the FPGA before sending it out. The fiber optic transmission rate of 1.8432 Gbps is calculated using the following formula: The fiber optic transmission line rate L = effective data rate S * 1.25 (8b / 10b encoding) * 1.25 (transmission efficiency); The effective data rate S and the parallel data bit width P are calculated using the following formulas: Number of parallel data paths N * Source data rate of each path M * Data width of each path W = Logic clock K * Parallel data width P = Effective data rate S.

[0033] Furthermore, the optical module converts the electrical signals from the high-speed serial transmission module into optical signals, which are then transmitted at high speed via optical fiber. like Figure 6 As shown, the high-speed serial receiving module converts the gigabit data stream into a high-speed serial data stream with a data rate of 73.728MHz*16b after deserialization, equalization, decoding, and CRC verification operations by the high-speed serial transceiver inside the FPGA. Furthermore, the serial-to-parallel conversion module performs frame parsing and sorting of the high-speed serial data stream with a data rate of 73.728MHz*16b into 32 synchronous parallel data streams with a data rate of 192*12KHz*16b. Furthermore, the multi-channel parallel data parsing module unpacks 32 synchronous parallel data streams with a data rate of 192*12KHz*16b into 6144 synchronous parallel data streams with a data rate of 12KHz*16b.

[0034] It should be noted that the above logic analysis data shows that it supports multiple parallel 1.47456Gbps data streams with a total rate of 1.8432Gbps on a Xilinx 7 series FPGA; application scenarios: suitable for optical communication and shortwave communication processing systems. Expansion Notes: The solution is adaptable to different FPGA architectures and supports flexible expansion by adjusting the number of sub-channels.

[0035] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.

[0036] It should be understood that the present invention is not limited to the content already described above, and various modifications and changes can be made without departing from its scope. The scope of the present invention is limited only by the appended claims.

Claims

1. A multi-channel parallel high-speed data transmission system based on FPGA, characterized in that, It includes a multi-channel parallel data input module, a parallel-to-serial conversion module, a high-speed serial transmission module, an optical module, a matching optical module, a high-speed serial receiving module, a serial-to-parallel conversion module, and a multi-channel parallel data parsing module connected in sequence. The multi-channel parallel data input module, parallel-to-serial conversion module, and high-speed serial transmission module are integrated and embedded on one FPGA chip, while the high-speed serial receiving module, serial-to-parallel conversion module, and multi-channel parallel data parsing module are integrated and embedded on another FPGA chip.

2. A method for multi-channel parallel high-speed data transmission based on FPGA, characterized in that, The multi-channel parallel high-speed data transmission system according to claim 1 includes the following process: Step 1: The received original multi-channel synchronous parallel data stream is divided into packets using the multi-channel parallel data input module, and the number of packets is determined accordingly. x Number of independent sub-channels; Step 2: Convert the parallel-to-serial conversion module to... x The data streams of each packet are dynamically reordered and framed into a high-speed serial data stream with a set data rate for transmission. Step 3: The high-speed serial data stream sent in Step 2 is CRC generated, encoded, and pre-emphasized by the high-speed serial transmission module, and then serialized to the set rate by the high-speed serial transceiver inside the FPGA chip. Step 4: The optical signal is transmitted from the optical module to the matching optical module, and then the matching optical module performs photoelectric conversion to convert the received optical signal into an electrical signal for output. Step 5: The received electrical signal is deserialized, equalized, decoded, and CRC checked by the high-speed serial transceiver inside the FPGA chip through the high-speed serial receiving module, and then converted into a high-speed serial data stream corresponding to the parallel-to-serial conversion module. Step 6: The high-speed serial data stream is parsed and sorted into frames using a serial-to-parallel conversion module. x A synchronous parallel data stream; Step 7: The data is parsed using a multi-path parallel data parsing module. x The synchronous parallel data stream is unpacked into the original multi-channel synchronous parallel data stream.

3. The multi-channel parallel high-speed data transmission method according to claim 2, characterized in that, In step 1, the number of packages x It is based on the internal resource structure of the FPGA chip, taking a power of 2, that is, 2. ^1 ~2 ^11 .

4. The multi-channel parallel high-speed data transmission method according to claim 2, characterized in that, In step 1, the number of multiple independent sub-channels and the number of packets... x They are identical, and each sub-channel contains a dedicated clock domain, data buffer, and routing resources.

5. The multi-channel parallel high-speed data transmission method according to claim 4, characterized in that, The dedicated clock domain uses an asymmetric PLL architecture to generate a multi-phase clock, and the clock of each sub-channel is independently adjustable.

6. The multi-channel parallel high-speed data transmission method according to claim 2, characterized in that, In step 2, the set data rate is matched with the operating clock frequency set by the FPGA chip.

7. The multi-channel parallel high-speed data transmission method according to claim 2, characterized in that, In step 3, the set rate is the fiber optic transmission line rate.

8. The multi-channel parallel high-speed data transmission method according to claim 2, characterized in that, The proposed multi-path parallel high-speed data transmission method employs a regional planning and cabling path method before data transmission to avoid overlapping of multiple parallel data streams within the same physical area.

9. The multi-channel parallel high-speed data transmission method according to claim 8, characterized in that, The regional planning cabling path method relies on the comprehensive tools in the Vivado design software to plan the regional layout and cabling of parallel data for each group of packages.

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