Communication method between core particles and core particles

Abstract

The invention relates to the technical field of computers, in particular to a communication method between core particles and the core particles. The method comprises the following steps: waking up D2D interconnection of a first core grain and D2D interconnection of a second core grain through a bypass within a preset time before communication data sent by at least one first function module of the first core grain reaches the D2D interconnection of the first core grain; wherein the shortest preset time is the time required for awakening the D2D interconnection of the first core particle or the D2D interconnection of the second core particle. According to the embodiment of the invention, the power consumption can be reduced while the communication speed between the core particles is ensured.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a chip-to-chip communication method and a chip. Background Technology

[0002] Chiplet, also known as "chiplet" or "small chip," is a technology that breaks down a large, feature-rich silicon die into multiple chiplets. These pre-manufactured chiplets, each capable of performing specific functions, are combined and integrated into a system-on-a-chip (SoC) through advanced packaging methods (such as 3D packaging).

[0003] High-speed die-to-die interconnects are a key technology for the implementation of Chiplet technology. When designing the interconnect interfaces between chips, chip design companies need to consider improving data throughput, reducing transmission latency and bit error rate, while also reducing the overall power consumption of the chip interconnects.

[0004] Modern CPU designs, especially server CPU designs, have widely adopted the chiplet architecture. The core and main memory controller may reside on different chips, and the core may need to access the main memory controller via a D2D interconnect. CPU performance is extremely sensitive to memory access latency, which is a crucial performance metric that can significantly impact the performance of applications requiring fast response times.

[0005] How to reduce communication delay between chips while controlling system power consumption is an urgent problem to be solved. Summary of the Invention

[0006] To address the problems in the prior art, embodiments of this specification provide an inter-chip communication method and a chip that can maintain high transmission speed while reducing power consumption.

[0007] This specification provides an embodiment of an inter-chip communication method, including, at a predetermined time before communication data sent by at least one first functional module of a first chip arrives at the D2D interconnect of the first chip, waking up the D2D interconnect of the first chip and the D2D interconnect of the second chip by bypassing.

[0008] The shortest predetermined time is the time required to wake up the D2D interconnect of the first chip or the D2D interconnect of the second chip.

[0009] As a further aspect of this specification,

[0010] Communication data sent by at least one first functional module of the first core reaches the D2D interconnect of the first core through a data bus;

[0011] The D2D interconnect of the first core sends the communication data to the D2D interconnect of the second core through a physical link.

[0012] At least one first functional module of the first chip wakes up the D2D interconnect of the first chip at a predetermined time via a first bypass, and wakes up the D2D interconnect of the second chip at the predetermined time via a second bypass.

[0013] As a further aspect of this specification, the first bypass includes at least one portion of the substrate trace between the first functional module and the D2D interconnect of the first chip; the second bypass includes at least one portion of the substrate trace between the first functional module and the D2D interconnect of the second chip.

[0014] As another further aspect of this specification,

[0015] The first functional module of the first chip wakes up the D2D interconnect of the first chip at a predetermined time via a first bypass, and wakes up the D2D interconnect of the second chip at the predetermined time via a second bypass, further comprising:

[0016] The first functional module, according to the predetermined time, directly wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip through the first bypass and the second bypass, respectively.

[0017] As another further aspect of this specification,

[0018] The first functional module, according to the predetermined time, directly wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip through the first bypass and the second bypass, respectively, further including...

[0019] Using the timer inside the first functional module, the D2D interconnect of the first chip is directly woken up through the first bypass according to the predetermined time, and the D2D interconnect of the second chip is directly woken up through the second bypass.

[0020] As another further aspect of this specification,

[0021] The first functional module of the first chip wakes up the D2D interconnect of the first chip at a predetermined time via a first bypass, and wakes up the D2D interconnect of the second chip at the predetermined time via a second bypass, further comprising:

[0022] Using a first timer in the first chip, the D2D interconnect of the first chip is woken up via the first bypass according to the predetermined time, and the D2D interconnect of the second chip is woken up via the second bypass.

[0023] As another further aspect of this specification,

[0024] Using a first timer in the first chip, waking up the D2D interconnect of the first chip via the first bypass according to the predetermined time further includes,

[0025] The first bypass includes a first wake-up signal transmitting interface, a first wake-up signal receiving interface, and the first timer;

[0026] The first functional module transmits a wake-up signal to the substrate traces through the first wake-up signal transmission interface;

[0027] The first wake-up signal is transmitted to the first timer through the substrate traces and the first wake-up signal receiving interface;

[0028] The first timer sends the wake-up signal to the D2D interconnect of the first chip according to the predetermined time.

[0029] As another further aspect of this specification,

[0030] Using a first timer in the first chip, waking up the D2D interconnect of the second chip via the second bypass according to the predetermined time further includes,

[0031] The wake-up signal is transmitted to the second wake-up signal receiving interface of the second chip through the substrate traces and the first wake-up signal receiving interface;

[0032] The second wake-up signal receiving interface of the second chip transmits the wake-up signal to the second timer of the second chip through the substrate traces;

[0033] The second timer of the second chip sends the wake-up signal to the D2D interconnect of the second chip according to the predetermined time.

[0034] As a further aspect of this specification, the D2D interconnect of the second chip is woken up via the second bypass according to the predetermined time using a first timer in the first chip, further comprising:

[0035] The first timer sends the wake-up signal to the D2D interconnect of the first chip according to the predetermined time, and transmits the wake-up signal to the D2D interconnect of the second chip through the first wake-up signal receiving interface, the substrate trace, and the second wake-up signal receiving interface of the second chip.

[0036] As a further aspect of this specification, waking up the D2D interconnect of the second chip via the second bypass using a first timer in the first chip according to the predetermined time further includes the first timer sending the wake-up signal to the D2D interconnect of the first chip according to the predetermined time, and transmitting the wake-up signal to the D2D interconnect of the second chip through the physical link between the D2D interconnect of the first chip and the D2D interconnect of the second chip.

[0037] As another further aspect of this specification,

[0038] The timer, which wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip according to a predetermined time, further includes,

[0039] The D2D interconnect of the first chip and the D2D interconnect of the second chip are woken up according to a preset delay time and the predetermined time, wherein the preset delay time is the time it takes for the communication data sent by the first functional module to reach the D2D interconnect of the first chip through the data bus.

[0040] As another further aspect of this specification,

[0041] After a predetermined time before the communication data sent by at least one first functional module of the first chip arrives at the D2D interconnect of the first chip, and after waking up the D2D interconnect of the first chip and the D2D interconnect of the second chip, the process further includes...

[0042] The D2D interconnect of the first chip is activated before or simultaneously with the arrival of the communication data at the D2D interconnect of the first chip; the D2D interconnect of the second chip is activated before or simultaneously with the arrival of the communication data at the D2D interconnect of the second chip.

[0043] The communication data is transmitted to the second core through the D2D interconnect of the first core after it is woken up and the D2D interconnect of the second core.

[0044] The D2D interconnect of the first chip and the D2D interconnect of the second chip enter an energy-saving state.

[0045] As a further aspect of this specification, the communication data, after being transmitted to the second core via the D2D interconnect of the first core after wake-up and the D2D interconnect of the second core, also includes...

[0046] After the communication data is transmitted to the second chip, after a predetermined time threshold, the D2D interconnect of the first chip and the D2D interconnect of the second chip enter an energy-saving state.

[0047] As a further aspect of this specification, the minimum preset time is the maximum value of the time required to wake up the D2D interconnect of the first chip or the D2D interconnect of the second chip.

[0048] This specification also provides a core element, comprising,

[0049] At least one first functional module, D2D interconnect of the first core;

[0050] At least one of the first functional modules is configured to implement the function of the chip and, at a predetermined time before the transmitted communication data arrives at the D2D interconnect of the first chip, wake up the D2D interconnect of the first chip and the D2D interconnect of the second chip by bypass; wherein the predetermined time is at least the time required to wake up the D2D interconnect of the first chip or the D2D interconnect of the second chip.

[0051] As another further aspect of this specification, it also includes,

[0052] A data bus is configured such that communication data sent by at least one first functional module reaches the D2D interconnect of the first core via the data bus;

[0053] The physical link is configured to transmit the communication data sent by the D2D interconnect of the first core to the D2D interconnect of the second core;

[0054] A first bypass is configured such that at least one of the first functional modules wakes up the D2D interconnect of the first chip ahead of the predetermined time via the first bypass.

[0055] The second bypass is configured such that at least one of the first functional modules wakes up the D2D interconnect of the second chip ahead of the predetermined time via the second bypass.

[0056] As a further aspect of this specification, the first bypass includes at least one portion of the substrate trace between the first functional module and the D2D interconnect of the first chip; the second bypass includes at least one portion of the substrate trace between the first functional module and the D2D interconnect of the second chip.

[0057] As a further aspect of this specification, the first functional module includes a timer that, according to the predetermined time, directly wakes up the D2D interconnect of the first chip through the first bypass and directly wakes up the D2D interconnect of the second chip through the second bypass.

[0058] As a further aspect of this specification, the first bypass also includes,

[0059] First wake-up signal sending interface, first wake-up signal receiving interface, first timer;

[0060] The first functional module transmits a wake-up signal to the substrate traces through the first wake-up signal transmission interface;

[0061] The first wake-up signal is transmitted to the first timer through the substrate traces and the first wake-up signal receiving interface;

[0062] The first timer sends the wake-up signal to the D2D interconnect of the first chip according to the predetermined time.

[0063] As another further aspect of this specification,

[0064] The second bypass also includes substrate traces between the first wake-up signal receiving interface and the second wake-up signal receiving interface of the second chip;

[0065] The second wake-up signal receiving interface is connected to the second timer of the second chip;

[0066] The second timer of the second chip is connected to the D2D interconnect of the second chip.

[0067] As a further aspect of this specification, the second bypass also includes,

[0068] The substrate trace between the first wake-up signal receiving interface and the second wake-up signal receiving interface of the second chip;

[0069] The second wake-up signal receiving interface is connected to the second chip via D2D interconnect.

[0070] As a further aspect of this specification, the second bypass also includes a physical link between the D2D interconnect of the first chip and the D2D interconnect of the second chip.

[0071] As a further aspect of this specification, the first wake-up signal transmission interface is located near the first functional module; the first timer is located near the D2D interconnect of the first chip.

[0072] This specification also provides a processor, including a chip for performing the above-described methods.

[0073] This specification also provides a computer device, including a memory and a computer program stored in the memory and executable on a processor, including the processor described above.

[0074] This specification also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the above-described method.

[0075] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0076] Using the embodiments of this specification, the functional module in the chip sends a wake-up signal to activate the chip's D2D interconnect at the same time as or shortly after transmitting communication data. The process of activating the D2D interconnects of the first chip and the second chip begins at a predetermined time. This means that the D2D interconnects of the first and second chips are activated simultaneously with or slightly before the arrival of communication data, allowing them to directly transmit the received communication data to other chips. The activation of the D2D interconnects can be timed by a clock or other means. This improves the transmission efficiency between chips and saves energy by activating the D2D interconnect only when communication data arrives. Attached Figure Description

[0077] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0078] Figure 1 The diagram shown is a flowchart of an inter-chip communication method according to an embodiment of this specification.

[0079] Figure 2a The diagram shown is a schematic diagram of the D2D interconnect structure of the first chip waking up the second chip in an embodiment of this specification.

[0080] Figure 2b The diagram shown is a schematic diagram of the D2D interconnect structure of the first chip waking up the second chip in an embodiment of this specification.

[0081] Figure 2cThe diagram shown is a schematic diagram of the D2D interconnect structure of the first chip waking up the second chip in an embodiment of this specification.

[0082] Figure 3 The diagram shown is a structural schematic of a core chip according to an embodiment of this specification;

[0083] Figure 4 The diagram shown is a structural schematic of a core chip according to an embodiment of this specification;

[0084] Figure 5 The diagram shown is a schematic diagram of a core structure with a first bypass according to an embodiment of this specification;

[0085] Figure 6 The diagram shown is a schematic diagram of a core structure with a first bypass according to an embodiment of this specification;

[0086] Figure 7a The diagram shown is a schematic diagram of the core structure for transmitting communication data across cores according to an embodiment of this specification.

[0087] Figure 7b The diagram shown is a schematic diagram of the substrate wiring in an embodiment of this specification;

[0088] Figure 8a The figure shown is a timing diagram illustrating the inter-chip communication data transmission in an embodiment of this specification.

[0089] Figure 8b The diagram shown is another timing diagram illustrating the inter-chip communication data transmission in an embodiment of this specification.

[0090] Figure 9 The diagram shown is a schematic representation of a computer device provided in an embodiment of this specification. Detailed Implementation

[0091] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0092] The first and second chips in the embodiments of this specification may be referred to as chiplets, dies, wafers, bare dies, etc. Multiple chips can be integrated into a single package using die-to-die (D2D) interconnect technology to form a more powerful chip. In the embodiments of this specification, the first chip is configured to communicate with the second chip, for example, the first chip and the second chip achieve communication connection through die-to-die (D2D) interconnect; and when one of the first chip and the second chip is described as a "chip", the other of the first chip and the second chip is described as "another chip".

[0093] The first and second chips can be processor chips, and multiple processor chips can be interconnected to form a more powerful processor chip. Functional modules within the first and second chips refer to hardware units within the chip that perform specific tasks, such as computing cores (CPU / GPU / AI cores), memory controllers (memory controllers, HBM controllers), I / O interface controllers (PCIe controllers), security encryption engines, etc. In the embodiments of this specification, these functional modules can be used for computation and control, for processing image data, or for performing neural network calculations, etc. A single chip may include multiple functional modules, such as 16 or 64. Communication data in the embodiments of this specification refers to instructions generated by the functional modules of a chip that require access to other chips, or instructions that require collaboration with other chips, or response information (or data) generated by the functional modules of a chip in response to requests from other functional modules of other chips, such as memory access instructions and memory access responses. The above description is merely illustrative and is not intended to limit the concepts of first chip, second chip, and communication data. In practical applications, the first and second chips can also be other types of chips, and the communication data can also be other interactive information between chips.

[0094] In some embodiments, the clocks of multiple interconnected chips can be generated by the same clock generator, meaning that multiple interconnected chips can share a single clock source. In other embodiments, multiple interconnected chips may also have their clock signals provided by multiple different clock generators, in which case the input clocks of some chips may not originate from the same source. Inconsistencies in timestamp data may exist between chips with the same clock source and between chips with different clock sources; therefore, timestamp synchronization operations can be performed in both cases.

[0095] In some embodiments, keeping the D2D interconnect constantly active, maintaining its clock and power supply, while the chip is idle results in significant power wastage. Various D2D interconnect technologies commonly employ clock gating and power gating techniques to save power. Maintaining D2D interconnect power supply, clock, and link transmission even when no data needs to be transmitted across chips during idle states leads to substantial power waste. Simply shutting down the D2D interconnect clock via clock gating saves minimal power. However, if clock gating (L1 or L2) is used to shut down the phase-locked loop (PLL) or the entire physical layer interface module (PHY), a considerable amount of time is required to restore D2D interconnect power and clock before returning to a loaded state, and even retrain the transmission link. This entire process is time-consuming. In a chiplet architecture CPU, multiple chips implement different functions and communicate with each other through D2D interconnect technology. When a functional module in one chiplet (such as the kernel) and a functional module in another chiplet (such as the main memory controller) return to the load state from an idle state, after the kernel issues the first memory access request, there is a long delay before the D2D interconnect of the local chiplet can be restored before it can be sent to the main memory controller chiplet. Furthermore, when the main memory controller responds to the memory access request, it also needs to wait for the D2D interconnect of the local chiplet to be restored before it can send the memory access response to the chiplet where the kernel is located, which seriously affects the performance of the CPU.

[0096] If the D2D interconnect enters a low-power state, the latency of a memory access request in the idle state is actually the sum of the data bus network latency and the D2D interconnect wake-up latency. Because large SoCs are often large in area and size and have high bandwidth requirements, the data bus network has a large cache capacity and long trace distance, resulting in a significant data bus network latency (potentially tens of nanoseconds). Furthermore, waking up the physical layer of the D2D interconnect also requires a significant latency (depending on the design, it can be as high as several to hundreds of nanoseconds). Ultimately, this leads to a large latency in the entire transmission path, severely impacting the transmission speed of memory access requests and thus affecting system application response time and performance. Conversely, if the D2D interconnect does not enter a low-power state in the idle state, although the D2D interconnect wake-up latency can be reduced, it will greatly increase the chip power consumption in the idle state. Therefore, there is a trade-off between power consumption and performance (response time).

[0097] like Figure 1The diagram shown is a flowchart of an inter-chip communication method according to an embodiment of this specification. The diagram describes a method for implementing inter-chip communication data transmission. When transmitting communication data between chips, a wake-up command for the D2D interconnect can be sent to both the first and second chip's D2D interconnects before the communication data arrives at the local D2D interconnect of the first chip. This wake-up signal can be a certain form of encoding (i.e., a string of 0s and 1s), or a high or low level. When the first chip's D2D interconnect can be woken up before or simultaneously with the arrival of the communication data (i.e., after completing the wake-up process), the communication data can be directly transmitted to the second chip's D2D interconnect upon arrival. The second chip's D2D interconnect can also be woken up in advance without waiting for the D2D interconnect to wake up, thereby reducing latency and improving the inter-chip communication speed. The method specifically includes:

[0098] Step 101: Before the communication data sent by at least one first functional module of the first core reaches the D2D interconnect of the first core, wake up the D2D interconnect of the first core and the D2D interconnect of the second core by bypassing a predetermined time; wherein the predetermined time is at least the time required to wake up the D2D interconnect of the first core or the D2D interconnect of the second core.

[0099] According to the method described in this specification, the functional module in the chip sends a wake-up signal to wake up the D2D interconnect of the first chip and the connected second chip at the same time as or shortly after sending communication data. The process of waking up the D2D interconnect begins at a first predetermined time. The D2D interconnect can be woken up at the same time as or slightly earlier than the arrival of communication data, and can directly send the received communication data to the corresponding chip. The D2D interconnect can be woken up according to a predetermined time using a clock, or through other means. This improves the transmission efficiency between chips and saves energy by waking up the D2D interconnect only when communication data arrives.

[0100] As one embodiment of this specification, communication data sent by at least one first functional module of the first core reaches the D2D interconnect of the first core via a data bus;

[0101] The D2D interconnect of the first core sends the communication data to the D2D interconnect of the second core through a physical link.

[0102] At least one first functional module of the first chip wakes up the D2D interconnect of the first chip at a predetermined time via a first bypass, and wakes up the D2D interconnect of the second chip at the predetermined time via a second bypass.

[0103] In this embodiment, the communication data sent by the first functional module takes a certain amount of time to reach the D2D interconnect of the first core through the data bus in the core, which may be approximately tens of nanoseconds. In the embodiments of this specification, when transmitting communication data through the data bus, this transmission delay time can be reused. Based on the transmission delay time, the D2D interconnect of the first core and the D2D interconnect of the second core are pre-wake-up through a bypass. The transmission delay time is data obtained by simulating and simulating the data bus of the core in advance and storing it in the core. Thus, the functional module of the core can send a wake-up signal later based on the data bus transmission delay, or send a wake-up signal at the same time as sending communication data. The wake-up signal is sent to the D2D interconnect of the first core and the D2D interconnect of the second core through a bypass (i.e., non-data bus) method.

[0104] The method described in this specification enables precise early wake-up of the D2D interconnects of the first and second chips before the actual arrival of communication data such as memory access requests or responses at the D2D interconnects of the second and third chips. Furthermore, it promptly shuts down the relevant circuit modules of the D2D interconnects after the communication data transmission is completed. This parallelizes the data bus network latency with the D2D interconnect wake-up latency, saving both D2D interconnect power consumption and memory access transmission latency, thus balancing performance and power consumption.

[0105] As one embodiment of this specification, the first bypass includes at least one portion of the substrate trace between the first functional module and the D2D interconnect of the first chip; the second bypass includes at least one portion of the substrate trace between the first functional module and the D2D interconnect of the second chip.

[0106] In this step, the bypass includes substrate wiring, which can be, for example, an organic substrate or a silicon interposer. The substrate wiring is usually done using photolithography-etching or semi-additive process (SAP). The patterning accuracy depends on the resolution of the photolithography equipment (e.g., laser direct writing can reach 10μm). The minimum linewidth / spacing can reach 10-20μm on the packaging substrate (e.g., Universal Chiplet Interconnect Express, UCIe standard), and the number of layers is usually 8-20. The data bus inside the chip is usually done using photolithography-etching-electroplating process, and nanoscale patterning is achieved through extreme ultraviolet lithography (EUV) or deep ultraviolet lithography (DUV). The minimum linewidth / spacing can reach 12-16nm at the 3nm process node, and the number of metal layers is usually 10-14. Because the substrate traces directly connect the first functional module and the D2D interconnect of the first core and the D2D interconnect of the second core, the path is short and the line width is large. The transmission speed is much higher than that of the data bus inside the core. Therefore, the wake-up signal can reach the D2D interconnect of the first core and the D2D interconnect of the second core in advance, so as to achieve the purpose of waking up the D2D interconnect of the first core and the D2D interconnect of the second core in advance.

[0107] In this embodiment, when the first functional module sends communication data to the second functional module, the D2D interconnect of the second core also needs a wake-up process before it can receive the communication data sent by the D2D interconnect of the first core. Therefore, in this embodiment, the D2D interconnect of the first core can be woken up before the communication data arrives at the D2D interconnect of the first core, and the D2D interconnect of the second core can also be woken up before the communication data arrives at the D2D interconnect of the second core. Thus, in the communication data transmission between cores, the communication data can be transmitted directly to the D2D interconnect of the second core through the physical link between cores with almost no need to wait for the wake-up of the D2D interconnect of the first core and the D2D interconnect of the second core.

[0108] As one embodiment of this specification, the method of waking up the D2D interconnect of the first chip at a predetermined time via a first bypass and waking up the D2D interconnect of the second chip at the predetermined time via a second bypass further includes...

[0109] The first functional module, according to the predetermined time, directly wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip through the first bypass and the second bypass, respectively.

[0110] In this step, the timer inside the first functional module directly wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip through the first bypass and the second bypass according to the predetermined time. The first functional module forms a timer through the gate circuits in the chip, or utilizes an existing timer in the first functional module. When communication data needs to be sent to other chips through the D2D interconnect of the first chip, a wake-up signal can be sent to the D2D interconnect of the first chip and the D2D interconnect of the second chip simultaneously with the transmission of communication data through the communication bus, or after a waiting time. That is, the waiting time is the time for the communication data to reach the D2D interconnect of the first chip according to the transmission of communication data through the communication bus minus the wake-up time of the D2D interconnect of the first chip (or the D2D interconnect of the second chip). The instruction to wake up the D2D interconnect of the first chip is sent through the first bypass, and the instruction to wake up the D2D interconnect of the second chip is sent through the second bypass. In this way, the wake-up process can be completed before (or simultaneously) the communication data reaches the D2D interconnect of the first chip, and the communication data can be directly received and transmitted to the second chip. The D2D interconnect of the second chip can also complete the wake-up process before (or simultaneously) the communication data reaches the D2D interconnect of the second chip, and directly receive the communication data sent by the D2D interconnect of the first chip.

[0111] As one embodiment of this specification, the method of waking up the D2D interconnect of the first chip at a predetermined time via a first bypass and waking up the D2D interconnect of the second chip at the predetermined time via a second bypass further includes...

[0112] Using a first timer in the first chip, the D2D interconnect of the first chip is woken up via the first bypass according to the predetermined time, and the D2D interconnect of the second chip is woken up via the second bypass.

[0113] In this step, besides implementing the timer within the first functional module as described above, the first timer can also be implemented without changing the first functional module, using circuitry within the chip. The first bypass includes a first wake-up signal transmitting interface and a first wake-up signal receiving interface. The first functional module connects to the substrate traces via the first wake-up signal transmitting interface and bumps. The wake-up signal requiring high-speed transmission can be directly sent to the target location of the chip via the substrate traces outside the chip. Then, at the target location, the wake-up signal is received by the first wake-up signal receiving interface and bumps, and the wake-up signal is then received inside the chip. Finally, the gate circuitry inside the chip implements the first wake-up signal transmission interface. A timer has a pre-stored waiting time corresponding to a predetermined time in its register. When the first timer receives a wake-up signal, it starts counting down according to the waiting time in the register. After the waiting time ends, the first timer sends a wake-up signal to the D2D interconnect of the first chip, and the D2D interconnect of the first chip begins the wake-up process. After the predetermined time has elapsed, the wake-up process is completed. At this time, the communication data transmitted through the data bus is transmitted to the D2D interconnect of the first chip, so that the D2D interconnect of the first chip can directly perform the communication data transmission process with the D2D interconnect of the second chip.

[0114] As one embodiment of this specification, the method of waking up the D2D interconnect of the second chip via the second bypass according to the predetermined time using a first timer in the first chip further includes...

[0115] The wake-up signal is transmitted to the second wake-up signal receiving interface of the second chip through the substrate traces and the first wake-up signal receiving interface;

[0116] The second wake-up signal receiving interface of the second chip transmits the wake-up signal to the second timer of the second chip through the substrate traces;

[0117] The second timer of the second chip sends the wake-up signal to the D2D interconnect of the second chip according to the predetermined time.

[0118] In this step, in the example of the D2D interconnect of the first chip waking up the second chip, such as Figure 2aThe diagram shows a schematic of the structure of the D2D interconnect of the first chip waking up the second chip in an embodiment of this specification. The first functional module can send a wake-up signal to the first timer via a first bypass, and simultaneously send the wake-up signal to the second chip via a second bypass independent of the first bypass. The second bypass can share the first wake-up signal sending interface and the first wake-up signal receiving interface of the first bypass, sending the wake-up signal to the first wake-up signal receiving interface via different substrate traces. The first wake-up signal receiving interface sends the wake-up signal to the second wake-up signal receiving interface of the second chip via substrate traces. The second wake-up signal receiving interface sends the wake-up signal to the second timer of the second chip. The first timer and the second timer are timed independently. When a predetermined time arrives, i.e., when the difference (AB) between the data bus delay time (A) and the wake-up time (B) of the D2D interconnect of the first chip or the D2D interconnect of the second chip arrives, the wake-up signal is sent to the D2D interconnect of the first chip and the D2D interconnect of the second chip in advance, thereby waking up the D2D interconnect of the first chip and the D2D interconnect of the second chip.

[0119] In other embodiments, the second bypass may also include a portion of the first bypass and substrate traces for D2D interconnects from the first chip to the second chip, thereby enabling the D2D interconnects that send a wake-up signal to the second chip.

[0120] As one embodiment of this specification, the method of waking up the D2D interconnect of the second chip via the second bypass according to the predetermined time using a first timer in the first chip further includes...

[0121] The first timer sends the wake-up signal to the D2D interconnect of the first chip according to the predetermined time, and transmits the wake-up signal to the D2D interconnect of the second chip through the first wake-up signal receiving interface, the substrate trace, and the second wake-up signal receiving interface of the second chip.

[0122] In this step, in the example of the D2D interconnect of the first chip waking up the second chip, such as Figure 2bThe diagram shown is a schematic of the structure of the D2D interconnect of the first chip waking up the second chip in an embodiment of this specification. The first functional module can send a wake-up signal to a first timer via a first bypass. The first timer counts down, and when the predetermined time arrives (i.e., the communication data is about to reach the D2D interconnect of the first chip before the predetermined time), the wake-up signal is simultaneously sent to the second wake-up signal receiving interface of the second chip via a second bypass independent of the first bypass. The second wake-up signal receiving interface directly sends the wake-up signal to the D2D interconnect of the second chip, thereby waking up the D2D interconnect of the second chip. In other words, the second bypass may not include the first bypass; it may only share the first wake-up signal sending interface and the first wake-up signal receiving interface in the first bypass. The wake-up signal is sent directly to the D2D interconnect of the second chip via substrate traces different from those of the first bypass, thus achieving early wake-up of the D2D interconnect of the second chip.

[0123] The method of this embodiment can wake up the D2D interconnect of the first core in advance through the functional module of the first core, and can also wake up the D2D interconnect of the second core in advance through the first functional module. By waking up the D2D interconnect of the second core in advance, the efficiency of cross-core communication data transmission can be further improved.

[0124] In one embodiment, although as Figure 2b As shown, the first wake-up signal transmission interface is located outside the first functional module, but in fact, the first wake-up signal transmission interface is an interface inside the first functional module, which is connected to the substrate traces through bumps.

[0125] In one embodiment, the second bypass may also not share the first wake-up signal sending interface and the first wake-up signal receiving interface in the first bypass, but use independent wake-up signal sending interface and wake-up signal receiving interface to transmit the wake-up signal to the D2D interconnect of the second chip.

[0126] The method described in this embodiment, through a shared interface or a separate interface and substrate wiring, can improve the efficiency of cross-chip communication data transmission as needed (e.g., for performance or cost considerations).

[0127] As one embodiment of this specification, the method of waking up the D2D interconnect of the second chip via the second bypass according to the predetermined time using a first timer in the first chip further includes: the first timer sending the wake-up signal to the D2D interconnect of the first chip according to the predetermined time, and transmitting the wake-up signal to the D2D interconnect of the second chip through the physical link between the D2D interconnect of the first chip and the D2D interconnect of the second chip.

[0128] In this step, such as Figure 2cThe diagram shown is a schematic of the structure of the D2D interconnect of the first chip waking up the second chip in an embodiment of this specification. The first functional module can send a wake-up signal to the local first timer through the first bypass. The timer of the first chip keeps track of the time. In response to the arrival of the predetermined time, it sends a wake-up signal to the D2D interconnect of the first chip, starting the wake-up process of the D2D interconnect of the first chip. The D2D interconnect of the first chip sends the wake-up signal to the D2D interconnect of the second chip through the physical link connected to the D2D interconnect of the second chip, starting the wake-up process of the D2D interconnect of the second chip. That is to say, when the first chip wakes up the D2D interconnect of the first chip using the first timer, it can use the original physical link to wake up the D2D interconnect of the second chip, thereby realizing the sending of the wake-up signal to the D2D interconnect of the second chip. In this embodiment, the second bypass is logical, sharing the first wake-up signal sending interface, the first wake-up signal receiving interface, and the substrate traces between the two of the first bypass. It also shares the physical link between the D2D interconnect of the first chip and the D2D interconnect of the second chip. Therefore, it can also be considered that the first chip can achieve early wake-up of the D2D interconnect of the first chip and the D2D interconnect of the second chip through a bypass.

[0129] In other embodiments, there are many possibilities for the independent or shared use of the interfaces (wake-up signal transmitting interface and wake-up signal receiving interface) of the first bypass and the second bypass, as well as the substrate wiring, which will not be elaborated here.

[0130] The method of this embodiment can wake up the D2D interconnect of the first chip in advance through the first functional module, and can also wake up the D2D interconnect of the second chip in advance. This can improve the efficiency of cross-chip communication data transmission while saving the power consumption of the D2D interconnect of the first chip and the D2D interconnect of the second chip.

[0131] As one embodiment of this specification, the D2D interconnect of the first chip and the D2D interconnect of the second chip are woken up according to a preset delay time and the predetermined time, wherein the preset delay time is the time it takes for the communication data sent by the first functional module to reach the D2D interconnect of the first chip through the data bus.

[0132] In this step, based on the chip's process and design, the time (A) for the communication data sent by the first functional module to reach the D2D interconnect of the first chip via the data bus can be obtained through simulation. The time required for the D2D interconnect of the first chip or the D2D interconnect of the second chip to be woken up, i.e., the predetermined time (B), can also be obtained through simulation based on the D2D interconnect process, design, and protocol followed.

[0133] As one embodiment, waking up the D2D interconnect of the first chip and the D2D interconnect of the second chip according to the preset delay time and the predetermined time can mean that when the first functional module generates communication data, such as a memory access request, it calculates the waiting time according to AB. After the waiting time ends, the first functional module directly sends a wake-up signal to the D2D interconnect of the first chip through the first bypass, so that it completes the wake-up process within the predetermined time; at the same time, the first functional module directly sends a wake-up signal to the D2D interconnect of the second chip through the second bypass, so that it completes the wake-up process within the predetermined time.

[0134] In another embodiment, when waking up the D2D interconnect of the second chip, the early wake-up time of the D2D interconnect of the second chip can be determined based on the data bus delay in the first chip and the wake-up time (second predetermined time) of the D2D interconnect of the second chip; alternatively, the early wake-up time of the D2D interconnect of the second chip can be determined by the data bus delay in the first chip and the wake-up time (first predetermined time) of the D2D interconnect of the first chip, i.e., the second predetermined time is equal to the first predetermined time.

[0135] In the above embodiments, when the first chip wakes up the D2D interconnect of the first chip in advance, the D2D interconnect of the second chip can also be woken up at the same time, thereby further improving communication efficiency and reducing latency.

[0136] As another embodiment, waking up the D2D interconnect of the first chip and the D2D interconnect of the second chip according to the preset delay time and the predetermined time can mean that when the first functional module generates communication data, such as a memory access request, it sends a wake-up signal to the first timer through the first wake-up signal sending interface, the first wake-up signal receiving interface and the substrate trace of the first bypass. The first timer counts according to the preset waiting time, wherein the preset waiting time is obtained by pre-calculating AB. After the waiting time ends, the first timer directly sends a wake-up signal to the D2D interconnect of the first chip and the D2D interconnect of the second chip, so that they complete the wake-up process within the predetermined time.

[0137] As one embodiment of this specification, after a predetermined time before the communication data sent by at least one first functional module of the first chip arrives at the D2D interconnect of the first chip, and after waking up the D2D interconnect of the first chip and the D2D interconnect of the second chip, the following steps are further included:

[0138] The D2D interconnect of the first chip is activated before or simultaneously with the arrival of the communication data at the D2D interconnect of the first chip; the D2D interconnect of the second chip is activated before or simultaneously with the arrival of the communication data at the D2D interconnect of the second chip.

[0139] The communication data is transmitted to the second core through the D2D interconnect of the first core after it is woken up and the D2D interconnect of the second core.

[0140] The D2D interconnect of the first chip and the D2D interconnect of the second chip enter an energy-saving state.

[0141] In this step, after the D2D interconnects of the first and second cores are awakened and communication data is transmitted to the second core, the D2D interconnects of the first and second cores immediately enter a power-saving state. The power-saving state may further include an idle state and a sleep state. The idle state refers to a state where no actual transmission is performed (e.g., memory access transmission state), which may be the transmission of meaningless scrambling codes such as 0 or 1 or predefined regularized signals or data structures (idle pattern), depending on the protocol specifications of the D2D interconnect itself. The sleep state refers to stopping the clock or stopping the power supply of the D2D interconnect to save power. The time range for stopping the clock and stopping the power supply depends on the requirements of the D2D interconnect protocol and the specific design architecture.

[0142] The method in this embodiment can effectively save energy consumption of D2D interconnect, and the method of early wake-up of D2D interconnect can also improve the transmission efficiency between cores.

[0143] like Figure 3 The diagram shown is a schematic representation of a chip according to an embodiment of this specification. The diagram depicts a first chip 300 capable of waking up the D2D interconnect before communication data arrives. This chip includes:

[0144] At least one first functional module 301, a D2D interconnect of the first core 302, a bypass 303, a second core 304, and a D2D interconnect of the second core 305;

[0145] At least one of the first functional modules 301 is configured to implement the function of the first chip 300, and to wake up the D2D interconnect 302 of the first chip and the D2D interconnect 305 of the second chip 304 via bypass 303 at a predetermined time before the transmitted communication data arrives at the D2D interconnect 302 of the first chip; wherein the predetermined time is at least the time required to wake up the D2D interconnect 302 of the first chip or the D2D interconnect 305 of the second chip.

[0146] Through the chip in the embodiments of this specification, the D2D interconnect of the first chip and the D2D interconnect of the second chip can be woken up before or simultaneously with the communication data arriving at the D2D interconnect of the first chip, thereby enabling a rapid response to the communication data transmission requirements without having to maintain the relatively high power consumption of the D2D interconnect of the first chip and the D2D interconnect of the second chip at all times.

[0147] As one embodiment of this specification, such as Figure 4 The diagram shown is a structural schematic of a core chip according to an embodiment of this specification. In this embodiment, only one core chip is used for illustration. Figure 4 It includes at least one first functional module 401, a D2D interconnect 402 of the first chip, and a data bus 403 configured to allow communication data sent by at least one first functional module 401 to reach the D2D interconnect 402 of the first chip through the data bus 403; and a first bypass 404 configured to allow at least one first functional module 401 to wake up the D2D interconnect 402 of the first chip through the first bypass at a predetermined time.

[0148] In this embodiment, the first bypass 404 includes at least one substrate trace 4041 between the first functional module 401 and the D2D interconnect 402 of the first chip. The substrate trace 4041 is a physical trace in an organic substrate or a silicon interposer. The substrate trace 4041 has a very large width and thickness relative to the traces inside the chip, and the delay is negligible. The first bypass 404, independent of the internal data bus of the chip, can control the transmission and reception of communication data through the IO control circuit (e.g., General Purpose IO, GPIO) of the first functional module 401. When the first functional module 401 needs to send communication data, its internal IO can send a wake-up signal to the D2D interconnect 402 of the first chip through the first bypass 404, based on the pre-obtained wake-up time required for the D2D interconnect 402 of the first chip. When the communication data is about to arrive at the D2D interconnect 402 of the first chip via the data bus 403, that is, when it is still a certain time away from arriving at the D2D interconnect 402 of the first chip, the wake-up signal to the D2D interconnect 402 of the first chip is sent to the D2D interconnect 402 of the first chip through the first bypass 404. This allows the D2D interconnect 402 of the first chip to complete the wake-up process before (or simultaneously with) the communication data arriving at the D2D interconnect 402 of the first chip.

[0149] As one embodiment of this specification, such as Figure 5 The diagram shown is a schematic of a chip structure with a first bypass according to an embodiment of this specification. The first bypass 404 also includes a first wake-up signal transmitting interface 4042, a first wake-up signal receiving interface 4043, and a first timer 4044.

[0150] The first wake-up signal sending interface 4042 is connected to the first functional module 401;

[0151] The first wake-up signal transmitting interface 4042 and the first wake-up signal receiving interface 4043 are connected through the substrate trace 4041;

[0152] The first wake-up signal receiving interface 4043 and the first timer 4044 are connected;

[0153] The first timer 4044 is connected to the D2D interconnect 402 of the first chip.

[0154] In this embodiment, the first wake-up signal transmitting interface 4042 and the first wake-up signal receiving interface 4043 can be composed of I / O interfaces inside the chip. The first wake-up signal transmitting interface 4042 can bring out the electrical connection relationship of the internal devices of the chip to the substrate through bumps. Fast communication and data transmission from one bump to another in the chip can be realized through substrate wiring. Furthermore, the first wake-up signal transmitting interface 4042 or the first wake-up signal receiving interface 4043 can be set to be closer to the device that needs to respond. For example, the first wake-up signal transmitting interface 4042 can be located inside the first functional module 401, and the bumps corresponding to the first wake-up signal transmitting interface 4042 can be connected to the chip. The block is located near the first functional module 401 (or possibly near the first wake-up signal sending interface 4042); the first wake-up signal receiving interface 4043 can be located near the D2D interconnect 402 of the first chip. A first timer 4044 is also connected between the first wake-up signal receiving interface 4043 and the D2D interconnect 402 of the first chip. The first timer 4044 can be located near the D2D interconnect 402 of the first chip. By setting the substrate trace between each node to the shortest distance, the efficiency of the first functional module 401 transmitting communication data to the D2D interconnect 402 of the first chip through the first bypass 404 can be further improved.

[0155] As one embodiment of this specification, such as Figure 6 The diagram shown is a schematic of a chip structure with a first bypass according to an embodiment of this specification. The first bypass 404 further includes a first wake-up signal transmitting interface 4042 and a first wake-up signal receiving interface 4043. The first functional module 401 includes a timer 4011, which is configured to directly wake up the D2D interconnect 402 of the first chip through the first wake-up signal transmitting interface 4042, the first wake-up signal receiving interface 4043 and the substrate trace 4041 of the first bypass 404 according to the predetermined time.

[0156] In this embodiment, a timer 4011 is constructed using gate circuits in the first functional module 401. When the first functional module 401 generates communication data to be sent to other chips, the first functional module 401 starts the timer 4011. At a predetermined time before the communication data is transmitted to the D2D interconnect 402 of the first chip via the data bus 403, the timer 4011 sends a wake-up signal to wake up the D2D interconnect 402 of the first chip. The wake-up signal is transmitted to the substrate trace through the first wake-up signal transmission interface 4042 (bump). 4041, and transmits the wake-up signal to the first wake-up signal receiving interface 4043 (bump) through the substrate trace 4041. The wake-up signal is then transmitted to the D2D interconnect 402 of the first chip for the wake-up process through the first wake-up signal receiving interface 4043. After the D2D interconnect 402 of the first chip completes the wake-up after a predetermined time, the communication data arrives at the D2D interconnect 402 of the first chip just in time. This allows the D2D interconnect 402 of the first chip to be woken up in advance, reducing the transmission waiting time inside the chip and improving the transmission efficiency.

[0157] In this embodiment, the first wake-up signal transmitting interface 4042 and the first wake-up signal receiving interface 4043 can also be set at a location close to the relevant device. For example, the first wake-up signal transmitting interface 4042 can be set inside the first functional module 401, and the first wake-up signal receiving interface 4043 can be set at a physical location inside the chip that is close to the D2D interconnect 402 of the first chip.

[0158] As an embodiment of this specification, the second core particle may also have the same structure as the core particle in the above embodiment. That is, the first core particle and the second core particle may have the same structure. When the second core particle needs to transmit communication data to the first core particle, the communication method between the two may be the same as in the above embodiment.

[0159] like Figure 7a The diagram shown is a schematic representation of the core structure for cross-core transmission of communication data according to an embodiment of this specification. Figure 7b The diagram shown is a schematic of the substrate wiring in an embodiment of this specification. Figure 8a The diagram shown is a timing schematic of inter-chip communication data transmission in an embodiment of this specification. Figure 8b The diagram shown is another timing schematic of inter-core communication data transmission in an embodiment of this specification. In this embodiment, the core core and the storage core are used as examples. Figure 7a , Figure 7b , Figure 8a and Figure 8b This specification describes the process of cross-chip transfer memory access requests and responses in embodiments of this specification.

[0160] exist Figure 7aIn the chip structure, the core chip includes a kernel module for initiating communication data for memory access requests; a D2D interconnect of the first chip for communication with the D2D interconnect of the second chip in the storage chip; and a timer implemented by a gate circuit near the physical location of the D2D interconnect of the first chip in the core chip. After receiving the wake-up signal from the kernel module, the timer starts counting down. When the pre-simulated or calculated waiting time is reached (the time for the data bus to transmit the memory access request - the time for the D2D interconnect of the first chip to be woken up), the timer sends an enable signal to the D2D interconnect of the first chip, causing the D2D interconnect of the first chip to enter the wake-up process. Both the wake-up signal sending interface and the wake-up signal receiving interface are connected to the substrate traces through bumps. The wake-up signal is transmitted through the substrate traces connected between the bumps, thereby achieving the purpose of quickly waking up the D2D interconnect of the first chip in advance.

[0161] Similarly, the structure in the storage core is basically similar to that of the kernel core, except that the functional module is the memory control module, and the generated communication data is memory access response data.

[0162] The wake-up signal is transmitted to the D2D interconnect of the first chip through the wake-up signal transmission interface in the core chip, the substrate traces, the wake-up signal receiving interface, and the timer. The wake-up signal is transmitted to the memory chip through the substrate traces between the wake-up signal receiving interface in the core chip and the wake-up signal receiving interface in the memory chip. The wake-up signal receiving interface in the memory chip transmits the wake-up signal to the timer in the memory chip. After the timer in the memory chip finishes timing, it sends the wake-up signal to the D2D interconnect of the second chip, thus achieving the purpose of transmitting the wake-up signal to the D2D interconnect of the second chip.

[0163] The physical layers of the two chips are interconnected via physical links in the organic substrate or silicon interposer within the package. Inside the chip, the core module of the core chip is connected to the D2D interconnect of the first chip, or the memory control module of the storage chip is connected to the D2D interconnect interface of the second chip via a data bus. This data bus has a relatively long transmission path and a relatively long transmission delay (tens or even hundreds of nanoseconds) within the chip. Figure 7bThe diagram shows a schematic of the substrate wiring in an embodiment of this specification. A wake-up signal transmitting interface is provided near the physical location of the kernel module or memory control module, and a wake-up signal receiving interface is provided near the D2D interconnect. The kernel module is connected to the substrate via the wake-up signal transmitting interface and bumps. The wake-up signal transmitting interface is connected to the wake-up signal receiving interface via substrate wiring. In this embodiment, the timer is not shown; only the wake-up signal receiving interface represents both the wake-up signal receiving interface and the timer. The timer can be implemented by gate circuits inside the kernel chip. The wake-up signal receiving interface is connected to the substrate via bumps to obtain the wake-up signal on the substrate wiring. The wake-up signal receiving interface and the timer can be connected via internal wiring within the chip, and the timer can also be connected to the D2D interconnect of the first chip via internal wiring. In other embodiments, the timer can also be implemented by a device outside the kernel chip. The timer can be connected to the substrate wiring to obtain the wake-up signal. The timer is connected to the wake-up signal receiving interface via bumps to transmit the wake-up signal to the kernel chip and then to the D2D interconnect of the first chip via wiring within the kernel chip. The wake-up signal sending interface and wake-up signal receiving interface of the memory chip, and the wake-up signal receiving interface of the memory chip and the wake-up signal receiving interface of the core chip, can all be connected via extremely short substrate traces, with minimal connection delay (picoseconds or a few nanoseconds). In this embodiment, the timer is not shown; only the wake-up signal receiving interface represents both the wake-up signal receiving interface and the timer. The timer of the memory chip is implemented by gate circuits within the memory chip. The wake-up signal receiving interface of the memory chip receives the wake-up signal from the substrate traces via bumps. The wake-up signal receiving interface and the timer of the memory chip can be connected via internal wiring within the chip. The timer of the memory chip and the D2D interconnect of the second chip can also be connected via internal wiring within the chip. After the timer of the memory chip completes its countdown, it sends the wake-up signal to the D2D interconnect of the second chip. Furthermore, as... Figure 7b As shown, the wake-up signal receiving interface of the core chip and the wake-up signal receiving interface of the storage chip are also connected via substrate traces. Specifically, the wake-up signal transmitting interface and the wake-up signal receiving interface of the core chip, the wake-up signal receiving interface and the wake-up signal transmitting interface of the storage chip, and the wake-up signal receiving interface of the core chip and the wake-up signal receiving interface of the storage chip are all connected via substrate traces.

[0164] When a kernel module in a kernel die runs a program, it generates memory access requests to retrieve program instructions or data. The kernel module first searches for instructions and data in its own caches (L1 / L2 / L3). If the required instructions or data are not found in the cache, it initiates a memory access request via the data bus to the memory control module of the storage die. The kernel module can determine the target location of the request based on the memory address. If the target address's memory control module is located on another storage die, it can simultaneously send wake-up signals to the D2D interconnect of the first die and the D2D interconnect of the second die via the wake-up signal receiving interface. The kernel module then sends the wake-up signal to the timers of both the kernel die and the storage die. The timer in the core die contains a wait time for waking up the D2D interconnect of the first die. This wait time can be pre-calculated by precisely calculating the delay (A) of the memory access request actually reaching the D2D interconnect interface via the data bus. This delay can be calculated during chip design based on factors such as memory access path distance, data transmission pipeline stages, and cache depth, and verified through simulation. This time is then stored as a parameter in the die's firmware FLASH, FUSE, ROM, registers, and other storage media. It also pre-calculates the delay (B) required for waking up the D2D interconnect of the first die. During the design phase, the wake-up delay can be calculated based on information such as the logic and pipeline depth, and the physical layer initialization process. This time can be verified through simulation, and stored as a parameter in the firmware FLASH, FUSE, ROM, registers, and other storage media of the chip. Based on (AB), the timer's wake-up delay for the first chip's D2D interconnect is obtained. The timer can then initiate the wake-up process of the first chip's D2D interconnect based on this delay. When a memory access request arrives at the first chip's D2D interconnect, the first chip's D2D interconnect has successfully woken up and immediately begins cross-chip transmission of the memory access request. Alternatively, the delay time can be pre-calculated and stored in a register associated with the timer.

[0165] Before sending the memory access response via the data bus, the memory control module of the storage chip sends a wake-up signal to a timer via the interconnection of the wake-up signal sending interface and the wake-up signal receiving interface. The timer can start timing based on a pre-calculated waiting time. Then, when the memory access response reaches the D2D interconnect of the second chip, the D2D interconnect of the second chip has just successfully woken up and immediately begins the cross-chip transmission of the memory access response. Specifically, the delay (C) for the memory access response to actually reach the D2D interconnect of the second chip via the data bus and the delay (B) required for the second chip's D2D interconnect to wake up are accurately calculated in advance. This waiting time is stored in the timer's register, and the timer starts the wake-up process of the second chip's D2D interconnect by the time (CB) ahead of schedule. As another embodiment, as in the previous embodiment, both B and C can be stored in the chip's firmware FLASH, FUSE, ROM, registers, or other storage media. The timer can calculate (CB) the waiting time based on these two parameters and start the wake-up process of the second chip's D2D interconnect based on the waiting time.

[0166] Figure 8a The described cross-chip communication data transmission process specifically includes:

[0167] Step 1: When the kernel module generates a memory access request, it sends a wake-up signal through the wake-up signal sending interface of the kernel chip, and transmits it to the wake-up signal receiving interface of the kernel chip and the wake-up signal receiving interface of the storage chip through the substrate connection. At the same time, the memory access request starts from the kernel module output and propagates through the data bus, and is expected to reach the D2D interconnect interface of the first chip after a time A.

[0168] Step 2: The wake-up signal receiving interfaces of the kernel chip and the storage chip wake up their respective timers and start the countdown. The countdown waiting time is calculated by configuring the register (AB).

[0169] In another embodiment, the wake-up signal can be sent only to the wake-up signal receiving interface on the kernel side. Then, a dedicated signal is provided by the physical link between the D2D interconnect of the first kernel and the D2D interconnect of the second kernel as the wake-up signal for the D2D interconnect of the second kernel, waking up the storage kernel. The D2D interconnect of the first kernel uses its own protocol-defined wake-up signal as the wake-up signal for the D2D interconnect of the second kernel, for example, by implementing a dedicated input / output signal (IO signal) between the physical layer interface module (PHY) of the first kernel's D2D interconnect and the PHY of the second kernel's D2D interconnect as a handshake signal to wake up the second kernel's D2D interconnect; or, the interconnect data interface between the PHY of the first kernel's D2D interconnect and the PHY of the second kernel's D2D interconnect can be reused to transmit a specific data pattern to represent the wake-up signal for the second kernel's D2D interconnect; alternatively, a clock signal can be directly sent to the D2D interconnect of the second kernel, with the clock paused during sleep and resumed during wake-up to indicate wake-up.

[0170] Step 3: After the timer countdown ends, the wake-up process of the D2D interconnect of the first chip and the D2D interconnect of the second chip begins.

[0171] In this step, the two D2D interconnects must successfully establish a connection through a complex handshake mechanism before data can be transmitted. In this embodiment, wake-up mainly refers to the process from when the two D2D interconnects exit low-power mode, establish a connection, and begin actually sending data. After time B, the D2D interconnects of the first chip and the second chip are successfully woken up.

[0172] In other embodiments, the wake-up time length (B) of the D2D interconnect of the first chip in the waiting time AB can also be the wake-up time length of the D2D interconnect of the second chip, or B can be the larger of the wake-up time length of the D2D interconnect of the first chip and the wake-up time length of the D2D interconnect of the second chip.

[0173] Step 4: After time A from the occurrence of Step 1, memory access requests arrive successively at the D2D interconnect of the first kernel chip via the data bus. At this time, the D2D interconnect of the first kernel chip has been successfully woken up by Step 3, and memory access requests can be smoothly transmitted to the D2D interconnect of the second storage chip via the D2D interconnect of the first kernel chip. After all memory access requests have been transmitted, the D2D interconnect of the first kernel chip enters an idle state for a period of time. The idle state of the D2D interconnect of the first kernel chip refers to a state in which no actual memory access transmission is performed. It may be continuously transmitting 0s, 1s, meaningless scrambling codes, or idle patterns, depending on the protocol specification of the D2D interconnect itself. Subsequently, it can enter a sleep state to save power. In the sleep state, the clock is usually stopped or even the power supply is stopped to save power. The scope of clock stopping and power supply stopping depends on the requirements of the D2D interconnect protocol and the specific design architecture.

[0174] In this step, the D2D interconnect of the second chip is also simultaneously awakened. Memory access requests can be successfully transmitted through the D2D interconnect of the second chip to the data bus of the storage chip, and then through the data bus to the memory management module. After all memory access request transmissions are completed, the D2D interconnect of the second chip enters an idle state for a period of time, and then can enter a sleep state to save power.

[0175] In this step, a D2D interconnect can be further divided into a transmitter and a receiver. For example, in the above embodiment, the D2D interconnect of the first chip includes TX1 and RX1, and the D2D interconnect of the second chip includes TX2 and RX2. During the transmission of a memory access request, TX1 of the first chip's D2D interconnect and RX2 of the second chip's D2D interconnect are woken up, and after the memory access request transmission ends, they respectively enter a power-saving state. During the transmission of the memory access request, RX1 of the first chip's D2D interconnect and TX2 of the second chip's D2D interconnect remain in a power-saving state (e.g., a sleep state), that is, only one direction of the D2D transmission path is woken up each time, resulting in better power saving.

[0176] Step 5: The memory access request reaches the memory control module through the data bus of the memory chip.

[0177] Figure 8b The described cross-chip communication data transmission process specifically includes:

[0178] Step 6: The memory control module receives the memory response and transmits the wake-up signal to the wake-up signal receiving interface of the memory chip and the wake-up signal receiving interface of the kernel chip through the wake-up signal sending interface of the memory chip and the substrate trace. At the same time, the actual memory access response is transmitted from the memory control module through the data bus. After the propagation time C through the data bus is calculated in advance, it reaches the D2D interconnect interface of the second chip.

[0179] Step 7: The kernel core's wake-up signal receiving interface wakes up the kernel core's timer, and the storage core's wake-up signal receiving interface wakes up the storage core's timer and starts the countdown. The countdown waiting time is configured via register (CB), where B is the wake-up time length of the second core's D2D interconnect interface.

[0180] In another embodiment, the wake-up signal can be sent only to the wake-up signal receiving interface on the storage die side, and then a dedicated signal is provided by the physical link between the D2D interconnect of the second die and the D2D interconnect of the first die to wake up the D2D interconnect of the first die of the core die.

[0181] Step 8: After the timers of the kernel chip and the storage chip have finished waiting for their respective timeout periods, the D2D interconnect of the second chip and the D2D interconnect of the first chip begin to wake up. After time B, the D2D interconnect of the second chip and the D2D interconnect of the first chip are successfully woken up.

[0182] In other embodiments, the wake-up time length (B) of the D2D interconnect of the second core in the waiting time CB can also be the wake-up time length of the D2D interconnect of the first core, or the larger of the wake-up time length of the D2D interconnect of the first core and the wake-up time length of the D2D interconnect of the second core can be used as B.

[0183] Step 9: After a time C since step 6, memory access responses arrive sequentially via the data bus at the D2D interconnect of the second memory chip. At this point, the D2D interconnect of the second memory chip has been successfully woken up by step 8, and the memory access responses can be smoothly transmitted to the D2D interconnect of the first memory chip in the core chip via the second memory chip's D2D interconnect. After all memory access response transmissions are complete, the D2D interconnect of the second memory chip enters an idle state for a period of time before entering a sleep state to save power.

[0184] After a time interval C following step 6, the D2D interconnect of the first kernel has been successfully woken up via step 8. Memory access responses transmitted via the D2D interconnect of the second kernel can then be successfully passed to the kernel kernel via the D2D interconnect of the first kernel. After all memory access response transmissions are completed, the D2D interconnect of the first kernel enters an idle state for a period of time before entering a sleep state to save power.

[0185] In this step, the D2D interconnect of the first chip in the above embodiment includes TX1 and RX1, and the D2D interconnect of the second chip includes TX2 and RX2. During the transmission of the memory access response, TX2 of the second chip's D2D interconnect and RX1 of the first chip's D2D interconnect are woken up, and after the memory access request transmission is completed, they respectively enter a power-saving state. During the transmission of the memory access response, TX1 of the first chip's D2D interconnect and RX2 of the second chip's D2D interconnect remain in a power-saving state (e.g., a sleep state), meaning that only one direction of the D2D transmission path is woken up each time, resulting in better power saving.

[0186] Step 10: The memory access response received by the D2D interconnect of the first chip is transmitted through the data bus and reaches the kernel module, thus ending the entire transmission process.

[0187] In one embodiment of this specification, a processor including a chip with the above-described structure can execute the aforementioned inter-chip communication method to achieve a faster data processing speed.

[0188] like Figure 9 The diagram illustrates a computer device according to an embodiment of this specification. The computer device in this embodiment may include the core components of this specification and utilize the aforementioned inter-core communication methods. These methods can also be run on the computer device in this embodiment to execute the methods described in this specification. The computer device 902 may include one or more processors 904, such as one or more central processing units (CPUs), each of which may implement one or more hardware threads. The computer device 902 may also include any memory 906 for storing information of any kind, such as code, settings, data, etc. Non-limitingly, for example, memory 906 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory may provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of the computer device 902. In one case, when processor 904 executes associated instructions stored in any memory or combination of memories, the computer device 902 may perform any operation of the associated instructions. The computer device 902 also includes one or more drive mechanisms 908 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0189] Computer device 902 may also include an input / output module 910 (I / O) for receiving various inputs (via input device 912) and providing various outputs (via output device 914). A specific output mechanism may include a presentation device 916 and an associated graphical user interface (GUI) 918. In other embodiments, the input / output module 910 (I / O), input device 912, and output device 914 may be omitted, and the device may function solely as a computer device within a network. Computer device 1202 may also include one or more network interfaces 920 for exchanging data with other devices via one or more communication links 922. One or more communication buses 924 couple the components described above together.

[0190] Communication link 922 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 922 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0191] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the methods described above.

[0192] This specification also provides a processor, including a chip that performs the methods described above. The processor may be a single-core or multi-core microprocessor, a system-on-a-chip (SoC), a graphics processing unit (GPU), or any integrated circuit that includes at least one computing core and has a hierarchical cache memory.

[0193] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the methods described above.

[0194] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0195] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0196] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0197] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0198] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0199] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0200] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0201] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0202] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0203] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.

Claims

1. A chip-to-chip communication method, characterized in that, include, At a predetermined time before the communication data sent by at least one first functional module of the first core arrives at the D2D interconnect of the first core, the D2D interconnect of the first core and the D2D interconnect of the second core are woken up by bypass. The shortest predetermined time is the time required to wake up the D2D interconnect of the first chip or the D2D interconnect of the second chip.

2. The method according to claim 1, characterized in that, Communication data sent by at least one first functional module of the first core reaches the D2D interconnect of the first core through a data bus; The D2D interconnect of the first core sends the communication data to the D2D interconnect of the second core through a physical link. At least one first functional module of the first chip wakes up the D2D interconnect of the first chip at a predetermined time via a first bypass, and wakes up the D2D interconnect of the second chip at the predetermined time via a second bypass.

3. The method according to claim 2, characterized in that, The first bypass includes at least one portion of the substrate trace between the first functional module and the first chip's D2D interconnect; the second bypass includes at least one portion of the substrate trace between the first functional module and the second chip's D2D interconnect.

4. The method according to claim 3, characterized in that, The first functional module of the first chip wakes up the D2D interconnect of the first chip at a predetermined time via a first bypass, and wakes up the D2D interconnect of the second chip at the predetermined time via a second bypass, further comprising: The first functional module, according to the predetermined time, directly wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip through the first bypass and the second bypass, respectively.

5. The method according to claim 4, characterized in that, The first functional module, according to the predetermined time, directly wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip through the first bypass and the second bypass, respectively, further including... Using the timer inside the first functional module, the D2D interconnect of the first chip is directly woken up through the first bypass according to the predetermined time, and the D2D interconnect of the second chip is directly woken up through the second bypass.

6. The method according to claim 3, characterized in that, The first functional module of the first chip wakes up the D2D interconnect of the first chip at a predetermined time via a first bypass, and wakes up the D2D interconnect of the second chip at the predetermined time via a second bypass, further comprising: Using a first timer in the first chip, the D2D interconnect of the first chip is woken up via the first bypass according to the predetermined time, and the D2D interconnect of the second chip is woken up via the second bypass.

7. The method according to claim 6, characterized in that, Using a first timer in the first chip, waking up the D2D interconnect of the first chip via the first bypass according to the predetermined time further includes, The first bypass includes a first wake-up signal transmitting interface, a first wake-up signal receiving interface, and the first timer; The first functional module transmits a wake-up signal to the substrate traces through the first wake-up signal transmission interface; The first wake-up signal is transmitted to the first timer through the substrate traces and the first wake-up signal receiving interface; The first timer sends the wake-up signal to the D2D interconnect of the first chip according to the predetermined time.

8. The method according to claim 7, characterized in that, Using a first timer in the first chip, waking up the D2D interconnect of the second chip via the second bypass according to the predetermined time further includes, The wake-up signal is transmitted to the second wake-up signal receiving interface of the second chip through the substrate traces and the first wake-up signal receiving interface. The second wake-up signal receiving interface of the second chip transmits the wake-up signal to the second timer of the second chip through the substrate traces; The second timer of the second chip sends the wake-up signal to the D2D interconnect of the second chip according to the predetermined time.

9. The method according to claim 7, characterized in that, Using a first timer in the first chip, waking up the D2D interconnect of the second chip via the second bypass according to the predetermined time further includes, The first timer sends the wake-up signal to the D2D interconnect of the first chip according to the predetermined time, and transmits the wake-up signal to the D2D interconnect of the second chip through the first wake-up signal receiving interface, the substrate trace, and the second wake-up signal receiving interface of the second chip.

10. The method according to claim 7, characterized in that, Using a first timer in the first chip, waking up the D2D interconnect of the second chip via the second bypass according to the predetermined time further includes the first timer sending the wake-up signal to the D2D interconnect of the first chip according to the predetermined time, and transmitting the wake-up signal to the D2D interconnect of the second chip through the physical link between the D2D interconnect of the first chip and the D2D interconnect of the second chip.

11. The method according to any one of claims 5 to 10, characterized in that, The timer, which wakes up the D2D interconnect of the first chip and the D2D interconnect of the second chip according to a predetermined time, further includes, The D2D interconnect of the first chip and the D2D interconnect of the second chip are woken up according to a preset delay time and the predetermined time, wherein the preset delay time is the time it takes for the communication data sent by the first functional module to reach the D2D interconnect of the first chip through the data bus.

12. The method according to claim 2, characterized in that, After a predetermined time before the communication data sent by at least one first functional module of the first chip arrives at the D2D interconnect of the first chip, and after waking up the D2D interconnect of the first chip and the D2D interconnect of the second chip, the process further includes... The D2D interconnect of the first chip is activated before or simultaneously with the arrival of the communication data at the D2D interconnect of the first chip; the D2D interconnect of the second chip is activated before or simultaneously with the arrival of the communication data at the D2D interconnect of the second chip. The communication data is transmitted to the second core through the D2D interconnect of the first core after it is woken up and the D2D interconnect of the second core. The D2D interconnect of the first chip and the D2D interconnect of the second chip enter an energy-saving state.

13. The method according to claim 12, characterized in that, The communication data, after being transmitted to the second core via the D2D interconnect of the first core after being woken up and the D2D interconnect of the second core, also includes... After the communication data is transmitted to the second chip, after a predetermined time threshold, the D2D interconnect of the first chip and the D2D interconnect of the second chip enter an energy-saving state.

14. The method according to claim 2, characterized in that, The minimum predetermined time is the maximum time required to wake up the D2D interconnect of the first chip or the D2D interconnect of the second chip.

15. A core element, characterized in that, Includes at least one first functional module and a first core of D2D interconnect; At least one of the first functional modules is configured to implement the function of the chip and, at a predetermined time before the transmitted communication data arrives at the D2D interconnect of the first chip, wake up the D2D interconnect of the first chip and the D2D interconnect of the second chip by bypass; wherein the predetermined time is at least the time required to wake up the D2D interconnect of the first chip or the D2D interconnect of the second chip.

16. The core according to claim 15, characterized in that, It also includes, A data bus is configured such that communication data sent by at least one first functional module reaches the D2D interconnect of the first core via the data bus; The physical link is configured to transmit the communication data sent by the D2D interconnect of the first core to the D2D interconnect of the second core; A first bypass is configured such that at least one of the first functional modules wakes up the D2D interconnect of the first chip ahead of the predetermined time via the first bypass. The second bypass is configured such that at least one of the first functional modules wakes up the D2D interconnect of the second chip ahead of the predetermined time via the second bypass.

17. The core according to claim 16, characterized in that, The first bypass includes at least one portion of the substrate trace between the first functional module and the first chip's D2D interconnect; the second bypass includes at least one portion of the substrate trace between the first functional module and the second chip's D2D interconnect.

18. The core according to claim 17, characterized in that, The first functional module includes a timer, which, according to the predetermined time, directly wakes up the D2D interconnect of the first chip through the first bypass and directly wakes up the D2D interconnect of the second chip through the second bypass.

19. The core according to claim 17, characterized in that, The first bypass also includes, First wake-up signal sending interface, first wake-up signal receiving interface, first timer; The first functional module transmits a wake-up signal to the substrate traces through the first wake-up signal transmission interface; The first wake-up signal is transmitted to the first timer through the substrate traces and the first wake-up signal receiving interface; The first timer sends the wake-up signal to the D2D interconnect of the first chip according to the predetermined time.

20. The core according to claim 19, characterized in that, The second bypass also includes, The substrate trace between the first wake-up signal receiving interface and the second wake-up signal receiving interface of the second chip; The second wake-up signal receiving interface is connected to the second timer of the second chip; The second timer of the second chip is connected to the D2D interconnect of the second chip.

21. The core chip according to claim 19, characterized in that, The second bypass also includes, The substrate trace between the first wake-up signal receiving interface and the second wake-up signal receiving interface of the second chip; The second wake-up signal receiving interface is connected to the second chip via D2D interconnect.

22. The core chip according to claim 19, characterized in that, The second bypass also includes a physical link between the D2D interconnect of the first chip and the D2D interconnect of the second chip.

23. The core chip according to claim 19, characterized in that, The first wake-up signal sending interface is located near the first functional module; the first timer is located near the D2D interconnect of the first chip.

24. A processor, characterized in that... Includes the core as described in any one of claims 15-23.

25. A computer device comprising a memory and a computer program stored in the memory and executable on a processor, characterized in that, Includes the processor as described in claim 24 above.

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