Method, device and equipment for testing duplexer, storage medium and program product

Abstract

The invention discloses a duplexer testing method and device, equipment, a storage medium and a program product, and the specific technical scheme comprises the steps: obtaining the performance parameters of a to-be-tested duplexer under a target wiring model, integrating a plurality of wiring models on a printed circuit board, each wiring model comprises three connection ports, and the connection ports are used for connecting the duplexer; and determining an optimal wiring model of the to-be-tested duplexer according to the performance parameters under each wiring model. Thus, through the printed circuit board integrated with various wiring models and the connection port provided by each wiring model, it is avoided that the duplexer is tested through welding a copper pipe, and the test efficiency is improved.

Description

Technical Field

[0001] This application belongs to the field of Internet of Things (IoT) technology, and in particular relates to a method, apparatus, equipment, storage medium, and program product for testing duplexers. Background Technology

[0002] In the field of mobile communications, a duplexer is a crucial component. It allows devices to transmit and receive signals simultaneously without interference. However, in practical use, insufficient isolation in the duplexer can cause strong signals from the transmitting end to leak to the receiving end, resulting in interference. Therefore, pre-testing the duplexer is essential to ensure its performance.

[0003] Currently, the testing method for duplexers typically involves soldering the duplexer onto a modular printed circuit board (PCB), and then connecting it to a testing instrument via soldered copper tubing. For example... Figure 1 As shown, users need to manually solder the duplexers onto the printed circuit board. This results in low testing efficiency for the duplexers. Summary of the Invention

[0004] This application provides a method, apparatus, device, storage medium, and program product for testing duplexers, which can improve the testing efficiency of duplexers.

[0005] In a first aspect, embodiments of this application provide a method for testing a duplexer, comprising: Obtain the performance parameters of the duplexer under the target routing model. The printed circuit board integrates multiple routing models, each of which includes three connection ports for connecting the duplexer. The optimal wiring model for the duplexer under test is determined based on the performance parameters of each wiring model.

[0006] In one possible implementation, obtaining the performance parameters of the duplexer under test under various wiring models includes: When there is one type of duplexer under test and one type of target routing model, the performance parameters of multiple duplexers under test are obtained for each target routing model in multiple printed circuit boards. Among them, the multiple duplexers to be tested are of the same type.

[0007] In one possible implementation, obtaining the performance parameters of the duplexer under test under various wiring models includes: When there is one type of duplexer to be tested and multiple types of target routing models, the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board are obtained. Among them, the multiple duplexers to be tested are of the same type, and the type of the target wiring model is the same as the type of wiring model in the printed circuit board.

[0008] In one possible implementation, obtaining the performance parameters of the duplexer under test under various wiring models includes: When there are multiple types of duplexers to be tested and multiple types of target routing models, for each duplexer to be tested, the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board are obtained. Among them, the multiple duplexers to be tested are of the same type.

[0009] In one possible implementation, after determining the optimal wiring model for the duplexer under test based on the performance parameters under each wiring model, the method further includes: Obtain the return loss and isolation of the duplexer under test; The optimal return loss point is determined based on the return loss and the isolation, so that the user can determine the actual optimal return loss point based on the optimal return point, the output of the power amplifier, and the isolation.

[0010] In one possible implementation, determining the optimal wiring model for the duplexer under test based on performance parameters under each wiring model includes: The performance parameters under each wiring model are weighted and summed to obtain a performance index score. The routing model with the highest maximum performance index score is taken as the optimal routing model.

[0011] Secondly, embodiments of this application provide a method for testing a duplexer, including: The acquisition module is used to acquire the performance parameters of the duplexer under the target routing model. The printed circuit board integrates multiple routing models, each of which includes three connection ports for connecting the duplexer. The determination module is used to determine the optimal wiring model for the duplexer under test based on the performance parameters of each wiring model.

[0012] Thirdly, embodiments of this application provide a terminal device, the device including: a processor and a memory storing computer program instructions; A method for implementing duplexer testing as described in the first aspect when the processor executes computer program instructions.

[0013] Fourthly, embodiments of this application provide a computer storage medium on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the duplexer testing method as described in the first aspect is implemented.

[0014] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform a duplexer test method as described in the first aspect.

[0015] This application provides a method, apparatus, device, storage medium, and program product for testing a duplexer. This application also provides a printed circuit board (PCB) integrating multiple wiring patterns, each providing three connection ports. Users can connect a duplexer to the wiring pattern via these ports. When the user connects the duplexer to the target wiring pattern, the performance parameters of the duplexer under the target wiring pattern are obtained. By comparing the performance parameters under different wiring patterns, the optimal wiring pattern for the duplexer can be determined. Thus, by using a PCB integrating multiple wiring patterns and the connection ports provided by each pattern, testing the duplexer by soldering copper tubing is avoided, improving testing efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is an exemplary schematic diagram of a method for testing a duplexer in the prior art, provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a duplexer testing method provided in an embodiment of this application; Figure 3 This is an exemplary schematic diagram of a printed circuit board provided in an embodiment of this application; Figure 4 This is an exemplary schematic diagram of a printed circuit board provided in an embodiment of this application; Figure 5 These are exemplary schematic diagrams of the five wiring models provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of a duplexer testing device provided in an embodiment of this application; Figure 7This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0018] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0019] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0020] It should be noted that the acquisition, storage, use, and processing of data in this application embodiment all comply with the relevant provisions of national laws and regulations.

[0021] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0022] Currently, the R&D process for RF duplexers includes three main steps: component selection, layout and routing model selection, and PCB fabrication and debugging. The performance of duplexers available on the market varies significantly, necessitating performance verification through testing during the component selection process. Specifically, users typically solder the duplexer onto the PCB using copper tubing for testing. However, this requires soldering the duplexer onto PCBs with different layouts and routing, leading to low testing efficiency.

[0023] Regarding the placement and routing model selection process, during placement and routing simulation, users perform simulations based on the component parameters and routing methods provided by the duplexer manufacturer. However, in actual routing, users need to select the routing method based on the actual application scenario of the duplexer. Thus, manually selecting the routing method also leads to low testing efficiency.

[0024] Regarding the board-building and debugging process, when the duplexer's output terminal transmits at high power, the high-power signal can interfere with the input link through the output link or the duplexer itself, resulting in a decrease in input sensitivity. To ensure that the duplexer's isolation meets application requirements, users need to repeatedly debug during board-building testing, which increases R&D costs and reduces the testing efficiency of the duplexer.

[0025] To address the problems in the prior art, embodiments of this application provide a method, apparatus, device, storage medium, and program product for duplexer testing. Figure 2 A schematic flowchart of a duplexer test according to an embodiment of this application is shown. This method is applied to electronic devices, such as... Figure 2 As shown, the method includes: S201. Obtain the performance parameters of the duplexer under the target wiring model.

[0026] The printed circuit board integrates multiple routing models, each including three connection ports for connecting to a duplexer. Performance parameters include transmitter insertion loss (TXIL), receiver insertion loss (RXIL), and isolation.

[0027] The printed circuit board (PCB) uses the same layer stack and board material as PCBs in common wiring models, reducing errors in the dielectric constant of the board material and the width of the impedance lines. The TX, RX, and TRX of each duplexer on the PCB are pre-processed for impedance and length to ensure that the impedance matches the corresponding link impedance in PCBs of common wiring models; in various wiring models, the length and impedance of the TX, RX, and TRX of each duplexer are consistent. Furthermore, there are no matching circuits around each duplexer under test, thus ensuring more accurate measured performance parameters.

[0028] Specifically, printed circuit boards such as Figure 3 As shown, Figure 3 The PCB shown has five different routing models deployed. Each routing model provides three connection ports: a transmit port (TX), a receive port (RX), and a transceiver port (TRX). In one example, Figure 3The actual printed circuit board shown is as follows: Figure 4 As shown.

[0029] Specifically, in the embodiments of this application, Figure 3 The wiring model shown can be as follows Figure 5 As shown, Figure 5 Five routing models are illustrated: common routing method, routing method with green solder mask removed from transmission lines, routing method with shielded vias reduced, routing method with TX reference to L3 layer, and routing method with TX through L3 layer.

[0030] The common routing method is 8 blind vias, 3 buried vias, with TX, RX, and TRX on the surface layer, referencing the L2 layer, and copper and wires covered with solder mask.

[0031] The routing method for removing solder mask from transmission lines is 8 blind vias and 3 buried vias. TX, RX, and TRX are routed on the surface layer, referencing layer L2. Copper surfaces and lines are not covered with solder mask.

[0032] The routing method to reduce shielded vias is 5 blind vias and 3 buried vias. TX, RX, and TRX are routed on the surface layer, referencing the L2 layer. Copper surfaces and lines are covered with solder mask.

[0033] The routing method for TX references the L3 layer is 8 blind vias and 3 buried vias. TX, RX, and TRX are routed on the surface layer. TX is referenced to the L3 layer, and RX and TRX are referenced to the L2 layer. Copper surfaces and lines are covered with solder mask.

[0034] The TX is routed on the L3 layer with 8 blind vias and 3 buried vias. The RX and TRX are routed on the surface layer, with reference to the L2 layer for the RX and TRX. The TX is routed on the L3 layer, with reference to the L2 / L4 layers. The copper surface and the lines are covered with solder mask.

[0035] S202. Based on the performance parameters of each cabling model, determine the optimal cabling model for the duplexer under test.

[0036] Using the above method, a printed circuit board (PCB) is provided, integrating multiple routing models. Each routing model provides three connection ports, allowing users to connect a duplexer to the routing model. When the user connects the duplexer under test to the target routing model, the performance parameters of the duplexer under test under the target routing model are obtained. By comparing the performance parameters under different routing models, the optimal routing model for the duplexer under test can be determined. Thus, by using a PCB integrating multiple routing models and the connection ports provided for each model, testing the duplexer by soldering copper tubing is avoided, improving testing efficiency.

[0037] In some embodiments of this application, the above-described S201 step of obtaining the performance parameters of the duplexer under the target wiring model can be categorized into three cases: Case 1: When there is one type of duplexer to be tested and one type of target routing model, obtain the performance parameters of multiple duplexers to be tested under the target routing models on multiple printed circuit boards.

[0038] Among them, multiple duplexers under test are of the same type. The wiring patterns included in the above multiple printed circuit boards are identical, and the positions of each wiring pattern on the printed circuit board are the same.

[0039] Thus, with one type of duplexer to be tested and one type of target routing model, multiple duplexers of the same duplexer are soldered to the same target routing model on multiple printed circuit boards. This allows for the acquisition of performance parameters of the multiple duplexers under the target routing models on multiple printed circuit boards. This verifies the performance of a duplexer under a specific routing model, and the selection of the duplexer is determined based on the performance parameters, providing an accurate basis for device selection.

[0040] Case 2: When there is one type of duplexer to be tested and multiple types of target routing models, obtain the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board.

[0041] Among them, multiple duplexers under test are of the same type, and the type of target wiring model is the same as the type of wiring model in the printed circuit board.

[0042] Taking duplexer A as an example, the performance parameters of multiple duplexers under test were obtained under different target routing models on the same printed circuit board, as shown in Table 1: Table 1

[0043] Thus, with one type of duplexer to be tested and multiple types of wiring models, multiple duplexers are soldered onto different wiring models on the same printed circuit board. By comparing and testing duplexers under different wiring models, the optimal wiring method for the duplexer is determined.

[0044] Case 3: When there are multiple types of duplexers to be tested and multiple types of target routing models, for each duplexer to be tested, obtain the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board.

[0045] Among them, multiple duplexers under test are of the same type.

[0046] In one example, there are 3 types of duplexers to be tested, and 5 types of wiring patterns on a printed circuit board. Therefore, for each type of duplexer to be tested, 5 duplexers are obtained, and then the 5 duplexers are soldered onto a printed circuit board respectively. In this way, the performance parameters of each duplexer to be tested under different wiring patterns can be obtained.

[0047] By using the method provided in the embodiments of this application, different models of duplexers are soldered onto different printed circuit boards, and the differences between different duplexers under different wiring models are measured, the optimal wiring method for multiple duplexers can be determined.

[0048] In some embodiments of this application, the above-mentioned step S202, determining the optimal wiring model for the duplexer under test based on the performance parameters of each wiring model, can be specifically implemented as follows: The performance parameters for each routing model are weighted and summed to obtain a performance score. The routing model with the highest maximum performance score is selected as the optimal routing model.

[0049] The weights corresponding to different performance parameters can be preset based on experience.

[0050] It should be noted that the above method for determining the optimal routing model is only an example. In actual implementation, users can determine the optimal routing model based on actual business needs and different performance parameters.

[0051] Using the method provided in this application, the performance parameters for each cabling model include transmitter insertion loss, receiver insertion loss, and isolation. By weighted summing of these three performance parameters, a performance score corresponding to each cabling model can be determined. Thus, the performance score can measure the performance level of each cabling model, and the optimal cabling model can be accurately determined based on the performance score.

[0052] In some embodiments of this application, after determining the optimal wiring model for the duplexer under test based on the performance parameters of each wiring model in S102 above, the method further includes: Step 1: Obtain the return loss and isolation of the duplexer under test.

[0053] Step 2: Determine the optimal return loss point based on return loss and isolation, so that users can determine the actual optimal return loss point based on the optimal return loss point, the power amplifier output, and the isolation.

[0054] In the actual surface mount debugging stage, users should take into account both the output of the power amplifier and ensure that the return loss point is close to the optimal point, so as to maximize the isolation of the duplexer.

[0055] The method provided in this application involves measuring the return loss and isolation of the duplexer under test using a testing instrument, and then determining the optimal return loss point using the measured return loss and isolation. This allows users to adjust the actual optimal return loss point based on the measured optimal return point, the power amplifier output, and the isolation, thereby improving the accuracy of the debugging and ensuring that the debugged duplexer better suits the actual application scenario.

[0056] Based on the same concept, embodiments of this application provide an apparatus for testing a duplexer, such as... Figure 6 As shown, the device includes: The acquisition module 601 is used to acquire the performance parameters of the duplexer under the target routing model. The printed circuit board integrates multiple routing models, each routing model including three connection ports, which are used to connect the duplexer. The determination module 602 is used to determine the optimal wiring model of the duplexer under test based on the performance parameters of each wiring model.

[0057] In one possible implementation, module 601 is specifically used for: When there is one type of duplexer under test and one type of target routing model, the performance parameters of multiple duplexers under test are obtained for each target routing model in multiple printed circuit boards. Among them, the multiple duplexers to be tested are of the same type.

[0058] In one possible implementation, module 601 is specifically used for: When there is one type of duplexer to be tested and multiple types of target routing models, the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board are obtained. Among them, the multiple duplexers to be tested are of the same type, and the type of the target wiring model is the same as the type of wiring model in the printed circuit board.

[0059] In one possible implementation, module 601 is specifically used for: When there are multiple types of duplexers to be tested and multiple types of target routing models, for each duplexer to be tested, the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board are obtained. Among them, the multiple duplexers to be tested are of the same type.

[0060] In one possible implementation, the acquisition module 601 is further configured to acquire the return loss and isolation of the duplexer under test; The determination module 602 is used to determine the optimal return loss point based on the return loss and the isolation, so that the user can determine the actual optimal return loss point based on the optimal return point, the output of the power amplifier, and the isolation.

[0061] In one possible implementation, module 602 is specifically used for: The performance parameters under each wiring model are weighted and summed to obtain a performance index score. The routing model with the highest maximum performance index score is taken as the optimal routing model.

[0062] It should be noted that the device for duplexer testing is the same as the method for duplexer testing described above. All implementation methods in the above method embodiments are applicable to the embodiments of this device and can achieve the same technical effect.

[0063] Figure 7 A schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application is shown.

[0064] The terminal device may include a processor 701 and a memory 702 storing computer program instructions.

[0065] Specifically, the processor 701 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0066] Memory 702 may include mass storage for data or instructions. For example, and not limitingly, memory 702 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 702 may include removable or non-removable (or fixed) media. Where appropriate, memory 702 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 702 is non-volatile solid-state memory.

[0067] In a particular embodiment, memory 702 may include read-only memory (ROM), random access memory (RAM), disk storage media device, optical storage media device, flash memory device, electrical, optical, or other physical / tangible memory storage device. Thus, generally, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to one aspect of this disclosure.

[0068] The processor 701 implements any of the duplexer testing methods described in the above embodiments by reading and executing computer program instructions stored in the memory 702.

[0069] In one example, the electronic device may also include a communication interface 703 and a bus 704. Wherein, as... Figure 7 As shown, the processor 701, memory 702, and communication interface 703 are connected through bus 704 and complete communication with each other.

[0070] The communication interface 703 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0071] Bus 704 includes hardware, software, or both, that couples components of an electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 704 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0072] Furthermore, in conjunction with the duplexer testing methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the duplexer testing methods in the above embodiments.

[0073] This application also provides a computer program product, including a computer program that, when executed by a processor, implements any of the duplexer testing methods described in the above embodiments.

[0074] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0075] The functional blocks shown in the above block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0076] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0077] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0078] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for testing a duplexer, characterized in that, include: Obtain the performance parameters of the duplexer under the target routing model. The printed circuit board integrates multiple routing models, each of which includes three connection ports for connecting the duplexer. The optimal wiring model for the duplexer under test is determined based on the performance parameters of each wiring model.

2. The method according to claim 1, characterized in that, The acquisition of performance parameters of the duplexer under test under various wiring models includes: When there is one type of duplexer under test and one type of target routing model, the performance parameters of multiple duplexers under test are obtained for each target routing model in multiple printed circuit boards. Among them, the multiple duplexers to be tested are of the same type.

3. The method according to claim 1, characterized in that, The acquisition of performance parameters of the duplexer under test under various wiring models includes: When there is one type of duplexer to be tested and multiple types of target routing models, the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board are obtained. Among them, the multiple duplexers to be tested are of the same type, and the type of the target wiring model is the same as the type of wiring model in the printed circuit board.

4. The method according to claim 1, characterized in that, The acquisition of performance parameters of the duplexer under test under various wiring models includes: When there are multiple types of duplexers to be tested and multiple types of target routing models, for each duplexer to be tested, the performance parameters of multiple duplexers to be tested under different target routing models on the same printed circuit board are obtained. Among them, the multiple duplexers to be tested are of the same type.

5. The method according to claim 1, characterized in that, After determining the optimal wiring model for the duplexer under test based on the performance parameters of each wiring model, the method further includes: Obtain the return loss and isolation of the duplexer under test; The optimal return loss point is determined based on the return loss and the isolation, so that the user can determine the actual optimal return loss point based on the optimal return loss point, the output of the power amplifier, and the isolation.

6. The method according to claim 1, characterized in that, The step of determining the optimal wiring model for the duplexer under test based on the performance parameters of each wiring model includes: The performance parameters under each wiring model are weighted and summed to obtain a performance index score. The routing model with the highest maximum performance index score is taken as the optimal routing model.

7. An apparatus for testing a duplexer, characterized in that, include: The acquisition module is used to acquire the performance parameters of the duplexer under the target routing model. The printed circuit board integrates multiple routing models, each of which includes three connection ports for connecting the duplexer. The determination module is used to determine the optimal wiring model for the duplexer under test based on the performance parameters of each wiring model.

8. An electronic device, characterized in that, The electronic device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the duplexer testing method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the duplexer testing method as described in any one of claims 1-6.

10. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the duplexer test method as described in any one of claims 1-6.

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