Memory device and memory system

Abstract

The invention provides a memory device and a memory system. The memory device includes a memory string. The memory string includes a plurality of first switching elements and a plurality of second switching elements. The second switching elements and the first switching elements are staggered and coupled in series. When the memory string has a first conductance value, each of the first switching elements has a first threshold voltage level and each of the second switching elements has a second threshold voltage level, and when the memory string has a second conductance value, each of the first switching elements has a first threshold voltage level and each of the second switching elements has a second threshold voltage level. Each switching element in a first portion of the first switching elements has a second threshold voltage level and each switching element in a second portion of the second switching elements has a first threshold voltage level, the first conductance value is less than the second conductance value, and the first threshold voltage level is greater than the second threshold voltage level.

Description

Technical Field

[0001] This disclosure relates to a memory technology, and more particularly to a memory device and memory system. Background Technology

[0002] Euclidean distance is the shortest distance between two points in Euclidean space and can be used as a general benchmark to measure the similarity between two data points. Euclidean distance is also applied in various fields, such as geometry, data mining, deep learning, and others. However, memory devices used to calculate Euclidean distance can be unstable and complex to operate. Therefore, designing stable and easy-to-operate memory devices for calculating Euclidean distance is an important research topic. Summary of the Invention

[0003] This disclosure includes a memory device. The memory device includes a memory string. The memory string includes a plurality of first switching elements and a plurality of second switching elements. The second switching elements are alternately arranged with the first switching elements and are coupled in series. When the memory string has a first conductance value, each of the first switching elements has a first threshold voltage level and each of the second switching elements has a second threshold voltage level. When the memory string has a second conductance value, each of the first switching elements in a first portion has a second threshold voltage level and each of the second switching elements in a second portion has a first threshold voltage level, wherein the first conductance value is less than the second conductance value, and the first threshold voltage level is greater than the second threshold voltage level.

[0004] In some embodiments, when the memory string has a third conductance value, one of the first switching elements has a third threshold voltage level, the second conductance value is greater than the third conductance value, and the third threshold voltage level is greater than the first threshold voltage level.

[0005] In some embodiments, when the memory string has a third conductance value, each switching element in a third portion of the first switching element has a second threshold voltage level and each switching element in a fourth portion of the second switching element has a first threshold voltage level, the third conductance value is greater than the second conductance value, the number of switching elements in the third portion is greater than the number of switching elements in the first portion, and the number of switching elements in the fourth portion is greater than the number of switching elements in the second portion.

[0006] In some embodiments, when the memory string has a third conductance value, a third switching element of the first switching element has a third threshold voltage level, the third conductance value is greater than the second conductance value, and the third threshold voltage level is greater than the first threshold voltage level.

[0007] In some embodiments, when the memory string has a fourth conductance value, the third switching element has a fourth threshold voltage level, the fourth conductance value is greater than the third conductance value, the first threshold voltage level is greater than the fourth threshold voltage level, and the second threshold voltage level is less than the fourth threshold voltage level.

[0008] This disclosure includes a memory device. The memory device includes: a first memory string for receiving a plurality of first word line signals; and a second memory string, coupled in parallel with the first memory string, for receiving a plurality of second word line signals. The first word line signals and the second word line signals correspond to an input bit. When the input bit has a first encoded value, each of a first portion of the first word line signal has a first voltage level, each of a second portion of the first word line signal has a second voltage level, and each of the second word line signals has a first voltage level. When the input bit has a second encoded value, each of a third portion of the second word line signal has a first voltage level, each of a fourth portion of the second word line signal has a second voltage level, and each of the first word line signals has a first voltage level, and the first encoded value is different from the second encoded value.

[0009] In some embodiments, the second voltage level is greater than the first voltage level.

[0010] In some embodiments, when the input bit has a wildcard code value, each of the first word line signal and the second word line signal has a first voltage level.

[0011] In some embodiments, when the input bit has a first encoded value, the input bit has a first logical value; when the input bit has a wildcard encoded value, the input bit has a second logical value greater than the first logical value; and when the input bit has a second encoded value, the input bit has a third logical value greater than the second logical value.

[0012] In some embodiments, the first memory string and the second memory string are further used to store a storage bit. When the storage bit has a first logic value, the first memory string and the second memory string have a first conductance value and a second conductance value, respectively. When the storage bit has a second logic value, the first memory string and the second memory string have a second conductance value and a first conductance value, respectively. The second conductance value is greater than the first conductance value.

[0013] In some embodiments, the second conductance value is proportional to the square of the difference between the second logic value and the first logic value.

[0014] In some embodiments, when the storage bit has a third logic value, the first memory string and the second memory string each have a third conductance value and a fourth conductance value, the third conductance value being proportional to the square of the difference between the third logic value and the first logic value, and the fourth conductance value being proportional to the square of the difference between the third logic value and the second logic value.

[0015] In some embodiments, when the storage bit has a fourth logic value, the first memory string and the second memory string each have a fifth conductance value and a sixth conductance value, the fifth conductance value being proportional to the square of the difference between the fourth logic value and the first logic value, and the sixth conductance value being proportional to the square of the difference between the fourth logic value and the second logic value.

[0016] In some embodiments, the difference between the fourth logic value and the third logic value is equal to the difference between the third logic value and the first logic value.

[0017] In some embodiments, the first memory string and the second memory string are further used to generate a first string current signal and a second string current signal, respectively. When the input bit has a first encoded value, the current level of the first string current signal is proportional to the square of the difference between the logic value of the input bit and the logic value of the storage bit, and when the input bit has a second encoded value, the current level of the second string current signal is proportional to the square of the difference between the logic value of the input bit and the logic value of the storage bit.

[0018] In some embodiments, when the input bit has a first encoded value, the second string current signal has a zero current level, and when the input bit has a second encoded value, the first string current signal has a zero current level.

[0019] In some embodiments, when the input bit has a wildcard code value, each of the first string current signal and the second string current signal has a zero current level.

[0020] This disclosure includes a memory system. The memory system includes: a plurality of memory blocks, each for receiving a plurality of string select line signals; and a sensing device for receiving a plurality of bit line signals from the memory blocks, wherein the memory blocks include a plurality of first memory string pairs, each of the first memory string pairs for storing a plurality of first storage bits, and each of the first memory string pairs for comparing the first storage bits with a plurality of input bits to generate a first bit line signal among the bit line signals.

[0021] In some embodiments, the memory block further includes a plurality of second memory string pairs, which are used to store a plurality of second memory bits and to compare the second memory bits and the input bits respectively to generate a second bit line signal in the bit line signal.

[0022] In some embodiments, the number of the first memory string pairs is half that of the memory blocks. Attached Figure Description

[0023] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings.

[0024] Figures 1A to 1H This schematically illustrates a portion of a memory device performing encoding operations according to an embodiment of the present disclosure;

[0025] Figure 2A and Figure 2B The schematic diagram illustrates a scenario where memory cells have different resistance values ​​according to an embodiment of the present disclosure;

[0026] Figure 2C A schematic diagram illustrating the distribution of threshold voltage levels of memory cells according to an embodiment of the present disclosure is shown.

[0027] Figure 2D The diagram illustrates various distributions of threshold voltage levels of memory cells according to embodiments of the present disclosure.

[0028] Figures 3A to 3J This schematically illustrates a portion of a memory device performing encoding operations according to an embodiment of the present disclosure;

[0029] Figures 4A to 4C The illustration schematically shows a memory device performing a search operation according to an embodiment of the present disclosure;

[0030] Figures 5A to 5H A schematic diagram illustrating storage bits for storing different logic values ​​in a memory device according to an embodiment of the present disclosure is shown.

[0031] Figure 6A The schematic diagram illustrates various encoding scenarios of the memory device according to embodiments of the present disclosure;

[0032] Figure 6B The illustration shows a schematic diagram of a memory device calculating various Euclidean distances according to an embodiment of the present disclosure;

[0033] Figure 6C A diagram illustrating a comparison between approximate Euclidean distance calculation and ideal Euclidean distance calculation of a memory device according to an embodiment of the present disclosure is shown schematically.

[0034] Figure 7A A schematic diagram of a memory device according to an embodiment of the present disclosure is shown;

[0035] Figure 7B A schematic diagram illustrating a memory device having N logic levels for its storage bits according to an embodiment of the present disclosure is shown.

[0036] Figure 7C The schematic diagram illustrates various encoding scenarios of the memory device according to embodiments of the present disclosure;

[0037] Figure 8 A schematic diagram of a memory system according to an embodiment of the present disclosure is shown.

[0038] Explanation of reference numerals in the attached figures:

[0039] 100, 300, 400, 700, 810: Memory devices

[0040] MS1, MSL1, MSR1: Memory strings

[0041] VBL: Voltage Level

[0042] TG, TS, T1~T128, TR1~TR96, TL1~TL96, TGL, TGR, TSL, TSR: Switching elements

[0043] N11, N71: Nodes

[0044] VSS: Reference voltage signal

[0045] ISTRING, ISL1, ISR1: String current signals

[0046] WL1~WL128, WLL1~WLL96, WLR1~WLR96, WLLm, WLL(m-1), WLL(m-2), WLRm, WLR(m-1), WLR(m-2), WL1_1, WL512_1, WL512_96: Word line signals

[0047] BL, BL0~BL128K: Bit line signals

[0048] SSL, SSLL, SSLR, SSL1~SSL512: String select line signals

[0049] GSL, GSLL, GSLR, GSL1~GSL512: Ground selection line signal

[0050] RSTRING, RSL, RSR: String resistors

[0051] HVT'', HVT, LVT, HVT1~HVT3, HVT-, HVT', HVT31~HVT34: Threshold voltage levels

[0052] GMS1, X, GL1, GR1, G: Conductivity values

[0053] ISTRL: Current Level

[0054] R, R'', r: Resistance values

[0055] MC1: Memory unit

[0056] VH2, VH1: Search bias voltage levels

[0057] n, m, N: positive integers

[0058] MSP1: Memory string pair

[0059] N41: Node

[0060] 601~602: Tables

[0061] L61~L66: Line segments

[0062] 800: Memory System

[0063] 820: Sensing device

[0064] 830: Temporary Encoding Device

[0065] 840: Output device

[0066] BK1~BK512: Memory blocks

[0067] MS1_0, MS2_0, MS1_128K, MS512_0, MS512_128K: Memory strings

[0068] MSP1_0, MSP1_128K, MSP3_128K: Memory string pairs

[0069] Y1~Y256: Input bits. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0071] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the scope of this application.

[0072] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this case pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context and this case, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0074] The following describes several embodiments of this invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the invention. That is, these practical details are not essential in some embodiments of this disclosure. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.

[0075] Figures 1A to 1H This is a schematic diagram illustrating an encoding operation on a portion of a memory device 100 according to some embodiments of this case. In some embodiments, the memory device 100 may include multiple memory strings, such as Figure 1A The memory string MS1 is shown. The memory string MS1 is used to generate a string current signal ISTRING through the memory string MS1 based on the voltage level VBL of the bit line signal BL and the resistance value of the memory string MS1 itself.

[0076] like Figure 1A As shown, the memory string MS1 includes switching elements TG, T1~T96, and TS. However, the embodiments of this disclosure are not limited thereto. In various embodiments, the memory string MS1 may include various numbers of switching elements; that is, 96 may be replaced with other positive integers. In various embodiments, the switching elements T1~T96 may be implemented using N-type metal-oxide-semiconductor (NMOS) transistors or P-type metal-oxide-semiconductor (PMOS) transistors.

[0077] like Figure 1A As shown, switching elements TG, T1~T96, and TS are connected in series and coupled to each other. One end of switching element TS is used to output the bit line signal BL, and the other end of switching element TS is coupled to one end of switching element T96. The other end of switching element T96 is coupled to one end of switching element T95. The other end of switching element T95 is coupled to one end of switching element T94, and so on. One end of switching element T1 is coupled to switching element T2, and the other end of switching element T1 is coupled to one end of switching element TG. The other end of switching element TG is used to receive the reference voltage signal VSS. Switching elements T1~T96 are arranged sequentially. In other words, odd-numbered switching elements T1, T3, ..., T93 and T95 are alternated with even-numbered switching elements T2, T4, ..., T94 and T96.

[0078] In some embodiments, the control terminals of the switching elements TG, T1~T96, and TS are used to receive the ground selection line signal GSL, the word line signals WL1~WL96, and the string selection line signal SSL, respectively. In some embodiments, the control terminal is referred to as the gate terminal.

[0079] In some embodiments, the reference voltage signal VSS has a ground voltage level. During operation, the bit line signal BL has a voltage level VBL higher than the ground voltage level to generate the string current signal ISTRING.

[0080] In some embodiments, two adjacent switching elements can operate as a single memory cell. For example, switching elements T96 and T95 can operate as memory cell MC48. Switching elements T94 and T93 can operate as memory cell MC47, and so on. Switching elements T2 and T1 can operate as memory cell MC1. The switching elements can have different threshold voltage levels to store different logic values. In some embodiments, the memory cell is referred to as an in-memory searching (IMS) cell.

[0081] In some embodiments, the IMS cell can be implemented using floating gate memory, split-gate memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, floating dot memory, dynamic random-access memory (DRAM), and / or other similar DRAM devices. In some embodiments, the memory cell can also be implemented using emerging memories, such as ferroelectric field-effect transistors (FeFETs). In various embodiments, the memory device 100 can be implemented using a two-dimensional cache structure or a three-dimensional cache structure.

[0082] During the encoding operation, switching elements T1~T96 are adjusted to the corresponding threshold voltage levels, causing the string resistor RSTRING of the memory string MS1 to have the corresponding resistance value. The current value of the string current signal ISTRING is equal to the voltage level VBL divided by the resistance value of the string resistor RSTRING.

[0083] exist Figure 1A In the illustrated embodiment, switching element T96 has a threshold voltage level HVT''. Each of switching elements T95, T93, ..., T3 and T1 has a threshold voltage level LVT, and each of switching elements T94, T92, ..., T4 and T2 has a threshold voltage level HVT.

[0084] Correspondingly, memory cell MC48 has a resistance value R'', and each of memory cells MC1 to MC47 has a resistance value R. In response to a threshold voltage level HVT'' being much greater than the threshold voltage level HVT, the resistance value R'' is much greater than the resistance value R. For example, the resistance value R'' can be greater than one hundred times the resistance value R. In this case, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 47 plus R'', that is, 47R + R''. Correspondingly, the conductance value GMS1 of the memory string MS1 is equal to the conductance value X multiplied by zero. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by zero.

[0085] exist Figure 1BIn the illustrated embodiment, each of the switching elements T95, T93, ..., T3 and T1 has a threshold voltage level LVT, and each of the switching elements T96, T94, T92, ..., T4 and T2 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC48 has a resistance value R.

[0086] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 48, that is, 48R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 1. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 1, which is also equal to the voltage level VBL divided by the resistance value 48R.

[0087] exist Figure 1C In the illustrated embodiment, each of the switching elements T95, T93, ..., T75 and T73 has a threshold voltage level LVT, and each of the switching elements T96, T94, T92, ..., T76 and T74 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC37 to MC48 has a resistance value R.

[0088] On the other hand, each of the switching elements T72, T70, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T71, T69, T67, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC36 has a resistance value r. The resistance value R is much larger than the resistance value r. For example, the resistance value R can be greater than one hundred times the resistance value r. The resistance value r is equal to zero resistance.

[0089] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 12, that is, 12R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 4. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 4, which is also equal to the voltage level VBL divided by the resistance value 12R.

[0090] exist Figure 1D In the illustrated embodiment, each of the switching elements T95, T93, T91, and T89 has a threshold voltage level LVT, and each of the switching elements T96, T94, T92, and T90 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC45 to MC48 has a resistance value R.

[0091] Furthermore, switching elements T88 and T87 have threshold voltage levels HVT1 and LVT, respectively, such that the resistance value of memory cell MC44 is equal to the resistance value R multiplied by 1.33, that is, 1.33R. The threshold voltage level HVT1 is greater than the threshold voltage level HVT and less than the threshold voltage level HVT''.

[0092] On the other hand, each of the switching elements T86, T84, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T85, T83, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC43 has a resistance value r.

[0093] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 5.33, that is, 5.33R. Correspondingly, the conductance value of the memory string MS1 is equal to the conductance value X multiplied by 9. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 9, which is also equal to the voltage level VBL divided by the resistance value 5.33R.

[0094] exist Figure 1E In the illustrated embodiment, each of the switching elements T95, T93, and T91 has a threshold voltage level LVT, and each of the switching elements T96, T94, and T92 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC46 to MC48 has a resistance value R.

[0095] On the other hand, each of the switching elements T90, T88, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T89, T87, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC45 has a resistance value r.

[0096] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 3, that is, 3R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 16. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 16, which is also equal to the voltage level VBL divided by the resistance value 3R.

[0097] exist Figure 1F In the illustrated embodiment, switching elements T95 and T96 have threshold voltage levels LVT and HVT, respectively. Correspondingly, memory cell MC48 has a resistance value R.

[0098] Furthermore, switching elements T93 and T94 have threshold voltage levels LVT and HVT2, respectively. Threshold voltage level HVT2 is smaller than threshold voltage level HVT and greater than threshold voltage level LVT. Correspondingly, the resistance value of memory cell MC47 is equal to the resistance value R multiplied by 0.92, that is, 0.92R.

[0099] On the other hand, each of the switching elements T92, T90, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T91, T89, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC46 has a resistance value r.

[0100] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 1.92, that is, 1.92R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 25. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 25, which is also equal to the voltage level VBL divided by the resistance value 1.92R.

[0101] exist Figure 1G In the illustrated embodiment, switching elements T95 and T96 have threshold voltage levels LVT and HVT1, respectively. Correspondingly, the resistance value of memory cell MC48 is equal to the resistance value R multiplied by 1.33, that is, 1.33R.

[0102] On the other hand, each of the switching elements T94, T92, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T93, T91, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC47 has a resistance value r.

[0103] At this point, the string resistor RSTRING has a resistance value of 1.33R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 36. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 36, and also equal to the voltage level VBL divided by the resistance value 1.33R.

[0104] exist Figure 1H In the illustrated embodiment, switching elements T95 and T96 have threshold voltage levels LVT and HVT3, respectively. Threshold voltage level HVT3 is greater than threshold voltage level HVT2 and less than threshold voltage level HVT. Correspondingly, the resistance value of memory cell MC48 is equal to the resistance value R multiplied by 0.97, that is, 0.97R.

[0105] On the other hand, each of the switching elements T94, T92, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T93, T91, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC47 has a resistance value r.

[0106] At this point, the string resistor RSTRING has a resistance value of 0.97R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 49. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 49, and also equal to the voltage level VBL divided by the resistance value 0.97R.

[0107] exist Figures 1A to 1H In the illustrated embodiment, the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 1. , , , , , , and In this way, 8 levels of Euclidean distance calculations can be performed using the memory device 100. This approach is based on a single-level cell (SLC) mode for Euclidean distance IMS cells. Compared to multi-level cell (MLC) and triple-level cell (TLC) modes, the SLC mode offers higher reliability.

[0108] Figure 2A and Figure 2B This is a schematic diagram illustrating a scenario where the memory cell MC1 has different resistance values, according to some embodiments of this case. Figure 2A and Figure 2B The illustrated embodiment uses memory cell MC1 as an example. However, other memory cells in the memory device 100, such as memory cells MC2 to MC48, also have features similar to memory cell MC1.

[0109] exist Figure 2A In the illustrated embodiment, switching elements T1 and T2 have threshold voltage levels LVT and HVT, respectively. Word line signals WL1 and WL2 have search bias levels VH2 and VH1, respectively. The search bias level VH2 is greater than the search bias level VH1. Correspondingly, switching element T2 has a smaller conductance, causing memory cell MC1 to have a resistance value R.

[0110] exist Figure 2BIn the illustrated embodiment, switching elements T1 and T2 have threshold voltage levels HVT and LVT, respectively. Word line signals WL1 and WL2 have search bias levels VH2 and VH1, respectively. Correspondingly, each of switching elements T1 and T2 has a large conductance value, such that the memory cell MC1 has a resistance value r.

[0111] Please refer to Figures 1A to 2B ,exist Figures 1A to 1H In the embodiment shown, each of the word line signals WL1, WL3, ..., WL93 and WL95 has a search bias level VH2, and each of the word line signals WL2, WL4, ..., WL94 and WL96 has a search bias level VH1.

[0112] Figure 2C This is a schematic diagram illustrating the distribution of threshold voltage levels of memory cells according to some embodiments of this case. Figure 2C The horizontal axis corresponds to voltage, and the vertical axis corresponds to the number of memory cells.

[0113] like Figure 2C As shown, the threshold voltage levels LVT, HVT, and search bias levels VH1 and VH2 are arranged sequentially on the horizontal axis. A memory window exists between the threshold voltage levels LVT and HVT. For the threshold voltage level LVT, each of the search bias levels VH2 and VH1 is a high gate overdrive voltage. For the threshold voltage level HVT, the search bias levels VH2 and VH1 are the high gate overdrive voltage and low gate overdrive voltage, respectively.

[0114] Figure 2D This is a schematic diagram illustrating various distributions of threshold voltage levels of memory cells according to some embodiments of this case. Figure 2D The horizontal axis corresponds to voltage, and the vertical axis corresponds to the number of memory cells.

[0115] like Figure 2D As shown, in different scenarios, memory cells can have different threshold voltage levels HVT-, HVT, HVT', and HVT''. Threshold voltage level HVT- is greater than threshold voltage level LVT. Threshold voltage level HVT is greater than threshold voltage level HVT-. Threshold voltage level HVT' is greater than threshold voltage level HVT. Threshold voltage level HVT'' is greater than threshold voltage level HVT'. Furthermore, each of threshold voltage levels HVT-, HVT, and HVT' is less than the search bias level VH1, and threshold voltage level HVT'' is greater than the search bias level VH1.

[0116] Please refer to Figure 2A and Figure 2DWhen switching elements T1 and T2 have threshold voltage levels LVT and HVT- respectively, the resistance of memory cell MC1 is equal to the resistance R multiplied by 0.5, i.e., 0.5R. When switching elements T1 and T2 have threshold voltage levels LVT and HVT respectively, memory cell MC1 has a resistance R. When switching elements T1 and T2 have threshold voltage levels LVT and HVT' respectively, the resistance of memory cell MC1 is equal to the resistance R multiplied by 1.5, i.e., 1.5R. When switching elements T1 and T2 have threshold voltage levels LVT and HVT'' respectively, memory cell MC1 has a resistance R''. In other words, the higher the threshold voltage level of switching element T2, the higher the resistance of memory cell MC1.

[0117] Figures 3A to 3I This is a schematic diagram illustrating a portion of a memory device 300 performing encoding operations according to some embodiments of this case. Please refer to... Figure 1A and Figure 3A Memory device 300 is a variation of memory device 100. The components of memory device 300 use the same numbering system as memory device 100. For the sake of brevity, the discussion will focus on the parts of memory device 300 that differ from memory device 100 rather than their similarities.

[0118] Compared to memory device 100, the memory string MS1 in memory device 300 further includes switching elements T97 to T128. However, the embodiments of this disclosure are not limited thereto. In various embodiments, the memory string MS1 may include various numbers of switching elements, that is, 128 may be replaced with other positive integers.

[0119] like Figure 3A As shown, the switching elements TG, T1~T128 and TS are connected in series and coupled to each other. The switching elements T1~T128 are arranged in sequence. In other words, the odd-numbered switching elements T1, T3, ..., T125 and T127 are alternately arranged with the even-numbered switching elements T2, T4, ..., T126 and T128.

[0120] Similar to switching elements T1~T96, adjacent pairs of switching elements T97~T128 can also be operated as a memory unit. For example, switching elements T128 and T127 can be operated as memory unit MC64. Switching elements T126 and T125 can be operated as memory unit MC63, and so on. Switching elements T98 and T97 can be operated as memory unit MC49.

[0121] exist Figure 3AIn the illustrated embodiment, each of the switching elements T127, T125, ..., T3 and T1 has a threshold voltage level LVT, and each of the switching elements T128, T126, ..., T4 and T2 has a threshold voltage level HVT''. Correspondingly, each of the memory cells MC1 to MC64 has a resistance value R''. In this case, the resistance value of the string resistor RSTRING is equal to the resistance value R'' multiplied by 64, that is, 64R''. Correspondingly, the conductance value GMS1 of the memory string MS1 is equal to the conductance value X multiplied by zero. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by zero. In various embodiments, in response to one or more of the memory cells MC1 to MC64 having a resistance value R'', the conductance value GMS1 is equal to the conductance value X multiplied by zero.

[0122] exist Figure 3B In the illustrated embodiment, each of the switching elements T127, T125, ..., T3 and T1 has a threshold voltage level LVT, and each of the switching elements T128, T126, ..., T4 and T2 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC64 has a resistance value R.

[0123] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 64, that is, 64R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 1. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 1, which is also equal to the voltage level VBL divided by the resistance value 64R.

[0124] exist Figure 3C In the illustrated embodiment, each of the switching elements T127, T125, ..., T99 and T97 has a threshold voltage level LVT, and each of the switching elements T128, T126, ..., T100 and T98 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC49 to MC64 has a resistance value R.

[0125] On the other hand, each of the switching elements T96, T94, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T95, T93, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC48 has a resistance value r.

[0126] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 16, that is, 16R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 4. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 4, which is also equal to the voltage level VBL divided by the resistance value 16R.

[0127] exist Figure 3D In the illustrated embodiment, each of the switching elements T125, T123, ..., T117 and T115 has a threshold voltage level LVT, and each of the switching elements T126, T124, ..., T118 and T116 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC58 to MC63 has a resistance value R. Additionally, switching elements T128 and T127 have threshold voltage levels HVT31 and LVT, respectively. The threshold voltage level HVT31 is greater than the threshold voltage level HVT. Correspondingly, the resistance value of the memory cell MC64 is equal to the resistance value R multiplied by 1.11, that is, 1.11R.

[0128] On the other hand, each of the switching elements T114, T112, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T113, T111, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC57 has a resistance value r.

[0129] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 7.11, that is, 7.11R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 9. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 9, which is also equal to the voltage level VBL divided by the resistance value 7.11R.

[0130] exist Figure 3E In the illustrated embodiment, each of the switching elements T127, T125, T123, and T121 has a threshold voltage level LVT, and each of the switching elements T128, T126, T124, and T122 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC61 to MC64 has a resistance value R.

[0131] On the other hand, each of the switching elements T120, T118, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T119, T117, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC60 has a resistance value r.

[0132] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 4, that is, 4R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 16. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 16, which is also equal to the voltage level VBL divided by the resistance value 4R.

[0133] exist Figure 3FIn the illustrated embodiment, each of switching elements T125 and T123 has a threshold voltage level LVT, and each of switching elements T126 and T124 has a threshold voltage level HVT. Correspondingly, each of memory cells MC62 and MC63 has a resistance value R. Additionally, switching elements T128 and T127 have threshold voltage levels HVT32 and LVT, respectively. The threshold voltage level HVT32 is less than the threshold voltage level HVT and greater than the threshold voltage level LVT. Correspondingly, the resistance value of memory cell MC64 is equal to the resistance value R multiplied by 0.56, that is, 0.56R.

[0134] On the other hand, each of the switching elements T122, T120, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T121, T119, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC61 has a resistance value r.

[0135] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 2.56, that is, 2.56R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 25. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 25, which is also equal to the voltage level VBL divided by the resistance value 2.56R.

[0136] exist Figure 3G In the illustrated embodiment, switching elements T125 and T126 have threshold voltage levels LVT and HVT, respectively, causing memory cell MC63 to have a resistance value R. Additionally, switching elements T128 and T127 have threshold voltage levels HVT33 and LVT, respectively. The threshold voltage level HVT33 is less than the threshold voltage level HVT but greater than the threshold voltage level LVT. Correspondingly, the resistance value of memory cell MC64 is equal to the resistance value R multiplied by 0.77, that is, 0.77R.

[0137] On the other hand, each of the switching elements T124, T122, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T123, T121, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC62 has a resistance value r.

[0138] At this point, the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by 1.77, that is, 1.77R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 36. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 36, which is also equal to the voltage level VBL divided by the resistance value 1.77R.

[0139] exist Figure 3H In the illustrated embodiment, switching elements T128 and T127 have threshold voltage levels HVT34 and LVT, respectively. The threshold voltage level HVT34 is greater than the threshold voltage level HVT. Correspondingly, the memory cell MC64 has a resistance value equal to the resistance value R multiplied by 1.3, that is, 1.3R.

[0140] On the other hand, each of the switching elements T126, T124, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T125, T123, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC63 has a resistance value r.

[0141] At this point, the string resistor RSTRING has a resistance value of 1.3R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 49. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 49, and also equal to the voltage level VBL divided by the resistance value 1.3R.

[0142] exist Figure 3I In the illustrated embodiment, switching elements T128 and T127 have threshold voltage levels HVT and LVT, respectively. Correspondingly, memory cell MC64 has a resistance value R.

[0143] On the other hand, each of the switching elements T126, T124, ..., T4 and T2 has a threshold voltage level LVT, and each of the switching elements T125, T123, ..., T3 and T1 has a threshold voltage level HVT. Correspondingly, each of the memory cells MC1 to MC63 has a resistance value r.

[0144] At this point, the string resistor RSTRING has a resistance value R. Correspondingly, the conductance value GMS1 is equal to the conductance value X multiplied by 64. The current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 64, and also equal to the voltage level VBL divided by the resistance value R.

[0145] Please refer to Figure 3D , Figure 3F , Figure 3G and Figure 3H The threshold voltage levels HVT31 to HVT34 correspond to resistance values ​​of 1.11R, 0.56R, 0.77R, and 1.3R, respectively. Correspondingly, threshold voltage level HVT34 is greater than threshold voltage level HVT31. Threshold voltage level HVT31 is greater than threshold voltage level HVT33. Threshold voltage level HVT33 is greater than threshold voltage level HVT32.

[0146] Please refer to Figures 2A to 3I,exist Figures 3A to 3I In the embodiment shown, each of the word line signals WL1, WL3, ..., WL125 and WL127 has a search bias level VH2, and each of the word line signals WL2, WL4, ..., WL126 and WL128 has a search bias level VH1.

[0147] exist Figures 3A to 3I In the illustrated embodiment, the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by 1. , , , , , , , and In this way, the Euclidean distance calculation at level 9 can be performed through the memory device 300.

[0148] Compared to memory device 100, memory device 300 has a higher stack of three-dimensional NAND (3D-NAND) elements. Correspondingly, memory device 300 can provide more levels of Euclidean distance operations. In addition, memory cells with resistance value r are placed close to the ground select line signal GSL to reduce substrate effects.

[0149] Figure 3J This is a schematic diagram illustrating encoding operations performed on a memory device according to some embodiments of this case. In various embodiments, the string current signal ISTRING can have different current levels to calculate different levels of Euclidean distance.

[0150] like Figure 3J As shown, for a positive integer m, the Euclidean distance of order (m+1) can be obtained by having a distance proportional to... , , , , , , , … The string current signal ISTRING of the current level is used for calculation.

[0151] Specifically, for a positive integer n, when the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n (i.e., (n)R), the string current signal ISTRING has a current level ISTRL, which is the voltage level VBL divided by (n)R.

[0152] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 4 (i.e., (n / 4)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 4)R.

[0153] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 9 (i.e., (n / 9)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 9)R.

[0154] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 16 (i.e., (n / 16)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 16)R.

[0155] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 25 (i.e., (n / 25)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 25)R.

[0156] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 36 (i.e., (n / 36)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 36)R.

[0157] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 49 (i.e., (n / 49)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 49)R.

[0158] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 64 (i.e., (n / 64)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 64)R.

[0159] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 81 (i.e., (n / 81)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL divided by (n / 81)R.

[0160] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by 100 (i.e., (n / 100)R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by n. That is, the voltage level VBL is divided by (n / 100)R, and so on.

[0161] When the resistance value of the string resistor RSTRING is equal to the resistance value R multiplied by n and divided by , (that is, (n / When )R), the current level of the string current signal ISTRING is equal to the current level ISTRL multiplied by )R. That is, the voltage level VBL divided by (n / )R. In Figures 1A to 1H In the embodiment shown, m equals 7 and n equals 48. Figures 3A to 3I In the embodiment shown, m equals 8 and n equals 64.

[0162] Figures 4A to 4C This is a schematic diagram illustrating a search operation performed by a memory device 400 according to some embodiments of this case. Figure 4A As shown, the memory device 400 includes at least one memory string pair MSP1. The memory string pair MSP1 includes memory strings MSL1 and MSR1. Memory strings MSL1 and MSR1 are coupled to each other at node N41.

[0163] In some embodiments, memory strings MSL1 and MSR1 are used to generate string current signals ISL1 and ISR1, respectively, and the string current signals ISL1 and ISR1 are added to node N41 to generate bit line signal BL.

[0164] like Figure 4A As shown, the memory string MSL1 includes switching elements TGL, TL1~TL96 and TSL connected in series. The control terminals of the switching elements TGL, TL1~TL96 and TSL are used to receive the ground selection line signal GSLL, the word line signals WLL1~WLL96 and the string selection line signal SSLL, respectively.

[0165] Similarly, the memory string MSR1 includes switching elements TGR, TR1~TR96 and TSR that are coupled in series with each other. The control terminals of the switching elements TGR, TR1~TR96 and TSR are used to receive the ground select line signal GSLR, the word line signals WLR1~WLR96 and the string select line signal SSLR, respectively.

[0166] Please refer to Figure 1A and Figure 4A The memory string MSL1 is one embodiment of the memory string MSL1. Switching elements TGL, TL1~TL96, and TSL correspond to switching elements TG, T1~T96, and TS, respectively. The ground select line signal GSLL, word line signals WLL1~WLL96, and string select line signal SSLL correspond to the ground select line signal GSL, word line signals WL1~WL96, and string select line signal SSL, respectively. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0167] Similarly, memory string MSR1 is one embodiment of memory string MS1. Switching elements TGR, TR1~TR96, and TSR correspond to switching elements TG, T1~T96, and TS, respectively. Ground select line signal GSLR, word line signals WLR1~WLR96, and string select line signal SSLR correspond to ground select line signal GSL, word line signals WL1~WL96, and string select line signal SSL, respectively. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0168] During the search operation, word line signals WLL1~WLL96 and WLR1~WLR96 can be used to carry input bit SB1. Figure 4A In the illustrated embodiment, input bit SB1 has a logic value of 0, 1, or 2, and a corresponding encoded value of 0.

[0169] In response to input bit SB1 having an encoded value of 0, each of word line signals WLR1 to WLR96 has a search bias level VH1, each of word line signals WLL1, WLL3, ..., WLL93 and WLL95 has a search bias level VH2, and each of word line signals WLL2, WLL4, ..., WLL94 and WLL96 has a search bias level VH1.

[0170] In some embodiments, the string selection line signals SSLL and SSLR may also operate differently depending on the encoded value of the input bit SB1. Figure 4A In the illustrated embodiment, in response to input bit SB1 having an encoded value of 0, string select line signal SSLL has an on voltage level to turn on switching element TSL, and string select line signal SSLR has an on voltage level or an off voltage level to turn on or off switching element TSR.

[0171] exist Figure 4B In the illustrated embodiment, input bit SB1 has a logic value of 3 or 4 and a wildcard encoded value. In some embodiments, the wildcard encoded value refers to any encoded value when input. In response to input bit SB1 having a wildcard encoded value, each of the word line signals WLR1~WLR96 and WLL1~WLL96 has a search bias level VH1.

[0172] On the other hand, in response to the wildcard code value of input bit SB1, string select line signal SSLL has an on or off voltage level to turn on or off switching element TSL, and string select line signal SSLR has an on or off voltage level to turn on or off switching element TSL.

[0173] exist Figure 4C In the illustrated embodiment, input bit SB1 has a logic value of 5, 6, or 7 and an encoded value of 7. In response to input bit SB1 having the encoded value 7, each of word line signals WLL1 to WLL96 has a search bias level VH1, each of word line signals WLR1, WLR3, ..., WLR93 and WLR95 has a search bias level VH2, and each of word line signals WLR2, WLR4, ..., WLR94 and WLR96 has a search bias level VH1.

[0174] On the other hand, in response to the input bit SB1 encoded value 7, the string selection line signal SSLL has an on or off voltage level to turn on or off the switching element TSL, and the string selection line signal SSLR has an on voltage level to turn on the switching element TSR.

[0175] Figures 5A to 5H This is a schematic diagram illustrating storage bits for storing different logic values ​​in a memory device 400 according to some embodiments of this case. For simplicity, some reference numerals are omitted. Figures 5A to 5H The designations of switching elements TGL, TL1~TL96, TSL, TGR, TR1~TR96, and TSR are not shown in the diagram.

[0176] In some embodiments, the memory string pair MSP1 is used to store the storage bit DT1. The storage bit DT1 can have various logical values. Please refer to... Figures 1A to 1H and Figure 5A In response to the logical value of storage bit DT1, each of the memory strings MSL1 and MSR1 has Figures 1A to 1H The threshold voltage level configuration of the memory string MS1 corresponding to one of them is shown.

[0177] exist Figure 5AIn the illustrated embodiment, storage bit DT1 has a logic value of 0. Correspondingly, memory string MSL1 has... Figure 1A The configuration shown, and the memory string MSR1 has Figure 1H The configuration is shown. In other words, the conductance value GL1 of memory string MSL1 is equal to the conductance value X multiplied by zero, and the string resistor RSL of memory string MSL1 has a resistance value of 47R+R''. The conductance value GR1 of memory string MSR1 is equal to the conductance value X multiplied by 49, and the string resistor RSR of memory string MSR1 has a resistance value of 0.97R.

[0178] exist Figure 5B In the illustrated embodiment, storage bit DT1 has a logic value of 1. Correspondingly, memory string MSL1 has... Figure 1B The configuration shown, and the memory string MSR1 has Figure 1G The configuration shown. In other words, the conductance GL1 is equal to the conductance X multiplied by 1, and the string resistor RSL has a resistance of 48 R. The conductance GR1 is equal to the conductance X multiplied by 36, and the string resistor RSR has a resistance of 1.33 R.

[0179] exist Figure 5C In the illustrated embodiment, storage bit DT1 has a logic value of 2. Correspondingly, memory string MSL1 has... Figure 1C The configuration shown, and the memory string MSR1 has Figure 1F The configuration shown. In other words, the conductance GL1 is equal to the conductance X multiplied by 4, and the string resistor RSL has a resistance of 12 R. The conductance GR1 is equal to the conductance X multiplied by 25, and the string resistor RSR has a resistance of 1.92 R.

[0180] exist Figure 5D In the illustrated embodiment, storage bit DT1 has a logic value of 3. Correspondingly, memory string MSL1 has... Figure 1D The configuration shown, and the memory string MSR1 has Figure 1E The configuration shown. In other words, the conductance value GL1 is equal to the conductance value X multiplied by 9, and the string resistor RSL has a resistance value of 5.33R. The conductance value GR1 is equal to the conductance value X multiplied by 16, and the string resistor RSR has a resistance value of 3R.

[0181] exist Figure 5E In the illustrated embodiment, storage bit DT1 has a logic value of 4. Correspondingly, memory string MSL1 has... Figure 1E The configuration shown, and the memory string MSR1 has Figure 1DThe configuration shown. In other words, the conductance value GL1 is equal to the conductance value X multiplied by 16, and the string resistor RSL has a resistance value of 3R. The conductance value GR1 is equal to the conductance value X multiplied by 9, and the string resistor RSR has a resistance value of 5.33R.

[0182] exist Figure 5F In the illustrated embodiment, storage bit DT1 has a logic value of 5. Correspondingly, memory string MSL1 has... Figure 1F The configuration shown, and the memory string MSR1 has Figure 1C The configuration shown. In other words, the conductance GL1 is equal to the conductance X multiplied by 25, and the string resistor RSL has a resistance of 1.92 R. The conductance GR1 is equal to the conductance X multiplied by 4, and the string resistor RSR has a resistance of 12 R.

[0183] exist Figure 5G In the illustrated embodiment, storage bit DT1 has a logic value of 6. Correspondingly, memory string MSL1 has... Figure 1G The configuration shown, and the memory string MSR1 has Figure 1B The configuration shown. In other words, the conductance GL1 is equal to the conductance X multiplied by 36, and the string resistor RSL has a resistance of 1.33R. The conductance GR1 is equal to the conductance X multiplied by 1, and the string resistor RSR has a resistance of 48R.

[0184] exist Figure 5H In the illustrated embodiment, storage bit DT1 has a logic value of 7. Correspondingly, memory string MSL1 has... Figure 1H The configuration shown, and the memory string MSR1 has Figure 1A The configuration shown. In other words, the conductance GL1 is equal to the conductance X multiplied by 49, and the string resistor RSL has a resistance of 0.97R. The conductance GR1 is equal to the conductance X multiplied by zero, and the string resistor RSR has a resistance of 47R+R''.

[0185] exist Figures 5A to 5H In the illustrated embodiment, the conductance value GL1 is proportional to the square of logic values ​​0 to 7, and the conductance value GR1 is proportional to the square of logic values ​​7 to 0. In response to two different logic values ​​of the storage bit DT1, the conductance values ​​GL1 and GR1 correspond to the square of the difference between the two logic values.

[0186] For example, in response to a logic value of 0 in storage bit DT1, the conductance value GR1 is proportional to the square of 7 (the difference between logic values ​​0 and 7). In response to a logic value of 7 in storage bit DT1, the conductance value GL1 is proportional to the square of 7 (the difference between logic values ​​0 and 7). In response to a logic value of 1 in storage bit DT1, the conductance value GL1 is proportional to the square of 1 (the difference between logic values ​​0 and 1), and the conductance value GR1 is proportional to the square of 6 (the difference between logic values ​​1 and 7).

[0187] Similarly, in response to storage bit DT1 having a logic value of 2, conductance value GL1 is proportional to the square of 2 (the difference between logic values ​​0 and 2), and conductance value GR1 is proportional to the square of 5 (the difference between logic values ​​2 and 7). The difference between logic values ​​2 and 1 is equal to the difference between logic values ​​1 and 0.

[0188] Figure 6A This is a schematic diagram illustrating various encoding scenarios of the memory device 400 according to some embodiments of this case. Please refer to... Figure 4A and Figure 6A In some embodiments, the memory strings MSL1 and MSR1 can be referred to as the left string and right string, respectively.

[0189] like Figure 6A As shown, when input bit SB1 has a logic value of 0, 1, or 2, input bit SB1 has an encoded value of 0. Correspondingly, word line signals WLL1~WLL96 have interleaved search bias levels VH1 and VH2. The string select line signal SSLL has an on-state voltage level. At this time, the memory string MSL1 can be processed as follows: Figures 1A to 1H The operation shown in memory string MS1 causes the string current signal ISL1 to have a current level corresponding to the logic value of storage bit DT1. In other words, the current level of string current signal ISL1 is proportional to the square of the difference between the logic value of input bit SB1 and the logic value of storage bit DT1.

[0190] On the other hand, in response to input bit SB1 having an encoded value of 0, each of the word line signals WLR1 to WLR96 has a search bias level VH1, causing at least one switching element in the memory string MSR1 to turn off. The string select line signal SSLR may have a turn-off voltage level. At this time, the string current signal ISR1 has a zero current level.

[0191] When input bit SB1 has a logic value of 3 or 4, input bit SB1 has a wildcard code value. Correspondingly, each of the word line signals WLL1~WLL96 and WLR1~WLR96 has a search bias level VH1, causing at least one switching element in each of the memory strings MSR1 and MSL1 to turn off. Each of the string select line signals SSLL and SSLR can have a shutdown voltage level. At this time, each of the string current signals ISL1 and ISR1 has a zero current level.

[0192] When input bit SB1 has logic values ​​5, 6, or 7, input bit SB1 has the encoded value 7. Correspondingly, word line signals WLR1~WLR96 have interleaved search bias levels VH1 and VH2. The string select line signal SSLR has an on-state voltage level. At this time, the memory string MSR1 can be processed as follows: Figures 1A to 1H The operation shown in memory string MS1 causes the string current signal ISR1 to have a current level corresponding to the logic value of storage bit DT1. In other words, the current level of string current signal ISR1 is proportional to the square of the difference between the logic value of input bit SB1 and the logic value of storage bit DT1.

[0193] On the other hand, in response to input bit SB1 having the encoded value 7, each of the word line signals WLL1 to WLL96 has a search bias level VH1, causing at least one switching element in the memory string MSL1 to turn off. The string select line signal SSLL may have a turn-off voltage level. At this time, the string current signal ISL1 has a zero current level.

[0194] In summary, logic values ​​0, 1, and 2 are grouped into coded value 0. Logic values ​​5, 6, and 7 are grouped into coded value 7. Logic values ​​3 and 4 are grouped into wildcard coded values, corresponding to string current signals with zero current level and without performing Euclidean distance calculations.

[0195] Figure 6B This is a schematic diagram illustrating the calculation of various Euclidean distances by a memory device 400 according to some embodiments of this invention. In some embodiments, a memory string pair MSP1 is used to generate a string current signal IST1. The string current signal IST1 is the sum of string current signals ISL1 and ISR1. In some embodiments, the memory device 400 can calculate the Euclidean distance using the string current signal IST1.

[0196] like Figure 6BAs shown, when input bit SB1 has an encoded value of 0, in response to the storage bit DT1 having logic values ​​0 to 7, the string current signal IST1 has current levels proportional to 0, 1, 4, 9, 16, 25, 36, and 49, respectively. When input bit SB1 has a wildcard encoded value, the string current signal IST1 has a zero current level. When input bit SB1 has an encoded value of 7, in response to the storage bit DT1 having logic values ​​0 to 7, the string current signal IST1 has current levels proportional to 49, 36, 25, 16, 9, 4, 1, and 0, respectively.

[0197] In some embodiments, the Euclidean distance D(x,y) between data points x and y can be expressed as the following equation (1).

[0198] … Equation (1).

[0199] In equation (1), k is a positive integer, and a data point x can be represented as k data values ​​in k dimensions. ), and the data point y can be represented as k data values ​​in k dimensions ( ).

[0200] In some embodiments, storage bit DT1 may correspond to a data value of data point x, such as data value. Input bit SB1 can correspond to a data value of data point y, for example, the data value... At this time, the current level of the string current signal IST1 is approximately proportional to... In this way, the memory device 400 can generate a bit line signal BL with a current level proportional to the square of the Euclidean distance D(x,y) through k memory string pairs.

[0201] Figure 6C A comparison diagram illustrating the approximate Euclidean distance calculation and the ideal Euclidean distance calculation of a memory device 400 according to some embodiments of this case. Figure 6C Tables 601 and 602 are included. Table 601 corresponds to the ideal Euclidean distance calculation. Table 602 corresponds to the approximate Euclidean distance calculation of the memory device 400 in this disclosure.

[0202] like Figure 6C As shown, the distribution in Table 601 is similar to that in Table 602. For example, Table 601 contains line segments L61 to L63. Table 602 contains line segments L64 to L66. Line segments L61 to L63 correspond to line segments L64 to L66, respectively. The current levels of line segments L62 and L65 are relatively low, while the current levels of line segments L61, L63, L64, and L66 are relatively high.

[0203] In some approaches, memory devices use only two switching elements to store one memory bit, resulting in lower reliability and robustness, and more complex word line signal operations.

[0204] Compared to the above approach, in the embodiments of this disclosure, the memory device 400 stores a storage bit DT1 through two memory strings MSL1 and MSR1, which makes the reliability and robustness higher, and the operation of word line signals WLL1~WLL96 and WLR1~WLR96 is simpler.

[0205] Figure 7A This is a schematic diagram illustrating a memory device 700 according to some embodiments of this case. Please refer to... Figure 7A and Figure 4A The memory device 700 is a variation of the memory device 400. The components of the memory device 700 use the same numbering system as those of the memory device 400. For the sake of brevity, the discussion will focus on the parts of the memory device 700 that differ from the memory device 400, rather than their similarities.

[0206] like Figure 7A As shown, memory device 700 includes a memory string pair MSP1. The memory string pair MSP1 includes memory strings MSL1 and MSR1. Memory string MSL1 is used to receive word line signals WLL1~WLLm. Memory string MSR1 is used to receive word line signals WLR1~WLRm. Where m is a positive integer.

[0207] Figure 7B This is a schematic diagram illustrating a memory device 700 with storage bit DT1 having N logic values, according to some embodiments of this case. Figure 7B As shown, in response to storage bit DT1 having logic values ​​from 0 to N, the conductance G of the left string (i.e., memory string MSL1) is proportional to... , , , … And the conductance G of the right string (i.e., the memory string MSR1) is proportional to... , , , .

[0208] Figure 7C These are schematic diagrams illustrating various encoding scenarios of the memory device 700 according to some embodiments of this case. For example... Figure 7CAs shown, when input bit SB1 has a logic value of 0, 1, 2, or 3, input bit SB1 has an encoded value of 0. Correspondingly, word line signals WLL1~WLLm have interleaved search bias levels VH1 and VH2. String select line signal SSLL has an on-state voltage level.

[0209] On the other hand, in response to input bit SB1 having an encoded value of 0, each of the word line signals WLR1~WLRm has a search bias level VH1, causing at least one switching element in the memory string MSR1 to turn off. The string select line signal SSLR may have a turn-off voltage level.

[0210] When input bit SB1 has one of logic values ​​from 4 to (N-4), input bit SB1 has a wildcard coded value. Correspondingly, each of the word line signals WLL1~WLLm and WLR1~WLRm has a search bias level VH1, causing at least one switching element in each of the memory strings MSR1 and MSL1 to be turned off. Each of the string select line signals SSLL and SSLR may have a shutdown voltage level.

[0211] When input bit SB1 has the logic value (N-3), (N-2), (N-1), or N, input bit SB1 has the encoded value N. Correspondingly, word line signals WLR1~WLRm have interleaved search bias levels VH1 and VH2. String select line signal SSLR has an on-state voltage level.

[0212] On the other hand, in response to input bit SB1 having the encoded value 7, each of the word line signals WLL1~WLLm has a search bias level VH1, causing at least one switching element in the memory string MSL1 to turn off. The string select line signal SSLL may have a turn-off voltage level.

[0213] Figure 8 This is a schematic diagram illustrating a memory system 800 according to some embodiments of this case. Figure 8 As shown, the memory system 800 includes a memory device 810, a sensing device 820, a temporary encoding device 830, and an output device 840. In some embodiments, the memory device 810 may be implemented using a three-dimensional NAND memory array.

[0214] In some embodiments, the memory device 810 is used to generate bit line signals BL0~BL128K, where K in 128K represents one thousand. However, this disclosure is not limited thereto. In various embodiments, the memory device can generate various numbers of bit line signals; that is, 128K can be replaced with other positive integers. The sensing device 820 may include a page buffer and a sensing amplifier, and is used to sense the search results corresponding to the bit line signals BL0~BL128K. The temporary encoding device 830 may include a cache buffer and a priority encoder. The output device 840 is used to output the pairing results of the memory device 810.

[0215] In some embodiments, the processing of bit line signals by the temporary encoding device 830 includes AND logic, OR logic, and counting logic processing, and may also include a combination of the above three logics. Please refer to Figures 1A to 8 The temporary encoding device 830 can receive sensing results from memory devices 100, 700 and / or 810, and control the sorting (which can be serial or parallel) and combine the sensing results to generate an overall search result as the pairing result output by the output device 840.

[0216] In some embodiments, the temporary encoding device 830 is further used to perform priority encoding on the search results corresponding to the bit line signals BL0~BL128K. For example, the temporary encoding device 830 integrates the search results corresponding to the bit line signals BL0~BL128K and preferentially selects the address of the bit line signal corresponding to the best search result (that is, the logical value of the input bit and the logical value of the storage bit are closest to each other).

[0217] like Figure 8 As shown, memory device 810 includes multiple memory blocks BK1 to BK512. However, this disclosure is not limited thereto. In various embodiments, memory device 810 may include various numbers of memory blocks; that is, 512 may be replaced with other positive integers.

[0218] In some embodiments, memory block BK1 is used to receive string select line signal SSL1, word line signals WL1_1~WL1_96, and ground select line signal GSL1. Memory block BK2 is used to receive string select line signal SSL2, word line signals WL2_1~WL2_96, and ground select line signal GSL2, and so on. Memory block BK512 is used to receive string select line signal SSL512, word line signals WL512_1~WL512_96, and ground select line signal GSL512.

[0219] like Figure 8As shown, memory block BK1 contains memory strings MS1_0 to MS1_128K. Memory block BK2 contains memory strings MS2_0 to MS2_128K, and so on. Memory block BK512 contains memory strings MS512_0 to MS512_128K.

[0220] In some embodiments, two adjacent memory strings used to generate the same bit-line signal can be similar to... Figure 4A The diagram illustrates the operation on memory string pair MSP1. For example, memory strings MS1_0 and MS2_0 can be operated as memory string pair MSP1_0. Memory strings MS3_0 and MS4_0 can be operated as memory string pair MSP2_0, and so on. Memory strings MS511_0 and MS512_0 can be operated as memory string pair MSP256_0.

[0221] Similarly, memory strings MS1_100 and MS2_100 can be operated as memory string pairs MSP1_100. Memory strings MS3_100 and MS4_100 can be operated as memory string pairs MSP2_100, and so on. Memory strings MS511_100 and MS512_100 can be operated as memory string pairs MSP256_100.

[0222] Similarly, memory strings MS1_128K and MS2_128K can be operated as memory string pairs MSP1_128K. Memory strings MS3_128K and MS4_128K can be operated as memory string pairs MSP2_128K, and so on. Memory strings MS511_128K and MS512_128K can be operated as memory string pairs MSP256_128K.

[0223] In some embodiments, memory string pairs MSP1_0 to MSP256_0 are used to store storage bits X1_0 to X256_0, respectively. Memory string pairs MSP1_1 to MSP256_1 are used to store storage bits X1_1 to X256_1, respectively, and so on. Memory string pairs MSP1_100 to MSP256_100 are used to store storage bits X1_100 to X256_100, respectively. Memory string pairs MSP1_128K to MSP256_128K are used to store storage bits X1_128K to X256_128K, respectively.

[0224] On the other hand, word line signals WL1_1~WL1_96 and WL2_1~WL2_96 are used to carry input bit Y1. Word line signals WL3_1~WL3_96 and WL4_1~WL4_96 are used to carry input bit Y2, and so on. Word line signals WL511_1~WL511_96 and WL512_1~WL512_96 are used to carry input bit Y256.

[0225] During the search operation, memory string pairs MSP1_0 to MSP256_0 are used to compare stored bits X1_0 to X256_0 and input bits Y1 to Y256 to generate a bit line signal BL0. At this time, the current level of the bit line signal BL0 is proportional to the square of the Euclidean distance between the data points of stored bits X1_0 to X256_0 and the data points of input bits Y1 to Y256.

[0226] Please refer to Figure 4A and Figure 8 Each of the memory string pairs MSP1_0 to MSP256_0 is an embodiment of the memory string pair MSP1. Bit line signal BL0 is an embodiment of the bit line signal BL. Therefore, some descriptions will not be repeated.

[0227] Similarly, during the search operation, memory string pairs MSP1_100~MSP256_100 are used to compare stored bits X1_100~X256_100 and input bits Y1~Y256 to generate bit line signal BL100. At this time, the current level of bit line signal BL100 is proportional to the square of the Euclidean distance between the data points of stored bits X1_100~X256_100 and the data points of input bits Y1~Y256, and so on.

[0228] Please refer to Figure 4A and Figure 8 Each of the memory string pairs MSP1_100 to MSP256_100 is an embodiment of the memory string pair MSP1. Bit line signal BL100 is an embodiment of the bit line signal BL. Therefore, some descriptions will not be repeated.

[0229] Similarly, during the search operation, the memory string pairs MSP1_128K~MSP256_128K are used to compare the stored bits X1_128K~X256_128K and the input bits Y1~Y256 to generate the bit line signal BL128K. At this time, the current level of the bit line signal BL0 is proportional to the square of the Euclidean distance between the data points of the stored bits X1_128K~X256_128K and the data points of the input bits Y1~Y256.

[0230] Please refer to Figure 4A and Figure 8Each of the memory string pairs MSP1_128K to MSP256_128K is an embodiment of the memory string pair MSP1. Bit line signal BL128K is an embodiment of the bit line signal BL. Therefore, some descriptions will not be repeated.

[0231] In summary, the 128K data points corresponding to the bit line signals BL0~BL128K can be compared with the data points of the input bits Y1~Y256 in one read cycle.

[0232] exist Figure 8 In the illustrated embodiment, the spatial dimension of the data points for storage bits and input bits is 256, where 256 is half the number of memory blocks, 512. In other words, the spatial dimension is defined by the number of memory blocks. In various embodiments, for a positive integer m, a spatial dimension of m / 2 can be implemented by opening m memory blocks.

[0233] In some embodiments, the square of the Euclidean distance between the data points of the storage bit and the data points of the input bit can be represented by a bit line signal generated by summing the current signals generated by the memory string, and can be detected by a sensing amplifier in the sensing device 820. The square root operation of the square of the Euclidean distance can also be performed by the sensing amplifier.

[0234] In some embodiments, the sensing amplifier may define current conditions to filter all data points and output only data points with high similarity to the central processing unit (CPU) and / or graphics processing unit (GPU).

[0235] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A memory device comprising a memory string (FIG. 1A, MS1), the memory string comprising: Multiple first switching elements (T96, T94, …, T2); and Multiple second switching elements (T95, T93, …, T1) are arranged alternately and coupled in series with the multiple first switching elements. When the memory string has a first conductance value (1×X), each of the plurality of first switching elements has a first threshold voltage level (HVT) and each of the plurality of second switching elements has a second threshold voltage level (LVT). When the memory string has a second conductance value (4×X), each of the first switching elements in a first portion (T72, T70, …, T2) of the plurality of first switching elements has the second threshold voltage level, and each of the second switching elements in a second portion (T71, T69, …, T1) of the plurality of second switching elements has the first threshold voltage level. The first conductivity value is less than the second conductivity value, and The first threshold voltage level is greater than the second threshold voltage level.

2. The memory device according to claim 1, wherein when the memory string has a third conductance value (0×X), one of the plurality of first switching elements has a third threshold voltage level (HVT''). The second conductivity value is greater than the third conductivity value, and The third threshold voltage level is greater than the first threshold voltage level.

3. The memory device according to claim 1, wherein when the memory string has a third conductance value (9×X), each of the third portions (T86, T84, …, T2) of the plurality of first switching elements has the second threshold voltage level and each of the fourth portions (T85, T83, …, T1) of the plurality of second switching elements has the first threshold voltage level. The third conductivity value is greater than the second conductivity value. The number of switching elements in the third part is greater than the number of switching elements in the first part, and The number of switching elements in the fourth part is greater than the number of switching elements in the second part.

4. The memory device according to claim 1, wherein when the memory string has a third conductance value (36×X), a third switching element (T96) of the plurality of first switching elements has a third threshold voltage level (HVT1). The third conductivity value is greater than the second conductivity value, and The third threshold voltage level is greater than the first threshold voltage level.

5. The memory device according to claim 4, wherein when the memory string has a fourth conductance value (49×X), the third switching element has a fourth threshold voltage level (HVT3). The fourth conductivity value is greater than the third conductivity value. The first threshold voltage level is greater than the fourth threshold voltage level, and The second threshold voltage level is lower than the fourth threshold voltage level.

6. A memory device comprising: A first memory string (Figure 4A, MSL1) is used to receive multiple first word line signals (WLL1~WLL96); and A second memory string (MSR1) is connected in parallel with the first memory string and is used to receive multiple second word line signals (WLR1~WLR96). The plurality of first word line signals and the plurality of second word line signals correspond to an input bit (SB1). When the input bit has a first encoded value (0), each of a first portion (WLL96, WLL94, ..., WLL2) of the plurality of first word line signals has a first voltage level (VH1), each of a second portion (WLL95, WLL93, ..., WLL1) of the plurality of first word line signals has a second voltage level (VH2), and each of the plurality of second word line signals has the first voltage level. When the input bit has a second encoded value (7), each of a third portion (WLR96, WLR94, ..., WLR2) of the plurality of second word line signals has the first voltage level, each of a fourth portion (WLR95, WLR93, ..., WLR1) of the plurality of second word line signals has the second voltage level, and each of the plurality of first word line signals has the first voltage level, and The first encoded value is different from the second encoded value.

7. The memory device of claim 6, wherein the second voltage level is greater than the first voltage level.

8. The memory device of claim 6, wherein each of the plurality of first word line signals and the plurality of second word line signals has the first voltage level when the input bit has a wildcard code value.

9. The memory device according to claim 8, wherein When the input bit has the first encoded value, the input bit has a first logical value (0, 1, or 2). When the input bit has the wildcard code value, the input bit has a second logic value (3 or 4) greater than the first logic value, and When the input bit has the second encoded value, the input bit has a third logic value (5, 6 or 7) that is greater than the second logic value.

10. The memory device of claim 6, wherein the first memory string and the second memory string are further configured to store a storage bit (DT1). When the storage bit has a first logic value (0), the first memory string and the second memory string have a first conductance value (0×X) and a second conductance value (49×X), respectively. When the storage bit has a second logic value (7), the first memory string and the second memory string respectively have the second conductance value and the first conductance value, and The second conductivity value is greater than the first conductivity value.

11. The memory device of claim 10, wherein the second conductance value is proportional to the square of the difference between the second logic value and the first logic value.

12. The memory device according to claim 10, wherein when the storage bit has a third logic value (1), the first memory string and the second memory string respectively have a third conductance value (1×X) and a fourth conductance value (36×X). The third conductance value is proportional to the square of the difference between the third logic value and the first logic value, and The fourth conductance value is proportional to the square of the difference between the third logic value and the second logic value.

13. The memory device according to claim 12, wherein when the storage bit has a fourth logic value (2), the first memory string and the second memory string respectively have a fifth conductance value (4×X) and a sixth conductance value (25×X). The fifth conductance value is proportional to the square of the difference between the fourth logic value and the first logic value, and The sixth conductance value is proportional to the square of the difference between the fourth logic value and the second logic value.

14. The memory device of claim 13, wherein the difference between the fourth logic value and the third logic value is equal to the difference between the third logic value and the first logic value.

15. The memory device of claim 10, wherein the first memory string and the second memory string are further configured to generate a first string current signal and a second string current signal, respectively. When the input bit has the first encoded value, the current level of the first string current signal is proportional to the square of the difference between the logic value of the input bit and the logic value of the storage bit, and When the input bit has the second encoded value, the current level of the second string current signal is proportional to the square of the difference between the logic value of the input bit and the logic value of the storage bit.

16. The memory device of claim 15, wherein When the input bit has the first encoded value, the second string current signal has a zero current level, and When the input bit has the second encoded value, the first string current signal has the zero current level.

17. The memory device of claim 15, wherein when the input bit has a wildcard code value, each of the first string current signal and the second string current signal has a zero current level.

18. A memory system comprising: Multiple memory blocks (Figure 8, BK1~BK512) are used to receive multiple string select line signals (SSL1~SSL512); and A sensing device (820) is used to receive multiple bit line signals (BL0~BL128K) from the plurality of memory blocks. The plurality of memory blocks contain a plurality of first memory string pairs (MSP1_0~MSP1_0), The plurality of first memory string pairs are respectively used to store a plurality of first storage bits (X1_0~X256_0), and The plurality of first memory string pairs are used to compare the plurality of first storage bits and the plurality of input bits (Y1~Y256) respectively to generate a first bit line signal (BL0) among the plurality of bit line signals.

19. The memory system of claim 18, wherein the plurality of memory blocks further comprises a plurality of second memory string pairs (MSP1_100~MSP1_100), The plurality of second memory string pairs are respectively used to store a plurality of second storage bits (X1_100~X256_100), and The plurality of second memory string pairs are used to compare the plurality of second storage bits and the plurality of input bits respectively to generate a second bit line signal (BL100) among the plurality of bit line signals.

20. The memory system of claim 18, wherein the number of the plurality of first memory string pairs is half the number of the plurality of memory blocks.

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