Memory system and method of controlling non-volatile memory

Abstract

Provided are a storage system capable of reducing the size of data that needs to be held, and a method for controlling a non-volatile memory. A controller of a memory system performs a third program operation on a memory cell connected to a k-th word line of a first string cell after performing a first write process on a memory cell of the first string cell. The controller executes a second write process to a memory cell connected to the second string cell. The controller performs a third program operation on the memory cell connected to the k-th word line of the second string cell, and a second program operation on the memory cell connected to the (k-1)-th word line of the second string cell, and then performs a fourth program operation on the memory cell connected to the k-th word line of the first string cell after performing a third program operation on the memory cell connected to the k-th word line of the second string cell and a second program operation on the memory cell connected to the (k-1)-th word line of the second string cell.

Description

Technical Field

[0001] Embodiments of the present invention relate to a storage system and a method for controlling non-volatile memory. Background Technology

[0002] In recent years, storage systems with non-volatile memory have become widely used. As one such storage system with semiconductor storage devices, solid-state drives (SSDs) with NAND flash memory are known.

[0003] Semiconductor storage devices like NAND flash memory contain multiple storage cells, each storing data. In order to write data to these multiple storage cells, the SSD controller performs a two-stage programming process.

[0004] During the two-stage programming process, the controller holds the data to be written until the second stage of programming is executed. Therefore, the controller requires resources to temporarily hold the data to be written. Additionally, in the event of an abnormal power outage, the controller needs to prevent the loss of the temporarily held data to be written. Therefore, the controller implements Power Loss Protection (PLP) for writing the data to the NAND flash memory.

[0005] Therefore, the increased capacity requirements of storage systems due to the amount of data that needs to be retained to perform the two-stage programming operations necessitate the development of technologies capable of reducing the amount of data that needs to be retained. Summary of the Invention

[0006] The technical problem to be solved by the embodiments of the present invention is to provide a storage system capable of reducing the size of data that needs to be retained during programming operations of non-volatile memory, and a method for controlling non-volatile memory.

[0007] According to an embodiment, the storage system includes a non-volatile memory and a storage controller. The non-volatile memory has a first string unit and a second string unit, bit lines, a first select gate line and a second select gate line, and first word lines to m word lines. Each of the first and second string units includes: a plurality of storage cells connected in series and containing storage cells from the first to the mth (m is an integer of 4 or more) and each capable of storing n bits (n is an integer of 4 or more) of data; and a select transistor connected in series with the plurality of storage cells. The bit lines are connected to the first and second string units. The first and second select gate lines are respectively connected to the gates of the select transistors of the first and second string units. The first to the mth word lines are respectively connected to the first to the mth storage cells of each of the first and second string units. The storage controller is configured to perform data writing operations on the storage cells using either a first write mode or a second write mode. Each of the first and second write modes includes a first-stage programming action and a second-stage programming action executed after the first-stage programming action. When using the first write mode, the storage controller performs a first programming action as part of the first-stage programming action, and a second programming action as part of the second-stage programming action, enabling the reading of the written n-bit data after the completion of the second-stage programming action. When using the second write mode, the storage controller performs a third programming action as part of the first-stage programming action, enabling the reading of the data written using the first-stage programming action from the storage cell at the writing destination after the completion of the first-stage programming action, and a fourth programming action as part of the second-stage programming action, enabling the reading of the written n-bit data after the completion of the second-stage programming action. The storage controller performs the first programming action on the storage cells of the first string unit connected to the first word line. After performing the first programming operation on the memory cell connected to the first word line of the first string unit, the storage controller performs the following first write process: the first write process involves performing the first programming operation on the memory cell connected to the (x+1)th word line of the first string unit (where x is an integer greater than or equal to 1 and less than (k-2), and k is an integer greater than or equal to 4 and less than m), and performing the second programming operation on the memory cell connected to the xth word line of the first string unit. After performing the first write process, the storage controller performs the third programming operation on the memory cell connected to the kth word line of the first string unit.After performing the third programming operation on the memory cell connected to the k-th word line of the first string unit, the storage controller performs the second programming operation on the memory cell connected to the (k-1)-th word line of the first string unit. After performing the second programming operation on the memory cell connected to the (k-1)-th word line of the first string unit, the storage controller performs the first programming operation on the memory cell connected to the first word line of the second string unit. After performing the first programming operation on the memory cell connected to the first word line of the second string unit, the storage controller performs the following second write process, which is a process of performing the first programming operation on the memory cell connected to the (x+1)-th word line of the second string unit and performing the second programming operation on the memory cell connected to the x-th word line of the second string unit. After performing the second write process, the storage controller performs the third programming operation on the storage cells of the second string unit connected to the k-th word line. After performing the third programming operation on the storage cells of the second string unit connected to the k-th word line, the storage controller performs the second programming operation on the storage cells of the second string unit connected to the (k-1)-th word line. After performing the second programming operation on the storage cells of the second string unit connected to the (k-1)-th word line, the storage controller performs the fourth programming operation on the storage cells of the first string unit connected to the k-th word line. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example configuration of a storage system according to an embodiment.

[0009] Figure 2 This is a block diagram illustrating an example of the configuration of a NAND chip according to an embodiment.

[0010] Figure 3 This is a diagram illustrating an example of the configuration of a memory cell array according to an embodiment.

[0011] Figure 4 This is a diagram illustrating an example of the configuration of each of the multiple blocks included in the storage cell array of the embodiment.

[0012] Figure 5 This is a diagram illustrating an example of the circuit configuration of a memory cell array according to an embodiment.

[0013] Figure 6 This is a cross-sectional view used to illustrate the structure of the string in the implementation method.

[0014] Figure 7 It is along Figure 6 A cross-sectional view of the storage cell along line VI-VI.

[0015] Figure 8 This is a schematic diagram illustrating the threshold distribution of a storage cell array in an implementation method.

[0016] Figure 9 This is a graph showing the change in the threshold voltage distribution of the memory cell caused by the first write in the first write mode of the memory system of the embodiment.

[0017] Figure 10 This is a graph showing the change in the threshold voltage distribution of the memory cell caused by the second write in the first write mode of the memory system of the embodiment.

[0018] Figure 11 This is a diagram illustrating the state transition of a memory cell caused by a single write operation.

[0019] Figure 12 This is a diagram illustrating the state transition of a storage cell caused by a two-step write operation performed in the storage system of the embodiment.

[0020] Figure 13 This is a graph showing the change in the threshold voltage distribution of the memory cells under the second write mode in the memory system of the embodiment.

[0021] Figure 14 This is a graph showing the change in the threshold voltage distribution of the memory cell under the third write mode in the memory system of the embodiment.

[0022] Figure 15 This is a diagram illustrating an example of the write sequence of the two-step write operation performed in the first comparison example.

[0023] Figure 16 This is a diagram illustrating an example of the write sequence of the two-step write operation performed in the second comparative example.

[0024] Figure 17 This is a diagram illustrating an example of the write sequence of the two-step write operation performed in the third comparison example.

[0025] Figure 18 This is a diagram illustrating an example of a one-step write operation and a two-step write operation performed in the fourth comparative example.

[0026] Figure 19 This is a diagram illustrating the first example of the write sequence of the two-step write operation performed in the embodiment.

[0027] Figure 20 This is a diagram illustrating the second example of the write sequence of the two-step write operation performed in the implementation.

[0028] Figure 21This is a diagram illustrating the third example of the write sequence of the two-step write operation performed in the implementation.

[0029] Figure 22 This diagram illustrates the three two-step writing methods in the implementation scheme.

[0030] Figure 23 This diagram illustrates the three writing modes in the implementation method.

[0031] Figure 24 This is a diagram illustrating an example of a command sequence used in the data write process of a storage system in an embodiment.

[0032] Figure 25 This is a diagram illustrating the steps of the first data write process performed in the storage system of the embodiment.

[0033] Figure 26 This is a diagram illustrating the steps of the second data write process performed in the storage system of the embodiment.

[0034] Explanation of reference numerals in the attached figures

[0035] 1…Information processing system, 2…Host, 3…Storage system, 4…Storage controller, 5…NAND flash memory, 7…Bus, 20…Internal bus, 21…Processor, 22…Memory, 40…Internal bus, 41…Host interface, 42…CPU, 43…RAM, 44…ROM, 45…ECC circuit, 46…NAND interface, 51…Control unit, 52…Storage cell array, 61…Power supply circuit, 62…Capacitor. Detailed Implementation

[0036] The embodiments will now be described with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating an example configuration of an information processing system 1 that includes a storage system 3 according to an embodiment. The storage system 3 according to the embodiment is a storage device that includes non-volatile memory.

[0038] Information processing system 1 includes host device (host) 2 and storage system 3. Host 2 and storage system 3 can be connected via bus 7.

[0039] Host 2 is an information processing device. Host 2 is, for example, a personal computer, a server computer, or a portable terminal. Host 2 accesses storage system 3. Specifically, host 2 sends write commands to storage system 3 as commands requesting the writing of data to non-volatile memory. Host 2 sends read commands to storage system 3 as commands requesting the reading of data from non-volatile memory.

[0040] Storage system 3 is a semiconductor storage device configured to write data to and read data from non-volatile memory. Storage system 3 is communicatively connected to host 2. Storage system 3 may be, for example, a solid-state drive (SSD) or SD card. TM Card implementation. Non-volatile memory, such as NAND flash memory.

[0041] Storage system 3 can be used as storage for host 2. Storage system 3 can be built into host 2, or it can be connected to host 2 via cable or network.

[0042] Communication between storage system 3 and host 2 is performed via bus 7. Bus 7 is mainly used for sending data and input / output commands (I / O commands) from host 2 to storage system 3, and for sending data and responses (acknowledgments) from storage system 3 to host 2. I / O commands are commands used to write or read data from NAND flash memory 5. For example, there are write commands for requesting data to be written to NAND flash memory 5, and read commands for requesting data to be read from NAND flash memory 5.

[0043] The interface used to connect storage system 3 to host 2 is based on SCSI, Serial Attached SCSI (SAS), ATA (AT Attachment), Serial ATA (SATA), or PCI Express. TM (PCIe TM Ethernet TM Fibrechannel, NVM Express TM (NVMe TM Standards such as )

[0044] Next, the internal structure of the storage system 3 will be described. The storage system 3 includes a storage controller 4, a NAND flash memory 5, and a power supply circuit 61. The storage system 3 may also include dynamic random access memory (DRAM), which is not shown. DRAM is volatile memory. The storage areas of the DRAM can be used, for example, to temporarily store data used to manage the storage system 3, data read from the NAND flash memory 5, and data to be written to the NAND flash memory 5.

[0045] Storage controller 4 is a storage controller that controls the NAND flash memory 5. Storage controller 4 is, for example, a control circuit like a System-on-a-chip (SoC). Storage controller 4 is electrically connected to the NAND flash memory 5. Storage controller 4 processes various commands received from host 2. Storage controller 4 executes write operations to the NAND flash memory 5 by processing write commands. Storage controller 4 executes read operations to retrieve data from the NAND flash memory 5 by processing read commands.

[0046] The storage controller 4 functions, for example, as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5. The data management performed by the FTL includes the management of mapping information representing the correspondence between logical addresses and physical addresses of the NAND flash memory 5. Block management includes the management of bad blocks, wear leveling, and garbage collection.

[0047] Logical addresses are used by host 2 to assign addresses to storage areas in storage system 3. A logical address is, for example, a logical block address (LBA).

[0048] A physical address is an address that specifies a storage location within a NAND flash memory. A physical address, for example, is a physical block address (PBA).

[0049] The management of the mapping between logical addresses and physical addresses is performed, for example, using a logical-to-physical address translation table (LPIP). The storage controller 4 uses the LPIP to manage the mapping between logical addresses and physical addresses in specific management units. The physical address corresponding to a logical address indicates the physical storage location within the NAND flash memory 5 where user data written to that logical address is located. The LPIP can be loaded from the NAND flash memory 5 into the DRAM during the startup of the storage system 3.

[0050] A write to a single page can only be performed once per P / E cycle. Therefore, the storage controller 4 does not write the updated user data corresponding to a logical address to the physical storage location that already contains the previous user data, but rather to a different physical storage location. Furthermore, the storage controller 4 invalidates the previous user data by updating the logical physical address translation table in a way that associates the logical address with that different physical storage location.

[0051] NAND flash memory 5 is a non-volatile memory. NAND flash memory 5 is, for example, a three-dimensional flash memory. NAND flash memory 5 contains multiple memory cells arranged in a matrix. Each memory cell can, for example, store 4 bits of data. The data that can be stored in each memory cell can also be more than 4 bits. The action of writing 4 bits of data to each memory cell is called a QLC (Quad-Level Cell) programming action, the action of writing 3 bits of data to each memory cell is called a TLC (Triple-Level Cell) programming action, the action of writing 2 bits of data to each memory cell is called an MLC (Multi-Level Cell) programming action, and the action of writing 1 bit of data to each memory cell is called an SLC (Single-Level Cell) programming action.

[0052] Next, an example of the internal structure of the storage controller 4 will be described. The storage controller 4 includes a host interface (host I / F) 41, a CPU 42, random access memory (RAM) 43, read-only memory (ROM) 44, ECC circuitry 45, and a NAND interface (NAND I / F) 46. These components are connected via an internal bus 40. The functions of each component of the storage controller 4 can be implemented using dedicated hardware, a processor executing programs, or a combination thereof. Furthermore, the storage controller 4 performs communication with the host 2.

[0053] Host interface 41 is an interface circuit that performs communication with host 2. Host interface 41 receives, for example, I / O commands and data from host 2. In addition, host interface 41 sends data and responses (acknowledgments) to host 2.

[0054] CPU42 is the processor. CPU42 controls the host interface 41, ECC circuit 45, and NAND interface 46. CPU42 loads the control program (firmware) stored in NAND flash memory 5 or ROM 44 into RAM 43. CPU42 performs various processes by executing the control program (firmware) loaded into RAM 43.

[0055] RAM43 is volatile memory. A portion of the storage area of ​​RAM43 is used, for example, to temporarily store information used to manage storage system 3. In addition, other portions of the storage area of ​​RAM43 can be used to temporarily store write data received from host 2 or read data read from NAND flash memory 5.

[0056] ROM44 is a non-volatile memory. For example, ROM44 stores firmware that controls the overall operation of the storage controller 4.

[0057] The ECC circuit 45 performs encoding and decoding processes. The ECC circuit 45 encodes data written to the NAND flash memory 5. Conversely, the ECC circuit 45 decodes data read from the NAND flash memory 5. During encoding, the ECC circuit 45 generates error correction codes and assigns these codes to the written data. During decoding, the ECC circuit 45 decodes the error correction codes assigned to the data read from the NAND flash memory 5, detecting the presence of error bits. If an error bit is detected, the ECC circuit 45 determines the error location and performs error correction.

[0058] NAND interface 46 is a circuit that controls the NAND flash memory 5 under the control of CPU 42. NAND interface 46 is electrically connected to the multiple NAND chips contained in the NAND flash memory 5.

[0059] Multiple NAND chips can operate independently. Therefore, the NAND chips function as units capable of parallel operation. The NAND interface 46 includes, for example, multiple NAND controllers (NANDCs) 461-1, 461-2, ..., 461-8. NANDCs 461-1, 461-2, ..., 461-8 are connected to channels ch1, ch2, ..., ch8, respectively. Each NANDC 461-1, 461-2, ..., 461-8 is connected to one or more NAND chips via its corresponding channel. Figure 1The example illustrates a scenario where four NAND chips are connected to each of channels ch1, ch2, ..., ch8. In this case, NANDC461-1 is connected to NAND chips #1, #9, #17, and #25 via channel ch1. NANDC461-2 is connected to NAND chips #2, #10, #18, and #26. Additionally, NANDC461-8 is connected to NAND chips #8, #16, #24, and #32. NAND chips #1, #2, ..., #8 are treated as memory bank BNK1. NAND chips #9, #10, ..., #16 are treated as memory bank BNK2. NAND chips #17, #18, ..., #24 are treated as memory bank BNK3. NAND chips #25, #26, ..., #32 are processed as memory bank BNK4. A memory bank is a unit that allows multiple NAND chips to operate in parallel through interleaving.

[0060] The power supply circuit 61 is a circuit that distributes the power supply voltage received from the host 2 to the various components of the storage system 3. For example, the power supply circuit 61 supplies power supply voltage to the storage controller 4 and the NAND flash memory 5. Additionally, the power supply circuit 61 includes a capacitor 62.

[0061] Capacitor 62 is a component capable of storing power. If the power supply voltage supplied from host 2 decreases without prior notification from host 2, power circuit 61 can use the power stored in capacitor 62 to temporarily supply power to memory controller 4 and NAND flash memory 5. For example, memory controller 4 can use the supplied power to write data that has not yet been written to NAND flash memory 5.

[0062] Next, an example of the configuration of the NAND chip in the NAND flash memory 5 will be described. Figure 2 This is a block diagram illustrating an example of the configuration of a NAND chip according to an embodiment. Figure 2 The image shows NAND chip #1, but other NAND chips have the same configuration as NAND chip #1.

[0063] NAND chip #1 is connected to NAND C461 of memory controller 4 via controller interface 50 of NAND flash memory 5. NAND chip #1 receives data to be written and commands from NAND C461. In addition, NAND chip #1 sends data read to NAND C461.

[0064] NAND chip #1 includes a control unit 51, a memory cell array 52, and a page buffer 53.

[0065] The control unit 51 controls the operation of the NAND chip #1 based on requests received from the memory controller 4. Specifically, upon receiving a write request, the control unit 51 controls the writing of the requested data to a specified address on the memory cell array 52. ​​Conversely, upon receiving a read request, the control unit 51 controls the reading of the requested data from the memory cell array 52 and sends the data to the memory controller 4 via the controller interface 50.

[0066] When writing data to the memory cell array 52, the page buffer 53 temporarily stores the data input from the memory controller 4. Similarly, when reading data from the memory cell array 52, the page buffer 53 temporarily stores the data read from the memory cell array 52. ​​During programming operations, the page buffer 53 sequentially stores the data received from the serial access controller 516 into the column address area specified by the column counter 515. Furthermore, during read operations, the page buffer 53 sequentially sends the data from the stored data at the column addresses specified by the column addresses back to the serial access controller 516.

[0067] The control unit 51 includes an oscillator 511, a sequencer 512, a command user interface 513, a voltage supply unit 514, a column counter 515, and a serial access controller 516.

[0068] Oscillator 511 is a circuit that generates a clock. The clock generated by oscillator 511 is supplied to the components including sequencer 512.

[0069] The sequencer 512 is a state machine driven by a clock supplied from the oscillator 511. The sequencer 512 performs control over access to the memory cell array 52, etc. For example, based on commands received from the command user interface 513, the sequencer 512 issues instructions for controlling various internal voltages, operation timing, etc. Furthermore, the sequencer 512 supplies the block address and page address contained in the address received from the command user interface 513 to the row decoder 521. Moreover, the sequencer 512 supplies the column address contained in the address received from the command user interface 513 to the column counter 515.

[0070] The command user interface 513 obtains commands and addresses from the commands, addresses, and data received from the memory controller 4 via I / O signal lines based on control signals. The command user interface 513 then translates the obtained commands and addresses into the sequencer 512.

[0071] The voltage supply unit 514 generates various internal voltages to be supplied to the word lines and various internal voltages to be supplied to the bit lines, and supplies them to the line decoder 521 and the sense amplifier 522.

[0072] During programming or reading operations, the column counter 515 starts with the column address supplied by the sequencer 512 and advances the column address sequentially according to the control signal supplied by the serial access controller 516.

[0073] During programming operations, the serial access controller 516 stores the data received serially from the controller interface 50 according to the width of each I / O signal line in the page buffer 53. Additionally, during read operations, the serial access controller 516 transmits the data received serially from the page buffer 53 according to the width of each I / O signal line to the controller interface 50.

[0074] The storage cell array 52 includes a row decoder 521 and a sense amplifier 522.

[0075] During programming and reading operations, the line decoder 521 decodes the block address and page address, selecting the word line corresponding to the page that is the access target contained in the block BLK of the access destination. Then, each line decoder 521 applies appropriate voltages to the selected word line and the non-selected word line.

[0076] During programming, the sense amplifier 522 transfers the corresponding data stored in the page buffer 53 to the memory cell transistor. Additionally, during read operations, the sense amplifier 522 senses the data read from the select word line to the bit line and stores the resulting data in the page buffer 53. The data stored in the page buffer 53 is then sent to the memory controller 4 via the serial access controller 516 and the controller interface 50.

[0077] Next, an example of the internal configuration of the memory cell array 52 will be described. Figure 3 This is a block diagram illustrating an example of the internal configuration of the storage cell array 52 according to an embodiment.

[0078] The storage cell array 52 contains multiple blocks BLK0 to BLKx-1. Each of blocks BLK0 to BLKx-1 functions as a unit for data erasure operations. Data erasure operations are also called erase operations, or simply erase operations. Each of blocks BLK0 to BLKx-1 is referred to as a physical block, flash block, or storage block.

[0079] Furthermore, each of blocks BLK0 to BLKx-1 contains multiple pages, namely pages P0 to Py-1. Pages P0 to Py-1 are each the unit of data write and data read operations. Each page P0 to Py-1, for example, contains multiple memory cells connected to the same word line.

[0080] Next, an example of block composition will be explained. Figure 4 This is a diagram showing an example of the configuration of each of the multiple blocks included in the memory cell array 52 of the NAND flash memory 5 of the storage system 3 according to the embodiment.

[0081] exist Figure 4 This section focuses on explaining the structure of block BLK0. Other blocks, for example, have the same structure as block BLK0. Block BLK0 contains 5 string units (SU0, SU1, SU2, SU3, and SU4). Furthermore, the number of string units SU contained in each BLK block is arbitrary. The 5 string units (SU0, SU1, SU2, SU3, and SU4) are arranged in a direction orthogonal (horizontal) to the direction in which the multiple word lines WL0 to WL7 are stacked. Each string unit SU contains multiple strings NS. One end of each string NS is connected to the corresponding bit line among the multiple bit lines (BL0 to BLn). Each string NS extends in the vertical direction. The control gates of the multiple memory cell transistors contained in each string NS are respectively connected to the multiple word lines (WL0, WL1, ..., WL7). The number of word lines can also be 9 or more.

[0082] Next, the circuit configuration of the blocks included in the memory cell array 52 will be described. Figure 5 This is a diagram illustrating an example of the circuit configuration of a block of the NAND flash memory 5 according to an embodiment.

[0083] exist Figure 5 The image shows the string units SU0 to SU4 contained in a certain BLK block.

[0084] A string unit SU is, for example, a collection of multiple strings NS that are selected together (summarized) in a programming or reading action. Each string unit SU contains multiple strings NS.

[0085] Each string NS is a collection of multiple memory cells MC connected in series. Multiple strings NS within a string cell SU are connected to any one of the bit lines BL0 to BLn (n is an integer greater than or equal to 1). A string NS contains multiple memory cells MC, and selection transistors ST1 and ST2. Figure 5 In the example, the string NS contains eight memory cells MC0 to MC7 and two selection transistors ST1 and ST2. Furthermore, the number of memory cells MC within the string NS is not limited to eight.

[0086] A memory cell (MC) is a memory element that stores data non-volatilely. The MC includes a control gate and a charge accumulation layer. The MC can be of type MONOS (Metal-Oxide-Nitride-Oxide-Silicon) or type FG (Floating Gate). The MONOS type uses an insulating layer in the charge accumulation layer. The FG type uses a conductive layer in the charge accumulation layer.

[0087] Selector transistors ST1 and ST2 are switching elements. Selector transistors ST1 and ST2 are used to select the series unit SU for various operations.

[0088] The gates of the selection transistors ST1 of each serial cell SU0 are connected to the selection gate line SGD0 corresponding to serial cell SU0. The gates of the selection transistors ST1 of each serial cell SU1 are connected to the selection gate line SGD1 corresponding to serial cell SU1. The gates of the selection transistors ST1 of each serial cell SU2 are connected to the selection gate line SGD2 corresponding to serial cell SU2. The gates of the selection transistors ST1 of each serial cell SU3 are connected to the selection gate line SGD3 corresponding to serial cell SU3. The gates of the selection transistors ST1 of each serial cell SU4 are connected to the selection gate line SGD4 corresponding to serial cell SU4. In contrast, the gates of the selection transistors ST2 of serial cells SU0 to SU4 are all connected to the selection gate line SGS. Alternatively, the gates of the selection transistors ST2 of serial cells SU0 to SU4 can be connected to different selection gate lines for each serial cell. The control gates of the memory cells MC0 to MC7 located in the same BLK are all connected to word lines WL0 to WL7.

[0089] The NAND flash memory 5 can perform programming and reading operations simultaneously on multiple memory cells MC connected to a word line within a single serial cell SU. During programming and reading operations, the set of memory cells MC selected together is called a memory cell group MG. The memory cell group MG is the unit of programming and reading operations and can be processed as a storage location. When each memory cell MC is configured to store 1 bit of data, the size of the data stored in each memory cell group MG is called a page. When each memory cell MC is configured to store 4 bits of data, the size of the data stored in each memory cell group MG is 4 pages. Hereinafter, the memory cell group MG will be referred to simply as a memory cell.

[0090] Next, the cross-sectional structure of the string NS will be explained. Figure 6 This is a cross-sectional view of a portion of the BLK block, specifically the string NS. For example... Figure 6 As shown, the memory pillar MP formed above the semiconductor substrate 70 is used as a string NS.

[0091] In the cross-sectional view shown below, the X-axis corresponds to the extension direction of the word line WL, the Y-axis corresponds to the extension direction of the bit line BL, and the Z-axis corresponds to the extension direction of the string NS relative to the semiconductor substrate 70. Additionally, components such as the insulating layer (interlayer insulating film) have been omitted for ease of observation.

[0092] The memory pillar MP formed above the semiconductor substrate 70 (in the direction of the Z-axis arrow) is used as a string NS.

[0093] A conductive layer 71 is disposed above the semiconductor substrate 70, separated by an insulating layer (not shown). Peripheral circuitry such as a sense amplifier 522 may be disposed on this insulating layer. The conductive layer 71 is formed, for example, in a plate shape extending along the XY plane, and is used as a source line SL.

[0094] A conductive layer 72 is disposed above the conductive layer 71, separated by an insulating layer (not shown). The conductive layer 72 is used as the select gate line SGS.

[0095] Above the conductive layer 72, an insulating layer (not shown) and a conductive layer 73 are alternately stacked multiple times (in... Figure 6 (8 times in the middle). Multiple conductive layers 73 are used as word lines WL0 to WL7 sequentially from the semiconductor substrate 70 side.

[0096] Above the top conductive layer 73, an insulating layer (not shown) and a conductive layer 74 are alternately stacked multiple times (in... Figure 6 (8 times in the middle). Multiple conductive layers 74 are used as word lines WL8 to WL15 sequentially from the semiconductor substrate 70 side. The spacing between the uppermost conductive layer 73 and the lowermost conductive layer 74 is, for example, larger than the spacing between adjacent conductive layers 73 or adjacent conductive layers 74.

[0097] Above the uppermost conductive layer 74, a conductive layer 75 is disposed, separated by an insulating layer (not shown). The conductive layer 75 is used as a select gate line (SGD). The conductive layers 72 to 75 are, for example, formed as plates extending along the XY plane.

[0098] Above the conductive layer 75, a conductive layer 77 is disposed, separated from an insulating layer (not shown). The conductive layers 77 extend along the Y-axis and are arranged linearly along the X-axis in multiples, each serving as a bit line BL.

[0099] The memory pillar MP extends along the Z-axis, penetrates the conductive layers 72-75, and contacts the conductive layer 71 at its bottom. The memory pillar MP includes: a lower pillar LMP, an upper pillar UMP formed above the lower pillar LMP, and a connector JT electrically connecting the lower pillar LMP and the upper pillar UMP. The lower pillar LMP and the upper pillar UMP, for example, have a tapered shape whose diameter increases from the semiconductor substrate 70 toward the bit line BL (along the Z-axis). The diameter of the connector JT along the XY plane is, for example, larger than the diameter of the lower pillar LMP and the upper pillar UMP at the contact portion that contacts the connector JT.

[0100] The memory column MP includes, for example, a core film 80, a semiconductor film 81, a laminated film 82, and a semiconductor section 83. The core film 80, the semiconductor film 81, and the laminated film 82 are each formed as continuous films, for example, in the lower column LMP, the connector section JT, and the upper column UMP.

[0101] Specifically, the core film 80 is disposed approximately at the center of the memory column MP and extends along the Z-axis. The core film 80, for example, has an upper end located above the conductive layer 75 and a lower end located below the conductive layer 72. The core film 80, for example, comprises an insulator such as silicon oxide (SiO2).

[0102] The semiconductor film 81 includes a cylindrical portion that covers the bottom and side surfaces of the core film 80 and is formed along the Z-axis. The semiconductor film 81 has an upper end located above the conductive layer 75 and a lower end in contact with the conductive layer 71. The semiconductor film 81 may contain, for example, polycrystalline silicon.

[0103] The laminated film 82 includes a cylindrical portion covering the sides of the semiconductor film 81 and formed along the Z-axis. For details regarding the construction of the laminated film 82, please refer to the section along the Z-axis. Figure 7 The sectional view of line VI-VI is Figure 7 Let me explain.

[0104] like Figure 7 As shown, the laminated film 82 includes a tunnel insulating film 82a, a charge storage film 82b, and a bulk insulating film 82c. The tunnel insulating film 82a covers the sides of the semiconductor film 81, and the charge storage film 82b covers the sides of the tunnel insulating film 82a. The bulk insulating film 82c covers the sides of the charge storage film 82b and is covered by a conductive layer 73.

[0105] Return again Figure 6 The configuration of the memory pillar MP will be described below. The semiconductor section 83 covers the upper surface of the core film 80 and is in contact with the portion of the semiconductor film 81 located above the core film 80. The semiconductor section 83 is, for example, cylindrical and located at the upper end of the upper pillar UMP.

[0106] A conductive layer 76 is provided between the upper surface of the semiconductor section 83 and the lower surface of the conductive layer 77. The conductive layer 76 is used as a contact CP that electrically connects the memory pillar MP and the bit line BL.

[0107] In the structure of the memory pillar MP described above, the portion where the lower pillar LMP intersects with the conductive layer 72 functions as the selection transistor ST2. The portions where the lower pillar LMP intersects with multiple conductive layers 73 function as memory cell transistors MT0 to MT7, respectively. The portions where the upper pillar UMP intersects with multiple conductive layers 74 function as memory cell transistors MC8 to MC15, respectively. The portion where the upper pillar UMP intersects with the conductive layer 75 functions as the selection transistor ST1. The semiconductor film 81 functions as the channel for the memory cell transistor MT and the selection transistors ST1 and ST2, respectively.

[0108] With the above-described structure, the memory pillars MP can function as a series NS. Furthermore, by arranging multiple memory pillars MP above the semiconductor substrate 70, a memory cell array 52 is formed. Figure 6 The diagram shows a 2Tier structure with two memory pillars MP, but it can also be a 3Tier structure or higher with three or more memory pillars arranged above the semiconductor substrate 70.

[0109] Next, the threshold voltage distribution in the memory cell MC will be explained. Figure 8 This is a schematic diagram illustrating the threshold distribution of the storage cell MC in the implementation method.

[0110] NAND flash memory 5 can hold more than 4 bits of data in each memory cell (MC). Figure 8The diagram illustrates the threshold voltage distribution when 4 bits of data are held in each storage cell MC during the data write process in the storage system 3 of the embodiment. The threshold voltage of each storage cell MC has a value corresponding to the held data. When 4 bits of data are stored in each storage cell MC, each storage cell MC can have one of 16 (=24) threshold voltages. These 16 threshold voltages represent states where the data is held as "1111", "0111", "0011", "1011", "1001", "0001", "0101", "1101", "1100", "1110", "1010", "1000", "0000", "0100", "0110", and "0010". The memory cell transistors MC that hold the data in the states of "1111", "0111", "0011", "1011", "1001", "0001", "0101", "1101", "1100", "1110", "1010", "1000", "0000", "0100", "0110", and "0010" are respectively referred to as being in the Er, A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O states. The memory cell MCs in the Er, A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O states have progressively higher threshold voltages in that order.

[0111] Even multiple memory cells (MCs) holding the same 4 bits of data may have different threshold voltages due to variations in their characteristics. However, the threshold voltages of multiple memory cells (MCs) holding the same 4 bits of data are included in the same state. Furthermore, in... Figure 8 In the figures that follow, the distribution of the threshold voltage is shown as a continuous curve, but in reality, the number of memory cell transistors (MC) is discrete.

[0112] To determine the data held by the memory cell MC of the object being read, the state of the memory cell MC is determined. To determine the state, read voltages VA, VB, VC, VD, VE, VF, VG, VH, VI, VJ, VK, VL, VM, VN, and VO are used. Hereinafter, the voltage of a certain magnitude applied to the memory cell MC of the object being read, including read voltages VA, VB, VC, VD, VE, VF, VG, VH, VI, VJ, VK, VL, VM, VN, and VO, used to determine the state of the memory cell MC, is sometimes referred to as read voltage VCGR.

[0113] The read voltage VA is higher than the highest threshold voltage of the memory cell MC in the Er state and lower than the lowest threshold voltage of the memory cell MC in the A state immediately after writing.

[0114] The read voltage VB is higher than the highest threshold voltage of the memory cell MC in state A immediately after writing and lower than the lowest threshold voltage of the memory cell MC in state B immediately after writing.

[0115] The read voltage VC is higher than the highest threshold voltage of the memory cell MC in state B immediately after writing and lower than the lowest threshold voltage of the memory cell MC in state C immediately after writing.

[0116] The read voltage VD is higher than the highest threshold voltage of the memory cell MC in state C immediately after writing and lower than the lowest threshold voltage of the memory cell MC in state D immediately after writing.

[0117] The read voltage VE is higher than the highest threshold voltage of the memory cell MC in the D state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the E state immediately after writing.

[0118] The read voltage VF is higher than the highest threshold voltage of the memory cell MC in the E state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the F state immediately after writing.

[0119] The read voltage VG is higher than the highest threshold voltage of the memory cell MC in the F state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the G state immediately after writing.

[0120] The read voltage VH is higher than the highest threshold voltage of the memory cell MC in the G state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the H state immediately after writing.

[0121] The read voltage VI is higher than the highest threshold voltage of the memory cell MC in the H state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the I state immediately after writing.

[0122] The read voltage VJ is higher than the highest threshold voltage of the memory cell MC in the I state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the J state immediately after writing.

[0123] The read voltage VK is higher than the highest threshold voltage of the memory cell MC in state J immediately after writing and lower than the lowest threshold voltage of the memory cell MC in state K immediately after writing.

[0124] The read voltage VL is higher than the highest threshold voltage of the memory cell MC in the K state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the L state immediately after writing.

[0125] The read voltage VM is higher than the highest threshold voltage of the memory cell MC in the L state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the M state immediately after writing.

[0126] The read voltage VN is higher than the highest threshold voltage of the memory cell MC in the M state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the N state immediately after writing.

[0127] The read voltage VO is higher than the highest threshold voltage of the memory cell MC in the N state immediately after writing and lower than the lowest threshold voltage of the memory cell MC in the O state immediately after writing.

[0128] The reading voltages VA, VB, VC, VD, VE, VF, VG, VH, VI, VJ, VK, VL, VM, VN, and VO are, for example, the default voltages. Readings using the reading voltage VX (where X is A, B, C, D, E, F, G, H, I, J, K, L, M, N, or O) are called X reads (XR).

[0129] Next, the fuzzy and fine-programming operations, which are the first write methods in the two-step write process, will be explained. (Refer to...) Figure 7 This section describes the first stage of programming actions in fuzzy and fine programming, namely fuzzy programming.

[0130] Figure 7 This is a graph showing the change in the distribution of the threshold voltage of the memory cell MC caused by the programming operation of the first stage performed in the memory system 3 of the embodiment.

[0131] The NAND flash memory 5 performs the first stage of programming based on commands received from the memory controller 4 and four pages of data. Four pages of data are written to the top page, upper page, middle page, and lower page of the memory cell at the write destination. These data are referred to, for example, as top page data, upper page data, middle page data, and lower page data. The sequencer 512 performs the first stage of programming based on the top page data, upper page data, middle page data, and lower page data. As part of the first stage of programming, the NAND flash memory 5 performs a coarse-write fuzzy programming operation, causing the threshold voltage of the memory cell MC to rise in an incomplete manner based on the data to be written.

[0132] Before performing the fuzzy programming operation, the memory cell MC is in the Er state. During the fuzzy programming operation, the sequencer 512 uses verification voltages VMA, VMB, VMC, VMD, VME, VMF, VMG, VMH, VMI, VMJ, VMK, VML, VMM, VMN, and VMO for verification. Verification voltages VMA, VMB, VMC, VMD, VME, VMF, VMG, VMH, VMI, VMJ, VMK, VML, VMM, VMN, and VMO are used to verify memory cells MC written to states A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O, respectively. That is, for example, verification of a memory cell MC written to state A during the fuzzy programming operation uses verification voltage VMA. Furthermore, for a memory cell transistor MC written to state A, if it has a threshold voltage above verification voltage VMA during the fuzzy programming operation, the verification of the fuzzy programming operation passes. The same applies to the other states. The verification voltages VMA, VMB, VMC, VMD, VME, VMF, VMG, VMH, VMI, VMJ, VMK, VML, VMM, VMN, and VMO have the following values.

[0133] VMA <VA

[0134] VMA <VMB<VB

[0135] VMB <VMC<VC

[0136] VMC <VMD<VD

[0137] VMD <VME<VE

[0138] VME <VMF<VF

[0139] VMF <VMG<VG

[0140] VMG <VMH<VH

[0141] VMH <VMI<VI

[0142] VMI <VMJ<VJ

[0143] VMJ <VMK<VK

[0144] VMK <VML<VL

[0145] VML <VMM<VM

[0146] VMM <VMN<VN

[0147] VMN <VMO<VO

[0148] Through fuzzy programming, memory cells MC transition to one of the following states: MEr, MA, MB, MC, MD, ME, MF, MG, MH, MI, MJ, MK, ML, MM, MN, and MO. Memory cells MC written to states A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O immediately after the fuzzy programming is completed are in states MA, MB, MC, MD, ME, MF, MG, MH, MI, MJ, MK, ML, MM, MN, and MO, respectively. Memory cells MC maintained at the Er level remain in the MEr state during the fuzzy programming process.

[0149] Next, refer to Figure 8 The second stage of programming actions in fuzzy and fine programming actions, namely fine programming actions, is explained.

[0150] Figure 8 This is a graph showing the change in the threshold voltage distribution of the memory cell MC caused by the programming operation in the second stage of the first write mode in the memory system 3 of the embodiment.

[0151] The NAND flash memory 5 receives data from the memory controller 4 that is to be written to the memory cell MC, which is the destination of the write operation. This data to be written is the same as the data used in the fuzzy programming operation, namely top page data, upper page data, middle page data, and lower page data. Furthermore, the NAND flash memory 5 performs a second-stage programming operation based on the received top page data, upper page data, middle page data, and lower page data. As the second-stage programming operation, the NAND flash memory 5 performs a precise write operation, namely fine programming, to complete the rise of the threshold voltage of the memory cell MC and complete the write operation.

[0152] In the fine-tuning operation, the sequencer 512 uses verification voltages VVA, VVB, VVC, VVD, VVE, VVF, VVG, VVH, VVI, VVJ, VVK, VVL, VVM, VVN, and VVO. These verification voltages are used to verify memory cells MC written to states A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O, respectively. For example, verification in the fine-tuning operation of a memory cell MC written to state A is performed using verification voltage VVA. Furthermore, if a memory cell MC written to state A has a threshold voltage above verification voltage VVA during the second-stage programming operation, it passes the fine-tuning operation verification. The same applies to other states. The verification voltages VVA, VVB, VVC, VVD, VVE, VVF, VVG, VVH, VVI, VVJ, VVK, VVL, VVM, VVN, and VVO have the following values.

[0153] VA <VVA<VVB

[0154] VB <VVB<VVC

[0155] VC <VVC<VVD

[0156] VD <VVD<VVE

[0157] VE <VVE<VVF

[0158] VF <VVF<VVG

[0159] VG <VVG<VVH

[0160] VH <VVH<VVI

[0161] VI <VVI<VVJ

[0162] VJ <VVJ<VVK

[0163] VK <VVK<VVL

[0164] VL <VVL<VVM

[0165] VM <VVM<VVN

[0166] VN <VVN<VVO

[0167] VO <VVO

[0168] One of the purposes of the two-step write operation is to suppress the occurrence of the threshold voltage of the memory cell transistor MC of the cell unit CU that has been written to, which is due to the writing to the adjacent cell unit CU instead of the intended state.

[0169] In contrast, this section explains the impact on nearby memory cells when performing a one-step write operation. In the case of a one-step write operation, the threshold voltage of the memory cell MC is reduced without passing through... Figure 10 The way of the upper side state from Figure 9 The state of the upper side towards Figure 10 The state change on the lower side. Figure 11 This is a diagram illustrating the state transition of a memory cell caused by a single write operation. A memory cell is also referred to as a unit of storage (CU), which contains multiple memory cells.

[0170] In a single write operation, a single write operation transitions the memory cell MC to the target state. The most significant transition is the large threshold voltage shift from the Er level to the 0 level. For example... Figure 11 Therefore, when performing a one-step write operation on cell CU(i+1) after writing to cell CUi (i is 0 or a natural number), the threshold voltage of the memory cell MC in cell CUi may unintentionally rise due to the increase in the threshold voltage of the memory cell MC in cell CU(i+1). Since this rise is significant, it may greatly affect the state of cell CUi. That is, in the case of performing a one-step write, the disturbance to nearby memory cells is large. As a result, the memory cell MC of cell CUi may transition to a state different from the intended state.

[0171] Next, the impact on adjacent memory cells in the case of performing a two-step write operation will be explained. Figure 12 This is a diagram illustrating the state transition of a storage cell caused by a two-step write operation performed in the storage system 3 of the embodiment.

[0172] In a two-step write operation, such as Figure 12 As shown, after the first stage of programming the unit CUi, the first stage of programming is performed on the unit CU(i+1). At this time, the threshold voltage of the memory cell MC in the unit CUi may rise due to the first stage of programming of the unit CU(i+1). However, subsequently, through the second stage of programming of the unit CU(i+1), the threshold voltage of the memory cell MC in the unit CU(i+1) is controlled to the target state. Thus, the disturbance caused by the first stage of programming of the unit CU(i+1) is absorbed by the subsequent second stage of programming, i.e., the fine programming.

[0173] The second-stage programming operation on cell unit CU(i+1) may interfere with cell unit CUi, which has completed the second-stage programming operation. However, the rise in threshold voltage caused by the second-stage programming operation is smaller than that caused by the first-stage programming operation, and therefore will not have a significant impact on the cell unit CUi, which has completed the write operation. Thus, it is possible to prevent the memory cell MC of cell unit CUi from unintentionally transitioning from the state after the write operation to other states.

[0174] Next, refer to Figure 13 The MLC and fine-tuning operations, which are the second write methods in the two-step write operation, are explained.

[0175] Figure 13 This is a graph showing the change in the threshold voltage distribution of the memory cell MC in the second write mode of the memory system 3 of the embodiment.

[0176] exist Figure 13 The figure shows the threshold voltage distribution after performing the first stage programming operation on the memory cell MC and the threshold voltage distribution after performing the second stage programming operation on the memory cell MC.

[0177] When performing MLC and fine programming operations as the second write method, the NAND flash memory 5 performs an MLC programming operation that writes 2 bits of data to each memory cell MC as the first stage of programming. Then, the NAND flash memory 5 performs a fine programming operation that writes 4 bits of data to each memory cell MC as the second stage of programming.

[0178] Figure 13 T1 shows the threshold voltage distribution corresponding to the erase state as the initial state before the programming action is performed. Figure 13 T2 shows the threshold voltage distribution after performing the MLC programming action as the first stage of programming. Figure 11 T3 shows the threshold voltage distribution after the fine programming action, which is the programming action of the second stage, is performed.

[0179] like Figure 11 As shown in T1, all memory cells of the memory cell array 52 in the initial state have threshold voltages contained in the threshold voltage distribution Er corresponding to the unwritten state (erase state).

[0180] The control unit 51 of the NAND flash memory 5 is as follows: Figure 12 As shown in T2, in the first stage of programming, based on the bit values ​​(bit values) that should be written to the next page and the middle page, each memory cell MC either keeps the threshold voltage distribution Er unchanged or changes to other threshold voltage distributions that are higher than the threshold voltage distribution Er.

[0181] Specifically, when the bit value written to the next page and the middle page is "11", the control unit 51 maintains the threshold voltage distribution S0 corresponding to the erase state. Furthermore, when the bit value written to at least one of the next page and the middle page is "0", the control unit 51 shifts the threshold voltage of the memory cell MC at the write destination to a higher value. That is, when the bit value written to the next page and the middle page is "01", the control unit 51 changes the memory cell MC at the write destination to threshold voltage distribution S2. Furthermore, when the bit value written to the next page and the middle page is "00", the control unit 51 changes the memory cell MC at the write destination to threshold voltage distribution S8. Furthermore, when the bit value written to the next page and the middle page is "10", the control unit 51 changes the memory cell MC at the write destination to threshold voltage distribution S12.

[0182] Here, the threshold voltage distributions S8 and S12 can also be coarsely programmed to widen the threshold region by slightly lowering the threshold voltage. This is because even if the interval between adjacent threshold regions widens during the MLC programming action performed as the first stage of programming, the threshold voltage distribution can ultimately be changed through the fine programming action performed as the second stage of programming.

[0183] Therefore, the memory cell is programmed with a 4-level voltage using the data from the next and middle pages. Here, the data writing in the MLC programming operation (the first stage of programming) is a programming operation that only writes the data from the next and middle pages. Therefore, the data required to perform this MLC programming operation is only the data from the next and middle pages. Furthermore, the threshold voltage distribution after performing this MLC programming operation is changed again by the subsequent second stage programming operation, i.e., the fine programming operation. Therefore, at the time of performing the MLC programming operation, there is no need to finely shape the threshold voltage distribution, enabling high-speed programming. Furthermore, the next and middle page data can be read from the memory cell after performing this MLC programming operation.

[0184] In addition, such as Figure 13 As shown in T3, in the fine programming operation, which is the second stage of programming, two pages of data (the previous page data and the top page data) are required to write data. Furthermore, the NAND flash memory 5 performs the programming operation by ultimately separating the data into 16 threshold voltage distributions after the fine programming operation. In this case, all page data can be read.

[0185] During fine-grained programming, the greater the change in the threshold voltage of the memory cell (MC) from the threshold voltage distribution after the first stage of programming, the greater the interference between adjacent cells. Therefore, when the threshold voltage distribution changes from the MLC programming operation to the fine-grained programming operation, it is preferable to minimize its maximum change. Figure 13 In the example, the maximum change in the threshold voltage distribution is the change of the five quantities of the threshold voltage distribution, namely the change of threshold voltage distribution S0 to S5 and the change of threshold voltage distribution S2 to S7.

[0186] Furthermore, typically, writing (programming) to a memory cell is performed by applying one or more programming voltage pulses to the corresponding word line. After each programming voltage pulse is applied, a read operation is performed to confirm whether the memory cell has moved beyond a threshold level. By repeatedly applying and reading these programming voltage pulses, the threshold voltage of the memory cell can be moved within a threshold region having a predetermined threshold distribution.

[0187] More specifically, in the case of writing multiple pages as in fine-grained programming, the threshold voltage of the corresponding memory cell is determined based on the data of all pages of the write target (in this case, the next, middle, previous, and top pages). The write operation is performed by gradually increasing the voltage value of multiple programming pulses to reach the determined threshold voltage. Memory cells (MCs) that have reached the target threshold voltage are excluded from the write target. Thus, the write operation is not performed page-by-page, but rather by aggregating all pages of the write target.

[0188] Next, refer to Figure 14 The TLC and fine programming operations, which are the third write methods in the two-step write operation, are explained.

[0189] Figure 14 This is a graph showing the change in the threshold voltage distribution of the memory cell MC under the third write mode in the memory system 3 of the embodiment.

[0190] exist Figure 14 The figure shows the threshold voltage distribution after performing the first stage programming operation on the memory cell MC and the threshold voltage distribution after performing the second stage programming operation on the memory cell MC.

[0191] When performing TLC and fine programming operations as the third write mode, the NAND flash memory 5 performs a TLC programming operation by writing 3 bits of data to each memory cell MC as the first stage of programming. Furthermore, the NAND flash memory 5 performs a fine programming operation by writing 4 bits of data to each memory cell MC as the second stage of programming.

[0192] Figure 14 T1 shows the threshold voltage distribution corresponding to the erase state as the initial state before the programming action is performed. Figure 14 T2 shows the threshold voltage distribution after the TLC programming action, which is the first stage of programming, is performed. Figure 14 T3 shows the threshold voltage distribution after the fine programming action, which is the programming action of the second stage, is performed.

[0193] like Figure 14 As shown in T1, all memory cells of the memory cell array 52 in the initial state have threshold voltages contained in the threshold voltage distribution S0 corresponding to the unwritten state (erase state).

[0194] The control unit 51 of the NAND flash memory 5 is as follows: Figure 14As shown in T2, in TLC programming, which is the first stage of programming, the threshold voltage distribution S0 of each memory cell MC is kept unchanged or changed to other threshold voltage distributions higher than the threshold voltage distribution S0, depending on the bit values ​​to be written to the next page, middle page, and top page.

[0195] Specifically, when the bit values ​​written to the bottom page, middle page, and top page are all "1", the control unit 51 does not inject charge. When any of the bit values ​​written to the bottom page, middle page, and top page is "0", the control unit 51 performs a programming operation by causing the threshold voltage of the memory cell MC at the write destination to change to a state higher than the threshold voltage distribution corresponding to the erase state.

[0196] That is, when the bit value written to the next page, middle page, and top page is "111", the control unit 51 maintains the threshold voltage distribution S0 corresponding to the erase state. Furthermore, when the bit value written to the next page, middle page, and top page is "011", the control unit 51 causes the memory cell MC at the write destination to change to the threshold voltage distribution S1. Furthermore, when the bit value written to the next page, middle page, and top page is "101", the control unit 51 causes the memory cell MC at the write destination to change to the threshold voltage distribution S4. Furthermore, when the bit value written to the next page, middle page, and top page is "001", the control unit 51 causes the memory cell MC at the write destination to change to the threshold voltage distribution S5. Furthermore, when the bit value written to the next page, middle page, and top page is "100", the control unit 51 causes the memory cell MC at the write destination to change to the threshold voltage distribution S8. Furthermore, when the bit value written to the next page, middle page, and top page is "110", the control unit 51 causes the memory cell MC at the write destination to switch to the threshold voltage distribution S9. When the bit value written to the next page, middle page, and top page is "000", the control unit 51 causes the memory cell MC at the write destination to switch to the threshold voltage distribution S12. And when the bit value written to the next page, middle page, and top page is "010", the control unit 51 causes the memory cell MC at the write destination to switch to the threshold voltage distribution S14.

[0197] Preferably, distributions S1, S4, S5, S8, S9, S12, and S14 are coarsely programmed to broaden the threshold voltage distribution in a manner that slightly lowers the threshold voltage. This reduces programming time. This is because even if the interval between adjacent threshold regions widens during the TLC programming action (the first stage), the threshold voltage distribution can ultimately be changed through the fine programming action (the second stage).

[0198] Furthermore, preferably, the intervals between adjacent distributions S8 and S9, and between adjacent threshold distributions S12 and S14, are narrower than the intervals between other adjacent distributions. Regarding the write bit values ​​of adjacent threshold distributions that narrow these intervals, the data in the middle page differs. That is, the data programmed by the TLC as part of the first-stage programming action appears as binary, thus enabling readings of the next page, middle page, and top page. However, by narrowing the intervals of the different threshold voltage distributions for the middle page data, the intervals of the different threshold distributions for the next and top pages data are ensured to be wide, increasing the margin during readings of the next and top pages.

[0199] Next, as Figure 14 As shown in T3, in the fine programming operation, which is the second stage of programming, writing data requires two pages: the middle page and the top page. Furthermore, the control unit 51 of the NAND flash memory 5 programs the threshold distribution after the fine programming operation (the second stage of programming) to a level where the final state after the fine programming operation, where adjacent distributions are separated, is a 16-value level. After performing the fine programming operation, the data of all pages can be read.

[0200] In the fine programming operation, which is the second stage of programming, the greater the change in the threshold voltage of the memory cell from the end of the TLC programming operation, the greater the interference between adjacent cells. Therefore, it is preferable that the change in the threshold distribution with the largest change in the memory cell threshold distribution is minimized. According to this embodiment, the largest change in the threshold distribution is one of the three threshold distribution values: S0 changing to S3, S4 changing to S7, and S8 changing to S11.

[0201] Furthermore, typically, programming is performed by applying one or more programming voltage pulses. With each programming pulse, the voltage value increases in stages. After each programming voltage pulse, a readout, called a check, is performed to confirm whether the memory cell has moved beyond a threshold boundary level. By repeatedly applying and reading out these programming voltage pulses, the threshold of the memory cell can be moved within a predetermined threshold distribution range.

[0202] Next, the writing order of the multiple storage units contained in the destination block is explained.

[0203] First, refer to Figure 15 The writing order in the first comparison example will be explained. Figure 15 This is a diagram illustrating an example of the write sequence of the two-step write operation in the first comparative example.

[0204] In the first comparative example, the memory controller instructs the NAND flash memory to perform a fuzzy-fine program operation as the first write mode. Furthermore, the memory controller specifies the memory cells for the write destination in a string-first manner within the write destination block. In the string-first write order, the memory controller performs the first-stage programming operation on memory cells connected to the same word line after performing the first-stage programming operation on multiple memory cells connected to subsequent word lines.

[0205] exist Figure 15 - Figure 21 In the diagram, the number recorded at the storage location corresponding to each storage unit indicates the order of programming actions written into the destination block.

[0206] For simplification, the storage units connected to word line WL A and belonging to string unit SUB will be represented as storage locations (A, B).

[0207] Specifically, first, the storage controller performs fuzzy programming on storage location (0,0) as the first stage of programming. The storage controller then performs fuzzy programming on storage location (0,1), storage location (0,2), storage location (0,3), and storage location (0,4). Thus, the storage controller completes the fuzzy programming of multiple storage cells connected to word line WL0.

[0208] Then, the storage controller performs a fuzzy programming action on the storage location (1, 0) as the first stage of programming. That is, corresponding to the completion of the fuzzy programming action on the storage cell connected to WL0, the controller begins the fuzzy programming action on the storage cell connected to WL1.

[0209] Then, corresponding to the completion of the fuzzy programming action for storage location (1, 0), the storage controller performs a fine programming action for storage location (0, 0) as the second stage of programming. That is, corresponding to the completion of the fuzzy programming action for storage cells belonging to the same string and connected to subsequent word lines, the storage controller performs a fine programming action.

[0210] During the period from performing fuzzy programming on memory location (0,0) to performing fine programming, fuzzy programming is performed on six memory locations, including memory location (0,0). During this time, the memory controller needs to hold the data to be written to each memory location until fine programming is performed. That is, if four pages of data are written to each of the six memory locations using QLC writing, a buffer capable of holding 6 × 4 pages of data is required on the memory controller. Furthermore, in the event of a power outage without prior notification from the host, the memory controller needs to use emergency power to write the temporarily held data to the NAND flash memory. Therefore, the larger the size of the data that has undergone fuzzy programming but not yet fine programming, the larger the required emergency power capacity.

[0211] Next, refer to Figure 16 The writing order in the second comparison example will be explained. Figure 16 This is a diagram illustrating an example of the write sequence of the two-step write operation in the second comparative example.

[0212] In the second comparative example, the memory controller performs MLC and fine programming operations as a second write method on the NAND flash memory. Furthermore, the memory controller specifies the memory cells in the write destination block in string priority. That is, the memory controller performs programming operations on each memory cell within the write destination block in the same order as in the first comparative example. However, since MLC and fine programming operations are performed, the memory controller writes 2 bits of data to each memory cell using the MLC programming operation, which is the first stage of programming.

[0213] Specifically, first, the storage controller performs an MLC programming operation as the first stage of programming for storage location (0,0). The storage controller then performs an MLC programming operation as the first stage of programming for storage location (0,1). Next, the storage controller performs an MLC programming operation as the first stage of programming for storage location (0,2). Finally, the storage controller performs an MLC programming operation as the first stage of programming for storage location (0,3). Finally, the storage controller performs an MLC programming operation as the first stage of programming for storage location (0,4). Thus, the storage controller completes the fuzzy programming operation for multiple storage cells connected to word line WL0.

[0214] Then, the controller performs an MLC programming action on the storage location (1, 0) as the first stage of programming. That is, corresponding to the completion of the MLC programming action on the storage cell connected to WL0, the controller begins the MLC programming action on the storage cell connected to WL1.

[0215] Then, corresponding to the completion of the MLC programming action for storage location (1,0), the storage controller performs a fine-grained programming action for storage location (0,0) as the second stage of programming. That is, corresponding to the completion of the MLC programming action for storage cells belonging to the same string and connected to subsequent word lines, the storage controller performs a fine-grained programming action.

[0216] During the period from performing MLC programming on storage location (0,0) to performing fine programming, MLC programming is performed on six storage locations within storage location (0,0). During this time, the storage controller needs to retain data that has not been written using MLC programming, which should be written to each storage location, until the fine programming operation is performed on each storage cell. That is, if four pages of data are written to each of the six storage locations using QLC programming, the storage controller needs to retain a buffer containing 6 × (4-2) pages of data because two pages of data have already been written via MLC programming. Therefore, by performing both MLC and fine programming operations instead of both fuzzy and fine programming operations, the second comparative example reduces the amount of data retained compared to the first comparative example.

[0217] However, MLC and fine-grained programming also have the drawback of degraded data reliability compared to fuzzy and fine-grained programming. This is because: Figure 13 As explained in the text, the maximum change in the threshold voltage distribution during the fine-programming action of MLC and fine-programming action is greater than the change in the threshold voltage distribution during the fine-programming action of fuzzy and fine-programming action.

[0218] Next, refer to Figure 17 The writing order in the third comparison example is explained. Figure 17 This is a diagram illustrating an example of the write sequence for the two-step write in the third comparison example.

[0219] In the third comparative example, the memory controller instructs the NAND flash memory to perform fuzzy and fine programming operations as the first write mode. Furthermore, the memory controller specifies the memory cells as write destinations in the write destination block in a word-line-first manner. In the word-line-first write sequence, the memory controller performs fuzzy and fine programming operations on the string of memory cells connected to N word lines until it performs fine programming operations on the string of memory cells belonging to that string. Then, the memory controller changes the write destination to the next string of memory cells. Here, N is the number of word lines bundled in the word-line-first approach. N is an integer greater than or equal to 1 and less than the number of word lines contained in the write destination block. Here, word lines that are multiples of N+1 are called boundary word lines.

[0220] exist Figure 17 The example shows the case where N is 3. That is, the 4th, 8th, ... word lines are boundary word lines.

[0221] Specifically, first, the storage controller performs a fuzzy programming operation on storage location (0,0) as the first stage of programming. Then, corresponding to the completion of the fuzzy programming operation on storage location (1,0), the storage controller performs a fine programming operation on storage location (0,0) as the second stage of programming. In other words, corresponding to the completion of the fuzzy programming operation on storage cells belonging to the same string and connected to subsequent word lines, the storage controller performs a fine programming operation.

[0222] During the period from performing fuzzy programming on storage location (0,0) to performing fine programming, the storage locations where fuzzy programming is performed are only storage locations (0,0) and (1,0). Therefore, the storage controller needs to hold the data that should be written to both storage locations. That is, when writing 4 pages of data to each of the two storage locations using QLC, a buffer is needed on the storage controller to hold 2 × 4 pages of data.

[0223] Then, the storage controller performs fuzzy programming on storage location (2, 0) as the first stage of programming. The storage controller then performs fine programming on storage location (1, 0) as the second stage of programming.

[0224] The storage controller performs a fuzzy programming action on storage location (3, 0) as the first stage of programming. Then, the storage controller performs a fine programming action on storage location (2, 0) as the second stage of programming.

[0225] Here, corresponding to the completion of the fuzzy programming action on the storage location (3, 0) connected to the word line WL3 which serves as the boundary word line, and the fine programming action on the storage location (2, 0) which becomes executable through the completion of this fuzzy programming action, the storage controller changes the serial unit to the serial unit SU1 for writing to the destination. The storage controller performs the fuzzy programming action on the storage location (0, 1) as the first stage of programming.

[0226] In this way, when the memory controller executes programming actions up to the memory cell that is connected to the boundary word line in the memory cell belonging to each string cell, it performs data writing to the memory cell that is connected to the word line following the boundary word line.

[0227] Then, the programming process continues. Upon completion of the fine-grained programming of storage location (2, 4), the storage controller performs fuzzy programming on storage location (4, 0). Then, the storage controller performs fine-grained programming on storage location (3, 0), which is connected to the boundary word line.

[0228] In the timing of fine-grained programming of storage location (3,0), the storage locations that have only performed fuzzy programming and not fine-grained programming are storage locations (3,0), (4,0), (3,1), (3,2), (3,3), and (3,4). That is, when the storage controller writes 4 pages of data to each storage cell using QLC, a buffer is needed on the storage controller to hold 6 × 4 pages of data.

[0229] Therefore, in the word-line-first write order of the third comparison example, there are locations such as storage location (0, 0) where the amount of data to be retained can be reduced compared to the first comparison example. However, when considering storage cells such as storage location (3, 0) that are connected to the boundary word line, the amount of data to be retained in the third comparison example is the same as that in the first comparison example.

[0230] Next, refer to Figure 18 The programming actions in the fourth comparative example are explained. Figure 18 This is a diagram illustrating examples of one-step and two-step write sequences in the fourth comparative example.

[0231] In the fourth comparative example, the memory controller instructs a one-step write operation for the NAND flash memory regarding memory cells connected to boundary word lines. Additionally, the memory controller performs a two-step write operation for the NAND flash memory regarding memory cells connected to word lines other than boundary word lines. The memory controller specifies the memory cells of the write destination in a word-line-first manner within the write destination block.

[0232] exist Figure 18 The example shows the case where N is 4. That is, the 5th, 10th, ... word lines are boundary word lines.

[0233] exist Figure 18 In this process, fuzzy and fine programming are performed as two-step write operations, while full-sequence programming is performed as a single write operation. In full-sequence programming, the controller performs any of the following operations on the memory cell connected to the boundary word line: TLC programming, MLC programming, or SLC programming. Therefore, 3 bits, 2 bits, or 1 bit of data are stored in the memory cell connected to the boundary word line. Here, we assume the case where the memory controller performs TLC programming as a full-sequence programming operation.

[0234] Specifically, first, the storage controller performs a fuzzy programming action as the first stage of programming for storage location (0,0). Then, corresponding to the completion of the fuzzy programming action for storage location (1,0), the storage controller performs a fine programming action as the second stage of programming for storage location (0,0). That is, corresponding to the completion of the fuzzy programming action for storage cells belonging to the same string and connected to subsequent word lines, the storage controller performs a fine programming action.

[0235] Then, the storage controller performs fuzzy programming on storage location (2, 0) as the first stage of programming. The storage controller then performs fine programming on storage location (1, 0) as the second stage of programming.

[0236] The storage controller performs a fuzzy programming action as the first stage of programming on the storage location (3, 0). Then, the storage controller performs a fine programming action as the second stage of programming on the storage location (2, 0) that is connected to WL2 and belongs to the serial unit SU0.

[0237] Then, the memory controller performs a full-sequence programming operation as a one-step write operation on the memory location (4,0) connected to the word line WL4, which serves as the boundary word line. That is, the memory controller writes 3 bits of data to the memory location (4,0) through this programming operation.

[0238] Then, corresponding to the completion of the full sequence programming action for storage location (4,0), the storage controller performs fine programming action for storage location (3,0) as the second stage programming action.

[0239] Corresponding to the completion of the fine programming action for storage location (3, 0), the storage controller changes the serial cell to serial cell SU1 for writing to the destination. Then, the storage controller performs a fuzzy programming action for storage location (0, 1) as the programming action of the first stage.

[0240] Then, the programming action proceeds (continues). When the full sequence programming action for storage location (4,4) and the fine programming action for storage location (3,4) are completed, the storage controller performs a fuzzy programming action on storage location (5,0) which is connected to word line WL5, which is connected after word line WL4, which serves as the boundary word line.

[0241] Thus, unlike the third comparative example, in the fourth comparative example, a full sequence programming operation is performed on the memory cell connected to the boundary word line. Therefore, it is not necessary to keep the data to be written to the memory cell connected to the boundary word line on the memory controller for an extended period of time. Specifically, at the timing when the fuzzy programming operation for memory location (5,0) has been completed, only memory location (5,0) has undergone fuzzy programming. As a result, in the fourth comparative example, the maximum size of the data that needs to be kept on the memory controller can be reduced compared to the third comparative example.

[0242] However, the full sequence programming performed on the memory cells connected to the boundary word line can be any of SLC programming, MLC programming, or TLC programming. Therefore, in the memory cells connected to the boundary word line, the data written to each memory cell ranges from 1 bit to 3 bits. Consequently, compared to writing 4 bits of data to each memory cell, the storage capacity of the memory system is reduced.

[0243] For example, in word-line priority mode where 4 word lines are bundled (N=4), programming 1 / 5 of the memory cells becomes a TLC programming operation, resulting in a maximum capacity loss of 0.5% for the memory system. Furthermore, when 9 word lines are bundled (N=9), programming 1 / 10 of the memory cells becomes a TLC programming operation, resulting in a maximum capacity loss of 0.25% for the memory system. The loss increases further when the entire sequence of programming operations for memory cells connected to boundary word lines is an MLC or SLC programming operation.

[0244] In contrast, in the storage system 3 of the implementation method, MLC and fine programming, or TLC and fine programming, are performed on the storage cells connected to the boundary word lines.

[0245] Reference Figure 19 The two-step write operation performed in the storage system 3 of the embodiment will be described. Figure 19 This is a diagram illustrating the first example of the two-step write sequence in the implementation method.

[0246] In the first example, the storage controller 4 instructs the NAND flash memory 5, regarding the memory cells connected to the boundary word lines, on both the MLC and fine programming operations as a two-step write operation. Additionally, the storage controller 4 instructs the NAND flash memory 5, regarding the memory cells connected to word lines other than the boundary word lines, on both the fuzzy and fine programming operations as a two-step write operation. The storage controller 4 specifies the memory cells of the write destination in a word-line-first manner within the write destination block.

[0247] exist Figure 19The example shows the case where N is 4. That is, the 5th, 10th, ... word lines are boundary word lines.

[0248] Specifically, first, the storage controller 4 performs a fuzzy programming operation on storage location (0,0) as the first stage of programming. Then, the storage controller 4 performs a fine programming operation on storage location (1,0) as the second stage of programming. In other words, corresponding to the completion of the fuzzy programming operation on the storage location (0,0) which belongs to the same string of cells and is connected to subsequent word lines, the storage controller 4 performs the fine programming operation.

[0249] Then, the storage controller 4 performs fuzzy programming on the storage location (2, 0) as the first stage of programming. The storage controller 4 then performs fine programming on the storage location (1, 0) as the second stage of programming.

[0250] The storage controller 4 performs a fuzzy programming action on the storage location (3, 0) as the first stage of programming. Then, the storage controller 4 performs a fine programming action on the storage location (2, 0) as the second stage of programming.

[0251] Then, the storage controller 4 performs an MLC programming action as the first stage of programming on the storage location (4,0) connected to the word line WL4, which serves as the boundary word line. That is, the storage controller 4 writes 2 bits of data to the storage location (4,0) through this programming action.

[0252] Furthermore, after performing MLC programming on storage location (4,0), storage controller 4 performs fine programming on storage location (3,0) as the second stage of programming.

[0253] The storage controller 4 has completed the fine programming operation on the storage location (3, 0) and changed the serial cell to serial cell SU1 for writing to the destination. Then, the storage controller 4 performs the fuzzy programming operation on the storage location (0, 1) as the first stage of programming.

[0254] Then, the programming process continues. Upon completion of the MLC programming operation for storage location (4,4) and the fine programming operation for storage location (3,4), the storage controller 4 performs a fuzzy programming operation as the first stage of programming for storage location (5,0), which is connected to word line WL5 following word line WL4 (the boundary word line). Then, the storage controller 4 performs a fine programming operation as the second stage of programming for storage location (4,0), which is connected to word line WL4 (the boundary word line).

[0255] At this point, the storage controller 4 uses the 2-bit data written in the first stage of the programming action to perform a fine-grained programming action as the second stage of the programming action. The storage controller 4 uses either Internal Data Load (IDL) or External Data Load (EDL).

[0256] When using IDL, the storage controller 4 sends an appended 2-bit data (e.g., top page data and previous page data) to the NAND flash memory 5. The NAND flash memory 5 reads the pre-written 2-bit data (e.g., middle page data and next page data). Then, the NAND flash memory 5 determines the target threshold voltage distribution based on the read 2-bit data and the received appended 2-bit data. The NAND flash memory 5 then performs fine-tuning operations based on the determined threshold voltage distribution.

[0257] When using EDL, the storage controller 4 reads two pre-written bits of data (e.g., middle page data and next page data) from the NAND flash memory 5. Then, the storage controller 4 combines the read two bits of data with the appended two bits of data (e.g., top page data and previous page data) to create four bits of data, and instructs fine-programming operations on the NAND flash memory 5 based on the created four bits of data.

[0258] Therefore, the storage controller 4 can maintain at least 2 additional bits of data (e.g., top page data and previous page data) until it performs fine programming on the storage cell connected to the boundary word line.

[0259] The memory locations (4,0), (5,0), (4,1), (4,2), (4,3), and (4,4) are the ones that only performed the first stage of programming and did not perform fine programming during the timing of the fine programming operation on memory location (4,0). All memory locations except memory location (5,0) have had 2 bits of data written to them via the MLC programming operation. That is, the memory controller 4 needs a buffer to hold 5×2 pages + 1×4 pages of data that should be written to each memory location. Therefore, compared to the first and third comparative examples, the required buffer size and the required capacitance of capacitor 62 can be reduced.

[0260] Furthermore, in the storage cells connected to the boundary word lines in the embodiments, only 4 bits of data are ultimately written. Therefore, the loss of maximum capacity of storage system 3, as seen in the fourth comparative example, is avoided.

[0261] This reduces the amount of data that needs to be held in storage controller 4 and avoids loss of data at the maximum capacity of storage system 3.

[0262] Next, refer to Figure 20 The two-step write operation performed in the storage system 3 of the embodiment will be described. Figure 20 This is a diagram illustrating the second example of the two-step write sequence in the implementation method.

[0263] In the second example, the memory controller 4 instructs the NAND flash memory 5, regarding the memory cells connected to the boundary word lines, on both TLC and fine programming operations as a two-step write operation. Additionally, the memory controller 4 instructs the NAND flash memory 5, regarding the memory cells connected to word lines other than the boundary word lines, on both fuzzy and fine programming operations as a two-step write operation. The memory controller 4 specifies the memory cells of the write destination in a word-line-first manner within the write destination block.

[0264] exist Figure 20 The example shows the case where N is 4. That is, the 5th, 10th, ... word lines are boundary word lines.

[0265] Specifically, first, the storage controller 4 performs a fuzzy programming operation on storage location (0,0) as the first stage of programming. Then, the storage controller 4 performs a fine programming operation on storage location (1,0) as the second stage of programming. In other words, corresponding to the completion of the fuzzy programming operation on the storage location (0,0) which belongs to the same string of cells and is connected to subsequent word lines, the storage controller 4 performs the fine programming operation.

[0266] Then, the storage controller 4 performs fuzzy programming on the storage location (2, 0) as the first stage of programming. The storage controller 4 then performs fine programming on the storage location (1, 0) as the second stage of programming.

[0267] The storage controller 4 performs a fuzzy programming action on the storage location (3, 0) as the first stage of programming. Then, the storage controller 4 performs a fine programming action on the storage location (2, 0) as the second stage of programming.

[0268] Then, the memory controller 4 performs a TLC programming operation as the first stage programming operation on the memory location (4, 0) connected to the word line WL4, which serves as the boundary word line. That is, the memory controller 4 writes 3 bits of data to the memory location (4, 0) through this programming operation.

[0269] Furthermore, after performing TLC programming on storage location (4,0), storage controller 4 performs fine programming on storage location (3,0) as the second stage of programming.

[0270] Accordingly, since the fine programming operation for storage location (3, 0) has been completed, storage controller 4 changes the serial cell to serial cell SU1 for writing to the destination. Then, storage controller 4 performs a fuzzy programming operation for storage location (0, 1) as the first stage of programming.

[0271] Then, the programming process proceeds. Upon completion of the TLC programming operation for storage location (4, 4) and the fine programming operation for storage location (3, 4), the storage controller 4 performs a fuzzy programming operation, the first stage of programming, on storage location (5, 0), which is connected to word line WL5 following word line WL4 (the boundary word line). Then, the storage controller 4 performs a fine programming operation, the second stage of programming, on storage location (4, 0), which is connected to word line WL4 (the boundary word line).

[0272] At this point, the memory controller 4 uses the 3 bits of data written in the first stage of programming to perform a fine-grained programming operation as the second stage of programming. The memory controller 4 uses, for example, EDL. The memory controller 4 reads the pre-written 3 bits of data (e.g., top page data, middle page data, and next page data) from the NAND flash memory 5. Then, the ECC circuit 45 of the memory controller 4 performs error correction. The memory controller 4 combines the 3 bits of data after error correction with an additional 1 bit of data (e.g., previous page data) to create 4 bits of data, and instructs the NAND flash memory 5 to perform a fine-grained programming operation based on the created 4 bits of data.

[0273] Therefore, the storage controller 4 can maintain at least one additional bit of data (e.g., previous page data) until it performs fine programming on the storage cell connected to the boundary word line.

[0274] The memory locations (4,0), (5,0), (4,1), (4,2), (4,3), and (4,4) are the ones where only the first stage of programming was performed during the timing of the fine programming operation on memory location (4,4). All memory locations except memory location (5,0) have had 3 bits of data written to them via TLC programming. This means that the memory controller 4 needs a buffer to hold 5 × 1 pages + 1 × 4 pages of data that should be written to each memory location. Therefore, compared to the first and third comparative examples, the required buffer size and the required capacitance of capacitor 62 can be reduced.

[0275] Here, refer to Figure 21This explains the situation where programming operations on memory cells connected to word lines other than the boundary word lines also perform TLC and fine programming operations. Figure 21 This is a diagram illustrating the third example of the two-step write sequence in the implementation method.

[0276] In the third example, the storage controller 4 instructs the NAND flash memory 5, regarding the memory cells connected to the boundary word lines, on both the TLC and fine programming operations as a two-step write operation. Additionally, the storage controller 4 also instructs the NAND flash memory 5, regarding the memory cells connected to word lines other than the boundary word lines, on both the TLC and fine programming operations as a two-step write operation. The storage controller 4 specifies the memory cells of the write destination in a word-line-first manner within the write destination block.

[0277] exist Figure 20 The output shows the case where N is 4. That is, the 5th, 10th, ... word lines are boundary word lines.

[0278] Specifically, first, the storage controller 4 performs a TLC programming operation as the first stage of programming on storage location (0,0). Then, the storage controller 4 performs a fine programming operation as the second stage of programming on storage location (1,0). In other words, the storage controller 4 performs the fine programming operation in accordance with the fact that the TLC programming operation for the storage cell belonging to the same string and connected to the subsequent word line has been completed. Furthermore, the fine programming operation performed on storage location (0,0) can be compared with... Figure 20 The TLC and fine programming actions described also use EDL for execution.

[0279] During the period from performing TLC programming on memory location (0,0) to performing fine programming, the memory locations that perform the first stage programming operation are only memory locations (0,0) and (1,0). Furthermore, 3 bits of data are written to each memory location using the TLC programming operation. Therefore, the memory controller 4 needs to hold the data to be appended to both memory locations. In other words, the memory controller 4 needs a buffer to hold 2×1 pages of data that should be written to each of the two memory locations.

[0280] Then, the storage controller 4 performs a TLC programming operation on the storage location (2, 0) as the first stage of programming. The storage controller 4 performs a fine programming operation on the storage location (1, 0) as the second stage of programming.

[0281] The storage controller 4 performs a TLC programming operation on the storage location (3, 0) as the first stage of programming. Then, the storage controller 4 performs a fine programming operation on the storage location (2, 0) as the second stage of programming.

[0282] Then, the storage controller 4 performs a TLC programming operation as the first stage programming operation on the storage location (4, 0) connected to the word line WL4, which serves as the boundary word line. The storage controller 4 performs a fine programming operation as the second stage programming operation on the storage location (3, 0).

[0283] The storage controller 4 has completed the fine-grained programming operation for storage location (3, 0) and changed the serial cell to serial cell SU1 for writing to the destination. Furthermore, the storage controller 4 performs a TLC programming operation for storage location (0, 1) as the first stage of programming.

[0284] Then, the programming process proceeds. Upon completion of the TLC programming operation for storage location (4, 4) and the fine programming operation for storage location (3, 4), the storage controller 4 performs a TLC programming operation as the first stage of programming for storage location (5, 0), which is connected to word line WL5 following word line WL4 (the boundary word line). Then, the storage controller 4 performs a fine programming operation as the second stage of programming for storage location (4, 0), which is connected to word line WL4 (the boundary word line).

[0285] The memory locations (4,0), (5,0), (4,1), (4,2), (4,3), and (4,4) are the ones where only the first stage of programming was performed during the timing of the fine programming operation on memory location (4,0). All six memory locations have had 3 bits of data written to them via TLC programming. This means that the memory controller 4 needs a buffer to hold 6 × 1 pages of data that should be written to each memory location. Therefore, compared to the first and third comparative examples, the required buffer size and the required capacitance of capacitor 62 can be reduced.

[0286] Next, the reliability and buffer size of the three two-step write methods will be explained. Figure 22 This diagram illustrates the three two-step writing methods in the implementation scheme.

[0287] The storage controller 4 instructs the NAND flash memory 5 to perform fuzzy and fine programming operations, MLC and fine programming operations, and TLC and fine programming operations as two-step write operations.

[0288] When performing fuzzy and fine programming operations, data reliability is high. On the other hand, when performing fuzzy and fine programming operations, a large data buffer is required in the storage controller 4.

[0289] When performing MLC and fine-tuning operations, data reliability is not very high. On the other hand, when performing MLC and fine-tuning operations, the required buffer size in storage controller 4 can be reduced.

[0290] When performing TLC and fine-grained programming, data reliability is higher than when performing MLC and fine-grained programming. This is because error correction is required by the ECC circuit 45 when performing TLC and fine-grained programming. Since error correction is performed in both writing steps, data reliability is guaranteed. Conversely, the buffer size required in the memory controller 4 can be reduced when performing TLC and fine-grained programming. The required buffer size increases when reading data written via TLC programming (the first stage of programming) is difficult. However, even in either case, the required buffer size can be reduced compared to the case of fuzzy and fine-grained programming.

[0291] Next, the combination of programming actions using these three writing methods will be explained. Figure 23 This diagram illustrates the three writing modes in the implementation method.

[0292] In this embodiment, the storage system 3 specifies the memory cell as the write destination using a word line (WL) priority method. When the memory cell as the write destination is determined using a word line priority method, the time from executing the first stage of programming to executing the second stage of programming is longer for memory cells connected to the boundary word line than for other memory cells. Therefore, regarding the writing method for programming operations performed on memory cells connected to the boundary word line, a scenario where the buffer size reduction effect is high is preferred.

[0293] Furthermore, regarding programming operations on memory cells connected to word lines other than boundary word lines, it is preferable to ensure data reliability.

[0294] Therefore, for programming operations on memory cells connected to the boundary word line, either MLC and fine programming operations, or TLC and fine programming operations, are performed. Conversely, for programming operations on memory cells connected to word lines other than the boundary word line, either fuzzy programming operations, or TLC and fine programming operations are performed.

[0295] Therefore, in Mode 1, the memory controller 4 performs MLC and fine-grained programming operations on memory cells connected to the boundary word line, and performs fuzzy and fine-grained programming operations on memory cells connected to word lines other than the boundary word line. An example using Mode 1 is shown in [reference needed]. Figure 19 The first example of a written order that has been explained.

[0296] In addition, as in Mode 2, the memory controller 4 performs TLC and fine programming operations on memory cells connected to the boundary word line, and performs fuzzy and fine programming operations on memory cells connected to word lines other than the boundary word line. An example using Mode 2 is shown in [reference needed]. Figure 20 The second example illustrates the writing order.

[0297] Additionally, as in Mode 3, TLC and fine-tuning operations are performed on memory cells connected to the boundary word line, and on memory cells connected to word lines other than the boundary word line. An example using Mode 3 is shown in [reference needed]. Figure 21 The third example illustrates the writing order.

[0298] Next, the sequence of commands sent from the storage controller 4 to the NAND flash memory 5 will be explained. Figure 24 This is a diagram illustrating an example of a command sequence used in the data write process of a storage system in an embodiment.

[0299] exist Figure 24 In the process, the storage controller 4 sends a sequence of commands, addresses, and data to the NAND flash memory 5.

[0300] The commands include XXh, YYh, and ZZh. Figure 24 80h in the address represents the end position of the command and indicates the beginning position of the address. Figure 24 In this context, 10h indicates the end of the command sequence.

[0301] XXh is the command to select the write mode. XXh represents one of the following: fuzzy and fine programming, MLC and fine programming, or TLC and fine programming.

[0302] YYh is a command that selects the step of a programming action. YYh represents either the programming action in stage 1 or the programming action in stage 2.

[0303] ZZh is a command that selects the page to write to. ZZh represents one of the following: top page, previous page, middle page, or next page.

[0304] The address consists of a column address and a row address. The column address and row address specify the address of the memory cell to which the write is destined.

[0305] tPROG This indicates the time when the programming action is performed. (t) PROG During this period, the NAND flash memory 5 becomes busy.

[0306] Next, the steps of the data write process performed by the storage controller 4 in mode 1 will be described. Figure 25 This is a diagram illustrating the steps of data writing processing performed in storage system 3 of the embodiment, using mode 1.

[0307] Since mode 1 is used, it is assumed that the memory controller 4 instructs the NAND flash memory 5 to perform MLC and fine programming operations for memory cells connected to the boundary word line, and to perform fuzzy and fine programming operations for memory cells connected to word lines other than the boundary word line.

[0308] First, the storage controller 4 determines the storage cell to be written to the destination (step S101). The storage controller 4 determines the storage cell to be written to the destination block based, for example, on a pre-determined write order.

[0309] The storage controller 4 determines whether the storage cell for the write destination determined in S101 is a storage cell connected to the boundary word line (step S102).

[0310] If the memory cell destined for the write is not connected to a boundary word line ("No" in S102), the memory controller 4 performs a fuzzy programming operation on the memory cell destined for the write (step S103). The memory controller 4 sends a command sequence containing the address of the memory cell specifying the write destination and a command specifying the fuzzy programming operation to the NAND flash memory 5.

[0311] The storage controller 4 determines whether a fine-grained programming operation can be performed on a certain storage cell by performing a fuzzy programming operation in S103 (step S104). Storage cells connected to the word line immediately preceding the word line to which the storage cell to which the fuzzy programming operation was performed in S204 belongs to the same string of cells can perform fine-grained programming. For example, if the word line connected to the storage cell to which the fuzzy programming operation was performed in S203 is a word line following a boundary word line, then the storage cell connected to the boundary word line can perform fine-grained programming.

[0312] If a fine-programming operation can be performed on a certain memory cell ("Yes" in S104), the memory controller 4 performs a fine-programming operation on the memory cell that can be fine-programmed in S104 (step S105). As a result, the memory cell at the destination stores 4 bits of data that can be read.

[0313] If it is impossible to perform fine programming on any memory cell ("No" in S104), the memory controller 4 skips step S105.

[0314] Storage controller 4 determines whether the data writing process is complete (step S106).

[0315] When the data writing process is complete (in S106, it is "Yes"), the storage controller 4 ends the data writing process.

[0316] If the data write process is not completed (in S106, it is "No"), the storage controller 4 returns to S101 to determine the storage cell of the next write destination.

[0317] Additionally, if the memory cell at the write destination is connected to the boundary word line ("Yes" in S102), the memory controller 4 performs an MLC programming operation on the memory cell at the write destination determined in S101 (step S107).

[0318] The storage controller 4 performs fine-grained programming operations (step S108) on storage cells that are capable of fine-grained programming operations by performing the MLC programming operation in S107. For example, storage cells that are connected to the word line immediately preceding the word line to which the storage cell to which the MLC programming operation was performed in S107 are connected, and that belong to the same string of cells, are capable of performing fine-grained programming operations.

[0319] Storage controller 4 determines whether the data writing process is complete (step S109).

[0320] When the data writing process is complete ("Yes" in S109), the storage controller 4 ends the data writing process.

[0321] If the data write process is not completed (No in S109), the storage controller 4 changes the serial unit of the write destination (step S110). For example, the storage controller 4 determines the serial unit following the serial unit to which the current write destination belongs as the serial unit of the write destination. Then, the storage controller 4 returns to S101 to determine the next write destination storage unit.

[0322] Next, the steps of the data write process performed by the storage controller 4 in mode 2 will be described. Figure 26 This is a diagram illustrating the steps of data writing processing performed in storage system 3 of the embodiment, using mode 2.

[0323] Since mode 2 is used, it is assumed that the memory controller 4 instructs the NAND flash memory 5 to perform TLC and fine programming operations for memory cells connected to the boundary word line, and to perform fuzzy and fine programming operations for memory cells connected to word lines other than the boundary word line.

[0324] First, the storage controller 4 determines the storage cell to be written to the destination (step S201). The storage controller 4 determines the storage cell to be written to the destination block based, for example, on a pre-determined write order.

[0325] The storage controller 4 determines whether the storage cell to which the write destination was determined in S201 is a storage cell connected to the boundary word line (step S202).

[0326] If the memory cell destined for the write is not connected to a boundary word line ("No" in S202), the memory controller 4 performs a fuzzy programming operation on the memory cell destined for the write (step S203). The memory controller 4 sends a command sequence containing the address of the memory cell specified for the write destination and a command specifying the fuzzy programming operation to the NAND flash memory 5. Alternatively, when using mode 3 instead of mode 2, the memory controller 4 performs a TLC programming operation on the memory cell destined for the write.

[0327] The storage controller 4 determines whether a fine-grained programming operation can be performed on a certain storage cell by performing a fuzzy programming operation in S203 (step S204). Storage cells connected to the word line immediately preceding the word line to which the storage cell to which the fuzzy programming operation was performed in S204 belong to the same string of cells can perform fine-grained programming. For example, if the word line connected to the storage cell to which the fuzzy programming operation was performed in S203 is a word line following a boundary word line, then the storage cell connected to the boundary word line can perform fine-grained programming.

[0328] If it is possible to perform fine programming on a certain memory cell ("Yes" in S204), the memory controller 4 performs fine programming on the memory cell for which fine programming can be performed in S204 (step S205). As a result, the memory cell at the destination stores 4 bits of data that can be read.

[0329] If it is impossible to perform fine programming on any memory cell ("No" in S204), the memory controller 4 skips step S205.

[0330] Storage controller 4 determines whether the data writing process is complete (step S206).

[0331] When the data writing process is complete (in S206, it is "Yes"), the storage controller 4 ends the data writing process.

[0332] If the data write process is not completed (in S206, it is "No"), the storage controller 4 returns to S201 and determines the storage cell of the next write destination.

[0333] Additionally, if the memory cell at the write destination is connected to a word line other than the boundary word line ("Yes" in S202), the memory controller 4 performs a TLC programming operation on the memory cell at the write destination determined in S201 (step S207).

[0334] The storage controller 4 performs fine programming operations (step S208) on storage cells that are capable of fine programming operations by executing the TLC programming operation in S207. For example, storage cells that are connected to the word line immediately preceding the word line to which the storage cell to which the TLC programming operation was performed in S207 are connected, and belong to the same string of cells, are capable of performing fine programming operations.

[0335] Storage controller 4 determines whether the data writing process is complete (step S209).

[0336] When the data writing process is complete (in S209, it is "Yes"), the storage controller 4 ends the data writing process.

[0337] If the data write process is not completed (No in S209), the storage controller 4 changes the serial unit of the write destination (step S210). For example, the storage controller 4 determines the serial unit following the serial unit to which the current write destination belongs as the serial unit of the write destination. Then, the storage controller 4 returns to S201 to determine the next write destination storage unit.

[0338] As explained above, in the storage system 3 according to the embodiment, the storage controller 4 determines the storage cell of the destination block in a word-line priority manner during the data write process. The storage controller 4 performs MLC and fine-programming operations as a two-step write operation on the storage cell connected to the boundary word line. Alternatively, the storage controller 4 can perform TLC and fine-programming operations instead of MLC and fine-programming operations as a two-step write operation on the storage cell connected to the boundary word line.

[0339] The storage controller 4 determines the storage cell to be written to in a word-line-first manner, thereby shortening the retention period required on the storage controller 4 for data that should be written to storage cells connected to word lines other than the boundary word lines.

[0340] In addition, by performing MLC and fine programming operations or TLC and fine programming operations on the memory cells connected to the boundary word line, the memory controller 4 can reduce the size of the data required for storage on the memory controller 4.

[0341] Furthermore, by performing MLC and fine-programming operations, or TLC and fine-programming operations, the storage controller 4 can ultimately write 4 bits of data even to storage cells connected to boundary word lines. Therefore, in the storage system 3 of the embodiment, loss of maximum capacity can be avoided.

[0342] Some embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and updates can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system comprising a non-volatile memory and a storage controller, The non-volatile memory has: The first and second string units each have multiple memory cells and a selection transistor. These multiple memory cells are connected in series and include memory cells from the first to the m-th memory cells, each capable of storing n bits of data. m is an integer greater than or equal to 4, n is an integer greater than or equal to 4, and the selection transistor is connected in series with the plurality of memory cells; Bit lines are connected to the first string unit and the second string unit; The first selection gate line and the second selection gate line are respectively connected to the gates of the selection transistors of the first string unit and the second string unit; and The first word line to the m-th word line are respectively connected to the first storage unit to the m-th storage unit of the first string unit and the second string unit. The storage controller is configured to perform data writing operations on the storage unit using a first write mode or a second write mode, wherein each of the first and second write modes includes a first-stage programming operation and a second-stage programming operation performed after the first-stage programming operation. The storage controller When using the first writing method, a first programming action is performed as a programming action in the first stage, and a second programming action is performed as a programming action in the second stage, which allows the written n bits of data to be read after the programming action in the second stage is completed. When using the second write method, a third programming action is performed as a programming action of the first stage, which allows the data written using the first stage programming action to be read from the storage unit of the write destination after the programming action of the first stage is completed. A fourth programming action is performed as a programming action of the second stage, which allows the n bits of data written to be read after the programming action of the second stage is completed. The storage controller is configured such that, The first programming action is performed on the storage unit connected to the first word line of the first string unit. After performing the first programming operation on the memory cell connected to the first word line of the first string unit, a first write operation is performed. The first write operation is a process of performing the first programming operation on the memory cell connected to the (x+1)th word line of the first string unit and performing the second programming operation on the memory cell connected to the xth word line of the first string unit, where x is an integer greater than or equal to 1 and less than (k-2), and k is an integer greater than or equal to 4 and less than m. After performing the first write operation, the third programming operation is performed on the memory cell connected to the k-th word line of the first string cell. After performing the third programming operation on the memory cell connected to the k-th word line in the first string unit, the second programming operation is performed on the memory cell connected to the (k-1)-th word line in the first string unit. After performing the second programming operation on the memory cell connected to the (k-1)th word line of the first string unit, the first programming operation is performed on the memory cell connected to the first word line of the second string unit. After performing the first programming operation on the memory cell connected to the first word line of the second string unit, a second write operation is performed. The second write operation is a process in which the first programming operation is performed on the memory cell connected to the (x+1)th word line of the second string unit, and the second programming operation is performed on the memory cell connected to the xth word line of the second string unit. After performing the second write operation, the third programming operation is performed on the memory cell of the second string unit connected to the k-th word line. After performing the third programming operation on the memory unit connected to the k-th word line of the second string unit, the second programming operation is performed on the memory unit connected to the (k-1)-th word line of the second string unit. After the second programming operation is performed on the memory cell connected to the (k-1)th word line of the second string unit, the fourth programming operation is performed on the memory cell connected to the kth word line of the first string unit.

2. The storage system according to claim 1, Where k is an integer less than m. The storage controller is configured such that, After performing the second programming operation on the memory cell connected to the (k-1)th word line in the second string unit, the first programming operation is performed on the memory cell connected to the (k+1)th word line in the first string unit. Then, the fourth programming action is performed on the storage unit in the first string unit that is connected to the k-th word line.

3. The storage system according to claim 2, The k is an integer less than or equal to (m / 2). The storage controller is configured such that, After the fourth programming action was performed on the memory unit connected to the k-th word line in the first string unit, Perform the third write process, which involves performing the first programming operation on the memory cell connected to the (k+x+1)th word line in the first string unit and performing the second programming operation on the memory cell connected to the (k+x)th word line in the first string unit. After the third write process is performed, the third programming operation is performed on the memory cell in the first string cell that is connected to the (2k)th word line.

4. The storage system according to claim 3, The storage controller is configured such that, After the third programming action was performed on the memory cell connected to the (2k)th word line in the first string cell, The second programming action is performed on the memory cell in the first string unit that is connected to the (2k-1)th word line.

5. The storage system according to claim 4, The storage controller is configured such that, After the second programming action is performed on the memory cell connected to the (2k-1)th word line in the first string cell, the first programming action is performed on the memory cell connected to the (k+1)th word line in the second string cell.

6. The storage system according to claim 5, The storage controller is configured such that, After performing the first programming action on the memory cell connected to the (k+1)th word line in the second string unit, the fourth programming action is performed on the memory cell connected to the kth word line in the second string unit.

7. The storage system according to claim 1, The storage controller is configured to, by causing the n-bit data to be coupled to a first threshold region to a second threshold region, which are defined in ascending voltage order. n The threshold region corresponds to the storage unit where the n-bit data is stored. The first threshold region corresponds to the erase state where the data in the storage unit has been erased. The second threshold region to the second n The threshold region corresponds to a write state where the voltage level is higher than that of the first threshold region and data has been written.

8. The storage system according to claim 7, The storage controller is configured such that, In the first programming action, the non-volatile memory is made to perform a threshold region of the memory cell that becomes the (2)th... n +1) Threshold region to (2) n +2 n Programming like any threshold region within the threshold region. In the second programming action, the non-volatile memory is made to perform a threshold region of the memory cell from the (2) n +1) Threshold region to (2) n +2 n The (2)th threshold region n The +p) threshold region is programmed to become the p-th threshold region as described above, where, p is 1 or higher and 2 n The following integers.

9. The storage system according to claim 7, The storage controller is configured such that, In the third programming action, the non-volatile memory is subjected to an erase state (2) whereby the threshold region of the memory cell becomes an erase state indicating that data has been erased based on 2 bits of the n bits. n +1) Threshold region and indicates voltage level ratio compared to the (2) n +1) The voltage level in the threshold region is high and the write state of the data written is in the (2)th step. n +2) Threshold region to (2) n The programming is similar to any threshold region within the +4) threshold region. In the fourth programming action, the non-volatile memory is made to cause the threshold region of the memory cell to change from the (2) n +1) Threshold region to (2) n +4) Any threshold region within the threshold region becomes the first threshold region to the second threshold region. n (2) in the threshold region n The programming is similar to that of any threshold region within a threshold region of / 4).

10. The storage system according to claim 7, The storage controller is configured such that, In the third programming action, the non-volatile memory is subjected to a second erase operation, in which the threshold region of the memory cell becomes an erase state indicating that the data has been erased based on the 3 bits of the n bits. n +1) Threshold region and indicates voltage level ratio compared to the (2) n +1) The voltage level in the threshold region is high and the write state of the data written is in the (2)th step. n +2) Threshold region to (2) n +8) Programming like any threshold region within the threshold region, In the fourth programming action, the non-volatile memory is made to cause the threshold region of the memory cell to change from the (2) n +1) Threshold region to (2) n +8) Any threshold region within the threshold region becomes the first threshold region to the second threshold region. n (2) in the threshold region n The programming is similar to that of any threshold region within the / 8) threshold regions.

11. The storage system according to claim 1, The first programming action is a vague programming action that occurs when data cannot be correctly read from the storage unit at the writing destination until the second programming action is completed. The second programming action is a fine-grained programming action that enables the readout of the written n-bit data after the second stage programming action is completed. The third programming action is an MLC (Multi-Level Cell) programming action that allows the 2-bit data written using the first programming action to be read from the storage unit at the write destination after the first programming action is completed. The fourth programming action is a fine-grained programming action that enables the n-bit data that has been written to be read from the storage unit of the writing destination after the programming action in the second stage is completed.

12. The storage system according to claim 1, The first programming action is a vague programming action that occurs when data cannot be correctly read from the storage unit at the writing destination until the second programming action is completed. The second programming action is a fine-grained programming action that enables the readback of the written n-bit data from the storage unit at the writing destination after the programming action in the second stage is completed. The third programming action is a TLC (Three-Level Cell) programming action that enables the reading of the 3-bit data written using the first programming action from the storage unit at the write destination after the first programming action is completed. The fourth programming action is a fine-grained programming action that enables the n-bit data that has been written to be read from the storage unit of the writing destination after the programming action in the second stage is completed.

13. A storage system comprising non-volatile memory and a storage controller, The non-volatile memory has: The first and second string units each have multiple memory cells and a selection transistor. These multiple memory cells are connected in series and include memory cells from the first to the m-th memory cells, each capable of storing n bits of data. m is an integer greater than or equal to 4, n is an integer greater than or equal to 4, and the selection transistor is connected in series with the plurality of memory cells; Bit lines are connected to the first string unit and the second string unit; The first selection gate line and the second selection gate line are respectively connected to the gates of the selection transistors of the first string unit and the second string unit; and The first word line to the m-th word line are respectively connected to the first storage unit to the m-th storage unit of the first string unit and the second string unit. The storage controller is configured to perform a first programming operation on the storage unit, and then perform a second programming operation after the first programming operation is completed, thereby performing a data writing operation on the storage unit. The storage controller is able to read the data written using the first programming action from the storage unit at the write destination after the first programming action is completed. The storage controller is able to read the n bits of data that have been written to the storage unit after the second programming action is completed. The storage controller is configured such that, The first programming action is performed on the storage unit connected to the first word line of the first string unit. After performing the first programming operation on the memory cell connected to the first word line of the first string unit, a first write operation is performed. The first write operation is a process of performing the first programming operation on the memory cell connected to the (x+1)th word line of the first string unit and performing the second programming operation on the memory cell connected to the xth word line of the first string unit, where x is an integer greater than or equal to 1 and less than (k-2), and k is an integer greater than or equal to 4 and less than m. After performing the first write operation, the first programming operation is performed on the memory cell connected to the k-th word line of the first string cell. After performing the first programming operation on the memory cell connected to the k-th word line of the first string unit, the second programming operation is performed on the memory cell connected to the (k-1)-th word line of the first string unit. After performing the second programming operation on the memory cell connected to the (k-1)th word line of the first string unit, the first programming operation is performed on the memory cell connected to the first word line of the second string unit. After performing the first programming operation on the memory cell connected to the first word line of the second string unit, a second write operation is performed. The second write operation is a process in which the first programming operation is performed on the memory cell connected to the (x+1)th word line of the second string unit, and the second programming operation is performed on the memory cell connected to the xth word line of the second string unit. After performing the second write operation, the first programming operation is performed on the memory cell connected to the k-th word line of the second string unit. After performing the first programming operation on the memory unit connected to the k-th word line of the second string unit, the second programming operation is performed on the memory unit connected to the (k-1)-th word line of the second string unit. After the second programming operation is performed on the memory cell connected to the (k-1)th word line of the second string unit, the second programming operation is performed on the memory cell connected to the kth word line of the first string unit.

14. The storage system according to claim 13, Where k is an integer less than m. The storage controller is configured such that, After performing the second programming operation on the memory cell connected to the (k-1)th word line in the second string unit, the first programming operation is performed on the memory cell connected to the (k+1)th word line in the first string unit. Then, the second programming action is performed on the storage unit in the first string unit that is connected to the k-th word line.

15. The storage system according to claim 14, The k is an integer less than or equal to (m / 2). The storage controller is configured such that, After performing the second programming action on the memory unit connected to the k-th word line in the first string unit, Perform the third write process, which involves performing the first programming operation on the memory cell connected to the (k+x+1)th word line in the first string unit and performing the second programming operation on the memory cell connected to the (k+x)th word line in the first string unit. After the third write process is performed, the first programming action is performed on the memory cell in the first string cell that is connected to the (2k)th word line.

16. The storage system according to claim 15, The storage controller is configured such that, After performing the first programming action on the memory cell connected to the (2k)th word line in the first string cell, The second programming action is performed on the memory cell in the first string unit that is connected to the (2k-1)th word line.

17. The storage system according to claim 16, The storage controller is configured such that, After the second programming action is performed on the memory cell connected to the (2k-1)th word line in the first string cell, the first programming action is performed on the memory cell connected to the (k+1)th word line in the second string cell.

18. The storage system according to claim 17, The storage controller is configured such that, After performing the first programming action on the memory cell connected to the (k+1)th word line in the second string unit, the second programming action is performed on the memory cell connected to the kth word line in the second string unit.

19. The storage system according to claim 13, The storage controller is configured to, by causing the n-bit data to be coupled to a first threshold region to a second threshold region, which are defined in ascending voltage order. n The threshold region corresponds to the storage unit where the n-bit data is stored. The first threshold region corresponds to the erase state where the data in the storage unit has been erased. The second threshold region to the second n The threshold region corresponds to a write state where the voltage level is higher than that of the first threshold region and data has been written.

20. The storage system according to claim 19, The storage controller is configured such that, In the first programming action, the non-volatile memory is caused to undergo a second erase operation, such that the threshold region of the memory cell becomes an erase state indicating that the data has been erased based on 3 bits of the n bits. n +1) Threshold region and indicates voltage level ratio compared to the (2) n +1) The voltage level in the threshold region is high and the write state of the data written is in the (2)th step. n +2) Threshold region to (2) n +8) Programming like any threshold region within the threshold region, In the second programming action, the non-volatile memory is made to perform a threshold region of the memory cell from the (2) n +1) Threshold region to (2) n +8) Any threshold region within the threshold region becomes the first threshold region to the second threshold region. n (2) in the threshold region n The programming is similar to that of any threshold region within the / 8) threshold regions.

21. A method for controlling a non-volatile memory, the non-volatile memory having: The first and second string units each have multiple memory cells and a selection transistor. These multiple memory cells are connected in series and include memory cells from the first to the m-th memory cells, each capable of storing n bits of data. m is an integer greater than or equal to 4, n is an integer greater than or equal to 4, and the selection transistor is connected in series with the plurality of memory cells; Bit lines are connected to the first string unit and the second string unit; The first selection gate line and the second selection gate line are respectively connected to the gates of the selection transistors of the first string unit and the second string unit; and The first word line to the m-th word line are respectively connected to the first storage unit to the m-th storage unit of the first string unit and the second string unit. The method includes: Perform the first programming action on the memory unit connected to the first word line of the first string unit. After performing the first programming operation on the memory cell connected to the first word line of the first string unit, a first write operation is performed. The first write operation is a process of performing the first programming operation on the memory cell connected to the (x+1)th word line of the first string unit and performing a second programming operation on the memory cell connected to the xth word line of the first string unit, where x is an integer greater than or equal to 1 and less than (k-2), and k is an integer greater than or equal to 4 and less than m. After performing the first write operation, the third programming operation is performed on the memory cell connected to the k-th word line of the first string cell. After performing the third programming operation on the memory cell connected to the k-th word line in the first string unit, the second programming operation is performed on the memory cell connected to the (k-1)-th word line in the first string unit. After performing the second programming operation on the memory cell connected to the (k-1)th word line of the first string unit, the first programming operation is performed on the memory cell connected to the first word line of the second string unit. After performing the first programming operation on the memory cell connected to the first word line of the second string unit, a second write operation is performed. The second write operation is a process in which the first programming operation is performed on the memory cell connected to the (x+1)th word line of the second string unit, and the second programming operation is performed on the memory cell connected to the xth word line of the second string unit. After performing the second write operation, the third programming operation is performed on the memory cell connected to the k-th word line of the second string cell. After performing the third programming operation on the memory cell connected to the k-th word line of the second string unit, the second programming operation is performed on the memory cell connected to the (k-1)-th word line of the second string unit, and After performing the second programming operation on the memory cell connected to the (k-1)th word line in the second string unit, the fourth programming operation is performed on the memory cell connected to the kth word line in the first string unit. The data writing operation to the storage unit can be performed using either a first write mode or a second write mode. Each of the first and second write modes includes a first-stage programming operation and a second-stage programming operation performed after the first-stage programming operation. The first writing method includes: performing the first programming action as a programming action in the first stage; and performing the second programming action as a programming action in the second stage, which enables the written n bits of data to be read out after the programming action in the second stage is completed. The second writing method includes: performing a third programming action as a programming action of the first stage, which enables the data written using the programming action of the first stage to be read from the storage unit of the writing destination after the programming action of the first stage is completed; and performing a fourth programming action as a programming action of the second stage, which enables the n bits of data written to be read after the programming action of the second stage is completed.

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