Establishment method of memory model and simulation method of memory circuit
By establishing linear and exponential models of memory cell strings, the problems of high simulation complexity and insufficient accuracy caused by multiple SPICE models in the existing technology are solved, realizing fast and accurate memory circuit simulation and reducing development time and cost.
Patent Information
- Application Number
- CN202411431676.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-22
- Filing Date
- 2024-10-14
- Publication Date
- 2026-03-03
AI Technical Summary
Existing technologies require maintaining multiple SPICE models to handle different threshold voltages when simulating NAND flash memory, resulting in high simulation complexity and insufficient accuracy, making it difficult to shorten development time and reduce costs.
By applying test conditions to the memory cell string, linear and exponential models are established, and the relationship between the impedance value of the memory cell string and the test voltage or temperature is recorded, reducing the number of SPICE models and using linear and exponential models to simulate the behavior of memory circuits.
It achieves fast and accurate memory circuit simulation, reduces the complexity of circuit models, reduces storage space requirements, and improves simulation accuracy.
Smart Images
Figure CN121601013A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method, and more particularly to a method for establishing a memory model and a method for simulating memory circuits. Background Technology
[0002] Generally, when reading data from a series-connected NAND flash memory, a read voltage is applied to the selected memory cell, and a pass voltage is applied to the unselected memory cells to read the data value stored in the selected cell. However, due to the series connection, the value read from the selected cell is also affected by the impedance of the other unselected memory cells. Furthermore, the current flowing through the memory cell string is also affected by temperature. Therefore, during flash memory development, SPICE models are used to simulate the memory circuitry and describe the parameters required for the simulation (e.g., parameters related to temperature or pass voltage effects). For example, by measuring and establishing the current-voltage characteristic curve of the transistor in the selected memory cell, and the effect of changing the pass voltage applied to the unselected memory cells on the current-voltage characteristic curve of the transistor in the selected memory cell, the parameters related to the pass voltage effect required for the simulation can be obtained.
[0003] However, to simulate different threshold voltages, existing technologies require generating multiple different SPICE models to describe the parameters needed for simulating each threshold voltage. This necessitates flash memory developers maintaining multiple SPICE models, increasing simulation complexity. Furthermore, as... Figure 1 As shown, to generate multiple different SPICE models for different threshold voltages, existing techniques simply shift the current-voltage characteristic curve (referred to as the first SPICE model) of the first threshold voltage applied to an unselected memory cell to the left to generate a second SPICE model related to the second threshold voltage. Alternatively, existing techniques simply shift the first SPICE model to the right to generate a third SPICE model related to the third threshold voltage. As a result, the simulation accuracy provided by these SPICE models still needs improvement, making it difficult to reduce development time and costs. Summary of the Invention
[0004] This invention provides a method for establishing a memory model and a method for simulating memory circuits, using a fast and accurate circuit model to simulate the circuit behavior of memory.
[0005] The method for establishing a memory model according to the present invention includes applying test conditions to a plurality of unselected memory cells in a memory cell string, wherein the threshold voltage of the selected memory cells in the memory cell string is programmed to a first threshold voltage value; performing multiple tests on the memory cell string by setting the test conditions to a plurality of test values to obtain a plurality of first impedance values corresponding to the test values respectively; and analyzing the test values and the corresponding first impedance values to obtain a linear model with a first slope value and a first intercept value, wherein the correspondence between the test values and the corresponding first impedance values under the first threshold voltage value satisfies the linear model.
[0006] The present invention provides a method for simulating a memory circuit, which is used to simulate the circuit behavior of a string of memory cells having unselected memory cells and selected memory cells. The method includes receiving a preset threshold voltage value; obtaining a slope value and an intercept value based on the preset threshold voltage value; and converting the slope value and the intercept value into a linear model, wherein the linear model records the correspondence between the test value of the unselected memory cell in the string of memory cells and the impedance value of the string of memory cells at the preset threshold voltage value.
[0007] Based on the above, the memory model establishment method and memory circuit simulation method of the present invention can summarize the relationship between the test conditions of the memory cell string and the change of the threshold voltage into several coefficients and a single or small number of models, and then perform simulation. Therefore, a fast and accurate circuit model can be used to simulate the circuit behavior of the memory. Attached Figure Description
[0008] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
[0009] Figure 1 A schematic diagram of several existing SPICE models;
[0010] Figure 2 This is a circuit diagram of a storage cell string according to Embodiment 1 of the present invention;
[0011] Figure 3A and Figure 3B This is a flowchart of the method for establishing a memory model according to Embodiment 1 of the present invention;
[0012] Figure 4A This is a schematic diagram of multiple linear models of the impedance value of the memory cell string MS and the test voltage under different threshold voltages of the selected memory cell in one embodiment of the present invention.
[0013] Figure 4B for Figure 4A A schematic diagram illustrating the exponential relationship between the slope of the line and the threshold voltage of the selected memory cell;
[0014] Figure 4C for Figure 4A A schematic diagram illustrating the exponential relationship between the intercept value of the line and the threshold voltage value of the selected memory cell;
[0015] Figure 4D This is a schematic diagram of multiple memory models according to embodiments of the present invention;
[0016] Figures 5A to 5C This is a flowchart of a simulation method for a memory circuit according to Embodiment 1 of the present invention. Detailed Implementation
[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0018] Figure 2 This is a circuit diagram of a memory cell string (MS) according to Embodiment 1 of the present invention. The memory cell string (MS) can be, for example, a NAND flash memory. The memory cell string (MS) includes a switch SWBL, memory cells MC1 to MC8, and a switch SWGND connected in series between the bit line BL and the reference ground voltage GND. Switches SWBL and SWGND can be controlled to be turned on or off by selection signal lines SELBL and SELGND, respectively, thus controlling the overall operation of the memory cell string (MS). Each memory cell MC1 to MC8 can receive corresponding signals through word lines WL1 to WL8 and bit line BL to perform programming and / or erasure operations, so that the threshold voltage of each memory cell MC1 to MC8 is controlled at the corresponding voltage value, thereby storing data.
[0019] In one embodiment, when reading data stored in one of the selected memory cells MC1 to MC8, a read voltage VR can be provided to the word line of the selected memory cell, and the voltage can also be provided to the word lines of other unselected memory cells in the memory cell string. Figure 2 For example, when memory cell MC5 is selected as the chosen memory cell for reading its stored data, the read voltage VR can be provided to the word line WL5 coupled to the selected memory cell MC5, and the voltage VP can be provided to the word lines WL1-WL4 and WL6-WL8 coupled to the other unselected memory cells MC1-MC4 and MC6-MC8 in the memory cell string MS. In this way, the read circuit in the memory system can read the current or impedance value flowing through the memory cell string MS through the bit line BL to determine the data value stored in the selected memory cell MC5.
[0020] During reading, the current or impedance value flowing through the memory cell string MS is limited to one of several corresponding value ranges due to the threshold voltage value of the selected memory cell MC5. The read circuit can determine the data value stored in the selected memory cell MC5 by judging which value range the sensed current or impedance value falls into. However, specifically, the current flowing through the memory cell string MS flows not only through the selected memory cell MC5 but also through the other unselected memory cells MC1-MC4 and MC6-MC8. In other words, the read operation for the selected memory cell MC5 is affected not only by the threshold voltage programmed for the selected memory cell MC5 but also by the impedance values of the unselected memory cells MC1-MC4 and MC6-MC8. More specifically, the impedance values of the unselected memory cells MC1-MC4 and MC6-MC8 are offset by the voltage value of the applied through voltage VP. When the impedance values of the unselected memory cells MC1~MC4 and MC6~MC8 deviate too much, causing the current flowing through the memory cell string MS to exceed the current range corresponding to the data value stored in the selected memory cell MC5, an error will occur in reading the memory string MS.
[0021] In addition, the current flowing through the memory cell string (MS) is also affected by temperature.
[0022] Therefore, this invention proposes a method for establishing a memory model and a method for simulating memory circuits to reduce the maintenance of SPICE models and to more accurately describe the parameters required for simulation (e.g., parameters related to temperature effects or voltage effects), thereby shortening the development time of flash memory and reducing read errors.
[0023] also, Figure 2 The memory cell string MS shown is for illustrative purposes only and is not intended to limit the hardware implementation of the memory cell string MS. Those skilled in the art can adjust or modify the number of memory cells in the memory cell string MS, or select the objects of memory cells, according to different design requirements.
[0024] Figure 3A and Figure 3B This is a flowchart illustrating the method for establishing a memory model according to Embodiment 1 of the present invention. The method for establishing a memory model in this embodiment can be applied to... Figure 2 The storage cell string MS shown may contain... Figure 2The memory system shown, consisting of a memory cell string MS, thus establishes a circuit model compatible with general or specific circuit simulation software. For example, the circuit model generated by the memory model establishment method is compatible with SPICE (Simulation Program with Integrated Circuit Emphasis) or similar circuit software, such as H-Spice, P-Spice, Cadence, Advanced Design System (ADS), etc.
[0025] In one embodiment of this disclosure, the method for establishing a memory model can vary the through voltage VP applied to an unselected memory cell MC and the measured current value, and establish a first prediction model based on the correspondence between the through voltage VP and the current value of the memory cell string MS. More specifically, the first prediction model is, for example, a linear model, and this disclosure can use the correspondence between the parameters (e.g., slope or intercept) of the first prediction model and different threshold voltage values of the selected memory cell MS in the memory cell string MS to establish a second prediction model, which is used to predict the slope or intercept value of the correspondence between the through voltage VP and the current value of the memory cell string MS at a specific threshold voltage value. In this embodiment, the second prediction model is a linear model. Furthermore, the test voltage provided by this method during testing is the aforementioned through voltage, which is explained prior to this.
[0026] Furthermore, in another embodiment of this disclosure, the method for establishing the memory model can be achieved by varying the test temperature applied to the memory cell string MS and the measured current value, and establishing a first prediction model based on the correspondence between the test temperature and the current value. Moreover, based on the correspondence between the parameters of the first prediction model (e.g., slope or intercept value) and different threshold voltage values of the selected memory cell MS in the memory cell string MS, this disclosure can be used to establish a second prediction model, which is used to predict the parameters of the first prediction model at a specific threshold voltage value.
[0027] Next, in this embodiment, the first prediction model and the second prediction model are recorded in a single SPICE model to facilitate subsequent simulation of the memory circuit. Test conditions can include changes in voltage or test temperature; however, this invention is not limited to these.
[0028] In detail, such as Figure 3A As shown, the method for establishing the memory model disclosed herein includes steps S30 to S32. Please refer to... Figure 2In step S30, when the threshold voltage of the selected memory cell MC5 in the memory cell string MS is programmed to the first threshold voltage value, the test voltage (i.e., the voltage VP) can be provided to the unselected memory cells MC1-MC4 and MC6-MC8 in the memory cell string MS. At the same time, the read voltage VR is also provided to the selected memory cell MC5 to facilitate subsequent read operations.
[0029] In step S31, the memory cell string MS is tested by setting multiple test voltage values to obtain a first impedance value corresponding to these test voltage values. Specifically, in step S31, all unselected memory cells MC1-MC4 and MC6-MC8 receive the same test voltage value, thereby measuring and recording the first impedance value of the memory cell string MS. Furthermore, after changing the test voltage value provided to the unselected memory cells MC1-MC4 and MC6-MC8, the above test procedure can be repeated to measure and record the first impedance value of the memory cell string MS corresponding to the changed test voltage value.
[0030] In step S32, the multiple test voltage values and measured first impedance values provided in step S31 can be analyzed to obtain and record the correspondence between the test voltage value and the corresponding first impedance value when the selected storage unit MC5 of the storage unit string MS is programmed with a first threshold voltage value, thereby establishing a first prediction model. More specifically, the correspondence between the test voltage value and the corresponding first impedance value can be linear, which can be represented by corresponding slope and intercept values. Therefore, in step S32, the slope and intercept values of the first prediction model established based on the correspondence between the test voltage value and the corresponding first impedance value can be stored in the SPICE model.
[0031] More specifically, given the first threshold voltage value, the first prediction model established based on the test voltage value and the corresponding first impedance value can be:
[0032] R = P1 × Vpass + P2
[0033] Where R corresponds to the first impedance value, Vpass corresponds to the test voltage value, P1 corresponds to the first slope value, and P2 corresponds to the first intercept value.
[0034] like Figure 3B As shown, the method for establishing the memory model in this disclosure, in addition to the following... Figure 3A In addition to steps S30 to S32 being executed in step S33, this embodiment also includes steps S34 to S38. Generally speaking, this embodiment can change the threshold voltage value of the selected memory cell to repeat the process. Figure 3ASteps S30 to S32 are used to obtain multiple first prediction models for selected memory cells with different threshold voltage values. Specifically, in the initial state, the threshold voltage of the selected memory cell M5 can be programmed, for example, to a first threshold voltage value, and after the first execution of step S33, the first prediction model corresponding to the first threshold voltage value is obtained.
[0035] In step S34, the number of executions in step S33 is used to evaluate whether a preset number of executions has been reached. If not (i.e., the number of executions in step S33 is less than the preset number of executions), the threshold voltage value of the selected memory cell is changed (step S35), and the process returns to step S33. Alternatively, if the judgment result in step S34 is yes, the relationship between the parameters in the multiple established first prediction models and the threshold voltage value of the selected memory cell is analyzed to establish a second prediction model (step S36). The preset number of executions can be set to 2 or more.
[0036] According to step S35, after changing the threshold voltage value of the selected memory cell MC5, the process returns to step S33. This allows for the acquisition of another first prediction model based on the correspondence between the impedance value of the memory cell string MS and the test voltage when the selected memory cell MC5 has a second threshold voltage value.
[0037] In one embodiment, establishing the second prediction model (step S36) includes steps S37 and S38. Step S37 analyzes the correspondence between first parameters (e.g., slope values) of multiple first prediction models and different threshold voltage values, while step S38 analyzes the correspondence between second parameters (e.g., intercept values) of multiple first prediction models and different threshold voltage values. Steps S37 and S38 can be executed simultaneously, or steps S37 and S38 can be appropriately ordered according to requirements before execution. The above execution sequence is within the scope of variant embodiments.
[0038] In this embodiment, in step S37, the correspondence between multiple slope values of multiple first prediction models and different threshold voltage values can be analyzed to establish an exponential model with a first exponential value and a first product value (the following is an example).
[0039] PX=C1×e Vt×C2
[0040] Where PX corresponds to the slope value of the first prediction model at the first threshold voltage value or the second threshold voltage value, C1 corresponds to the first product value, Vt corresponds to the first threshold voltage value or the second threshold voltage value, and C2 corresponds to the first exponent value. In this embodiment, by substituting the first threshold voltage value and the second threshold voltage value (the number of which depends on the aforementioned preset number of times) and the slope value of the corresponding first prediction model into the above exponent model, the corresponding first product value and the first exponent value can be obtained.
[0041] In this embodiment, in step S38, the correspondence between multiple intercept values of multiple first prediction models and different threshold voltage values can be analyzed to establish an exponential model with a second exponential value and a second product value (the following is an example).
[0042] PX = C3 × e Vt×C4
[0043] Where PX corresponds to the intercept value of the first prediction model at the first or second threshold voltage value, C3 corresponds to the second product value, Vt corresponds to the first or second threshold voltage value, and C4 corresponds to the second exponential value. In this embodiment, the corresponding second product value and second exponential value can be obtained by substituting the first and second threshold voltage values (the number of which depends on the aforementioned preset number of times) and the intercept value of the corresponding first prediction model into the above exponential model.
[0044] Next will be Figures 4A to 4C Let's take an example to illustrate. Figure 3A , Figure 3B The method for establishing the memory model. Figure 4A This is a schematic diagram illustrating multiple linear models of the impedance value of the memory cell string MS and the test voltage under different threshold voltages of the selected memory cell MC5, according to an embodiment of the present invention. Specifically, after executing steps S30 to S32 (i.e., step S33), a linear model of the impedance value of the memory cell string MS and the test voltage can be obtained. Furthermore, by executing the loop formed by steps S33 and S35 multiple times, multiple linear models of the changing relationship between the impedance value of the memory cell string MS and the test voltage can be obtained.
[0045] Figure 4A Lines L1 to L3 are shown, representing multiple linear models of the impedance value of the memory cell string MS versus the test voltage under different threshold voltages of different selected memory cells MC5. For example, line L1 is the linear model when the selected memory cell MC5 stores a data value of 0 and the threshold voltage is -4.5V. Line L2 is the linear model when the selected memory cell MC5 stores a data value of 0 and the threshold voltage is -2.5V. Line L3 is the linear model when the selected memory cell MC5 stores a data value of 1 and the threshold voltage is 4.7V.
[0046] further,
[0047] Once a sufficient number of linear models are obtained, step S36 can be performed to analyze the relationship between the slope and intercept values of these linear models and the threshold voltage value of the selected memory cell MC5. For example... Figure 4B As shown, it can be based on Figure 4A The slope values of lines L1 to L3 in the graph exhibit an exponential or logarithmic distribution relationship with their corresponding threshold voltage values, thereby establishing an exponential model C1 with a first product value and a first exponent value. Therefore, by substituting the slope values and the corresponding threshold voltage values into the exponential model C1, the first product value and the first exponent value can be calculated.
[0048] like Figure 4C As shown, it can be based on Figure 4A The exponential or logarithmic distribution relationship between the intercept values of lines L1 to L3 and their corresponding threshold voltage values is used to establish an exponential model C2 with a second product value and a second exponential value. Therefore, by substituting the intercept values and the corresponding threshold voltage values into the exponential model C2, the second product value and the second exponential value can be calculated.
[0049] Figure 4D The memory model shown is through Figure 3A or Figure 3B The memory model was obtained using the method for establishing the memory model. For example, Figure 4D The memory model shown can be, for example, a memory model that is... Figure 4A The impedance value is obtained by taking the reciprocal of the impedance value.
[0050] like Figure 4D As shown, through Figure 3A or Figure 3B The various linear memory models established by this method not only exhibit different conduction currents at different threshold voltage values, but also different saturation currents after conduction. Thus, Figure 3A or Figure 3B The memory model established by this method can record more accurate memory circuit behavior with less memory space, thus effectively improving the time required for the overall circuit design process and the accuracy of the simulation results.
[0051] Simply put, Figure 3BThe method for establishing the memory model involves performing multiple tests on the memory cell string MS to obtain multiple linear models between the impedance value of the memory cell string MS and the test voltage / through voltage under different threshold voltage values for the selected memory cell MC5. More specifically, these linear models are represented and stored by slope values and intercept values. Furthermore, these slope values and intercept values can be further analyzed to obtain an exponential model recording the relationship between the slope value and the threshold voltage of the selected memory cell MC5, and an exponential model recording the relationship between the intercept value and the threshold voltage of the selected memory cell MC5. More specifically, the bases in these two exponential models can be the same and are derived from the same preset exponential model. Therefore, the memory model establishment method ultimately only needs to store the first product value, the first exponential value, the second product value, the second exponential value, and the preset exponential model to represent all linear models between the impedance value of the memory cell string MS and the test voltage / through voltage under all threshold voltage values. This further reduces the storage space of the memory model, reduces the time required for circuit simulation, and increases the accuracy of circuit simulation.
[0052] In one embodiment, the above Figure 3A , Figure 3B The memory model can be established using a computer device, which may include a processor and memory. The computer device can be coupled to the target memory via a test bench or probe card to obtain the impedance value of the memory cell string (MS). Alternatively, the impedance value of the memory cell string can be tested and stored before being provided to the execution unit. Figure 3A , Figure 3B A computer device for establishing a memory model.
[0053] Figure 5A The simulation method for memory circuits can be used, for example, to simulate memory circuits like... Figure 2 Electrical behavior and operational performance of the memory cell string MS in the database. Figure 5A The simulation method for the memory circuit includes steps S50 to S53. In step S50, a preset threshold voltage value can be received. In step S51, a slope value and an intercept value are obtained based on the preset threshold voltage value. In step S52, the slope value and intercept value are converted into a linear model, wherein the linear model records the correspondence between the test voltage value of the unselected memory cell in the memory cell string and the impedance value of the memory string under the preset threshold voltage value.
[0054] Specifically, in step S51, the received preset threshold voltage value may be, for example, the preset programmed threshold voltage of the selected memory cell MC5 in the memory cell string MS.
[0055] In step S52, the threshold voltage of the selected memory cell MC5 is programmed below a preset threshold voltage value, and the correspondence between the impedance value of the memory cell string MS and the voltage across it can be obtained. For example, the correspondence between the test voltage value and the corresponding first impedance value can be linear. This linear relationship changes with the preset threshold voltage value programmed to the selected memory cell MC5. Therefore, after receiving the preset threshold voltage value, the linear model corresponding to the preset threshold voltage value can be obtained by, for example, looking up a table or other suitable method. More specifically, since the straight line of the linear model can be represented by the slope and intercept values, obtaining the linear model below the preset threshold voltage value can be achieved by obtaining the slope and intercept values of the linear model and substituting them into the preset linear model for reconstruction. The preset linear model is:
[0056] R = P1 × Vpass + P2
[0057] Where R corresponds to the impedance value of the memory cell string MS, Vpass corresponds to the through voltage value, P1 corresponds to the slope value of the linear model, and P2 corresponds to the intercept value of the linear model. Therefore, by substituting the slope value and intercept value into the preset linear model, the correspondence between the impedance value and the through voltage value of the memory cell string MS can be restored to a linear formula.
[0058] Figure 5B Similar to Figure 5A ,only Figure 5B The method for simulating the memory circuit includes steps S50 to S52, as well as steps S53 to S55 executed in step S51.
[0059] In detail, in step 53, a first exponent value, a first intercept value, a second exponent value, a second intercept value, and a preset exponent model can be obtained. The first exponent value, the first intercept value, the second exponent value, and the second intercept value are coefficients in the preset exponent model. The first exponent value and the first intercept value can be coefficients in the preset exponent model corresponding to the slope value, while the second exponent value and the second intercept value can be coefficients in the preset exponent model corresponding to the intercept value. Preset exponent model
[0060] PX=C1×e Vt×C2
[0061] When PX corresponds to the slope value, C1 corresponds to the first product value, Vt corresponds to the preset threshold voltage value, and C2 corresponds to the first exponent value. When PX corresponds to the intercept value, C1 corresponds to the second product value, Vt corresponds to the preset threshold voltage value, and C2 corresponds to the second exponent value. Thus, after obtaining the first exponent value, the first intercept value, the second exponent value, the second intercept value, and the preset exponent model, the first exponent value and the first intercept value can be substituted into the preset exponent model to obtain an exponent model showing the relationship between the slope value and the threshold voltage. Furthermore, the second exponent value and the second intercept value can be substituted into the preset exponent model to obtain another exponent model showing the relationship between the intercept value and the threshold voltage.
[0062] In step S54, the slope value is obtained based on the first exponent value and the first intercept value. Specifically, in step S53, an exponential model of the relationship between the slope value and the threshold voltage has been obtained based on the first exponent value and the first intercept value. Therefore, in step S54, the threshold voltage can be substituted into the exponential model to obtain the slope value of the linear relationship between the impedance value of the memory cell string MS and the through voltage under the preset threshold voltage value.
[0063] In step S55, the intercept value is obtained based on the second exponent value and the second intercept value. Specifically, in step S53, an exponential model of the relationship between the intercept value and the threshold voltage has been obtained based on the second exponent value and the second intercept value. Therefore, in step S55, the threshold voltage can be substituted into the exponential model to obtain the intercept value of the linear relationship between the impedance value of the memory cell string MS and the through voltage under the preset threshold voltage value.
[0064] Overall, steps S53 to S55 can be summarized as obtaining the slope value and the linear relationship between the impedance value of the memory cell string MS and the voltage based on the preset threshold voltage value and the preset exponential model. Therefore, after completing steps S53 to S55, step S52 can be executed to convert the slope value and intercept value into a linear model.
[0065] Figure 5C Can be continued Figure 5A or Figure 5B This is performed after step S52. More specifically, Figure 5C The simulation method for the memory circuit can be based on the linear model obtained in step S52 to correct the voltage values applied to the unselected memory cells MC1~MC4 and MC6~MC8 of the memory cell string MS. Figure 5C The simulation method for the memory circuit includes steps S56 to S59.
[0066] In step S56, a preset test voltage value is obtained and input into a linear model to obtain the impedance value corresponding to the preset test voltage value of the memory cell string under a preset threshold voltage. Specifically, the preset test voltage value is the preset voltage value to be supplied to the unselected memory cells MC1-MC4 and MC6-MC8 of the memory cell string MS. Therefore, by substituting the preset test voltage value into the linear model, the circuit behavior of the memory cell string MS can be simulated through the linear model to obtain the impedance value of the memory cell string MS when the selected memory cell MC5 is programmed to be below the preset threshold voltage value.
[0067] In step S57, the impedance value corresponding to the preset test voltage value can be compared with the target impedance range to determine whether the impedance value falls within the target impedance range. More specifically, the target impedance range can be, for example, the impedance range or impedance specification specified by the system for the selected memory cell MC5 of the memory cell string MS at that threshold voltage value. Therefore, when it is determined that the impedance value corresponding to the preset test voltage value falls within the target impedance range, step S58 is executed to maintain the preset test voltage value. Conversely, when it is determined that the impedance value corresponding to the preset test voltage value does not fall within or exceeds the target impedance range, step S59 is executed to correct the preset test voltage value based on a linear relationship.
[0068] Specifically, in step S59, one of the endpoints closer to the impedance value in the target impedance range can be substituted into the linear relationship to obtain the corrected test voltage value, and the corrected test voltage value can be used as the through voltage value of the unselected storage cells MC1~MC4 and MC6~MC8 in the storage cell string MS.
[0069] In this way, through Figure 5C The simulation method for memory circuits can simulate individual memory cells before they leave the factory, thereby correcting the voltage applied to unselected memory cells under different conditions, thus improving the accuracy of memory system data.
[0070] In one embodiment, the above Figures 5A to 5C The simulation method for the memory circuit can be implemented using a computer device, which may include a processor and a memory. The computer device may store a first slope value, a first intercept value, a second slope value, a second intercept value, and a preset exponential model to obtain the impedance value of the memory cell string MS.
[0071] Figure 5A and Figure 5BThe simulation method for memory circuits can be performed by, for example, a simulation program with integrated circuit emphasis (SPICE) or similar circuit software, such as H-Spice, P-Spice, Cadence, advanced design system (ADS), or other suitable circuit software.
[0072] The above is used to execute Figure 3A , Figure 3B The computer device used to establish the memory model, or the device used to execute... Figures 5A to 5C In a computer device employing an analog method for storage circuitry, the processor may be, for example, a Central Processing Unit (CPU), or other programmable general-purpose or special-purpose microcontroller units (MCUs), microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), graphics processing units (GPUs), arithmetic logic units (ALUs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), any other type of integrated circuit, state machine, processor based on an Advanced Reduced Instruction Set Machine (ARM), or other similar elements or combinations thereof. Furthermore, the memory in the computer device may be, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or similar elements or combinations thereof, used to store steps, instructions, modules, or various application programs executable by the processor.
[0073] In summary, the memory model establishment method disclosed herein can analyze the relationship between the memory cell string and the threshold voltage, summarizing it into several coefficients and a single or small number of models, thus representing the impedance change of the memory cell string under all threshold voltages. Correspondingly, the aforementioned memory circuit simulation method can convert several coefficients and models into accurate circuit behavior of the memory cell string. Furthermore, the memory circuit simulation method can further correct the through voltage applied to unselected memory cells, effectively improving the accuracy of memory circuit operation. Therefore, all of the above methods can effectively reduce the complexity of the circuit model, reduce the storage space of the memory model, reduce the time required for circuit simulation, and increase the accuracy of circuit simulation.
[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for establishing a memory model, characterized in that, The method for establishing the memory model includes: Test conditions are applied to multiple unselected memory cells in a string of memory cells, wherein the threshold voltage of the selected memory cells in the string of memory cells is programmed to a first threshold voltage value; By setting the test conditions to multiple test values, the memory cell string is tested multiple times to obtain multiple first impedance values corresponding to the multiple test values; and The plurality of test values and their corresponding plurality of first impedance values are analyzed to obtain a linear model with a first slope value and a first intercept value, wherein the correspondence between the plurality of test values and their corresponding plurality of first impedance values under the first threshold voltage value satisfies the linear model.
2. The method for establishing a memory model according to claim 1, wherein the test conditions are test voltage, test temperature, or a combination thereof.
3. The method for establishing a memory model according to claim 1, wherein the linear model is: R = P1 × Vpass + P2 Where R corresponds to each of the first impedance values, Vpass corresponds to each of the test values, P1 corresponds to the first slope value, and P2 corresponds to the first intercept value.
4. The method for establishing a memory model according to claim 1 further includes: The selected memory cell is programmed based on the second threshold voltage value; The test conditions applied to the plurality of unselected memory cells are set to the plurality of test values to perform multiple tests on the string of memory cells to obtain a plurality of second impedance values; as well as Analyze the plurality of test values and the plurality of corresponding second impedance values to obtain the second slope value and the second intercept value of the linear model satisfied by the plurality of test values and the plurality of second impedance values under the second threshold voltage value.
5. The method for establishing a memory model according to claim 4, wherein the first threshold and the second threshold satisfy an exponential model, and the method for establishing a memory model further includes: Analyze the first slope value and the second slope value to obtain the first exponent value and the first product value in the exponential model; as well as Analyze the first intercept value and the second intercept value to obtain the second exponent value and the second product value in the exponential model.
6. The method for establishing a memory model according to claim 5, wherein the exponential model is: PX=C1×e Vt×C2 Where PX corresponds to the first slope value or the second slope value, C1 corresponds to the first product value, Vt corresponds to the set first threshold voltage value or the second threshold voltage value of the selected memory cell, and C2 corresponds to the first exponent value. Wherein, when PX corresponds to the first intercept value or the second intercept value, C1 corresponds to the second product value, Vt corresponds to the set first threshold voltage value or the second threshold voltage value of the selected storage cell, and C2 corresponds to the second exponent value.
7. A method for simulating a memory circuit, used to simulate the behavior of a circuit having a plurality of unselected memory cells and a string of selected memory cells, characterized in that, The simulation method for the memory circuit includes: Receive a preset threshold voltage value; The slope and intercept values are obtained based on the preset threshold voltage value; and The slope value and the intercept value are converted into a linear model, wherein the linear model records the correspondence between the test values of the plurality of unselected memory cells in the memory cell string and the impedance value of the memory string at the preset threshold voltage value.
8. The simulation method for a memory circuit according to claim 7, wherein the test value is a test voltage value, a test temperature value, or a combination thereof.
9. The simulation method for a memory circuit according to claim 7, wherein the linear model is: R = P1 × Vpass + P2 Where R corresponds to the impedance value, Vpass corresponds to the test value, P1 corresponds to the slope value, and P2 corresponds to the intercept value.
10. The simulation method for a memory circuit according to claim 7, wherein the step of obtaining the slope value and the intercept value based on the preset threshold voltage value includes: The slope value and the slope value are obtained based on the preset threshold voltage value and the preset exponential model.
11. The method for simulating a memory circuit according to claim 10, further comprising: Substitute the first exponent value, the first product value, and the preset threshold voltage value into the preset exponent model to obtain the slope value; as well as The second exponent value, the second product value, and the preset threshold voltage value are substituted into the preset exponent model to obtain the intercept value.
12. The simulation method for a memory circuit according to claim 11, wherein the preset exponential model is: PX=C1×e Vt×C2 Where PX corresponds to the slope value, C1 corresponds to the first product value, Vt corresponds to the preset threshold voltage value, and C2 corresponds to the first exponent value. Wherein, when PX corresponds to the intercept value, C1 corresponds to the second product value, Vt corresponds to the preset threshold voltage value, and C2 corresponds to the second exponential value.
13. The simulation method for a memory circuit according to claim 7, further comprising, after the step of converting the slope value and the intercept value into the linear model: Obtain a preset test value and input the preset test value into the linear model to obtain the impedance value corresponding to the preset test value of the storage cell string under the preset threshold voltage value.
14. The method for simulating a memory circuit according to claim 13, further comprising: Compare the impedance value with the target impedance range; When the impedance value falls within the target impedance range, the preset test value is maintained; as well as When the impedance value exceeds the target impedance range, the preset test value is corrected according to the linear relationship.
15. The simulation method for a memory circuit according to claim 14, wherein the step of correcting the preset test value based on the linear relationship includes: Substitute one of the endpoints of the target impedance range that is closer to the impedance value into the linear relationship to obtain the corrected test value.