Pi-shaped chip high-voltage pulse attenuation network resistor and manufacturing method thereof

Abstract

The invention discloses a pi-shaped chip high-voltage pulse attenuation network resistor and a manufacturing method thereof, and belongs to the technical field of electronic components. The network resistor structure comprises a ceramic substrate, a resistive layer, a resistive layer R1, a resistive layer R2, a resistive layer R3, a surface electrode, a back electrode, a side electrode, an electrode nickel-plated layer, an electrode lead-tin-plated layer, a glass protection layer and an epoxy resin layer. The manufacturing method comprises the following steps: printing a surface electrode on the upper surface of a ceramic substrate, printing a back electrode on the lower surface of the ceramic substrate, printing a resistive layer bridged on the surface electrode, printing protective glass on the resistive layer, carrying out laser resistance trimming on the resistive layer, printing an epoxy resin protective layer and a mark on the protective glass, and sputtering a metal layer on the end surface. And preparing an electrode nickel-plated layer and a lead-tin-plated layer on the end surface. The problems that in the prior art, overheat burnout is likely to occur, electrodes are likely to be eroded in a humid or sulfur-containing environment, and the manufacturing precision and stability are difficult to improve and control are solved. The resistor is widely applied to the technical field of attenuation network resistors.

Description

Technical Field

[0001] This invention belongs to the field of electronic components technology, and more specifically to the field of attenuator technology. In particular, it relates to a π-type chip high-voltage pulse attenuation network resistor and its manufacturing method. Background Technology

[0002] In the field of electronic communications, π-type attenuation networks are widely used due to their ability to effectively attenuate signals and match impedance, ensuring maximum power transmission and reducing high-frequency signal reflection. This attenuator design resembles the Greek letter π, containing a series grounding resistor and two parallel shunt resistors, forming a perfectly symmetrical resistor network. Traditional manufacturing methods primarily rely on screen printing and laser trimming techniques. This involves printing three resistors (R1, R2, R3, where R2 and R3 have the same resistance value) on a substrate and adjusting their values ​​to create an attenuation network with specific attenuation performance. The process typically includes the following steps: First, selecting a suitable substrate material, such as an alumina substrate or an aluminum nitride substrate, and pre-treating it; then, printing the resistor material onto the substrate using screen printing to form the desired resistor pattern; next, adjusting the resistance value of the printed resistors using laser trimming technology to meet design requirements; finally, preparing electrodes at both ends of the resistors using end coating or sputtering followed by electroplating to complete the fabrication of the attenuation network.

[0003] Despite the progress made in the fabrication of π-type attenuation networks, some shortcomings remain: 1. In traditional manufacturing methods, the effective area of ​​the resistor is relatively small, and the input and output areas are the same, limiting the power capacity and pulse resistance of the attenuation network. In high-frequency, high-power applications, overheating and burnout are common problems. 2. Electrode materials used in existing technologies, such as silver and copper, have poor resistance to sulfidation. In humid, sulfur-containing environments, the electrodes are easily corroded by sulfides, leading to a decline in attenuation network performance or even failure. 3. While traditional screen printing and laser trimming techniques can manufacture and adjust resistor values, they suffer from limitations in improving manufacturing precision and stability, exhibiting large dispersion and poor stability. Especially in the fabrication of high-precision, high-stability attenuation networks, more precise control and adjustment are required.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The technical problem to be solved by this invention is to address the inherent defects in the existing π-type attenuation network manufacturing process, which leads to overheating and burnout in high-voltage, high-frequency, and high-power applications, and to the problem that the electrodes are easily corroded in humid or sulfur-containing environments, making it difficult to improve and control the manufacturing precision and stability.

[0006] The purpose of this invention is to provide a π-type chip-type high-voltage pulse attenuation network structure and its manufacturing method for attenuating high-voltage pulses.

[0007] Therefore, the present invention provides a π-type chip-type high-voltage pulse attenuation network resistor, such as... Figure 1-3 As shown. Includes: Ceramic substrate 1, resistive layer 2, R1 resistive layer 21, R2 resistive layer 22, R3 resistive layer 23, electrode 3, surface electrode 31, back electrode 32, side electrode 33, electrode nickel plating layer 34, electrode lead-tin plating layer 35, glass protective layer 4, epoxy resin layer 5.

[0008] The resistive layer 2 includes an R1 resistive layer 21, an R2 resistive layer 22, and an R3 resistive layer 23. The R1 resistive layer 21 is square and located on the left side of the ceramic substrate 1. The R2 resistive layer 22 and the R3 resistive layer 23 are square and located parallel to each other on the right side of the ceramic substrate 1. The upper and lower ends of the R1 resistive layer 21 are connected to the bottom ends of the corresponding U-shaped electrodes, respectively. The left end of the R2 resistive layer 22 is connected to the right side of the upper U-shaped electrode of the R1 resistive layer 21, and the right end of the R2 resistive layer 22 is connected to the corresponding square electrode. The left end of the R3 resistive layer 23 is connected to the right side of the lower U-shaped electrode of the R1 resistive layer 21, and the right end of the R3 resistive layer 23 is connected to the corresponding square electrode.

[0009] The electrode 3 includes a front electrode 31, a back electrode 32, a side electrode 33, a nickel plating layer 34, and a lead-tin plating layer 35. There are four front electrodes 31 located on the front surface of the ceramic substrate 1. The left side of the two U-shaped electrodes connected to both ends of the R1 resistor layer 21 is located at the left end of the front surface of the ceramic substrate 1, and the right side of the square electrode connected to the R2 resistor layer 22 and the R3 resistor layer 23 is located at the right end of the front surface of the ceramic substrate 1. There are four back electrodes 32, two located at the left end of the back surface of the ceramic substrate 1 and two located at the right end of the back surface of the ceramic substrate 1. There are four side electrodes 33, two at each end of the ceramic substrate 1, which are connected to the corresponding front electrodes 31 on the front surface of the ceramic substrate 1. The nickel plating layer 34 is located on the outer surface of the side electrodes 33, and the lead-tin plating layer 35 is located on the outer surface of the nickel plating layer 34.

[0010] The glass protective layer 4 is located on the resistive layer and the surface electrode 31.

[0011] The epoxy resin layer 5 is located on top of the glass protective layer 4.

[0012] The method for fabricating a π-type chip high-voltage pulse attenuation network resistor includes the following steps: S1: Scribing the ceramic substrate; S2: Print surface electrodes on the upper surface of the ceramic substrate; S3: Print the back electrode on the lower surface of the ceramic substrate; S4: The electrode is sintered at high temperature; S5: Printed resistor layers (R1, R2, R3) are bridged on the electrodes. The R1 resistor layer is vertical, while the R2 and R3 resistor layers are symmetrically distributed laterally. S6: Print protective glass on the resistive layer; S7: High-temperature firing of the resistive layer and protective glass; S8: Laser trimming of the resistive layer; S9: Print an epoxy resin protective layer and markings on the protective glass; S10: Low-temperature firing of epoxy resin protective layer and marking; S11: Perform a primary cleaving of a ceramic substrate with a resistor; S12: End face sputtered metal layer (side electrode 33). S13: Perform secondary slicing on the ceramic substrate after end-face sputtering; S14: Electrode nickel plating layer 34 is prepared on the end face; S15: Prepare lead-tin plating layer 35 on the end face electrode.

[0013] The advantages of this invention are as follows: By increasing the effective resistive area and employing electrode materials with better end-face sputtering and sulfur resistance, the power capacity, pulse resistance, and sulfur resistance of the π-type plate-type high-voltage pulse attenuation network are significantly improved, enabling it to better adapt to high-frequency, high-power, and highly corrosive application environments. In high-frequency, high-power applications, it maintains stable performance and is less prone to overheating or burnout.

[0014] Using gold electrodes or high-palladium-silver electrodes with good sulfide resistance as the leads of the resistor can resist the corrosion of sulfides in the air and maintain the stability and reliability of the attenuation network. At the same time, during end-face sputtering, the overlap between the encapsulation layer and the electrode is sputtered with NiCr metal, and then electroplated with Ni and SnPb layers, which can effectively isolate the air and protect the inner electrode from corrosive substances.

[0015] During the manufacturing process, precise manufacturing and resistance adjustment of the resistors were achieved by optimizing the parameters of screen printing and laser trimming techniques. Simultaneously, advanced electrode fabrication processes were employed to improve the quality and stability of the electrodes, thereby ensuring the overall performance and reliability of the attenuation network. By optimizing the manufacturing process and adopting advanced technologies, this invention improves the manufacturing efficiency and stability of the π-type chip-type high-voltage pulse attenuation network, reduces production costs and failure rates, and provides strong support for large-scale production and application.

[0016] This invention is widely used in the field of attenuation network resistor technology. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the planar structure of a π-type plate-type high-voltage pulse attenuation network.

[0018] Figure 2 This is a schematic diagram of the longitudinal structure of a π-type plate-type high-voltage pulse attenuation network.

[0019] Figure 3 This is a schematic diagram of the three-dimensional structure of a π-type plate-type high-voltage pulse attenuation network.

[0020] In the figure: 1 is a ceramic substrate, 2 is a resistive layer, 21 is the R1 resistive layer, 22 is the R2 resistive layer, 23 is the R3 resistive layer, 3 is an electrode, 31 is the front electrode, 32 is the back electrode, 33 is the side electrode, 34 is the electrode nickel plating layer, 35 is the electrode lead-tin plating layer, 4 is the glass protective layer, and 5 is the epoxy resin layer. Detailed Implementation

[0021] like Figure 1-3 As shown, the specific implementation of the π-type chip high-voltage pulse attenuation network resistor and its manufacturing method is as follows: The ceramic substrate is a 96% alumina ceramic substrate with a thickness of 0.5 mm to 3 mm.

[0022] The scribing is done with laser.

[0023] The electrode is a gold electrode or a high-palladium-silver electrode with a thickness of 5μm to 25μm.

[0024] The back electrode is a gold electrode or a high-palladium-silver electrode with a thickness of 5μm to 25μm.

[0025] The high-temperature sintering temperature of the electrode is 800~900℃, and the time is 30min~90min.

[0026] The thickness of the resistive layer is 5~25μm.

[0027] The sheet resistance of the resistive layer is 1Ω to 1MΩ.

[0028] The input resistor and the output resistor have the same resistance value, i.e., R2=R3.

[0029] The thickness of the protective glass is 5μm to 25μm.

[0030] The high-temperature firing temperature of the resistive layer and the protective glass layer is 600~700℃, and the time is 30~90min.

[0031] The laser trimming is either U-shaped or L-shaped.

[0032] The thickness of the epoxy resin protective layer is 5μm to 35μm.

[0033] The low-temperature firing temperature is 100℃~300℃, and the time is 30min~90min.

[0034] The thickness of the Ni metal layer is 10 nm to 500 nm.

[0035] The thickness of the SnPb layer on the end face is 5μm~35μm.

[0036] S1: Scribing the ceramic substrate; S2: Print a silver-palladium back electrode on the surface of the ceramic substrate: The thickness of the silver-palladium electrode is 5μm~25μm. For example, 10μm, 15μm or 20μm.

[0037] S3: Print gold or high-palladium-silver electrodes on the lower surface of the ceramic substrate: The thickness of the gold or high-palladium-silver electrodes is 5μm to 25μm. For example, 10μm, 15μm, or 20μm.

[0038] S4: The electrode is sintered at high temperature; S5: Printed resistive layers (R1, R2, R3) bridged on the electrodes: The thickness of the resistive layers is 5μm~25μm. For example, 10μm, 15μm, or 20μm. The sheet resistance of the resistive layers is 1Ω~1MΩ. For example: input resistor R2 is 75Ω, resistor R1 is 120Ω, output resistor R3 is 75Ω, characteristic impedance is 50Ω, voltage attenuation coefficient is 5:1, rated power is 3W, pulse voltage is 600V. The area of ​​input resistor R2 is larger than the area of ​​R1, and the area of ​​R1 is larger than the area of ​​output resistor R3, i.e., S R2 >S R1 >S R3 .

[0039] S6: Print protective glass on the resistive layer; S7: High-temperature firing of the resistive layer and protective glass; S8: Laser trimming of the resistive layer: using U-shaped or L-shaped trimming; S9: Print an epoxy resin protective layer and markings on the protective glass; S10: Low-temperature firing of epoxy resin protective layer and marking; S11: Perform a primary cleaving of a ceramic substrate with a resistor; S12: End face sputtered metal layer: The end face sputtered metal layer is a Ni layer with a thickness of 10~500nm, such as 100nm, 200nm or 300nm; S13: Perform secondary slicing on the ceramic substrate after end-face sputtering; S14: The end face is electroplated with SnPb layer with a thickness of 5μm~35μm, such as 10μm, 15μm or 20μm.

[0040] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This invention includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all possible implementations. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this invention are within the protection scope of this invention.

Claims

1. A π-type chip high-voltage pulse attenuation network resistor, characterized in that, include: Ceramic substrate, resistive layer, R1 resistive layer, R2 resistive layer, R3 resistive layer, electrode, front electrode, back electrode, side electrode, electrode nickel plating layer, electrode lead-tin plating layer, glass protective layer, epoxy resin layer. The resistive layers include resistive layers R1, R2, and R3. Resistive layer R1 is square and located on the left side of the ceramic substrate. Resistive layers R2 and R3 are square and located parallel to each other on the right side of the ceramic substrate. The top and bottom ends of resistive layer R1 are connected to the bottom ends of the corresponding U-shaped electrodes. The left end of resistive layer R2 is connected to the right side of the upper U-shaped electrode of resistive layer R1, and the right end of resistive layer R2 is connected to the corresponding square electrode. The left end of resistive layer R3 is connected to the right side of the lower U-shaped electrode of resistive layer R1, and the right end of resistive layer R3 is connected to the corresponding square electrode. The electrodes include a front electrode, a back electrode, side electrodes, a nickel plating layer, and a lead-tin plating layer. There are four front electrodes located on the front surface of the ceramic substrate. The left side of the two U-shaped electrodes connected to both ends of the R1 resistor layer is located at the left end of the front surface of the ceramic substrate, and the right side of the square electrodes connected to the R2 and R3 resistor layers is located at the right end of the front surface of the ceramic substrate. There are four back electrodes, two located at the left end of the back surface of the ceramic substrate and two located at the right end of the back surface of the ceramic substrate. There are four side electrodes, two at each end of the ceramic substrate, which are connected to the corresponding front electrodes on the front surface of the ceramic substrate. The nickel plating layer is located on the outer surface of the side electrodes, and the lead-tin plating layer is located on the outer surface of the nickel plating layer. The glass protective layer is located on top of the resistive layer and the surface electrode; The epoxy resin layer is located on top of the glass protective layer.

2. The π-type chip high-voltage pulse attenuation network resistor as described in claim 1, characterized in that: The ceramic substrate is a 96% alumina ceramic substrate with a thickness of 0.5 mm to 3 mm.

3. The π-type chip high-voltage pulse attenuation network resistor as described in claim 1, characterized in that: The electrode is a gold electrode or a high-palladium-silver electrode with a thickness of 5μm~25μm; The back electrode is a gold electrode or a high-palladium-silver electrode with a thickness of 5μm to 25μm.

4. The π-type chip high-voltage pulse attenuation network resistor as described in claim 1, characterized in that: The thickness of the resistive layer is 5~25μm; The sheet resistance of the resistive layer is 1Ω to 1MΩ.

5. The π-type chip high-voltage pulse attenuation network resistor as described in claim 1, characterized in that: The thickness of the protective glass is 5μm~25μm; The thickness of the epoxy resin protective layer is 5μm~35μm; The thickness of the Ni layer is 10 nm to 500 nm; The thickness of the SnPb layer is 5μm to 35μm.

6. The manufacturing method of a π-type chip high-voltage pulse attenuation network resistor as described in claim 1, characterized in that, Includes the following steps: S1: Scribing the ceramic substrate; S2: Print surface electrodes on the upper surface of the ceramic substrate; S3: Print the back electrode on the lower surface of the ceramic substrate; S4: The electrode is sintered at high temperature; S5: Printed resistor layers R1, R2 and R3 are bridged on the electrode. R1 resistor layer is vertical, and R2 and R3 resistor layers are symmetrically distributed laterally. S6: Print protective glass on the resistive layer; S7: High-temperature firing of the resistive layer and protective glass; S8: Laser trimming of the resistive layer; S9: Print an epoxy resin protective layer and markings on the protective glass; S10: Low-temperature firing of epoxy resin protective layer and marking; S11: Perform a primary cleaving of a ceramic substrate with a resistor; S12: End face sputtered side electrode metal layer; S13: Perform secondary slicing on the ceramic substrate after end-face sputtering; S14: Prepare a nickel plating layer on the end face of the electrode; S15: Prepare lead-tin plating on the end face of the electrode.

7. The manufacturing method of a π-type chip high-voltage pulse attenuation network resistor as described in claim 6, characterized in that: The electrode is a gold electrode or a high-palladium silver electrode, and the high-temperature sintering temperature is 800~900℃, and the time is 30min~90min.

8. The manufacturing method of a π-type chip high-voltage pulse attenuation network resistor as described in claim 6, characterized in that: The high-temperature firing temperature of the resistive layer and the protective glass layer is 600~700℃, and the time is 30~90min.

9. The manufacturing method of a π-type chip high-voltage pulse attenuation network resistor as described in claim 6, characterized in that: The laser trimming is either U-shaped or L-shaped.

10. The manufacturing method of a π-type chip high-voltage pulse attenuation network resistor as described in claim 6, characterized in that: The epoxy resin protective layer is fired at a low temperature of 100℃ to 300℃ for 30 minutes to 90 minutes.

Images