Error amplifier and DC-DC system
By introducing pull-up and pull-down modules into the DC-DC system, the transient response capability of the error amplifier is enhanced, the output voltage fluctuation problem caused by load current changes is solved, and the system achieves fast stability and efficient response.
Patent Information
- Application Number
- CN202411179612.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2026-03-03
AI Technical Summary
Traditional DC-DC systems are prone to instantaneous voltage fluctuations when the load current changes suddenly, leading to system instability and insufficient transient response capability.
Pull-up and pull-down modules are introduced to change the instantaneous output impedance of the error amplifier when the load changes, thereby increasing the -3dB and 0dB bandwidth of the loop. The load current change is detected by the transient detection module, and the output voltage is adjusted by the pull-up and pull-down modules.
It improves the transient response capability of DC-DC systems, shortens recovery and adjustment times, ensures system stability, avoids feedback voltage exceeding the common-mode input range, and has low power consumption without affecting steady-state loop characteristics.
Smart Images
Figure CN121602929A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to an error amplifier and a DC-DC system. Background Technology
[0002] In traditional DC-DC (Direct Current to Direct Current) systems, when the load current suddenly increases, the output voltage of the DC-DC system may experience a momentary undershoot due to insufficient system response speed; conversely, when the load current suddenly decreases, the output voltage of the DC-DC system may experience a momentary overshoot. Therefore, during transient response, if the transient response capability is insufficient, such fluctuations can lead to large fluctuations in the output voltage of the DC-DC system, and may even cause system instability. Summary of the Invention
[0003] The purpose of this application is to provide an error amplifier and a DC-DC system that can improve the transient response capability of the system.
[0004] One aspect of this application provides an error amplifier. The error amplifier includes an error amplification module and a transient enhancement module. The transient enhancement module includes a transient detection module, a buffer module, and a transient enhancement execution module. The error amplification module outputs a transient detection voltage and an output voltage based on a feedback voltage and a reference voltage, respectively. The buffer module buffers the output voltage of the error amplification module. The transient detection module detects changes in the load current of the DC-DC system based on the transient detection voltage. The transient enhancement execution module is connected to the output terminal of the transient detection module and includes a pull-up module and a pull-down module. The pull-up module pulls up the output voltage of the error amplification module when the transient detection module detects a decrease in the load current. The pull-down module pulls down the output voltage of the error amplification module (buffered by the buffer module) when the transient detection module detects an increase in the load current.
[0005] Further, the error amplification module includes a current source, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor. One end of the current source is connected to the power supply voltage, and the other end of the current source is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, respectively. The gates of the first PMOS transistor and the second PMOS transistor provide the reference voltage and the feedback voltage, respectively. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor through the first resistor. One end of the first resistor connected to the drain of the second NMOS transistor is used to output the transient detection voltage, and the other end of the first resistor is used to output the output voltage. The gates of the first NMOS transistor and the second NMOS transistor both provide a fourth bias voltage, and the gate of the first NMOS transistor is shorted to its drain. The sources of the first NMOS transistor and the second NMOS transistor are both grounded.
[0006] Furthermore, the error amplification module further includes a third PMOS transistor and a fourth PMOS transistor, wherein the gates of the third PMOS transistor and the fourth PMOS transistor are both connected to a first bias voltage; the source of the third PMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor; the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor through the first resistor.
[0007] Furthermore, the buffer module includes a source follower, which includes a twelfth NMOS transistor and a twelfth PMOS transistor. The output voltage is provided to the gate of the twelfth NMOS transistor, and the source of the twelfth NMOS transistor is used to output the buffered output voltage of the error amplification module. The drain of the twelfth NMOS transistor is connected to the drain of the twelfth PMOS transistor. The gate and drain of the twelfth PMOS transistor are shorted, and the source of the twelfth PMOS transistor is connected to the power supply voltage.
[0008] Furthermore, the transient enhancement execution module also includes an inverter circuit. The transient enhancement execution module has a first node and a second node. The pull-up module is connected to the first node, the first node is connected to the second node through the inverter circuit, and the pull-down module is connected to the second node.
[0009] Furthermore, the transient detection module includes a seventh NMOS transistor, the transient detection voltage is provided to the gate of the seventh NMOS transistor, the drain of the seventh NMOS transistor is connected to the first node, and the source of the seventh NMOS transistor is connected to ground.
[0010] Furthermore, the pull-up module includes a fifth PMOS transistor and a third NMOS transistor, wherein the gate of the fifth PMOS transistor provides a second bias voltage, the source of the fifth PMOS transistor is connected to the power supply voltage, and the drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is connected to the output voltage, and the gate of the third NMOS transistor is connected to the first node.
[0011] Furthermore, the pull-down module includes a tenth NMOS transistor and an eleventh NMOS transistor, wherein,
[0012] The gate of the tenth NMOS transistor is provided with a fourth bias voltage, the source of the tenth NMOS transistor is grounded, and the drain of the tenth NMOS transistor is connected to the source of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor is connected to the second node, and the drain of the eleventh NMOS transistor is connected to the buffered output voltage.
[0013] Furthermore, the transient enhancement execution module further includes a seventh PMOS transistor, a fourth NMOS transistor, and a first capacitor. The inverter circuit includes a tenth PMOS transistor, an eighth NMOS transistor, an eleventh PMOS transistor, and a ninth NMOS transistor. The gate of the seventh PMOS transistor provides a third bias voltage. The source of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded, and its gate is connected to the first node. The gate of the tenth PMOS transistor and the eighth NMOS transistor... The gates of all transistors are connected to the drain of the seventh PMOS transistor and to one end of the first capacitor; the other end of the first capacitor is grounded; the drains of the tenth PMOS transistor and the eighth NMOS transistor are both connected to the gate of the eleventh PMOS transistor; the source of the tenth PMOS transistor is connected to the power supply voltage, and the source of the eighth NMOS transistor is grounded; the source of the eleventh PMOS transistor is connected to the power supply voltage, and the drain of the eleventh PMOS transistor is connected to the drain of the ninth NMOS transistor and serves as the second node; the gate of the ninth NMOS transistor is provided with a fourth bias voltage, and the source of the ninth NMOS transistor is grounded.
[0014] Furthermore, the transient enhancement execution module also includes a fifth NMOS transistor and a sixth NMOS transistor, wherein the gate of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor; the transient detection voltage is provided to the gate of the sixth NMOS transistor, and the drain of the sixth NMOS transistor is connected to the first node.
[0015] Furthermore, the transient enhancement execution module also includes a sixth PMOS transistor and an eighth PMOS transistor, wherein the gate of the sixth PMOS transistor is provided with a second bias voltage, the source of the sixth PMOS transistor is connected to the power supply voltage, and the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor; the gate of the eighth PMOS transistor is provided with a third bias voltage, and the drain of the eighth PMOS transistor is connected to the first node.
[0016] Another aspect of this application provides a DC-DC system. The DC-DC system includes an error amplifier as described above.
[0017] The error amplifier and DC-DC system of one or more embodiments of this application change the instantaneous output impedance of the error amplifier when the load changes by introducing pull-up and pull-down modules, thereby increasing the -3dB bandwidth of the loop and shortening the recovery time; at the same time, the 0dB bandwidth of the loop is increased, the adjustment time is shortened, and thus the transient response capability of the system can be improved. Attached Figure Description
[0018] Figure 1 This refers to the waveform change of the output voltage of a DC-DC system when the load current of the DC-DC system changes.
[0019] Figure 2 This is a schematic block diagram of an error amplifier according to one embodiment of this application.
[0020] Figure 3 for Figure 2 A schematic block diagram of a specific embodiment of the error amplifier shown.
[0021] Figure 4 This application illustrates the Bode plot change of a DC-DC system after the intervention of a transient enhancement module, according to one embodiment of the present application.
[0022] Figure 5 This is a schematic diagram of a DC-DC system according to an embodiment of this application. Detailed Implementation
[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.
[0024] Figure 1 This paper reveals the waveform change of the output voltage of a DC-DC system when the load current changes. For example... Figure 1 As shown, the load of the DC-DC system changes from heavy load to light load at time t1, and the load current decreases, causing the system's output voltage Vo to overshoot; the load of the DC-DC system changes from light load to heavy load at time t2, and the load current increases, causing the system's output voltage Vo to undershoot.
[0025] exist Figure 1 In the middle, t u_1 and t d_1 Defined as loop response time, it refers to the time from when the output voltage Vo of a DC-DC system begins to change to when the switching transistor in the DC-DC system turns on. During this time, the DC-DC system has not yet made corresponding adjustments to the load change, therefore, the change in output voltage Vo is relatively small. The length of the loop response time and the magnitude of the change in output voltage Vo within the response time mainly depend on the intermediate frequency gain of the entire closed-loop system and the timing of the load current change.
[0026] t u_2 and t d_2 Defined as the loop settling time, during which the DC-DC system rapidly adjusts its duty cycle based on load changes, the inductor current gradually balances with the load current, and the output voltage Vo prepares to recover to steady state. The impact of load changes on the output voltage Vo can be considered a large signal; therefore, the adjustment of the error amplifier (EA) also falls into the large signal category. u_2 and t d_2 The length of t is related to the bandwidth and slew rate of the error amplifier. Additionally, t u_1 and t d_1 The magnitude of the change in output voltage Vo over time will also affect t. u_2 and t d_2 The duration of the transient response. The smaller the change in output voltage Vo during the transient response, the shorter the time required for the adjustment phase of the transient response.
[0027] t u_3 and t d_3Defined as the loop recovery time, this is the period during which the DC-DC system fine-tunes the output current, and the output voltage Vo gradually stabilizes to the preset value. The recovery time is mainly related to the -3dB bandwidth and phase margin of the DC-DC system. The larger the system bandwidth, the shorter the recovery time. Figure 1 In the middle, t u_3 The corresponding phase margin is too large, which manifests as overdamping; t d_3 A small phase margin results in underdamping. Poor phase margin increases recovery time.
[0028] Since optimizing loop response time is relatively difficult and ineffective, there are two main approaches to optimizing the transient performance of DC-DC systems:
[0029] (1) Optimize loop recovery time
[0030] By introducing faster-changing loop information, such as adding a current loop to an architecture with only a voltage loop, a "fast loop" is added to a system that originally only had a "slow-response loop," increasing the feedforward path. Essentially, this changes the architecture to improve the -3dB bandwidth of the loop, thereby reducing the recovery time. In addition, the introduction of the current loop also serves as a compensation to supplement the phase margin.
[0031] (2) Optimize loop adjustment time
[0032] Techniques for optimizing loop settling time are collectively referred to as nonlinear loop transient enhancement. When the load changes, the system's processing speed depends on the slowest changing node in the loop. In a DC-DC system with an error amplifier, this node is often the output node of the error amplifier. Therefore, speeding up the change of the error amplifier's output node can shorten the settling time. Common techniques include slew rate enhancement and variable compensation techniques, both of which essentially improve dynamic performance by increasing the loop bandwidth during load transitions.
[0033] However, introducing a current loop makes designing its weight in the loop control more difficult and requires analysis in conjunction with other loops. Using variable compensation techniques may lead to a decrease in compensation reliability. Furthermore, none of the methods mentioned above can guarantee that the input feedback voltage V of the error amplifier will remain constant when the system faces large load fluctuations. FB It is still within the common-mode input voltage requirement range.
[0034] This application provides an error amplifier with transient enhancement capability. Combining the above two approaches, it introduces pull-up and pull-down modules to change the instantaneous output impedance of the error amplifier when the load changes, thereby increasing the -3dB bandwidth of the loop to shorten the recovery time; at the same time, it increases the 0dB bandwidth of the loop and shortens the settling time, thus improving the transient response capability of the system.
[0035] The error amplifier of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.
[0036] Figure 2 A schematic block diagram of an error amplifier 100 according to one embodiment of this application is shown. Figure 2 As shown, an error amplifier 100 in one embodiment of this application includes an error amplification module 110 and a transient enhancement module 120. The transient enhancement module 120 includes a transient detection module 121, a buffer module 122, and a transient enhancement execution module 123.
[0037] The error amplification module 110 can be based on the feedback voltage V FB The transient detection voltage EA_OUT and the output voltage Vout are respectively output from the reference voltage Vref.
[0038] The buffer module 122 can buffer the output voltage Vout of the error amplification module 110 to improve the driving capability.
[0039] The transient detection module 121 can detect changes in the load current of a DC-DC system based on the transient detection voltage EA_OUT.
[0040] The transient enhancement execution module 123 is connected to the output terminal of the transient detection module 121. The transient enhancement execution module 123 includes a pull-up module 124 and a pull-down module 125. When the transient detection module 121 detects a decrease in load current, the pull-up module 124 can pull up the output voltage Vout. When the transient detection module 121 detects an increase in load current, the pull-down module 125 can pull down the output voltage Vcomp of the error amplification module 110 after buffering by the buffer module 122.
[0041] The transient enhancement execution module 123 of this application only intervenes when a load change occurs. When the DC-DC system is in a steady state, the transient enhancement execution module 123 does not participate in the operation. Therefore, it will not destroy the original loop characteristics of the system in a steady state.
[0042] Figure 3 Revealed Figure 2 A schematic block diagram of a specific embodiment of the error amplifier 100 is shown. Figure 3 As shown, in some embodiments, the error amplification module 110 may include a current source I1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a first resistor R1.
[0043] One end of the current source I1 is connected to the power supply voltage VDD, and the other end of the current source I1 is connected to the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2.
[0044] The gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are respectively provided with the reference voltage Vref and the feedback voltage V. FB The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor through the first resistor R1. One end of the first resistor R1 connected to the drain of the second NMOS transistor MN2 serves as one output terminal of the error amplifier module 110, used to output the transient detection voltage EA_OUT; the other end of the first resistor R1 can serve as the other output terminal of the error amplifier module 110, used to output the output voltage Vout.
[0045] By introducing a first resistor R1 into the error amplifier 100, not only can the output impedance of the error amplifier 100 be increased, but the output of the error amplifier 100 can also be separated into two voltages: the transient detection voltage EA_OUT and the output voltage Vout. The transient detection voltage EA_OUT can be input to the transient detection module 121 to detect changes in the output load.
[0046] The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to a fourth bias voltage Vbn1. The gate and drain of the first NMOS transistor MN1 are shorted, and the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both grounded to Vss. The first NMOS transistor MN1 and the second NMOS transistor MN2 form a current mirror.
[0047] In other embodiments, the error amplification module 110 of this application may further include a third PMOS transistor MP3 and a fourth PMOS transistor MP4 to introduce a cascode structure in the error amplification module 110, thereby increasing the output impedance of the error amplifier 100, improving the gain of the amplifier, and thus improving the output accuracy of the DC-DC system; at the same time, it can ensure that the drain potentials of the first PMOS transistor MP1 and the second PMOS transistor MP2 are equal, thereby ensuring the fair distribution of the tail current (i.e., current source I1).
[0048] The gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the first bias voltage Vb1.
[0049] The source of the third PMOS transistor MP3 is connected to the drain of the first PMOS transistor MP1, and the drain of the third PMOS transistor MP3 is connected to the drain of the first NMOS transistor MN1.
[0050] The source of the fourth PMOS transistor MP4 is connected to the drain of the second PMOS transistor MP2, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the second NMOS transistor MN2 through the first resistor R1.
[0051] In some embodiments, the buffer module 122 of this application may include, for example, a source follower, which can play an isolation role in voltage transmission. Because it is in a high-impedance state to the preceding circuit and a low-impedance state to the following circuit, the source follower can effectively isolate the mutual influence between the preceding and following circuits, reducing signal interference and noise transmission.
[0052] like Figure 3 As shown, the source follower may include a twelfth NMOS transistor MN12 and a twelfth PMOS transistor MP12. The output voltage Vout is supplied to the gate of the twelfth NMOS transistor MN12. The source of the twelfth NMOS transistor MN12 serves as the output terminal, used to output the buffered output voltage Vcomp. The drain of the twelfth NMOS transistor MN12 is connected to the drain of the twelfth PMOS transistor MP12. The gate and drain of the twelfth PMOS transistor MP12 are shorted, and the source of the twelfth PMOS transistor MP12 is connected to the power supply voltage VDD.
[0053] The transient enhancement execution module 123 of this application also includes an inverter circuit. The transient enhancement execution module 123 has a first node A and a second node B. A pull-up module 124 is connected to the first node A, the first node A is connected to the second node B through the inverter circuit, and a pull-down module 125 is connected to the second node B. This allows the potentials of the first node A and the second node B to be opposite, thereby ensuring that when the system load changes, only one of the corresponding modules, the pull-up module 124 and the pull-down module 125, can operate. That is, when the pull-up module 124 is working, the pull-down module 125 is not working; and when the pull-down module 125 is working, the pull-up module 124 is not working.
[0054] In some embodiments, the transient detection module 121 of this application may include a seventh NMOS transistor MN7. The transient detection voltage EA_OUT is provided to the gate of the seventh NMOS transistor MN7, the drain of the seventh NMOS transistor MN7 is connected to the first node A, and the source of the seventh NMOS transistor MN7 is connected to ground Vss.
[0055] In some embodiments, the pull-up module 124 of this application includes a fifth PMOS transistor MP5 and a third NMOS transistor MN3. The gate of the fifth PMOS transistor MP5 provides a second bias voltage Vb2, the source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD, and the drain of the fifth PMOS transistor MP5 is connected to the drain of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 is connected to the output voltage Vout, and the gate of the third NMOS transistor MN3 is connected to the first node A.
[0056] In some embodiments, the pull-down module 125 of this application includes a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11. The gate of the tenth NMOS transistor MN10 is provided with a fourth bias voltage Vbn1, the source of the tenth NMOS transistor MN10 is grounded to Vss, and the drain of the tenth NMOS transistor MN10 is connected to the source of the eleventh NMOS transistor MN11. The gate of the eleventh NMOS transistor MN11 is connected to the second node B, and the drain of the eleventh NMOS transistor MN11 is connected to the buffered output voltage Vcomp.
[0057] The first NMOS transistor MN1 forms a current mirror with the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10.
[0058] Continue to refer to Figure 3 The transient enhancement execution module 123 of this application also includes a seventh PMOS transistor MP7, a fourth NMOS transistor MN4, and a first capacitor C1. The inverter circuit includes a tenth PMOS transistor MP10, an eighth NMOS transistor MN8, an eleventh PMOS transistor MP11, and a ninth NMOS transistor MN9.
[0059] The gate of the seventh PMOS transistor MP7 is provided with a third bias voltage Vb3. The source of the seventh PMOS transistor MP7 is connected to the drain of the fifth PMOS transistor MP5, and the drain of the seventh PMOS transistor MP7 is connected to the drain of the fourth NMOS transistor MN4. The source of the fourth NMOS transistor MN4 is grounded to Vss, and the gate of the fourth NMOS transistor MN4 is connected to the first node A.
[0060] The gates of the tenth PMOS transistor MP10 and the eighth NMOS transistor MN8 are both connected to the drain of the seventh PMOS transistor MP7, and to one end of the first capacitor C1; the other end of the first capacitor C1 is grounded to Vss. The drains of the tenth PMOS transistor MP10 and the eighth NMOS transistor MN8 are both connected to the gate of the eleventh PMOS transistor MP11. The source of the tenth PMOS transistor MP10 is connected to the power supply voltage VDD, and the source of the eighth NMOS transistor MN8 is grounded to Vss.
[0061] The source of the eleventh PMOS transistor MP11 is connected to the power supply voltage VDD, and the drain of the eleventh PMOS transistor MP11 is connected to the drain of the ninth NMOS transistor MN9 and serves as the second node B; the gate of the ninth NMOS transistor MN9 provides the fourth bias voltage Vbn1, and the source of the ninth NMOS transistor MN9 is grounded Vss.
[0062] Optionally, the transient enhancement execution module 123 of this application further includes a ninth PMOS transistor MP9. The source of the tenth PMOS transistor MP10 is connected to the power supply voltage VDD through the ninth PMOS transistor MP9. The gate of the ninth PMOS transistor MP9 is provided with a second bias voltage Vb2, the source of the ninth PMOS transistor MP9 is connected to the power supply voltage VDD, and the drain of the ninth PMOS transistor MP9 is connected to the source of the tenth PMOS transistor MP10.
[0063] In some embodiments, the transient enhancement execution module 123 of this application may further include a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. The gate of the fifth NMOS transistor MN5 is connected to the drain of the seventh PMOS transistor MP7, the source of the fifth NMOS transistor MN5 is grounded to Vss, and the drain of the fifth NMOS transistor MN5 is connected to the source of the sixth NMOS transistor MN6. The transient detection voltage EA_OUT is provided to the gate of the sixth NMOS transistor MN6, and the drain of the sixth NMOS transistor MN6 is connected to the first node A.
[0064] When the load current increases, the seventh NMOS transistor MN7 turns on. When MN7 turns on, its drain potential is pulled low, which in turn pulls down the gate potential of the fourth NMOS transistor MN4. This causes the current in the branch containing MN4 to decrease, and its drain potential to rise. Consequently, the gate potential of the fifth NMOS transistor MN5 is pulled high, and MN5 turns on, further helping to pull down the drain potential of MN7. By adding the fifth and sixth NMOS transistors MN5 and MN6, positive feedback is introduced, forcing the voltage at node A to quickly enter a deterministic state, rapidly enabling transient enhancement.
[0065] In some embodiments, the transient enhancement execution module 123 of this application may further include a sixth PMOS transistor MP6 and an eighth PMOS transistor MP8. The gate of the sixth PMOS transistor MP6 is provided with a second bias voltage Vb2, the source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8. The gate of the eighth PMOS transistor MP8 is provided with a third bias voltage Vb3, and the drain of the eighth PMOS transistor MP8 is connected to the first node A.
[0066] By adding the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8, a fixed-current branch can be introduced. The current at the first node A is determined by comparing the current in the branch containing the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8 with the current in the branch containing the seventh NMOS transistor MN7 and the current in the branch containing the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6. Based on this comparison, a specific voltage level can be assigned to the first node A, which controls the magnitude of the current injected into the output voltage Vout of the error amplifier module 110.
[0067] Reference Figure 3 When the load current changes from a light load to a heavy load, due to the inductance Ls of the DC-DC system (such as... Figure 5 The inductor current (as shown) cannot change abruptly, and the output capacitor C of the DC-DC system... out (like Figure 5 (As shown) it will discharge outwards, causing the output voltage of the DC-DC system to undershoot. Due to the feedback voltage V of the error amplifier 100 FB The feedback voltage V of the error amplifier 100 is obtained by dividing the output voltage of the DC-DC system through a resistor divider network. FB Undershoot can also occur. Because the gate voltage and drain current of a PMOS transistor are negatively correlated, the feedback voltage V... FBThe decrease in voltage causes an increase in the current in the branches containing the second PMOS transistor MP2, the fourth PMOS transistor MP4, and the first resistor R1. Since the current source I1 is equal to the sum of the currents in the branches containing the first PMOS transistor MP1, the third PMOS transistor MP3, and the first NMOS transistor MN1, and the currents in the branches containing the second PMOS transistor MP2, the fourth PMOS transistor MP4, and the first resistor R1, and because the currents in the branches containing the second PMOS transistor MP2, the fourth PMOS transistor MP4, and the first resistor R1 increase, the current in the branches containing the first PMOS transistor MP1, the third PMOS transistor MP3, and the first NMOS transistor MN1 decreases. Because the first NMOS transistor MN1 and the second NMOS transistor MN2 form a current mirror, the current in the branch containing the second NMOS transistor MN2 is positively correlated with the current in the branch containing the first NMOS transistor MN1. Therefore, the current in the branch containing the second NMOS transistor MN2 decreases, and the transient detection voltage EA_OUT is pulled high, causing the seventh NMOS transistor MN7 to conduct. The potential of node A is pulled low, the third NMOS transistor MN3 and the fourth NMOS transistor are turned off, the current in the branch containing the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 charges the first capacitor C1, the gate potential of the tenth PMOS transistor MP10 and the eighth NMOS transistor MN8 becomes high, and the tenth PMOS transistor MP10 and the eighth NMOS transistor MN8 form an inverter. Therefore, the gate potential of the eleventh PMOS transistor MP11 becomes low. According to the negative correlation between the gate voltage and the drain current of a PMOS transistor, the current in the branch containing the eleventh PMOS transistor MP11 increases. Since the first NMOS transistor MN1 and the ninth NMOS transistor MN9 form a current mirror, and the ninth NMOS transistor MN9 is a fixed current reflected from the current mirror, the potential of node B is pulled high, and the eleventh NMOS transistor MN11 is turned on. The output introduces a pull-down branch consisting of the eleventh NMOS transistor MN11 and the tenth NMOS transistor MN10, which can pull down the buffered output voltage Vcomp of the error amplifier module 110 that was originally going to surge, thus accelerating the process of the buffered output voltage Vcomp from the surge unsteady state to the steady state.
[0068] When the load current changes from heavy load to light load, the inductor current of the DC-DC system is greater than the current required by the load. The excess inductor current will flow to the output capacitor C of the DC-DC system. out (like Figure 5 As shown, during charging, the output voltage of the DC-DC system overshoots, therefore, the feedback voltage V of the error amplifier 100... FBThis will also cause the current in the branches containing the second PMOS transistor MP2 and the fourth PMOS transistor MP4 to decrease, while the current in the branch containing the second NMOS transistor MN2 increases. The transient detection voltage EA_OUT is pulled low, the drain current of the seventh NMOS transistor MN7 decreases, the potential of the first node A is pulled high, the third NMOS transistor MN3 turns on, and a portion of the current from the fifth PMOS transistor MP5 is drawn into the output voltage Vout. This introduces a pull-up branch to pull up the output voltage Vout, which was originally intended to be pushed down, thus accelerating the process of the buffered output voltage Vcomp transitioning from the unstable state to the steady state. At this time, the potential of the second node B is low, the eleventh NMOS transistor MN11 is cut off, the pull-down module 125 is not working, and the output voltage Vout from the pre-amplifier module 110 is directly output through the source follower to obtain the buffered output voltage Vcomp.
[0069] In terms of bandwidth, the introduction of the pull-up module 124 or the pull-down module 125 in this application will cause the output of the error amplifier 100 to be connected in parallel with the impedance of a branch on the basis of the original impedance. Therefore, the total output impedance of the error amplifier 100 is smaller than the impedance in steady state during transient process.
[0070] Low-frequency gain A of error amplifier 100 V0 The formula for the principal pole P1 is as follows:
[0071] A V0 =g m R out
[0072]
[0073] Among them, g m R is the transconductance of error amplifier 100. out C is the output impedance of error amplifier 100. out This is the output capacitor of error amplifier 100.
[0074] Therefore, it can be seen from the above formula that after the transient enhancement module 120 intervenes, the low-frequency gain A of the error amplifier 100 of this application is... V0 It will decrease, the dominant pole P1 will increase, and the loop recovery time will decrease.
[0075] Figure 4 This application discloses a Bode plot change in a DC-DC system after the intervention of the transient enhancement module 120, according to one embodiment of this application. Figure 4As shown, in a DC-DC system, the 0dB bandwidth often includes not only the dominant pole P1 of the error amplifier 100 output stage, but also the zero Z0 compensated by the error amplifier 100 output stage and the secondary pole P2 in the loop. To simplify the Bode plot, only the zeros and poles Z0 within the 0dB bandwidth are shown. The low-frequency gain of the entire system, besides the low-frequency gain of the error amplifier 100, also includes the gain from the system's output voltage to the feedback voltage of the error amplifier 100, achieved through resistors R2 and R3 (e.g., ...). Figure 5 The feedback proportional gain of the resistor divider network (shown) and the gain coefficient provided by the output of error amplifier 100 to the output of the DC-DC system are represented here as a constant k. Figure 4 In the diagram, the dashed line represents the Bode plot of the DC-DC system without load change, and the solid line represents the Bode plot of the DC-DC system after load change and the intervention of the transient enhancement module 120. Figure 4 It can be seen that after the load changes and the transient enhancement module 120 intervenes, the low-frequency gain of the DC-DC system increases from kA. V0 Change to kA v0 The low-frequency gain of the DC-DC system decreases; simultaneously, the dominant pole changes from P1 to P1', the dominant pole becomes larger, and the -3dB bandwidth increases. Therefore, the response recovery time of the DC-DC system decreases; the 0dB bandwidth of the DC-DC system changes from f... c Change to f c As the 0dB bandwidth increases, the response adjustment time of the DC-DC system decreases, while the compensated zero point Z0 and secondary pole P2 remain unchanged.
[0076] Since the 0dB and 3dB bandwidths of a DC-DC system are better the larger they are, the error amplifier 100 of this application can simultaneously increase the 0dB and 3dB bandwidth loops after the transient enhancement module 120 is involved. Therefore, the system's response adjustment time and response recovery time can be shortened, and the transient response performance of the system can be improved.
[0077] The error amplifier 100 of this application, by incorporating a transient enhancement module 120 and introducing a pull-up module 124 and a pull-down module 125 within the transient enhancement module 120, can achieve at least the following beneficial technical effects:
[0078] (1) Stabilize the system operating point: This prevents a large change in the output voltage Vcomp of the error amplification module 110 after a large load jump, which in turn affects the feedback voltage V. FB Exceeding the common-mode input voltage range of the error amplifier 100 will worsen the transient response and ensure the normal operating point of the system.
[0079] (2) Low power consumption: In steady state, the transient enhancement module 120 does not consume additional current and does not damage the original loop characteristics of the system in steady state. The transient enhancement module 120 only intervenes when a load change occurs.
[0080] (3) At the same time, the response recovery time and adjustment time are reduced: By introducing pull-up module 124 and pull-down module 125 to make a brief adjustment to the output impedance of error amplifier 100, the -3dB bandwidth and 0dB bandwidth of the loop are increased simultaneously during the transient response, and the response recovery time and adjustment time of the system are reduced, thereby improving the transient response capability of the system.
[0081] This application also provides a DC-DC system. Figure 5 A schematic diagram of a DC-DC system 200 according to an embodiment of this application is shown. Figure 5 As shown, the DC-DC system of one embodiment of this application can utilize the error amplifier 100 described in the above embodiments.
[0082] The DC-DC system 200 of this application can have beneficial technical effects that are substantially similar to those of the error amplifier 100 described above, so it will not be described again here.
[0083] The error amplifier and DC-DC system provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the error amplifier and DC-DC system of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the spirit and principles of this application, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. An error amplifier, applied in a DC-DC system, characterized in that, It includes an error amplification module and a transient enhancement module. The transient enhancement module includes a transient detection module, a buffer module, and a transient enhancement execution module. The error amplification module is used to output transient detection voltage and output voltage based on feedback voltage and reference voltage, respectively; The buffer module is used to buffer the output voltage of the error amplification module; The transient detection module is used to detect changes in the load current of the DC-DC system based on the transient detection voltage; The transient enhancement execution module is connected to the output terminal of the transient detection module and includes a pull-up module and a pull-down module. The pull-up module is used to pull up the output voltage of the error amplification module when the transient detection module detects that the load current decreases. The pull-down module is used to pull down the output voltage of the error amplification module after it has been buffered by the buffer module when the transient detection module detects that the load current increases.
2. The error amplifier as described in claim 1, characterized in that, The error amplification module includes a current source, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor, wherein... One end of the current source is connected to the power supply voltage, and the other end of the current source is connected to the source of the first PMOS transistor and the source of the second PMOS transistor respectively. The gate of the first PMOS transistor and the gate of the second PMOS transistor respectively provide the reference voltage and the feedback voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor through the first resistor. The end of the first resistor connected to the drain of the second NMOS transistor is used to output the transient detection voltage, and the other end of the first resistor is used to output the output voltage. The gates of the first NMOS transistor and the second NMOS transistor are both provided with a fourth bias voltage, and the gate of the first NMOS transistor is shorted to the drain, while the source of the first NMOS transistor and the source of the second NMOS transistor are both grounded.
3. The error amplifier as described in claim 2, characterized in that, The error amplification module further includes a third PMOS transistor and a fourth PMOS transistor, wherein... The gates of the third PMOS transistor and the fourth PMOS transistor are both connected to a first bias voltage. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor. The source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor through the first resistor.
4. The error amplifier as described in claim 1, characterized in that, The buffer module includes a source follower, which comprises a twelfth NMOS transistor and a twelfth PMOS transistor, wherein... The output voltage is provided to the gate of the twelfth NMOS transistor, the source of the twelfth NMOS transistor is used to output the buffered output voltage, and the drain of the twelfth NMOS transistor is connected to the drain of the twelfth PMOS transistor. The gate and drain of the twelfth PMOS transistor are shorted together, and the source of the twelfth PMOS transistor is connected to the power supply voltage.
5. The error amplifier as described in claim 1, characterized in that, The transient enhancement execution module further includes an inverter circuit. The transient enhancement execution module has a first node and a second node. The pull-up module is connected to the first node, the first node is connected to the second node through the inverter circuit, and the pull-down module is connected to the second node.
6. The error amplifier as described in claim 5, characterized in that, The transient detection module includes a seventh NMOS transistor, the transient detection voltage is provided to the gate of the seventh NMOS transistor, the drain of the seventh NMOS transistor is connected to the first node, and the source of the seventh NMOS transistor is connected to ground.
7. The error amplifier as described in claim 5, characterized in that, The pull-up module includes a fifth PMOS transistor and a third NMOS transistor, wherein, The gate of the fifth PMOS transistor is provided with a second bias voltage, the source of the fifth PMOS transistor is connected to the power supply voltage, and the drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor. The source of the third NMOS transistor is connected to the output voltage, and the gate of the third NMOS transistor is connected to the first node.
8. The error amplifier as described in claim 5, characterized in that, The pull-down module includes a tenth NMOS transistor and an eleventh NMOS transistor, wherein, The gate of the tenth NMOS transistor is provided with a fourth bias voltage, the source of the tenth NMOS transistor is grounded, and the drain of the tenth NMOS transistor is connected to the source of the eleventh NMOS transistor. The gate of the eleventh NMOS transistor is connected to the second node, and the drain of the eleventh NMOS transistor is connected to the buffered output voltage.
9. The error amplifier as described in claim 7, characterized in that, The transient enhancement execution module further includes a seventh PMOS transistor, a fourth NMOS transistor, and a first capacitor; the inverter circuit includes a tenth PMOS transistor, an eighth NMOS transistor, an eleventh PMOS transistor, and a ninth NMOS transistor. The gate of the seventh PMOS transistor is provided with a third bias voltage, the source of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is connected to the first node; The gate of the tenth PMOS transistor and the gate of the eighth NMOS transistor are both connected to the drain of the seventh PMOS transistor and to one end of the first capacitor; the other end of the first capacitor is grounded; the drain of the tenth PMOS transistor and the drain of the eighth NMOS transistor are both connected to the gate of the eleventh PMOS transistor; the source of the tenth PMOS transistor is connected to the power supply voltage; and the source of the eighth NMOS transistor is grounded. The source of the eleventh PMOS transistor is connected to the power supply voltage, and the drain of the eleventh PMOS transistor is connected to the drain of the ninth NMOS transistor and serves as the second node. The gate of the ninth NMOS transistor is provided with a fourth bias voltage, and the source of the ninth NMOS transistor is grounded.
10. The error amplifier as claimed in claim 9, characterized in that, The transient enhancement execution module further includes a fifth NMOS transistor and a sixth NMOS transistor, wherein, The gate of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the fifth NMOS transistor is grounded, and the drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor. The transient detection voltage is provided to the gate of the sixth NMOS transistor, the drain of which is connected to the first node.
11. The error amplifier as claimed in claim 9, characterized in that, The transient enhancement execution module further includes a sixth PMOS transistor and an eighth PMOS transistor, wherein, The gate of the sixth PMOS transistor is provided with a second bias voltage, the source of the sixth PMOS transistor is connected to the power supply voltage, and the drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is provided with a third bias voltage, and the drain of the eighth PMOS transistor is connected to the first node.
12. A DC-DC system, characterized in that, Including the error amplifier as described in any one of claims 1 to 11.