Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system are provided. The semiconductor device includes: a memory cell structure in a cell array region; an electrode stack structure including a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked in the connection region; and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stack structure and electrically connected to the plurality of electrodes. The plurality of electrode contact portions includes a first contact portion and a second contact portion. The first contact portion includes a first conductive portion, and a first side insulating layer between the electrode stack structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulating layer between the electrode stack structure and the second conductive portion. The second side insulating layer has a shape or structure different from a shape or structure of the first side insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefits to Korean Patent Application No. 10-2024-0110459, filed on August 19, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices and electronic systems including such semiconductor devices. Background Technology

[0004] In electronic systems that implement data storage, semiconductor devices capable of storing high-capacity data are required. Therefore, methods for increasing the data storage capacity of semiconductor devices are being investigated. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0005] This disclosure attempts to provide a semiconductor device capable of enhancing reliability and productivity, as well as an electronic system including the semiconductor device.

[0006] A semiconductor device according to an embodiment includes: a memory cell structure located in a cell array region; an electrode stack structure including a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked at least in a connection region; and a plurality of electrode contact portions passing through or penetrating at least a portion of the electrode stack structure and electrically connected to the plurality of electrodes, respectively. The plurality of electrode contact portions include a first contact portion and a second contact portion. The first contact portion includes a first conductive portion and a first side insulating layer between the electrode stack structure and the first conductive portion. The second contact portion includes a second conductive portion and a second side insulating layer between the electrode stack structure and the second conductive portion. The second side insulating layer has a shape or structure different from that of the first side insulating layer.

[0007] An electronic system according to an embodiment includes: a main substrate; a semiconductor device located on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate. The semiconductor device includes: a memory cell structure located in a cell array region; an electrode stack structure including a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked at least in a connection region; and a plurality of electrode contact portions passing through or penetrating at least a portion of the electrode stack structure and electrically connected to the plurality of electrodes, respectively. The plurality of electrode contact portions include a first contact portion and a second contact portion. The first contact portion includes a first conductive portion and a first side insulating layer between the electrode stack structure and the first conductive portion. The second contact portion includes a second conductive portion and a second side insulating layer between the electrode stack structure and the second conductive portion. The second side insulating layer has a shape or structure different from that of the first side insulating layer.

[0008] A semiconductor device according to an embodiment includes: a memory cell structure located in a cell array region; an electrode stack structure including a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked at least in a connection region; and a plurality of electrode contact portions passing through or penetrating at least a portion of the electrode stack structure and electrically connected to the plurality of electrodes, respectively. At least one of the plurality of electrode contact portions includes a conductive portion and a side insulating layer between the electrode stack structure and the conductive portion. The side insulating layer includes a first portion and a second portion, the first portion being disposed above at least one of the plurality of electrode contact portions, and the second portion having a thickness less than that of the first portion and being disposed below or below the first portion.

[0009] According to embodiments, multiple vias can be formed using a partial etching process based on a binary system, which simplifies the process of forming gate contact portions and reduces the area of ​​the connection region. A first layer, serving as at least a partial portion of the side insulating layer, can be formed before subsequent partial etching processes, preventing damage to the stacked structure or electrode stack that may occur during subsequent partial etching processes, and allowing for the stable formation of vias with relatively large depths. This improves the reliability and productivity of the semiconductor device. Attached Figure Description

[0010] Figure 1 This is a schematic partial cross-sectional view of a semiconductor device according to an example embodiment.

[0011] Figure 2 It is shown Figure 1 An enlarged partial cross-sectional view of an example of a channel structure included in the semiconductor device shown.

[0012] Figure 3 It is shown Figure 1 A cross-sectional view of the connection region of the cell region included in the semiconductor device shown.

[0013] Figure 4 It is shown Figure 3 A cross-sectional view of part A.

[0014] Figure 5 It is shown Figure 3 A cross-sectional view of part B.

[0015] Figure 6 It is shown Figure 3 A cross-sectional view of part C.

[0016] Figures 7 to 18 This is a cross-sectional view illustrating an example manufacturing method of a semiconductor device.

[0017] Figure 19 This is a cross-sectional view showing a gate contact portion included in a semiconductor device according to an example embodiment.

[0018] Figure 20 This is a cross-sectional view showing a gate contact portion included in a semiconductor device according to an example embodiment.

[0019] Figure 21 This is a cross-sectional view showing a gate contact portion included in a semiconductor device according to an example embodiment.

[0020] Figure 22 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment.

[0021] Figure 23 This is a schematic diagram illustrating an electronic system including a semiconductor device according to an example embodiment.

[0022] Figure 24 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to an example embodiment.

[0023] Figure 25 This is a schematic cross-sectional view of a semiconductor package including a semiconductor device according to an example embodiment.

[0024] Figure 26 This is a schematic cross-sectional view of a semiconductor package including a semiconductor device according to an example embodiment. Detailed Implementation

[0025] To those skilled in the art, embodiments of this disclosure will be described more fully below with reference to the accompanying drawings to facilitate its practice. This disclosure may be implemented in various different forms and is not limited to the embodiments provided herein.

[0026] For clarity of description, irrelevant parts are omitted, and identical or similar parts are indicated by the same reference numerals throughout this specification.

[0027] Furthermore, since the dimensions and / or thicknesses of the parts, regions, components, units, layers, films, substrates, etc. shown in the accompanying drawings may be arbitrarily shown for better understanding and ease of explanation, this disclosure is not limited to the dimensions and / or thicknesses shown. In the accompanying drawings, the thicknesses of parts, regions, components, units, layers, films, substrates, etc., may be enlarged or exaggerated for ease of explanation and / or simplified illustration.

[0028] It will be understood that when a component, such as a part, region, component, unit, layer, film, substrate, etc., is referred to as being "on" another component, the component may be directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly on" another component, there are no intermediate components. Furthermore, when a component is referred to as being "on" or "above" a reference component, the component may be positioned on or below the reference component, and does not necessarily have to be "on" or "above" the reference component in the opposite direction of gravity. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, or described as "in contact" or "in contact with" another element (or any form of using the word "in contact"), there are no intermediate components at the point of contact.

[0029] Furthermore, throughout the specification, unless explicitly stated otherwise, the words “including,” “containing,” or “comprising,” as well as variations thereof, shall be understood to imply the inclusion of other components rather than the exclusion of any other components.

[0030] Furthermore, throughout the specification, the phrases “in a plane,” “in a plane,” “in a plan view,” or “in a plan view” can indicate the view of a portion from above or at the top, and the phrases “in a section” or “in a section view” can indicate the view of a section taken along the vertical direction from the side.

[0031] When referring to orientation, layout, location, shape, size, quantity, or other measure, terms such as “identical,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, quantities, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0032] In the following text, refer to Figures 1 to 18 The semiconductor device and its manufacturing method according to the example embodiments will be described in detail.

[0033] Figure 1 This is a schematic partial cross-sectional view of a semiconductor device 10 according to an example embodiment. Figure 2 It is shown Figure 1 An enlarged partial cross-sectional view of an example of the channel structure CH included in the semiconductor device 10 shown.

[0034] Reference Figure 1 and Figure 2 The semiconductor device 10 according to an embodiment may include a cell region 100 comprising a memory cell structure and a circuit region 200 comprising a peripheral circuit structure configured to control the operation of the memory cell structure. For example, the circuit region 200 and the cell region 100 may be respectively connected to... Figure 23 The electronic system 1000 shown includes a semiconductor device 1100, with corresponding first structure 1100F and second structure 1100S. For example, the circuit region 200 and the cell region 100 may each include... Figure 25 The semiconductor chip 2200 shown is a portion of the first structure 3100 and the second structure 3200.

[0035] Circuit region 200 may include peripheral circuit structures on the first substrate 210, and cell region 100 may include a gate stack structure 120 and a channel structure CH serving as a memory cell structure on the second substrate 110. Circuit region 200 may include a first wiring portion 280, and cell region 100 may include a second wiring portion 180 electrically connected to the memory cell structure.

[0036] In this embodiment, cell region 100 may be disposed on circuit region 200. Therefore, it is not necessary to separately ensure the area corresponding to circuit region 200 from cell region 100. Thus, the area of ​​semiconductor device 10 can be reduced. However, the embodiment is not limited to this, and circuit region 200 may be disposed close to cell region 100. Various other modifications are possible.

[0037] The circuit region 200 may include a first substrate 210, and circuit elements 220 and a first wiring portion 280 on the first substrate 210.

[0038] The first substrate 210 may be a semiconductor substrate comprising a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate comprising or formed of a semiconductor material, or it may be a semiconductor substrate with a semiconductor layer located on a base substrate. For example, the first substrate 210 may include monocrystalline silicon or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc., or may be formed from monocrystalline silicon or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc.

[0039] The circuit element 220 on the first substrate 210 may include any of a variety of circuit elements that control the operation of the memory cell structure in the control unit region 100. For example, the circuit element 220 may constitute a decoder circuit 1110 (see reference 1110). Figure 23 Page buffer 1120 (reference) Figure 23 ), Logic circuit 1130 (reference) Figure 23 The peripheral circuit structure of ) etc.

[0040] Circuit element 220 may include, for example, multiple transistors, but the embodiments are not limited thereto. For example, circuit element 220 may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, inductors, etc.

[0041] A first wiring portion 280 on the first substrate 210 can be electrically connected to a circuit element 220. In an embodiment, the first wiring portion 280 may include a plurality of wiring layers 286 spaced apart from each other, with an interlayer insulating layer 282 inserted therebetween, and the plurality of wiring layers 286 electrically connected via contact vias 284 to form a desired path. The wiring layers 286 or contact vias 284 may include any of a variety of conductive materials, and the interlayer insulating layer 282 may include any of a variety of insulating materials. For example, the interlayer insulating layer 282 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, or be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0042] Cell region 100 may include cell array region 102 and connection region 104. Gate stack structure 120 and channel structure CH may be located on second substrate 110 in cell array region 102. Structures connecting gate stack structure 120 and / or channel structure CH in cell array region 102 to circuit region 200 or external circuitry may be located in cell array region 102 and / or connection region 104.

[0043] In an embodiment, the second substrate 110 may include a semiconductor layer comprising a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate comprising or formed of a semiconductor material, or it may be a semiconductor substrate with the semiconductor layer located on a base substrate. For example, the second substrate 110 may include silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc., or be formed of silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. A p-type dopant or an n-type dopant may be doped into the semiconductor layer included in the second substrate 110. For example, a p-type dopant may include boron (B), gallium (Ga), etc., or an n-type dopant may include phosphorus (P), arsenic (As), etc. However, the embodiments are not limited to the material of the second substrate 110, the conductivity type of the dopant doped into the semiconductor layer, etc.

[0044] In the cell array region 102, a gate stack structure 120 and a channel structure CH can be disposed. The gate stack structure 120 may include an interlayer insulating layer 132 and a gate electrode 130 alternately stacked on a first surface (e.g., the front surface or the upper surface) of the second substrate 110. The channel structure CH may extend in a direction intersecting (e.g., perpendicular to) the second substrate 110 (the Z-axis direction in the figures) while penetrating the gate stack structure 120. In this document, the X-axis direction and the Y-axis direction may be perpendicular to each other and parallel to the upper surface of the second substrate 110, and may be referred to as the horizontal direction. The Z-axis direction may be perpendicular to both the X-axis direction and the Y-axis direction, and may be referred to as the vertical direction. The Z-axis direction may be perpendicular to the upper surface of the second substrate 110.

[0045] In an embodiment, horizontal conductive layers 112 and 114 may be disposed in the cell array region 102 between the second substrate 110 and the gate stack structure 120. Horizontal conductive layers 112 and 114 may electrically connect (e.g., directly connect) the channel structure CH and the second substrate 110. Horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 and / or a second horizontal conductive layer 114 sequentially stacked on the second substrate 110. The first horizontal conductive layer 112 may serve as a partial portion of the common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may be used together with the second substrate 110 as a common source line.

[0046] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may comprise a semiconductor material (e.g., polysilicon). For example, the first horizontal conductive layer 112 may comprise a polysilicon layer containing dopants. Embodiments are not limited thereto. The second horizontal conductive layer 114 may comprise a material different from that of the first horizontal conductive layer 112 (e.g., an insulating material), or the second horizontal conductive layer 114 may be omitted.

[0047] A gate stack structure 120, in which the interlayer insulating layer 132 and the gate electrode 130 are stacked alternately, can be disposed on a second substrate 110 (e.g., a first horizontal conductive layer 112 and a second horizontal conductive layer 114 disposed on the second substrate 110).

[0048] The gate electrode 130 may comprise any of a variety of conductive materials. For example, the gate electrode 130 may comprise a metallic material (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), polycrystalline silicon, a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or a combination thereof, or may be formed of a metallic material (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), polycrystalline silicon, a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or a combination thereof. Figure 2 As shown in the enlarged portion, a portion of an insulating material or a barrier layer 156 formed of an insulating material (e.g., a first barrier layer 156a) may be disposed outside the gate electrode 130. For example, the first barrier layer 156a may contact the upper surface, lower surface, and side surface of the gate electrode 130. The interlayer insulating layer 132 may comprise any of a variety of insulating materials. For example, the interlayer insulating layer 132 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than silicon oxide, or combinations thereof, or may be formed of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than silicon oxide, or combinations thereof.

[0049] In an embodiment, a channel structure CH may be provided. The channel structure CH may extend in a direction intersecting the second substrate 110 (e.g., a direction perpendicular to the second substrate 110 or the Z-axis direction in the figures) to penetrate the gate stack structure 120.

[0050] The channel structure CH may include a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may also include a core insulating layer 142 located inside the channel layer 140. In some embodiments, the core insulating layer 142 may be omitted. The channel structure CH may also include channel pads 144 on the channel layer 140 and / or the core insulating layer 142. The channel pads 144 may contact the upper surface of the core insulating layer 142. The gate dielectric layer 150 between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a barrier layer 156 sequentially located on the channel layer 140. The tunneling layer 152 can contact the side and bottom surfaces of the channel layer 140, the charge storage layer 154 can contact the side and bottom surfaces of the tunneling layer 152, and the barrier layer 156 can contact the side and bottom surfaces of the charge storage layer 154.

[0051] Each channel structure CH forms a memory cell string, and multiple channel structures CH can be spaced apart from each other, forming rows and columns in a planar view. For example, multiple channel structures CH can be configured to form any of various shapes in a planar view, such as a grid shape, a zigzag shape, etc. The channel structure CH can have a columnar shape. For example, in a cross-sectional view, the channel structure CH can have sloping side surfaces, such that the width of the channel structure CH decreases towards the second substrate 110 due to a high aspect ratio. However, the embodiments are not limited to this, and the arrangement, structure, shape, etc., of the channel structures CH can be modified in various ways.

[0052] The channel layer 140 may include a semiconductor material (e.g., polysilicon). The core insulating layer 142 may include any of a variety of insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, or may be formed of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0053] The tunneling layer 152 may include an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) capable of allowing charge tunneling. The charge storage layer 154 may serve as a data storage region, and may include polysilicon, silicon nitride, etc. The barrier layer 156 may include an insulating material capable of preventing unwanted charge flow into the gate electrode 130. The barrier layer 156 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In an embodiment, the barrier layer 156 may include a first barrier layer 156a comprising a portion extending horizontally on the gate electrode 130, and a second barrier layer 156b extending vertically between the first barrier layer 156a and the charge storage layer 154.

[0054] However, the materials, stacking structure, etc. of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150 can be modified in different ways, and the embodiments are not limited thereto.

[0055] The channel pad 144 may cover the upper surface of the core insulating layer 142 and is configured to be electrically connected to the channel layer 140. For example, the channel pad 144 may contact the upper surface of the core insulating layer 142. The channel pad 144 may include a conductive material (e.g., polysilicon doped with dopants), but the embodiments are not limited thereto.

[0056] In an embodiment, the gate stack structure 120 may include a plurality of gate stack portions 121 and 122 stacked sequentially. Each of the plurality of gate stack portions 121 and 122 may include at least a portion of an interlayer insulating layer 132 and a gate electrode 130 stacked alternately with each other. Thus, the number of stacked gate electrodes 130 can be increased, and therefore the number of memory cells can be increased in a stable structure. Figure 1 As an example, a gate stack structure 120 is shown including a first gate stack portion 121 and a second gate stack portion 122. In some embodiments, the gate stack structure 120 may include one gate stack portion or three or more gate stack portions.

[0057] When multiple gate stack portions 121 and 122 are provided as described above, the channel structure CH may include multiple channel portions CH1 and CH2 that pass through the multiple gate stack portions 121 and 122, respectively. For example, channel portion CH1 may penetrate gate stack portion 121, and channel portion CH2 may penetrate gate stack portion 122. The multiple channel portions CH1 and CH2 may be connected to each other. In a cross-sectional view, each of the multiple channel portions CH1 and CH2 may have a sloping side surface, such that the width of each of the multiple channel portions CH1 and CH2 decreases towards the second substrate 110 due to a high aspect ratio. Bending portions due to the difference in width of the multiple channel portions CH1 and CH2 may be provided at the connection portions of the multiple channel portions CH1 and CH2. In some embodiments, the multiple channel portions CH1 and CH2 may have continuously extending sloping side surfaces without bending portions. Figure 2In the illustration, as an example, each of the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of a plurality of channel portions CH1 and CH2 extends continuously to have an integral structure. In some embodiments, the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of the plurality of channel portions CH1 and CH2 may be formed separately and electrically connected to each other. In some embodiments, individual channel pads may be additionally provided at the connection portions of the plurality of channel portions CH1 and CH2. Thus, the embodiments are not limited to the shape of the plurality of channel portions CH1 and CH2.

[0058] In an embodiment, the gate stack structure 120 may be divided into multiple portions by a separation structure 146 in a plan view. The separation structure 146 may extend in a direction intersecting (e.g., perpendicular to) the second substrate 110 (e.g., the Z-axis direction in the figures) to pass through or penetrate the gate stack structure 120. In an example embodiment, the bottom surface of the separation structure 146 may contact the upper surface of the second substrate 110. An upper separation region 148 may be disposed at the upper portion of the gate stack structure 120. For example, the upper separation region 148 may extend through the upper interlayer insulating layer 132 and the gate electrode 130. In a plan view, the separation structure 146 and / or the upper separation region 148 may extend longitudinally in the extension direction of the gate electrode 130 (the X-axis direction in the figures). Multiple separation structures 146 and / or multiple upper separation regions 148 may be spaced apart from each other at predetermined intervals in a direction intersecting the extension direction of the gate electrode 130 (the Y-axis direction in the figures).

[0059] The separation structure 146 and / or the upper separation region 148 may comprise, or be formed of, any of a variety of insulating materials. For example, the separation structure 146 or the upper separation region 148 may comprise, or be formed of, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiments are not limited thereto, and the structure, shape, material, etc., of the separation structure 146 or the upper separation region 148 may be modified in various ways.

[0060] The connection region 104 and the second wiring portion 180 can be configured to connect the gate stack structure 120 and the channel structure CH in the cell array region 102 to the circuit region 200 or external circuitry. The connection region 104 can be located at the periphery of the cell array region 102, and a portion of the second wiring portion 180 can be located within the connection region 104.

[0061] In an embodiment, the second wiring portion 180 may include components that electrically connect the gate electrode 130, the channel structure CH, the horizontal conductive layers 112 and 114, and / or the second substrate 110 to the circuit region 200 or external circuitry. For example, the second wiring portion 180 may include a bit line 182, a gate contact portion 190, a source contact portion 186, an input / output connection wiring 188, a contact via 180a, and a connection wiring 180b. The contact via 180a may be connected to the bit line 182, the gate contact portion 190, the source contact portion 186, and / or the input / output connection wiring 188. For example, the contact via 180a may contact the bit line 182, the gate contact portion 190, the source contact portion 186, and / or the input / output connection wiring 188. Connection wiring 180b can be electrically connected to bit line 182, gate contact portion 190, source contact portion 186, input / output connection wiring 188 and / or contact via 180a.

[0062] Bit line 182 may extend longitudinally in a direction intersecting the extension direction of gate electrode 130 (X-axis direction in the figure) (Y-axis direction in the figure). Bit line 182 may be electrically connected to channel structure CH (e.g., channel pad 144) via contact via 180a (e.g., bit line contact via through or through interlayer insulating layer 132).

[0063] In the connection region 104, multiple gate contact portions 190 may pass through or penetrate the gate stack structure 120 to be electrically connected to multiple gate electrodes 130, respectively. In an embodiment, the gate stack structure 120 may be disposed at least in the connection region 104. More specifically, the gate stack structure 120 may be disposed in both the cell array region 102 and the connection region 104. For example, in the connection region 104, the extension lengths of the multiple gate electrodes 130 may be substantially the same. Substantially the same may refer to differences within process tolerances (e.g., less than 10%).

[0064] As described above, in the embodiments, portions of the gate stack structure 120 that are partially removed to electrically connect the gate electrode 130 and the gate contact portion 190 may be omitted (e.g., portions with a stepped shape). The connection structure between the plurality of gate contact portions 190 and the plurality of gate electrodes 130 will be described in more detail.

[0065] In connection region 104, source contact portion 186 may pass through or penetrate cell insulating layer 132a and be electrically connected to horizontal conductive layers 112 and 114 and / or second substrate 110. For example, horizontal conductive layers 112 and 114 may contact the side surface of source contact portion 186, and second substrate 110 may contact the side surface and bottom surface of source contact portion 186. In an example embodiment, the lower surface of source contact portion 186 may be lower than the upper surface of second substrate 110. Cell insulating layer 132a may contact the side surface of source contact portion 186. Input / output connection wiring 188 may pass through or penetrate gate stack structure 120 or be disposed outside gate stack structure 120 to be electrically connected to first wiring portion 280. Cell insulating layer 132a may be an insulating layer disposed on, around, and / or near gate stack structure 120. For example, the unit insulating layer 132a may contact the end surfaces of the interlayer insulating layer 132 and the gate electrode 130, the source contact portion 186 and the side surfaces of the input / output connection wiring 188, the upper and side surfaces of the horizontal conductive layers 112 and 114, and the upper surface of the second substrate 110.

[0066] exist Figure 1 In the illustration, each of the source contact portion 186 and / or the input / output connection wiring 188 is shown to have a sloping side surface, such that the width of the source contact portion 186 and / or the input / output connection wiring 188 decreases toward the second substrate 110 due to a high aspect ratio, and the bent portion is provided at the connection portion of the plurality of gate stack portions 121 and 122 in the cross-sectional view. However, the embodiment is not limited thereto. In some embodiments, the source contact portion 186 and / or the input / output connection wiring 188 may not include the bent portion at the connection portion of the plurality of gate stack portions 121 and 122. Various other modifications are possible.

[0067] For clear understanding and simple explanation, in Figure 1 In the example shown, the connection wiring 180b is a single layer on the same plane as the bit line 182, and an additional insulating layer 132b is located on the portion other than the connection wiring 180b. However, the embodiments are not limited to this. In some embodiments, for electrical connection with the bit line 182, the gate contact portion 190, the source contact portion 186, and / or the input / output connection wiring 188, the connection wiring 180b may include multiple wiring layers and may also include contact vias.

[0068] Through the electrical connection between the second wiring portion 180 and the first wiring portion 280, the bit line 182, which is connected to the channel structure CH, the gate electrode 130, the horizontal conductive layers 112 and 114 and / or the second substrate 110, can be electrically connected to the circuit element 220 of the circuit region 200.

[0069] Reference Figures 3 to 6 as well as Figure 1 The connection structure of the multiple gate contact portions 190 and the multiple gate electrodes 130 will be described in detail.

[0070] Figure 3 It is shown Figure 1 A cross-sectional view of the connection region 104 of the cell region 100 included in the semiconductor device 10 shown. Figure 4 It is shown Figure 3 A cross-sectional view of part A. Figure 5 It is shown Figure 3 A cross-sectional view of part B. Figure 6 It is shown Figure 3 A cross-sectional view of part C.

[0071] Reference Figure 1 and Figures 3 to 6 In the connection region 104, a plurality of gate contact portions 190 may pass through or penetrate a portion of the gate stack structure 120 and may be electrically connected to a plurality of gate electrodes 130 (e.g., in contact with a plurality of gate electrodes 130).

[0072] In an embodiment, each gate contact portion 190 may extend downward from the upper surface of the gate stack structure 120 to the lower surface of the gate stack structure 120, and may pass through or penetrate a portion of the gate stack structure 120 in a direction intersecting the second substrate 110 (e.g., a vertical direction perpendicular to the second substrate 110 or the Z-axis direction in the figures). The upper surface of the gate stack structure 120 may refer to the surface adjacent to the second wiring portion 180 in the vertical direction, and the lower surface of the gate stack structure 120 may refer to the surface opposite to or adjacent to the second wiring portion 180 in the vertical direction. Unless otherwise described, in the specification, with respect to cell region 100, upper or upper surface may refer to the portion or surface adjacent to the second wiring portion 180, and lower or lower surface may refer to the portion or surface opposite to or adjacent to the second wiring portion 180 or the second substrate 110.

[0073] Each gate contact portion 190 may pass through or penetrate a portion of the gate stack structure 120 to have a depth reaching the connecting gate electrode 130c among the plurality of gate electrodes 130. The plurality of gate contacts 190 may be respectively connected to the plurality of gate electrodes 130. In the vertical direction (Z-axis direction in the figures), the plurality of gate electrodes 130 may be disposed at different heights, and the plurality of gate contacts 190 may each have different depths to reach the plurality of gate electrodes 130.

[0074] For example, the first gate contact portion 1901 may be electrically connected to the first gate electrode 1301. The nth gate contact portion may be electrically connected to the nth gate electrode, and the kth gate contact portion may be electrically connected to the kth gate electrode. n may be a natural number greater than 1 and less than k, and k may be the total number of the plurality of gate electrodes 130 or the total number of the plurality of gate contact portions 190.

[0075] In the accompanying drawings, gate electrode 130 is shown as an example including first gate electrode 1301 to sixteenth gate electrode 1316. In this case, first gate contact portion 1901 to fifth gate contact portion 1905 can be electrically connected to first gate electrode 1301 to fifth gate electrode 1305, respectively. Sixth gate contact portion to twelfth gate contact portion (not shown) can be electrically connected to sixth gate electrode 1306 to twelfth gate electrode 1312, respectively. Thirteenth gate contact portion 1913 to sixteenth gate contact portion 1916 can be electrically connected to thirteenth gate electrode 1313 to sixteenth gate electrode 1316, respectively. As described above, a plurality of gate contact portions 190 can be electrically connected to a plurality of gate electrodes 130, respectively.

[0076] For clarity and simplicity, the accompanying drawings illustrate, by way of example, that the depth of the plurality of gate contact portions 190 can increase sequentially away from the cell array region 102, but the embodiment is not limited thereto. The arrangement of the plurality of gate contact portions 190 can be modified in various ways.

[0077] Based on a gate contact portion 190, a plurality of gate electrodes 130 may include a connecting gate electrode 130c electrically connected to the gate contact portion 190, and may include one or more penetrating gate electrodes 130p and / or one or more remaining gate electrodes 130r. A penetrating gate electrode 130p may be one or more gate electrodes 130 that are penetrated by the gate contact portion 190 and electrically insulated from the gate contact portion 190 through a side insulating layer 190i. A penetrating gate electrode 130p may be a gate electrode 130 disposed on or above the connecting gate electrode 130c. A remaining gate electrode 130r may be one or more gate electrodes 130 that are not penetrated by the gate contact portion 190 and electrically insulated from the gate contact portion 190. A remaining gate electrode 130r may be a gate electrode 130 below the connecting gate electrode 130c.

[0078] In the first gate contact portion 1901, the first gate electrode 1301 may be a connecting gate electrode 130c, and the gate electrode 130 below the connecting gate electrode 130c may be the remaining gate electrode 130r. Because the first gate contact portion 1901 does not have a gate electrode 130 above the connecting gate electrode 130c, there is no penetrating gate electrode 130p corresponding to the first gate contact portion 1901. In the nth gate contact portion, the nth gate electrode may be a connecting gate electrode 130c, one or more gate electrodes 130 on or above the connecting gate electrode 130c may be penetrating gate electrodes 130p, and one or more gate electrodes 130 below the connecting gate electrode 130c may be the remaining gate electrode 130r. In the kth gate contact portion ( Figure 3 In the sixteenth gate contact portion 1916), the kth gate electrode ( Figure 3 The sixteenth gate electrode 1316 in the diagram can be a connecting gate electrode 130c, and the gate electrode 130 on or above the connecting gate electrode 130c can be a penetrating gate electrode 130p. Because the kth gate contact portion does not have a gate electrode 130 below the connecting gate electrode 130c, there is no remaining gate electrode 130r corresponding to the kth gate contact portion.

[0079] In one embodiment, each gate contact portion 190 may be electrically connected to the upper surface of the connecting gate electrode 130c (e.g., in contact with the upper surface of the connecting gate electrode 130c). However, the embodiment is not limited thereto. Each gate contact portion 190 may be electrically connected to another portion (e.g., a side surface) of the connecting gate electrode 130c (e.g., in contact with another portion (e.g., a side surface) of the connecting gate electrode 130c).

[0080] In an embodiment, each gate contact portion 190 may include a conductive portion 190c and a side insulating layer 190i. The side insulating layer 190i may be disposed between the conductive portion 190c and the gate stack structure 120.

[0081] In each gate contact portion 190, a side insulating layer 190i may be disposed at least between the side surface of the conductive portion 190c and the side surface of the penetrating gate electrode 130p, thereby electrically insulating the conductive portion 190c and the penetrating gate electrode 130p. The side insulating layer 190i may not be disposed on the lower surface of the conductive portion 190c and / or the upper surface of the connecting gate electrode 130c. For example, the side insulating layer 190i may not be disposed between the upper surface of the connecting gate electrode 130c and the lower surface of the gate contact portion 190. For example, the lower surface of the side insulating layer 190i may contact the connecting gate electrode 130c, or it may be disposed between the upper and lower surfaces of the interlayer insulating layer 132 disposed on the connecting gate electrode 130c.

[0082] Thus, the side insulating layer 190i can surround the entire portion of the side surface of the gate contact portion 190 corresponding to the penetrated gate electrode 130p, and stably insulate between the gate contact portion 190 and the penetrated gate electrode 130p. However, the embodiment is not limited to this, and the position of the side insulating layer 190i, the connection position of the gate contact portion 190 and the connection position of the gate electrode 130c can be modified differently.

[0083] For example, the conductive portion 190c may have a columnar shape (e.g., a columnar shape with a planar shape of a circle or polygon). The side insulating layer 190i may have a planar shape such as an annular shape, ring shape, frame shape, etc., surrounding the conductive portion 190c.

[0084] In the accompanying drawings, as an example, a cross-sectional view shows that the gate contact portion 190 or the conductive portion 190c may have a sloping side surface, such that the width of the gate contact portion 190 or the conductive portion 190c decreases toward the second substrate 110 due to a high aspect ratio. However, the embodiments are not limited to this, and the shape, structure, etc., of the gate contact portion 190 or the conductive portion 190c may be modified in various ways.

[0085] In an embodiment, the gate contact portion 190 inside the via PH can be electrically connected to the upper portion of the connecting gate electrode 130c. For example, multiple via PHs may be included. Each of the multiple via PHs can pass through or penetrate the gate stack structure 120, and the multiple via PHs can be spaced apart from each other while the gate stack structure 120 is inserted therebetween. A gate contact portion 190 can be disposed in a via PH. The lower surface of the conductive portion 190c of a gate contact portion 190 in a via PH can be electrically connected to the upper surface of the connecting gate electrode 130c (e.g., in contact with the upper surface of the connecting gate electrode 130c). For example, multiple gate contact portions 190 can be disposed in multiple spaced-apart via PHs, such that the multiple gate contact portions 190 and the multiple via PHs correspond one-to-one. In an embodiment, the via PH can have any of a variety of planar shapes such as circular, polygonal, elliptical, etc., and the embodiment is not limited to the planar shape of the via PH.

[0086] Therefore, the pad region (e.g., pad insulating layer) through which multiple gate contact portions 190 pass together, the additional insulating layer (e.g., pad insulating layer) disposed between the multiple gate contact portions 190 other than the interlayer insulating layer 132, or the portion of the gate stack structure 120 used for electrical connection of the gate contact portions 190 (e.g., the portion with a stepped shape) can be removed. For example, without the pad region or pad insulating layer, the multiple gate contact portions 190 can be electrically connected to the multiple gate electrodes 130 separately or individually. Therefore, the process of electrically connecting the gate contact portions 190 and the gate electrodes 130 can be simplified, and the area of ​​the connection region 104 can be reduced.

[0087] On the other hand, in a comparative example including a pad region, the process involves etching a portion of the gate stack structure (e.g., forming a portion with a stepped shape), forming a pad insulating layer covering the stepped portion of the gate stack structure, and electrically connecting multiple gate contact portions that pass through or penetrate a pad insulating layer together to multiple gate electrodes. Therefore, the processes for forming the pad region and forming the gate contact portions can be complex. In a pad region or pad insulating layer where multiple gate contact portions pass through together, it is necessary to ensure the width between the multiple gate contact portions to prevent misalignment. Therefore, the area of ​​the connection region may need to be increased.

[0088] In an embodiment, the plurality of gate contact portions 190 may include a first contact portion 192 and a second contact portion 196. The side insulating layer 190i of the first contact portion 192 and the side insulating layer 190i of the second contact portion 196 may have different shapes or structures. More specifically, the first contact portion 192 may include a first conductive portion 192c and a first side insulating layer 192i disposed between the gate stack structure 120 and the first conductive portion 192c. The second contact portion 196 may include a second conductive portion 196c and a second side insulating layer 196i disposed between the gate stack structure 120 and the second conductive portion 196c. The second side insulating layer 196i may have a different shape or structure than the first side insulating layer 192i.

[0089] like Figure 4 and Figure 5 As shown, the first conductive portion 192c of the first contact portion 192 may include or be formed of a conductive material, and may fill at least a portion of the via PH in the portion other than the first side insulating layer 192i. For example, the first conductive portion 192c may include or be formed of tungsten (W), copper (Cu), aluminum (Al), etc., or may also include a diffusion barrier layer. However, the embodiments are not limited to the material of the first conductive portion 192c.

[0090] The first side insulating layer 192i of the first contact portion 192 may include a first portion R1 and a second portion R2, wherein the thickness of the second portion R2 is less than the thickness of the first portion R1. The thickness T1 of the first portion R1 or the thickness T2 of the second portion R2 can be measured in a direction perpendicular to the side surface of the first side insulating layer 192i. For example, the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2 can be measured in a direction parallel to the upper surface of the second substrate 110. The thickness T1 of the first portion R1 may refer to the average thickness of the first portion R1 or the thickness of the portion of the first portion R1 adjacent to the second portion R2. The thickness T2 of the second portion R2 may refer to the average thickness of the second portion R2 or the thickness of the portion of the second portion R2 adjacent to the first portion R1.

[0091] In the vertical direction (Z-axis direction in the attached figure), the first portion R1 can be located at the upper part of the first contact portion 192 and can be spaced apart from the lower surface of the first contact portion 192. For example, the upper surface of the first portion R1 can be set adjacent to the upper surface of the first contact portion 192. For example, the upper surface of the first portion R1 can be located in the same plane as the upper surface of the first contact portion 192. The lower surface of the first portion R1 can be spaced apart from the lower surface of the first contact portion 192. The lower surface of the first portion R1 can be spaced apart from the lower surface of the first contact portion 192, while a portion corresponding to at least one penetrating gate electrode 130p (e.g., multiple penetrating gate electrodes 130p) is inserted therebetween.

[0092] In the vertical direction (Z-axis direction in the attached figure), the second portion R2 may be located below or below the first portion R1. The second portion R2 may include one or more portions corresponding to one of the plurality of gate electrodes 130.

[0093] In an embodiment, the first side insulating layer 192i may include a first layer 190a and a second layer 190b. The first layer 190a may be disposed in the first portion R1, and the second layer 190b may be disposed on the inner surface of the first layer 190a in the first portion R1 and the second portion R2.

[0094] More specifically, the first layer 190a may be disposed in the first portion R1 on the side surface of the gate stack structure 120 (e.g., in contact with the side surface of the gate stack structure 120). The second layer 190b may be disposed in the first portion R1 on the inner surface of the first layer 190a (e.g., in contact with the inner surface of the first layer 190a), and may be disposed in the second portion R2 on the side surface of the gate stack structure 120 (e.g., in contact with the side surface of the gate stack structure 120). However, the embodiments are not limited thereto. In some embodiments, an additional layer may be disposed between two adjacent portions (the first layer 190a and the second layer 190b) of the gate stack structure 120.

[0095] The inner surface of the first side insulating layer 192i (e.g., the second layer 190b) may contact the outer surface of the first conductive portion 192c. However, the embodiments are not limited thereto, and an additional layer may be disposed between the inner surface of the first side insulating layer 192i (e.g., the second layer 190b) and the outer surface of the first conductive portion 192c.

[0096] As described above, the first layer 190a and the second layer 190b can be disposed together in the first part R1, and the second layer 190b can be disposed separately in the second part R2 without the first layer 190a. For example, the first part R1 and the second part R2 can have different stacking structures, and the first part R1 and the second part R2 can have different thicknesses.

[0097] The inner surface of the first side insulating layer 192i (e.g., the second layer 190b) may have an inclined surface that is tilted relative to the vertical direction (Z-axis direction in the figures) of the semiconductor device 10 without any stepped or bent portions. The outer surface of the first side insulating layer 192i (e.g., the first layer 190a and the second layer 190b) may have an inclined surface that is tilted relative to the vertical direction, and the step S may be provided between the first portion R1 and the second portion R2. However, the embodiments are not limited thereto. In some embodiments, the inner surface of the first side insulating layer 192i (e.g., the second layer 190b) may have a vertical surface that is parallel to the vertical direction (Z-axis direction in the figures) of the semiconductor device 10 without any stepped or bent portions. The outer surface of the first side insulating layer 192i (e.g., the first layer 190a and the second layer 190b) may have a vertical surface that is parallel to the vertical direction, and the step S may be provided between the first portion R1 and the second portion R2.

[0098] The first layer 190a may be an insulating layer configured to protect the stacked structure 120s (refer to) for the gate stacked structure 120 in a subsequent partial etching process (e.g., fourth partial etching process E4). Figure 7 For example, the first layer 190a can be an insulating layer configured to protect the stacked structure 120s in subsequent partial etching processes using a hard mask. The first layer 190a can be referred to as a protective layer, a cover layer, a pad layer, a first insulating layer, etc. By using the first layer 190a to protect the stacked structure 120s, the depth of the vias PH formed in the subsequent partial etching processes can be increased, and the time and cost of forming the vias PH can be reduced. This will be described in more detail in the method of manufacturing the semiconductor device 10.

[0099] The second layer 190b can be an insulating layer formed on the multiple vias PH after a process for forming multiple vias PH is performed to electrically insulate the penetrating gate electrode 130p and the first conductive portion 192c. The second layer 190b can be referred to as an electrical insulating layer, a second insulating layer, etc.

[0100] When the first layer 190a and the second layer 190b may comprise different materials, the boundary between the first layer 190a and the second layer 190b can be seen or confirmed. Even when the first layer 190a and the second layer 190b comprise the same material, the boundary between the first layer 190a and the second layer 190b can be seen or confirmed through the manufacturing process. For example, the boundary between the first layer 190a and the second layer 190b can be seen or confirmed when the first layer 190a and the second layer 190b are formed by different processes and have different compositions or properties, or when the properties of the inner surface of the first layer 190a change over time between the processes forming the first layer 190a and the second layer 190b. When the first layer 190a and the second layer 190b contain the same material and there may be difficulty in confirming the boundary between the first layer 190a and the second layer 190b, the position of the first layer 190a and the second layer 190b can be determined or anticipated by the difference in thickness between the first part R1 and the second part R2 or by the step S between the first part R1 and the second part R2.

[0101] For example, the distance between the inner surface of the gate electrode 130 corresponding to the first portion R1 and the first conductive portion 192c can be greater than the distance between the inner surface of the other gate electrode 130 corresponding to the second portion R2 and the first conductive portion 192c. The distance between the inner surface of the gate electrode 130 and the first conductive portion 192c can be the distance between the inner surface of the gate electrode 130 adjacent to the first conductive portion 192c and the outer surface of the first conductive portion 192c in the extending direction of the gate electrode 130. When multiple gate electrodes 130 correspond to the first portion R1 and multiple gate electrodes 130 correspond to the second portion R2, the multiple gate electrodes 130 corresponding to the first portion R1 can have an inclined inner surface parallel to the inclined outer surface of the first conductive portion 192c, and the multiple gate electrodes 130 corresponding to the second portion R2 can have an inclined inner surface parallel to the inclined outer surface of the first conductive portion 192c. The multiple gate electrodes 130 corresponding to the first part R1 and the multiple gate electrodes 130 corresponding to the second part R2 can be spaced apart from each other by the step S.

[0102] In this embodiment, the first layer 190a and / or the second layer 190b may comprise any of a variety of insulating materials. For example, the first layer 190a and the second layer 190b may comprise the same material, or the first layer 190a and the second layer 190b may comprise different materials from each other.

[0103] For example, the first layer 190a may include an oxide (e.g., silicon oxide), an oxide oxynitride (e.g., silicon oxynitride), a low-dielectric-constant material having a dielectric constant lower than silicon oxide, or a combination thereof, or may be formed of an oxide (e.g., silicon oxide), an oxide oxynitride (e.g., silicon oxynitride), a low-dielectric-constant material having a dielectric constant lower than silicon oxide, or a combination thereof. The first layer 190a may include a single layer or multiple layers. For example, the second layer 190b may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), a low-dielectric-constant material having a dielectric constant lower than silicon oxide, or a combination thereof, or may be formed of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), a low-dielectric-constant material having a dielectric constant lower than silicon oxide, or a combination thereof. The second layer 190b may include a single layer or multiple layers.

[0104] In this embodiment, the difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a can be 0.5 nm or greater (e.g., 1 nm or greater) in the direction perpendicular to the side surface of the first side insulating layer 192i. Thus, the first layer 190a can have a thickness of 0.5 nm or greater (e.g., 1 nm or greater) to stably protect the stacked structure 120s. In this document, the height of the step S can be the distance between the outer surface of the second layer 190b and the outer surface of the first layer 190a in the horizontal direction (e.g., parallel to the upper surface of the second substrate 110).

[0105] For example, in the direction perpendicular to the side surface of the first side insulating layer 192i, the difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a can be 20 nm or less (e.g., 10 nm or less, e.g., 5 nm or less). As described above, the thickness of the first layer 190a can be reduced, and the area or volume of the first conductive portion 192c can be sufficiently ensured.

[0106] However, the embodiments are not limited thereto, and the thickness of the first layer 190a may be less than 0.5 nm (e.g., 1 nm) or greater than 20 nm (e.g., 10 nm, 5 nm as an example).

[0107] In embodiments, the ratio (T2 / T1) of the thickness T2 of the second portion R2 to the thickness T1 of the first portion R1 in the direction perpendicular to the side surface of the first side insulating layer 192i can be in the range of 0.5 to 1. In some embodiments, the difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a in the direction perpendicular to the side surface of the first side insulating layer 192i can be the same as or less than the thickness T2 of the second portion R2 or the thickness of the second layer 190b. The first layer 190a may have a relatively small thickness configured to protect the stacked structure 120s in subsequent partial etching processes, and the second layer 190b may have a relatively large thickness to enhance the electrical insulation properties between the gate stacked structure 120 and the first conductive portion 192c. However, embodiments are not limited thereto. In some embodiments, in the direction perpendicular to the side surface of the first side insulating layer 192i, the ratio (T2 / T1) of the thickness T2 of the second portion R2 to the thickness T1 of the first portion R1 may be less than 0.5. In some embodiments, the difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a may be greater than the thickness T2 of the second portion R2 or the thickness of the second layer 190b.

[0108] In embodiments, the difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a in the direction perpendicular to the side surface of the first side insulating layer 192i may be less than the thickness of the interlayer insulating layer 132 in the vertical direction (Z-axis direction in the figures) or the thickness of the gate electrode 130 in the vertical direction (Z-axis direction in the figures). The first layer 190a may have a relatively small thickness configured to protect the stacked structure 120s in subsequent partial etching processes. However, embodiments are not limited thereto. In some embodiments, the difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a may be the same as or greater than the thickness of the interlayer insulating layer 132 or the thickness of the gate electrode 130.

[0109] However, the embodiments are not limited to this, and the difference TD between the thickness T1 of the first part R1 and the thickness T2 of the second part R2, the height of the step S, the thickness of the first layer 190a, the thickness of the second layer 190b, etc., can be modified differently.

[0110] For clarity, the accompanying drawings illustrate, by way of example, portions of the first layer 190a and the second layer 190b sequentially disposed on the upper surface of the gate stack structure 120. Furthermore, the boundaries between the upper surfaces of the gate stack structure 120 and portions of the first layer 190a and the second layer 190b located on the upper surface of the gate stack structure 120 are shown. However, the embodiments are not limited thereto. In some embodiments, portions of the first layer 190a and / or the second layer 190b located on the upper surface of the gate stack structure 120 may be removed. In some embodiments, the boundaries of portions of the first layer 190a and / or the second layer 190b located on the upper surface of the gate stack structure 120 may not be visible or identifiable in the final structure.

[0111] like Figure 6As shown, the second conductive portion 196c of the second contact portion 196 may include or be formed of a conductive material, and may fill at least a partial portion of the via PH in the portion other than the second side insulating layer 196i. For example, the second conductive portion 196c may include tungsten (W), copper (Cu), aluminum (Al), etc., or be formed of tungsten (W), copper (Cu), aluminum (Al), etc., or may also include a diffusion barrier layer. The second conductive portion 196c may include the same conductive material as the first conductive portion 192c, or be formed of the same conductive material as the first conductive portion 192c, or the second conductive portion 196c may be formed together with the first conductive portion 192c by the same process as the first conductive portion 192c. However, the embodiments are not limited thereto. In some embodiments, the second conductive portion 196c may include a conductive material different from the material of the first conductive portion 192c, or be formed of a conductive material different from the material of the first conductive portion 192c, or the second conductive portion 196c may be formed by a different process than the first conductive portion 192c. As described above, the embodiments are not limited to the material of the second conductive portion 196c.

[0112] The second side insulating layer 196i of the second contact portion 196 may have a different shape or structure than the first side insulating layer 192i. For example, the second side insulating layer 196i may not include the layers included in the first side insulating layer 192i, the second side insulating layer 196i may include layers not included in the first side insulating layer 192i, or the shape, arrangement, relative position, etc. of the layers included in the first side insulating layer 192i and the second side insulating layer 196i (e.g., the first layer 190a and / or the second layer 190b) may be different from each other.

[0113] For example, the second side insulating layer 196i may include, throughout its entirety, a portion corresponding to the first portion R1 of the first side insulating layer 192i (e.g., a portion having the same material, structure, or thickness as the first portion R1), but may not include the portion corresponding to the second portion R2. For example, in the first side insulating layer 192i and the second side insulating layer 196i, the arrangement or relative position of the first layer 190a and the second layer 190b may differ from each other.

[0114] In an embodiment, in the second side insulating layer 196i, the first layer 190a and the second layer 190b can extend completely and continuously from the upper surface of the second contact portion 196 to the lower surface of the second contact portion 196. For example, in the second side insulating layer 196i, a portion including the first layer 190a and the second layer 190b (i.e., the portion corresponding to the first portion R1) can be completely disposed from the upper surface of the second contact portion 196 to the lower surface of the second contact portion 196.

[0115] More specifically, in the second side insulating layer 196i, the first layer 190a may be disposed on the side surface of the gate stack structure 120, and the second layer 190b may be disposed on the inner side surface of the first layer 190a. For example, the second side insulating layer 196i may not include the portion of the second layer 190b that contacts the side surface of the gate stack structure 120. For example, in the second side insulating layer 196i, the first layer 190a may contact the side surface of the gate stack structure 120, and the second layer 190b may contact the first layer 190a. However, the embodiments are not limited thereto. In some embodiments, in the second side insulating layer 196i, an additional layer may be disposed between the first layer 190a and the side surface of the gate stack structure 120, or an additional layer may be disposed between the second layer 190b and the first layer 190a.

[0116] The inner surface of the second side insulating layer 196i (e.g., the second layer 190b) may contact the outer surface of the second conductive portion 196c. However, the embodiments are not limited to this, and an additional layer may be disposed between the inner surface of the second side insulating layer 196i (e.g., the second layer 190b) and the outer surface of the second conductive portion 196c.

[0117] As described above, the first layer 190a and the second layer 190b can be disposed together in the entire portion of the second side insulating layer 196i, and the entire portion of the second side insulating layer 196i can have the same stacking structure. Therefore, the entire portion of the second side insulating layer 196i can have substantially the same thickness. "Substantially the same thickness" can include thicknesses with differences due to process errors (e.g., a thickness difference of less than 10% or less than 0.5 nm). However, the embodiments are not limited to this.

[0118] The inner surface of the second side insulating layer 196i (e.g., the second layer 190b) may have an inclined surface that is tilted relative to the vertical direction (Z-axis direction in the figures) of the semiconductor device 10 without any stepped or bent portions. The outer surface of the second side insulating layer 196i (e.g., the first layer 190a) may also have an inclined surface that is tilted relative to the vertical direction without any stepped or bent portions. However, the embodiments are not limited thereto. In some embodiments, the inner surface of the second side insulating layer 196i (e.g., the second layer 190b) may have a vertical surface that is parallel to the vertical direction (Z-axis direction in the figures) of the semiconductor device 10 without any stepped or bent portions. The outer surface of the second side insulating layer 196i (e.g., the first layer 190a) may include a vertical surface that is parallel to the vertical direction.

[0119] In an embodiment, the first contact portion 192 may include a plurality of first contact portions 192 with different depths, and the second contact portion 196 may include a plurality of second contact portions 196 with different depths. The plurality of first contact portions 192 may include a first base contact portion 193, and may also include a first additional contact portion 194.

[0120] The process of forming multiple gate contact portions 190 (e.g., multiple first contact portions 192 and multiple second contact portions 196) may include a prior partial etching process (see reference). Figures 8 to 10 ), the process of forming the first layer 190a (refer to Figure 11 ), and subsequent partial etching processes (refer to Figure 13 ) and / or additional etching processes EA (refer to Figure 14 The process for forming the second layer 190b (refer to...) Figure 15 ), and the process for forming the conductive portion 190c (refer to Figure 17 A preliminary partial etching process can be performed before the process of forming the first layer 190a. A subsequent partial etching process can be performed after the process of forming the first layer 190a (see [reference]). Figure 13 ) and / or additional etching processes EA (refer to Figure 14 ).

[0121] In multiple partial etching processes (previous partial etching process and subsequent partial etching process), the interlayer insulating layer 132 and the layers on the interlayer insulating layer 132 can be etched according to binary etching (e.g., sacrificial insulating layer 130s (refer to...)). Figure 7 This is used to form vias PH. For example, in a preceding partial etching process and / or a subsequent partial etching process, 1, 2, 4, ..., 2 can be etched. (m-1) An interlayer insulating layer 132, and a sacrificial insulating layer 130s or more sacrificial insulating layers 130s thereon. m can be a natural number greater than 1, and is the total number of partial etching processes. The m-th partial etching process can be the longest partial etching process with the longest etching depth. The etching depth of the m-th partial etching process can be greater than the etching depth of the other partial etching processes and the additional etching process EA.

[0122] For example, in the first etching process E1, one (i.e., 2) can be etched. 0 (1) interlayer insulating layer 132. In the nth part of the etching process, 2 can be etched. (n-1) An interlayer insulation layer 132 and a sacrificial insulation layer 130s or more sacrificial insulation layers 130s thereon.

[0123] As described above, by repeatedly performing a binary partial etching process, multiple vias (PH) of different depths can be formed with a small number of etching processes. For example, when the binary partial etching process is repeated four times, fifteen vias (PH) of different depths can be formed. For example, when the binary partial etching process is repeated five times, thirty-one vias (PH) of different depths can be formed. For example, when the binary partial etching process is repeated six times, sixty-three vias (PH) of different depths can be formed. Thus, the number of etching processes can be effectively reduced.

[0124] As described above, for clarity and simplicity, the accompanying drawings, as an example, illustrate sixteen gate electrodes 130. In this case, the sixteen vias PH corresponding to the sixteen gate contact portions 190 can be formed by four partial etching processes (i.e., first to fourth partial etching processes E1, E2, E3, and E4) and an additional etching process EA. Hereinafter, it is shown or described by way of example that the first to third partial etching processes E1, E2, and E3 are preceding partial etching processes, and the fourth partial etching process E4 is a subsequent partial etching process. However, the embodiments are not limited thereto. Therefore, the number of gate electrodes 130 can be modified differently, the number of multiple partial etching processes and / or the number of additional etching processes EA can be modified differently, or the number of preceding partial etching processes and / or the number of subsequent partial etching processes can be modified differently.

[0125] The process of forming the first contact portion 192 may include a previous partial etching process, a process of forming the first layer 190a, a subsequent partial etching process and / or an additional etching process EA, a process of forming the second layer 190b, and a process of forming the conductive portion 190c.

[0126] The process of forming the first substrate contact portion 193 in the first contact portion 192 may include a preceding partial etching process, a process of forming the first layer 190a, a subsequent partial etching process, a process of forming the second layer 190b, and a process of forming the conductive portion 190c. For example, referring to... Figure 3 and Figure 4To form the fifteenth gate contact portion 1915 of the first substrate contact portion 193, a first to third partial etching process E1, E2, and E3 of the preceding partial etching process can be performed. A first layer 190a can be formed on the inner surface of the portion formed by the first to third partial etching processes E1, E2, and E3. A fourth partial etching process E4 of the subsequent partial etching process can be performed, and a second layer 190b and a conductive portion 190c can be formed. Thus, a first portion R1, where the first layer 190a and the second layer 190b are disposed together, can be disposed in the portion formed by the first to third partial etching processes E1, E2, and E3, and a second portion R2, where the second layer 190b is disposed, can be disposed in the portion formed by the fourth partial etching process E4.

[0127] The process of forming the first additional contact portion 194 in the first contact portion 192 may include a preceding partial etching process, a process of forming the first layer 190a, a subsequent partial etching process, an additional etching process EA, a process of forming the second layer 190b, and a process of forming the conductive portion 190c. For example, referring to... Figure 3 and Figure 5 To form the sixteenth gate contact portion 1916 of the first additional contact portion 194, a first to third partial etching process E1, E2, and E3 of the preceding partial etching process can be performed. A first layer 190a can be formed on the inner surface of the portion formed by the first to third partial etching processes E1, E2, and E3. A fourth partial etching process E4 and an additional etching process EA can be performed, and a second layer 190b and a conductive portion 190c can be formed. Thus, a first portion R1, where the first layer 190a and the second layer 190b are disposed together, can be disposed in the portion formed by the first to third partial etching processes E1, E2, and E3, and a second portion R2, where the second layer 190b is disposed, can be disposed in the portion formed by the fourth partial etching process E4 and the additional etching process EA.

[0128] The process of forming the second contact portion 196 may include a preceding partial etching process, a process of forming the first layer 190a, a process of forming the second layer 190b, and a process of forming the conductive portion 190c. For example, the process of forming the second contact portion 196 may not include a subsequent partial etching process and / or an additional etching process EA. For example, refer to… Figure 3 and Figure 6To form the fifth gate contact portion 1905 of the second contact portion 196, a first partial etching process E1 and a third partial etching process E3, which are previous partial etching processes, can be performed. A first layer 190a can be formed on the inner surface of the portion formed by the first partial etching process E1 and the third partial etching process E3, and a second layer 190b and a conductive portion 190c can be formed. Therefore, the first layer 190a and the second layer 190b can be provided together in the entire portion formed by the first partial etching process E1 and the third partial etching process E3. Thus, portions where the second layer 190b is provided without the first layer 190a (e.g., the portion corresponding to the second portion R2 of the first side insulating layer 192i) are not required.

[0129] In an embodiment, the depth of each of the plurality of first contact portions 192 may be greater than the depth of each of the plurality of second contact portions 196. This may be because, as described above, the first contact portions 192 can be formed by additionally performing a subsequent partial etching process and / or an additional etching process EA, compared to the second contact portions 196.

[0130] In this embodiment, the number of first contact portions 192 can be greater than the number of second contact portions 196. The total number of vias PH of different depths formed by the processes from the first etching process E1 to the nth etching process can be 1, 2, 4, ..., 2. (n-1) The sum, that is, can be {2} (n-1) -1}. The total number of vias PH of different depths formed by the (n+1)th etching process can be 2. n For example, the total number of vias PH of different depths formed by the (n+1)th etching process can be greater than the total number of vias PH of different depths formed by the processes from the first etching process E1 to the nth etching process. For example, the total number of vias PH of different depths formed by the first etching process to the third etching processes E1, E2 and E3 can be seven, and the total number of vias PH of different depths formed by the fourth etching process E4 can be eight. Furthermore, the first contact portion 192 may also include a first additional contact portion 194 formed by the additional etching process EA.

[0131] However, the embodiments are not limited thereto. Depending on the order of the multiple part etching processes and / or additional etching processes EA according to binary, the number of first contact portions 192 may be the same as or less than the number of second contact portions 196.

[0132] In an embodiment, in each first contact portion 192, the number of gate electrodes 130 corresponding to the second portion R2 (e.g., connecting gate electrode 130c and / or the remaining gate electrode 130r) can be greater than the number of gate electrodes 130 corresponding to the first portion R1 (e.g., penetrating gate electrode 130p). The number of interlayer insulating layers 132 etched by the process from the first portion etching process E1 to the nth portion etching process can be 1, 2, 4, ..., 2 (n-1) The sum, that is, can be {2} (n-1) -1}. The number of interlayer insulating layers 132 etched by the (n+1)th part of the etching process can be 2. n For example, the number of interlayer insulating layers 132 etched by the (n+1)th part etching process can be greater than the number of interlayer insulating layers 132 etched by processes from the first part etching process E1 to the nth part etching process. Therefore, the number of gate electrodes 130 in the portion corresponding to the (n+1)th part etching process can be greater than the number of gate electrodes 130 in the portions corresponding to processes from the first part etching process E1 to the nth part etching process. For example, the total number of interlayer insulating layers 132 etched by processes from the first part etching process to the third part etching processes E1, E2, and E3 can be seven, and the total number of gate electrodes 130 thereon can be six. For example, the total number of interlayer insulating layers 132 etched by the fourth part etching process E4 can be eight, and the total number of gate electrodes 130 thereon can be seven or eight.

[0133] Therefore, the number of gate electrodes 130 corresponding to the second portion R2 formed by the subsequent partial etching process can be greater than the number of gate electrodes 130 corresponding to the first portion R1. Furthermore, the second portion R2 may also include portions formed by an additional etching process EA.

[0134] However, the embodiments are not limited thereto. Depending on the order of the multiple partial etching processes and / or additional etching processes EA according to binary, the number of gate electrodes 130 corresponding to the second portion R2 formed by the subsequent partial etching processes may be the same as or less than the number of gate electrodes 130 corresponding to the first portion R1.

[0135] In an embodiment, a subsequent partial etch process performed after the formation of the first layer 190a may include the m-th partial etch process of the longest partial etch process. For example, when the partial etch process may include the first to the fourth partial etch processes E1, E2, E3, and E4, the subsequent partial etch process may include the fourth partial etch process E4. Thus, in the longest partial etch process with the longest etching depth, the first layer 190a can stably protect the stacked structure 120s used for the gate stacked structure 120.

[0136] However, the embodiments are not limited thereto. Therefore, subsequent partial etching processes may include multiple partial etching processes, or may be varied according to the order of the multiple partial etching processes in the binary representation. Various other modifications are possible.

[0137] According to an embodiment, a plurality of vias PH for the plurality of gate contact portions 190 can be formed using a binary partial etching process, which simplifies the process of forming the gate contact portions 190 and reduces the area of ​​the connection region 104. The first layer 190a can be formed before subsequent partial etching processes, preventing potential damage to the stacked structure 120s in subsequent partial etching processes, and allowing for the stable formation of vias PH with relatively large depths. This improves the reliability and productivity of the semiconductor device 10.

[0138] Specifically, when the number of gate electrodes 130 included in the gate stack structure 120 is increased to increase the memory capacity, the number of gate contact portions 190 can be increased and the gate contact portions 190 can have a relatively high aspect ratio. In this case, according to the embodiment, the area of ​​the connection region 104 can be effectively reduced, and a via PH with a relatively high aspect ratio can be stably formed.

[0139] In the following text, refer to Figures 7 to 18 The method of manufacturing a semiconductor device according to an embodiment will be described in more detail below. To the extent that elements are not described in detail below, it will be understood that the elements are substantially the same as corresponding elements described elsewhere in this disclosure. The parts not described above will be described in detail.

[0140] Figures 7 to 18 This is a cross-sectional view illustrating an example manufacturing method of a semiconductor device. Figure 7 , Figure 16 and Figure 18 In the diagram, the cell array region 102 and the connecting region 104 are shown together as... Figure 1 The local part corresponds. In Figures 8 to 15 and Figure 17 In the diagram, the connecting region 104 is shown as... Figure 3 Correspondingly. In the following text, in the method of manufacturing semiconductor device 10, the gate stack structure 120, the channel structure CH, the separation structure 146, and the gate contact portion 190 are mainly described.

[0141] like Figure 7As shown, a second substrate 110 and a stacked structure 120s can be formed on the circuit region 200, and a channel sacrificial layer 122s extending through or penetrating the stacked structure 120s can be formed. After forming a horizontal insulating layer 116 and a second horizontal conductive layer 114 on the second substrate 110, the stacked structure 120s can be formed. The channel sacrificial layer 122s can penetrate or penetrate the stacked structure 120s, the horizontal insulating layer 116, and the second horizontal conductive layer 114.

[0142] More specifically, a second substrate 110 can be formed on the circuit region 200, and a horizontal insulating layer 116, a second horizontal conductive layer 114, and a stacked structure 120s can be formed on the second substrate 110. The stacked structure 120s can be formed by alternately stacking the interlayer insulating layer 132 and the sacrificial insulating layer 130s.

[0143] The sacrificial insulating layer 130s can be obtained by using the gate electrode 130 (refer to) through subsequent processes. Figure 16 The sacrificial insulating layer 130s can be formed to correspond to the portion where the gate electrode 130 will be formed. At least a portion of the horizontal insulating layer 116 can be replaced by the first horizontal conductive layer 112 (see reference) through subsequent processes. Figure 16 The horizontal insulating layer 116 may be formed to include a portion that will form the first horizontal conductive layer 112.

[0144] The horizontal insulating layer 116 and / or the sacrificial insulating layer 130s may include materials different from those of the interlayer insulating layer 132. For example, the interlayer insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant materials, etc., or may be formed of silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant materials, etc. The sacrificial insulating layer 130s may include at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, and may include materials different from those of the interlayer insulating layer 132.

[0145] In an embodiment, the stacked structure 120s may include a plurality of stacked structures 120d and 120e sequentially stacked on the second substrate 110. The channel sacrificial layer 122s may include a plurality of channel sacrificial portions that pass through or penetrate the plurality of stacked structures 120d and 120e, respectively. However, the embodiments are not limited thereto.

[0146] In an embodiment, the stacked structure 120s can be disposed in the region of the cell array region 102 where the channel sacrificial layer 122s is disposed, and in the connection region 104 where the gate contact portion 190 is disposed (see reference). Figure 17 (in the region).

[0147] It can be used to form a channel structure CH (refer to) Figure 16An initial penetration portion is formed at a portion of the stacked structure 120s, and the initial penetration portion can be filled with a sacrificial material to form a channel sacrificial layer 122s. The initial penetration portion can be formed by an etching process (e.g., dry etching process), and the initial penetration portion can be filled by any of a variety of processes (e.g., deposition process, etc.). The channel sacrificial layer 122s can include at least one of polysilicon, tungsten, titanium nitride, and carbon, or can be formed from at least one of polysilicon, tungsten, titanium nitride, and carbon. However, the embodiments are not limited thereto, and the channel sacrificial layer 122s can include any of a variety of materials.

[0148] Subsequently, as Figures 8 to 14 As shown, multiple vias PH for multiple gate contact portions 190 can be formed by multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) and / or an additional etching process EA. A first layer 190a can be formed between two sequential processes in the multiple partial etching processes.

[0149] For clear understanding and simple explanation, in Figures 8 to 14 In its description, it is shown and described as an example that the number of sacrificial insulating layers 130s is sixteen, and that the first part etching process through the fourth part etching processes E1, E2, E3 and E4, and an additional etching process EA are performed. For clarity, in Figures 8 to 14 The diagram shows the positions of the first vias PH1 to PH5 corresponding to the first to fifth gate contact portions, and the positions of the thirteenth vias PH13 to PH16 corresponding to the thirteenth to sixteenth gate contact portions. However, the embodiment is not limited to this, and the number of sacrificial insulating layers 130s can be modified differently, and the number of partial etching processes and / or the number of additional etching processes EA can be modified differently depending on the number of sacrificial insulating layers 130s.

[0150] In an embodiment, the number of interlayer insulating layers 132 on each sacrificial insulating layer 130s can be converted to binary. For example, the vertical or horizontal position of each sacrificial insulating layer 130s can be converted to binary. Based on the binary representation, multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) and / or additional etching processes EA can be performed to form multiple vias PH with different depths.

[0151] Multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) can be cyclic etching processes. In each partial etching process, a mask can be formed, a binary partial etching process can be performed, and the mask can be removed. For example, an interlayer insulating layer 132 and one or more layers thereon (e.g., a sacrificial insulating layer 130s or multiple sacrificial insulating layers 130s, see reference) can be etched according to binary. Figure 7 This is used to form vias (PH). For example, in a multi-part etching process, 1, 2, 4, ..., 2 can be etched. (m-1) Each interlayer insulating layer 132, and a single sacrificial insulating layer 130s or multiple sacrificial insulating layers 130s thereon. m can be a natural number greater than 1, and is the total number of partial etching processes. The m-th partial etching process can be the longest partial etching process with the longest etching depth. The etching depth of the m-th partial etching process can be greater than the etching depth of the other partial etching processes and the additional etching process EA.

[0152] For example, the position of the first interlayer insulating layer located at the topmost position (i.e., 1) is converted to 1 according to binary, and the first interlayer insulating layer located at the topmost position can be etched by the first partial etching process E1, and a first via PH1 reaching the first sacrificial insulating layer can be formed. The position of the fifth interlayer insulating layer located at the fifth position from the top (i.e., 5) is converted to 101 according to binary, and a fifth via PH5 reaching the fifth sacrificial insulating layer can be formed by performing the first partial etching process E1 and the third partial etching process E3. The position of the fifteenth interlayer insulating layer located at the fifteenth position from the top (i.e., 15) is converted to 1111 according to binary, and a fifteenth via PH15 reaching the fifteenth sacrificial insulating layer can be formed by performing the first partial etching process E1, the second partial etching process E2, the third partial etching process E3 and the fourth partial etching process E4. The position of the sixteenth interlayer insulating layer (i.e., 16) located at the sixteenth position from the top is based on the sum of binary 1111 and one, and the sixteenth via PH16 reaching the sixteenth sacrificial insulating layer can be formed by performing a first part etching process E1, a second part etching process E2, a third part etching process E3, a fourth part etching process E4 and an additional etching process EA.

[0153] In an embodiment, a first layer 190a may be formed between two sequential processes included in a plurality of partial etching processes (e.g., first partial etching processes to fourth partial etching processes E1, E2, E3, and E4). Based on the first layer 190a, partial etching processes performed before the processes forming the first layer 190a may be referred to as preceding partial etching processes, and partial etching processes performed after the processes forming the first layer 190a may be referred to as subsequent partial etching processes. The fourth partial etching process E4, which etches the longest depth, may be referred to as the longest partial etching process.

[0154] In an embodiment, the process of forming the first layer 190a can be performed before the longest partial etching process. For example, the first layer 190a can be formed between the third partial etching process E3 and the fourth partial etching process E4 of the longest partial etching process. The first to third partial etching processes E1, E2 and E3 can be preceding partial etching processes, and the fourth partial etching process E4 of the longest partial etching process can be a subsequent partial etching process.

[0155] More specifically, such as Figure 8 As shown, in the first etching process E1, portions of multiple vias PH corresponding to the first etching process E1 can be selectively etched. For example, in the first etching process E1, an interlayer insulating layer 132 (e.g., a first interlayer insulating layer disposed at the uppermost position) can be etched in the portions corresponding to the first via PH1, the third via PH3, the fifth via PH5, the seventh via, the ninth via, the eleventh via, the thirteenth via PH13, the fifteenth via PH15, and the sixteenth via PH16.

[0156] In the first partial etching process E1 of the preceding partial etching process, a photosensitive material or a photoresist layer formed of a photosensitive material can be used as a mask. For example, a first photoresist mask M1 can be formed by forming a photoresist layer on the stacked structure 120s and performing a patterning process to form a first opening P1 in the portion where the first partial etching process E1 will be performed. The patterning process for forming the first opening P1 can be performed by photolithography. Thus, in the patterning process for forming the first opening P1, the etching process can be omitted, and the first photoresist mask M1 can be formed without damaging the stacked structure 120s.

[0157] In the portion exposed by the first opening P1 of the first photoresist mask M1, a first partial etching process E1 can be performed to etch an interlayer insulating layer 132 (e.g., the first interlayer insulating layer disposed at the uppermost position). The first partial etching process E1 can be performed by any of a variety of etching processes (e.g., a dry etching process). After the etching process, the first photoresist mask M1 can be removed. For the process of removing the first photoresist mask M1, any of a variety of processes can be used.

[0158] Subsequently, as Figure 9 As shown, in the second etching process E2, portions of multiple vias PH corresponding to the second etching process E2 can be selectively etched. For example, in the second etching process E2, in the portions corresponding to the second via PH2, the third via PH3, the sixth via, the seventh via, the tenth via, the eleventh via, the fourteenth via PH14, the fifteenth via PH15, and the sixteenth via PH16, two interlayer insulating layers 132 and one or two sacrificial insulating layers 130s thereon can be etched. More specifically, in the portions corresponding to the second via PH2, the sixth via, the tenth via, and the fourteenth via PH14 where the second etching process E2 is first performed, two interlayer insulating layers 132 and one sacrificial insulating layer 130s thereon can be etched. In the portions corresponding to the third through-hole PH3, the seventh through-hole, the eleventh through-hole, the fifteenth through-hole PH15, and the sixteenth through-hole PH16, which are executed after the first part of the etching process E1, two interlayer insulating layers 132 and two sacrificial insulating layers 130s thereon can be etched.

[0159] In the second partial etching process E2 of the preceding partial etching process, a photosensitive material or a photoresist layer formed of a photosensitive material can be used as a mask. For example, the second photoresist mask M2 can be formed by forming a photoresist layer on the stacked structure 120s and performing a patterning process to form a second opening P2 in the portion where the second partial etching process E2 will be performed. The patterning process for forming the second opening P2 can be performed by a photolithography process. Thus, in the patterning process for forming the second opening P2, the etching process can be omitted, and the second photoresist mask M2 can be formed without damaging the stacked structure 120s.

[0160] In the portion exposed by the second opening P2 of the second photoresist mask M2, a second partial etching process E2 can be performed, etching the two interlayer insulating layers 132 and one or two sacrificial insulating layers 130s thereon. The second partial etching process E2 can be performed using any of a variety of etching processes (e.g., dry etching). After the etching process, the second photoresist mask M2 can be removed. For the process of removing the second photoresist mask M2, any of a variety of processes can be used.

[0161] Subsequently, as Figure 10 As shown, in the third etching process E3, portions of multiple vias PH corresponding to the third etching process E3 can be selectively etched. For example, in the third etching process E3, in the portions corresponding to the fourth via PH4, the fifth via PH5, the sixth via, the seventh via, the twelfth via, the thirteenth via PH13, the fourteenth via PH14, the fifteenth via PH15, and the sixteenth via PH16, four interlayer insulating layers 132 and three or four sacrificial insulating layers 130s thereon can be etched. More specifically, in the portions corresponding to the fourth via PH4 and the twelfth via where the third etching process E3 is first performed, four interlayer insulating layers 132 and three sacrificial insulating layers 130s thereon can be etched. In the portions corresponding to the fifth through-hole PH5, sixth through-hole, seventh through-hole, thirteenth through-hole PH13, fourteenth through-hole PH14, fifteenth through-hole PH15 and sixteenth through-hole PH16, which are subjected to the third etching process E3 after the first etching process E1 and / or the second etching process E2, four interlayer insulating layers 132 and four sacrificial insulating layers 130s thereon can be etched.

[0162] In the third partial etching process E3 of the preceding partial etching process, a photosensitive material or a photoresist layer formed of a photosensitive material can be used as a mask. For example, the third photoresist mask M3 can be formed by forming a photoresist layer on the stacked structure 120s and performing a patterning process to form a third opening P3 in the portion where the third partial etching process E3 will be performed. The patterning process for forming the third opening P3 can be performed by a photolithography process. Thus, in the patterning process for forming the third opening P3, the etching process can be omitted, and the third photoresist mask M3 can be formed without damaging the stacked structure 120s.

[0163] In the portion exposed by the third opening P3 of the third photoresist mask M3, a third-part etching process E3 can be performed, etching four interlayer insulating layers 132 and three or four sacrificial insulating layers 130s thereon. The third-part etching process E3 can be performed using any of a variety of etching processes (e.g., dry etching). After the etching process, the third photoresist mask M3 can be removed. For the process of removing the third photoresist mask M3, any of a variety of processes can be used.

[0164] As described above, after the first to third partial etching processes E1, E2, and E3 of the previous partial etching process, as Figure 11 As shown, a first layer 190a can be formed. Therefore, the first layer 190a can be formed between the first to third partial etching processes E1, E2 and E3 of the preceding partial etching process and the fourth partial etching process E4 of the subsequent partial etching process.

[0165] The first layer 190a can be formed inside each of the plurality of vias PH. For example, the first layer 190a can be formed on the inner surface and the lower surface of each of the plurality of vias PH, and the first layer 190a can also be formed on the upper surface of the stacked structure 120s. The process of forming the first layer 190a can be performed by any of a variety of processes (e.g., deposition processes, etc.). However, the embodiments are not limited thereto.

[0166] Subsequently, as Figure 12 and Figure 13 As shown, in the fourth etching process E4, portions of multiple vias PH corresponding to the fourth etching process E4 can be selectively etched. For example, in the fourth etching process E4, in the portions corresponding to the eighth to twelfth vias, the thirteenth to sixteenth vias PH13, PH14, PH15 and PH16, eight interlayer insulating layers 132 and seven or eight sacrificial insulating layers 130s thereon can be etched.

[0167] In the subsequent fourth-part etching process, E4, a hard mask layer HML or a hard mask HM can be used as a mask. For example, as... Figure 12 As shown, a hard mask layer HML can be formed on the stacked structure 120s, and a patterned mask layer PM can be formed. A fourth opening P4 (see reference) can be formed. Figure 13The patterned mask layer PM corresponding to the opening P. A patterning process can be performed to remove the portion of the hard mask layer HML exposed by the opening P of the patterned mask layer PM. In the patterning process of the hard mask layer HML, an etching material that can etch more of the hard mask layer HML than the material included in the first layer 190a and / or the stacked structure 120s, or that can etch the hard mask layer HML without etching the material included in the first layer 190a and / or the stacked structure 120s, can be used. Thus, as Figure 13 As shown, a hard mask HM with a fourth opening P4 can be formed.

[0168] Hard mask HMs can include any of a variety of materials that are highly selective and easily removable. For example, hard mask HMs can include, or be formed of, carbon-based materials containing carbon. Hard mask HMs can include spin-coated hard masks (SOH), amorphous carbon layers (ACL), etc., or be formed of, spin-coated hard masks (SOH), amorphous carbon layers (ACL), etc. However, embodiments are not limited thereto, and the materials of hard mask HMs can be modified differently.

[0169] In the portion exposed through the fourth opening P4 of the hard mask HM, a fourth-part etching process E4 can be performed, etching eight interlayer insulating layers 132 and seven or eight sacrificial insulating layers 130s thereon. The fourth-part etching process E4 can be performed using any of a variety of etching processes (e.g., dry etching). In the fourth-part etching process E4, etching materials that do not etch the hard mask HM or etch the hard mask HM with less material than the stacked structure 120s can be used. After the etching process, the hard mask HM can be removed. For the process of removing the hard mask HM, any of a variety of processes can be used.

[0170] The etching material used in the fourth part etching process E4 allows for minimal or no etching of the hard mask HM. Furthermore, the etching material in the fourth part etching process E4 allows for less etching of the hard mask HM compared to the first to third photoresist masks M1, M2, and M3. Therefore, the limitation on etching depth can be overcome in the fourth part etching process E4, which is the longest partial etching process. In the fourth part etching process E4, the via PH can be formed stably to the desired layer. Therefore, process margin can be ensured.

[0171] In the fourth part of the longest partial etching process, etching process E4, the hard mask HM can be retained to have sufficient thickness. This prevents damage to the stacked structure 120s that might occur if the remaining mask thickness in the etching process is small. For example, in a comparative example where the remaining mask thickness (e.g., the remaining photoresist mask) in the etching process is small, ions may reflect at the side surfaces of the mask, and the portion of the stacked structure adjacent to the upper portion of the vias may be undesirably etched. Consequently, the diameter or width of the vias can increase, potentially causing interference between adjacent vias, and electrical properties may deteriorate.

[0172] In this embodiment, the lower portion of the first layer 190a located on the sacrificial insulating layer 130s can protect the sacrificial insulating layer 130s during the patterning process of the hard mask layer HML. For example, in a process of removing the hard mask layer HML in a via PH with a relatively large depth, the first layer 190a in a via PH with a relatively small depth can protect the sacrificial insulating layer 130s below the first layer 190a. Thus, unnecessary damage or puncture to the sacrificial insulating layer 130s can be prevented during the patterning process of the hard mask layer HML. Consequently, the via PH can be stably formed to the desired location.

[0173] Furthermore, in the fourth etching process E4, the side portion of the first layer 190a located on the side surface of the stacked structure 120s can prevent damage to the side surface of the stacked structure 120s. For example, during the etching process, ions may reflect at the side surface of the mask and may etch the side surface of the stacked structure 120s adjacent to the upper portion of the via PH. The side portion of the first layer 190a can prevent unnecessarily etching of the side surface of the stacked structure 120s.

[0174] In this embodiment, the first layer 190a can be formed before performing the longest partial etching process, and the depth of the via PH formed by the longest partial etching process can be increased. This reduces the number of processes required to form vias PH with relatively large depths, and reduces manufacturing costs and time. In this embodiment, the first layer 190a can be formed before performing the longest partial etching process, and damage to the stack structure 120s that may occur during the longest partial etching process can be minimized.

[0175] On the other hand, in the comparative example using the photoresist mask in the longest partial etching process, the photoresist mask may be easily etched, and there may be limitations in forming vias with relatively large depths. Therefore, in order to perform an etching process with a large etching depth, multiple etching processes, each with a small etching depth, can be repeatedly performed. As a result, the number of processes forming vias may be large, and there may be difficulties in reducing the cost and time of the manufacturing process.

[0176] However, the embodiments are not limited to this, and the order, number, etc., of the processes forming the first layer 190a can be modified differently. See below for further details. Figure 19 and Figure 20 Other embodiments are described.

[0177] In this embodiment, multiple vias PH can be formed by using a binary-based multi-part etching process, and the number of etching processes required to form multiple vias PH can be greatly reduced.

[0178] like Figure 14 As shown, in the additional etching process EA, the portion corresponding to the additional etching process EA can be selectively etched. For example, in the additional etching process EA, in the portion corresponding to the sixteenth via PH16, an interlayer insulating layer 132 and a sacrificial insulating layer 130s thereon can be etched. In the additional etching process EA, a photosensitive material or a photoresist layer formed of a photosensitive material can be used as a mask. Reference can be applied. Figures 8 to 10 Description of the photoresist layer.

[0179] In the embodiment, one via PH is shown and described as an example of performing the additional etching process EA, but multiple via PHs may be performed in the additional etching process EA. In the additional etching process EA, a partial etching process based on binary may be performed, or a partial etching process performed sequentially may be performed.

[0180] In the above description, an additional etching process EA is shown as an example after performing multiple partial etching processes. However, the embodiments are not limited to this, and the additional etching process EA can be performed before the multiple partial etching processes or between two processes in the multiple partial etching processes. For example, the additional etching process EA can be performed between a previous partial etching process and a subsequent partial etching process (e.g., between a previous partial etching process and the process forming the first layer 190a). Various other modifications are possible.

[0181] Subsequently, as Figure 15As shown, a side insulating layer 190i can be formed by forming a second layer 190b inside the via PH (e.g., on the inner surface of the via PH and on the first layer 190a on the inner surface of the via PH). After forming the side insulating layer 190i, a through sacrificial layer 190s can be formed on the first layer 190a and / or the second layer 190b on the inner surface of the via PH. The through sacrificial layer 190s can include at least one of polysilicon, tungsten, titanium nitride, and carbon, or be formed of at least one of polysilicon, tungsten, titanium nitride, and carbon. However, the embodiments are not limited thereto, and the through sacrificial layer 190s can include any of a variety of materials.

[0182] Subsequently, as Figure 16 As shown, a channel structure CH, a gate electrode 130, and a separation structure 146 can be formed.

[0183] More specifically, this can be achieved by removing the channel sacrificial layer 122s (refer to...). Figure 7 The through-port is formed by etching. The process of forming the through-port can be performed using any of a variety of etching processes (e.g., dry etching). In an embodiment, a gate dielectric layer 150 (see reference 150) can be sequentially formed in the through-port. Figure 2 ), channel layer 140 (reference) Figure 2 ) and core insulation layer 142 (refer to Figure 2 And it can form channel pads 144 (refer to) Figure 2 The process of forming the gate dielectric layer 150, the channel layer 140, the core insulating layer 142, or the channel pad 144 can be performed by any of a variety of processes (e.g., deposition process, etc.).

[0184] An opening for penetrating the stacked structure 120s can be formed in the region corresponding to the separation structure 146, and the sacrificial insulating layer 130s can be replaced by the gate electrode 130 (see reference). Figure 15 Furthermore, the openings for the separation structure can be filled with insulating materials to form the separation structure 146.

[0185] In this embodiment, the opening for the separation structure can be formed by an etching process (e.g., dry etching process, etc.). The sacrificial insulating layer 130s can be selectively removed by an etching process (e.g., wet etching process) via the opening for the separation structure. The gate electrode 130 can be formed by filling the removed portion of the sacrificial insulating layer 130s with a conductive material. As a result, the area where the sacrificial insulating layer 130s is disposed can be replaced by the gate electrode 130. In this case, the formation of the barrier layer 156 (see reference) can also be performed before the process of filling the conductive material constituting the gate electrode 130. Figure 2 A portion thereof (e.g., the first barrier layer 156a (see reference)) Figure 2The process described is as follows. However, the embodiments are not limited to this. The openings for the separation structure can be filled by any of a variety of processes (e.g., deposition processes, etc.).

[0186] In some embodiments, the opening for the separation structure 146 may expose the horizontal insulating layer 116. During an etching process through the opening for the separation structure, at least a portion of the horizontal insulating layer 116 and at least a portion of the gate dielectric layer 150 may be removed, and material may be used to fill the first horizontal conductive layer 112. Thus, the first horizontal conductive layer 112 can be formed.

[0187] In some embodiments, an upper separation region 148 may be formed at a local portion of the gate stack structure 120. The upper separation region 148 may be formed by forming an opening for a separation pattern via an etching process using a mask layer and filling at least a local portion of the opening for the separation pattern with an insulating material. The opening for the separation pattern may be formed by an etching process (e.g., dry etching process, etc.). The opening for the separation pattern may be filled by any of a variety of processes (e.g., deposition process, etc.). The order of the processes for forming the opening of the separation structure and the processes for forming the opening of the separation pattern may be modified differently.

[0188] In this embodiment, as an example, an opening for the separation structure 146 is described after the formation of the via PH, the side insulating layer 190i, and the through sacrificial layer 190s. However, the embodiment is not limited to this. In some embodiments, the opening for the separation structure 146 may be formed before the formation of the via PH, and a sacrificial layer may be formed in the opening for the separation structure 146. In this case, after removing the sacrificial layer in the opening for the separation structure 146, a replacement process for the gate electrode 130, a replacement process for the first horizontal conductive layer 112, etc., may be performed.

[0189] Subsequently, as Figure 17 As shown, the penetrating sacrificial layer can be removed 190 seconds (refer to...). Figure 16 Furthermore, the lower portion of the second layer 190b (i.e., the portion of the second layer 190b located on the gate electrode 130) can be removed. The conductive portion 190c can be formed by filling the via PH with a conductive material. Thus, the gate contact portion 190 can be formed.

[0190] Subsequently, as Figure 18 As shown, a second wiring portion 180 may be formed, including bit lines 182 electrically connected to the channel structure CH, etc.

[0191] According to an embodiment, a plurality of vias PH can be formed using a binary partial etching process, and the number of processes for forming the plurality of vias PH can be reduced. In the previous partial etching process performed before the formation of the first layer 190a, a photoresist layer can be used as a mask to prevent damage to the stacked structure 120s. In the subsequent partial etching process performed after the formation of the first layer 190a, damage to the stacked structure 120s can be prevented through the first layer 190a even when a hard mask HM is used as a mask. Therefore, the subsequent partial etching process using the hard mask HM can be performed, and the depth of the vias PH can be increased, and the number of etching processes for forming the vias PH can be reduced. As a result, the cost and time of the manufacturing process can be reduced.

[0192] In the accompanying drawings, vias PH (e.g., vias PH13, PH14, PH15, and PH16) formed by multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) and / or additional etching processes EA are shown, passing through or penetrating multiple gate stack portions 121 and 122. However, the embodiments are not limited thereto. Vias PH may be formed to correspond to each of the multiple gate stack portions 121 and 122, and may include multiple portions corresponding to the multiple gate stack portions 121 and 122, respectively.

[0193] In the above description, the semiconductor device 10 is described as an example of a NAND flash memory device, including a gate stack structure 120 and a channel structure CH as a memory cell structure, and including a gate contact portion 190 electrically connected to the gate electrode 130.

[0194] However, the embodiments are not limited thereto. In some embodiments, the semiconductor device may include an electrode stack structure formed by stacking two layers of different materials. The semiconductor device may include an electrode stack structure comprising a plurality of interlayer insulating layers and a plurality of electrodes stacked alternately with each other. For example, the electrode stack structure may be formed by alternately stacking a plurality of semiconductor material layers (e.g., silicon layers) and a plurality of interlayer insulating layers (e.g., oxide layers). A plurality of electrode contact portions may be electrically connected to a plurality of electrodes, respectively. The plurality of electrode contact portions may have a shape or structure corresponding to the shape or structure of the gate contact portion 190. For example, the gate contact portion 190 may also be referred to as a plurality of electrode contact portions. The description of the electrical connection structure between the gate contact portion 190 and the gate electrode 130 may be applied to the electrical connection structure between the electrode contact portion and the electrode, and the description of the gate contact portion 190 may be applied to the electrode contact portion. For example, a semiconductor device including electrode contact portions having a shape or structure corresponding to the shape or structure of the gate contact portion 190 may be a DRAM, etc.

[0195] In the above description, an electrode stack structure comprising multiple electrodes and multiple interlayer insulating layers is shown as an example. In some embodiments, a stack structure formed by alternately stacking semiconductor material layers comprising different materials (e.g., silicon layers and silicon-germanium layers) can be applied. Various other modifications are possible.

[0196] In the following text, refer to Figures 19 to 22 The semiconductor device and its manufacturing method according to embodiments will be described in more detail below. To the extent that elements are not described in detail below, it will be understood that the elements are substantially the same as corresponding elements described elsewhere in this disclosure. The parts not described above will be described in detail.

[0197] Figure 19 This is a cross-sectional view showing a gate contact portion included in a semiconductor device according to an example embodiment. Figure 19 Showing with Figure 4 The corresponding part. For clarity, an example is described including sixteen gate electrodes 130 or sixteen sacrificial insulating layers, and a via PH can be formed by a first-part etching process through four-part etching processes E1, E2, E3, and E4, and an additional etching process EA. However, the embodiment is not limited to this, and the number of gate electrodes 130 or sacrificial insulating layers can be modified differently, or the number of partial etching processes and / or additional etching processes can be modified differently depending on the number of gate electrodes 130 or sacrificial insulating layers.

[0198] Reference Figure 19 In this embodiment, the subsequent partial etching process performed after the process of forming the first layer 190a may include multiple partial etching processes. For example, the process of forming the first layer 190a may not be performed exactly before the longest partial etching process.

[0199] This will be described using the fifteenth gate contact portion 1915 as an example. To form the fifteenth gate contact portion 1915, a first partial etching process E1 and a second partial etching process E2, which are preceding partial etching processes, can be performed. A first layer 190a can be formed in the portion formed by the first partial etching process E1 and the second partial etching process E2. Subsequent partial etching processes E3 and E4, which are subsequent partial etching processes, can be performed, and a second layer 190b and a conductive portion 190c can be formed. Thus, a first portion R1, where the first layer 190a and the second layer 190b are disposed together, can be disposed in the portion formed by the first partial etching process E1 and the second partial etching process E2. A second portion R2, where the second layer 190b is disposed separately without the first layer 190a, can be disposed in the portion formed by the third partial etching process E3 and the fourth partial etching process E4.

[0200] As mentioned above, the order of the processes for forming the first layer 190a, the number of subsequent partial etching processes, etc., can be modified differently.

[0201] Figure 20 This is a cross-sectional view showing a gate contact portion included in a semiconductor device according to an example embodiment. Figure 20 Showing with Figure 4 The corresponding part. For clarity, an example is described including sixteen gate electrodes 130 or sixteen sacrificial insulating layers, and a via PH can be formed by a first-part etching process through four-part etching processes E1, E2, E3, and E4, and an additional etching process EA. However, the embodiment is not limited to this, and the number of gate electrodes 130 or sacrificial insulating layers can be modified differently, or the number of partial etching processes and / or additional etching processes can be modified differently depending on the number of gate electrodes 130 or sacrificial insulating layers.

[0202] Reference Figure 20 In this embodiment, the process of forming the first layer 190a may include multiple processes. In the following text, to distinguish them from each other, the first layer 190a formed first may be referred to as the first cover layer 190e, and the first layer 190a formed subsequently may be referred to as the second cover layer 190f.

[0203] As an example, a first capping layer 190e is described as being formed between a second partial etching process E2 and a third partial etching process E3, and a second capping layer 190f is formed between a third partial etching process E3 and a fourth partial etching process E4. Based on the first capping layer 190e, the first partial etching process E1 and the second partial etching process E2 can be preceding partial etching processes, and the third partial etching process E3 can be a subsequent partial etching process. Based on the second capping layer 190f, the third partial etching process E3 can be a preceding partial etching process, and the fourth partial etching process E4 can be a subsequent partial etching process.

[0204] This will be described using the fifteenth gate contact portion 1915 as an example. First, a first partial etching process E1 and a second partial etching process E2 based on the first capping layer 190e can be performed. The first capping layer 190e can be formed in the portion formed by the first partial etching process E1 and the second partial etching process E2. A third partial etching process E3 based on the first capping layer 190e can then be performed. Subsequently, a second capping layer 190f can be formed in the second insulating portion IR2 formed by the first to third partial etching processes E1, E2 and E3. A fourth partial etching process E4 can then be performed. Subsequently, a second layer 190b and a first conductive portion 192c can be formed. Thus, the fifteenth gate contact portion 1915 can be formed.

[0205] The first side insulating layer 192i of the first contact portion 192 may include a first portion R1 and a second portion R2, wherein the thickness of the second portion R2 is less than the thickness of the first portion R1. The first portion R1 may include a first insulating portion IR1 and a second insulating portion IR2. The first insulating portion IR1 may be the portion in which a first cover layer 190e, a second cover layer 190f, and a second layer 190b are disposed. The second insulating portion IR2 may be the portion in which a second cover layer 190f and a second layer 190b are disposed without the first cover layer 190e. The second portion R2 may be the portion in which the second layer 190b is disposed without the first layer 190a (i.e., the first cover layer 190e and the second cover layer 190f).

[0206] The thickness of the second insulating portion IR2 may be less than the thickness of the first insulating portion IR1, and the thickness of the second portion R2 may be less than the thickness of the second insulating portion IR2. The thickness of the first insulating portion IR1 may refer to the average thickness of the first insulating portion IR1 or the thickness of the portion of the first insulating portion IR1 adjacent to the second insulating portion IR2. The thickness of the second insulating portion IR2 may be the average thickness of the second insulating portion IR2 or the thickness of the portion of the second insulating portion IR2 adjacent to the first insulating portion IR1 or the second portion R2. The thickness T2 of the second portion R2 may refer to the average thickness of the second portion R2 or the thickness of the portion of the second portion R2 adjacent to the second insulating portion IR2.

[0207] In the vertical direction (Z-axis direction in the attached figure), the first insulating portion IR1 can be disposed above the first contact portion 192 and can be spaced apart from the lower surface of the first contact portion 192. For example, the upper surface of the first insulating portion IR1 can be disposed adjacent to the upper surface of the first contact portion 192. For example, the upper surface of the first insulating portion IR1 can be disposed in the same plane as the upper surface of the first contact portion 192. The lower surface of the first insulating portion IR1 can be spaced apart from the lower surface of the first contact portion 192, while a second insulating portion IR2 and a second portion R2 are inserted therebetween. The lower surface of the first insulating portion IR1 can be spaced apart from the lower surface of the first contact portion 192, while portions corresponding to the plurality of penetrating gate electrodes 130p are inserted therebetween.

[0208] In the vertical direction (Z-axis direction in the attached figure), the second insulating portion IR2 can be disposed between the first insulating portion IR1 and the second portion R2. Therefore, the second insulating portion IR2 can be spaced apart from the upper surface of the first contact portion 192, with the first insulating portion IR1 inserted therebetween, and can be spaced apart from the lower surface of the first contact portion 192, with the second portion R2 inserted therebetween. The lower surface of the second insulating portion IR2 can be spaced apart from the lower surface of the first contact portion 192, with at least one portion corresponding to the penetrated gate electrode 130p inserted therebetween.

[0209] In the vertical direction (Z-axis direction in the attached figure), the second part R2 can be located at the lower part of the second insulating part IR2 or below the second insulating part IR2.

[0210] In an embodiment, the first side insulating layer 192i may include a first cover layer 190e, a second cover layer 190f, and a second layer 190b. The first cover layer 190e may be partially disposed in the first insulating portion IR1. The second cover layer 190f may be partially disposed in the first insulating portion IR1, the second insulating portion IR2, and on the inner surface of the first cover layer 190e. The second layer 190b may be disposed on the inner surface of the second cover layer 190f in the first insulating portion IR1, the second insulating portion IR2, and the second portion IR2.

[0211] More specifically, the first capping layer 190e may be disposed in the first insulating portion IR1 on the side surface of the gate stack structure 120 (e.g., in contact with the side surface of the gate stack structure 120 in the first insulating portion IR1). The second capping layer 190f may be disposed in the first insulating portion IR1 on the inner surface of the first capping layer 190e (e.g., in contact with the inner surface of the first capping layer 190e in the first insulating portion IR1), and may be disposed in the second insulating portion IR2 on the side surface of the gate stack structure 120 (e.g., in contact with the side surface of the gate stack structure 120 in the second insulating portion IR2). The second layer 190b may be disposed in the first insulating portion IR1 and the second insulating portion IR2 on the inner surface of the second capping layer 190f, and may be disposed in the second portion R2 on the side surface of the gate stack structure 120 (e.g., in contact with the side surface of the gate stack structure 120 in the second portion R2). However, the embodiments are not limited thereto. In some embodiments, an additional layer may be disposed between two adjacent portions of the gate stack structure 120, the first cover layer 190e, the second cover layer 190f, and the second layer 190b.

[0212] The inner surface of the first side insulating layer 192i (e.g., the second layer 190b) may contact the outer surface of the first conductive portion 192c. However, the embodiments are not limited thereto, and an additional layer may be disposed between the inner surface of the first side insulating layer 192i (e.g., the second layer 190b) and the outer surface of the first conductive portion 192c.

[0213] As described above, the first cover layer 190e, the second cover layer 190f, and the second layer 190b can be disposed together in the first insulating portion IR1, and the second cover layer 190f and the second layer 190b can be disposed in the second insulating portion IR2. Furthermore, the second layer 190b can be disposed alone in the second portion R2 if the first cover layer 190e and the second cover layer 190f are absent. For example, the first portion R1 and the second portion R2 can have different stacking structures with or without the first cover layer 190e and / or the second cover layer 190f, and the first insulating portion IR1 and the second insulating portion IR2 can have different stacking structures with or without the first cover layer 190e.

[0214] The inner surface of the first side insulating layer 192i (e.g., the second layer 190b) may have an inclined surface that is tilted relative to the vertical direction (Z-axis direction in the figures) of the semiconductor device, without any stepped or curved portions. The outer surface of the first side insulating layer 192i (e.g., the first cover layer 190e, the second cover layer 190f, and the second layer 190b) may have an inclined surface that is tilted relative to the vertical direction. A first step may be provided between the first insulating portion IR1 and the second insulating portion IR2, and a second step may be provided between the first insulating portion IR1 and the second portion IR2. However, the embodiments are not limited thereto, and at least a portion of the inner and / or outer surfaces of the first side insulating layer 192i may include a vertical surface parallel to the vertical direction of the semiconductor device.

[0215] Reference Figures 1 to 6 The description of step S in the embodiments can be applied to either the first step or the second step. See reference... Figures 1 to 6 The description of the first layer 190a in the embodiments can be applied to the thickness of the first cover layer 190e or the thickness of the second cover layer 190f. (Refer to...) Figures 1 to 6 The description of the second layer 190b in the embodiments can be applied to the thickness of the second layer 190b.

[0216] For example, in a direction perpendicular to the side surface of the first side insulating layer 192i, the height of the first step or the second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f can be 0.5 nm or greater (e.g., 1 nm or greater) and / or 20 nm or less (e.g., 10 nm or less, for example, 5 nm or less). However, the embodiments are not limited to this, and the height of the first step or the second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f can be less than 0.5 nm (e.g., 1 nm) and / or greater than 20 nm (e.g., 10 nm, or, as an example, 5 nm).

[0217] For example, in a direction perpendicular to the side surface of the first side insulating layer 192i, the height of the first step or the second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f may be the same as or less than the thickness of the second layer 190b. However, the embodiments are not limited thereto. In some embodiments, the height of the first step or the second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f may be greater than the thickness of the second layer 190b.

[0218] In embodiments, the height of the first step or the second step in the direction perpendicular to the side surface of the first side insulating layer 192i, the thickness of the first cover layer 190e in the direction perpendicular to the side surface of the first side insulating layer 192i, or the thickness of the second cover layer 190f in the direction perpendicular to the side surface of the first side insulating layer 192i may be less than the thickness of the interlayer insulating layer 132 in the vertical direction (Z-axis direction in the figures) or the thickness of the gate electrode 130 in the vertical direction (Z-axis direction in the figures). However, embodiments are not limited thereto. In some embodiments, the height of the first step or the second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f may be the same as, or greater than, the thickness of the interlayer insulating layer 132 or the thickness of the gate electrode 130.

[0219] For example, the thickness of the second capping layer 190f can be the same as or greater than the thickness of the first capping layer 190e. This could be because the etching depth in the fourth partial etching process E4 performed after the process of forming the second capping layer 190f can be greater than the etching depth in the third partial etching process E3 performed after the process of forming the first capping layer 190e. However, the embodiments are not limited to this, and the thickness of the second capping layer 190f can be less than the thickness of the first capping layer 190e.

[0220] When the first cover layer 190e and the second cover layer 190f comprise different materials, the boundary between the first cover layer 190e and the second cover layer 190f can be seen or confirmed. When the first cover layer 190e and the second cover layer 190f comprise the same material, the boundary between the first cover layer 190e and the second cover layer 190f can be seen or confirmed by the manufacturing process. For example, the boundary between the first cover layer 190e and the second cover layer 190f can be seen or confirmed when the first cover layer 190e and the second cover layer 190f are formed by different processes and have different compositions or properties, or when the properties of the inner surface of the first cover layer 190e change over time between the processes of forming the first cover layer 190e and forming the second cover layer 190f. When the first cover layer 190e and the second cover layer 190f comprise the same material and there may be difficulty in confirming the boundary between the first cover layer 190e and the second cover layer 190f, the position of the first cover layer 190e and the second cover layer 190f can be determined or anticipated by the difference in thickness or the first step.

[0221] When the first layer 190a comprises multiple layers as described above, the stacked structure can be protected in multiple partial etching processes. In the above description, as an example, the formation of the first cover layer 190e and the second cover layer 190f prior to the sequentially executed third partial etching process E3 and fourth partial etching process E4 are described, but the embodiments are not limited thereto. The order of the processes forming the multiple layers of the first layer 190a, the number of subsequent partial etching processes performed after each of the multiple layers of the first layer 190a, etc., can be modified differently.

[0222] In an embodiment, the second contact portion including the second side insulating layer may include a portion throughout the entire portion corresponding to the first portion R1 (i.e., the first insulating portion IR1 and the second insulating portion IR2) of the first side insulating layer 192i, and may include a portion corresponding to the second portion R2. The outer surface of the second side insulating layer may include a portion corresponding to the first step between the portion corresponding to the first insulating portion IR1 and the portion corresponding to the second insulating portion IR2.

[0223] Figure 21 This is a cross-sectional view showing a gate contact portion included in a semiconductor device according to an example embodiment. Figure 21 It shows the relationship with Figure 4 The corresponding part.

[0224] Reference Figure 21In the semiconductor device according to the embodiment, a recess R may be partially disposed on the inner surface of the first layer 190a included in the gate contact portion 190. The thickness of the portion of the first layer 190a with the recess R may be less than the thickness of the other portion of the first layer 190a without the recess R. For example, the recess R may be disposed at the upper part of the gate stack structure. A partial portion of the first layer 190a can be etched by ions reflected from the side surface of the mask in a subsequent partial etching process, and the recess R can be formed. Therefore, a partial portion of the first layer 190a can be etched when ions are reflected at the mask and unnecessary portions are etched. As a result, damage to the stack structure can be effectively prevented.

[0225] exist Figure 21 As an example, the recess R of the first layer 190a is shown to correspond to a portion of the interlayer insulating layer 132 (i.e., the first interlayer insulating layer) located at the uppermost position, but the embodiment is not limited thereto. The recess R of the first layer 190a may be configured to correspond to at least a portion of the interlayer insulating layer 132 or the gate electrode 130.

[0226] Figure 22 This is a schematic cross-sectional view of a semiconductor device 20 according to an example embodiment.

[0227] Reference Figure 22 The semiconductor device 20 according to the embodiment may have a chip-to-chip (C2C) structure bonded by a wafer bonding type. For example, a lower chip including a circuit region 200a with peripheral circuit structures disposed on a first substrate 210 may be manufactured, an upper chip including a cell region 100a with memory cell structures disposed on an initial substrate may be manufactured, and the semiconductor device 20 may be manufactured by bonding the lower chip and the upper chip.

[0228] The circuit region 200a may include a first substrate 210, a circuit element 220, a first wiring portion 280, and a first bonding structure 200b electrically connected to the first wiring portion 280 at a surface facing the cell region 100a. The area other than the first bonding structure 200b at the surface facing the cell region 100a may be covered by a first bonding insulating layer 200i.

[0229] Cell region 100a may include a second substrate 110a, a gate stack structure 120, a channel structure CH, a second wiring portion 180, and a second bonding structure 100b electrically connected to the second wiring portion 180 at a surface facing circuit region 200a. The region other than the second bonding structure 100b may be covered by a second bonding insulating layer 100i.

[0230] In some embodiments, the second substrate 110a may be a semiconductor layer comprising a semiconductor material. For example, the second substrate 110a may be a semiconductor layer comprising monocrystalline silicon or polycrystalline silicon, germanium, silicon-germanium, etc., or formed from monocrystalline silicon or polycrystalline silicon, germanium, silicon-germanium, etc. In some embodiments, the second substrate 110a may further comprise an insulating layer. For example, the initial substrate disposed in the cell region 100a may be removed after the cell region 100a is bonded to the circuit region 200a, and a semiconductor layer and / or an insulating layer may be formed.

[0231] In an embodiment, the gate stack structure 120 may be sequentially stacked on the lower portion of the second substrate 110a as shown in the figures, and may have Figure 1 The gate stack structure 120 shown is configured in a vertically inverted manner. The channel structure CH penetrating the gate stack structure 120 can have... Figure 2 The channel structure CH shown is arranged in a vertically reversed manner. Therefore, in the cross-sectional view, the channel structure CH can have sloping side surfaces, such that the width of the channel structure CH decreases from the circuit region 200a toward the second substrate 110a. The channel pad 144 and the second wiring portion 180 at the upper part of the gate stack structure 120 can be adjacent to the circuit region 200a.

[0232] For example, the first bonding structure 200b and / or the second bonding structure 100b may include aluminum, copper, tungsten, or alloys thereof, or be formed of aluminum, copper, tungsten, or alloys thereof. For example, the first bonding structure 200b and the second bonding structure 100b may include copper or be formed of copper, such that the unit region 100a and the circuit region 200a can be bonded to each other by copper-to-copper bonding (e.g., direct bonding).

[0233] In an embodiment, the channel structure CH may include a protruding portion CHP protruding from the surface of the gate stack structure 120 opposite to the second wiring portion 180. The gate dielectric layer 150 is not disposed at the protruding portion CHP, and the channel layer 140 disposed at the protruding portion CHP may be exposed to the outside. The second substrate 110a may be electrically connected to the channel layer 140 disposed at the protruding portion CHP. However, the embodiment is not limited thereto. In some embodiments, such as Figure 1 As shown, horizontal conductive layers 112 and 114 may be included. Various other modifications are possible.

[0234] In an embodiment, the semiconductor device 20 may include input / output pads and input / output connection wiring electrically connected to the input / output pads. The input / output connection wiring may be electrically connected to a portion of the second bonding structure 100b. The input / output pads may be disposed on an insulating layer, for example, covering the outer surface of the second substrate 110a. In some embodiments, additional input / output pads electrically connected to the circuit region 200a may be provided.

[0235] For example, circuit region 200a and unit region 100a can be respectively with Figure 23 The electronic system 1000 shown includes corresponding portions of a first structure 1100F and a second structure 1100S of a semiconductor device 1100. For example, circuit region 200a and cell region 100a may respectively include... Figure 26 The regions of the first structure 4100 and the second structure 4200 of the semiconductor chip 2200a shown.

[0236] The following will describe in detail an example of an electronic system that includes semiconductor devices.

[0237] Figure 23 This is a schematic diagram illustrating an electronic system including a semiconductor device according to an example embodiment.

[0238] Reference Figure 23 The electronic system 1000 according to an embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0239] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, a reference. Figures 1 to 22 The NAND flash memory device described herein. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S disposed on the first structure 1100F. In some embodiments, the first structure 1100F may be positioned close to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL between the bit line BL and the common source line CSL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR.

[0240] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified differently depending on the embodiment.

[0241] In this embodiment, the lower transistor LT1 or LT2 may include a ground select transistor, and the upper transistor UT1 or UT2 may include a string select transistor. The first lower gate line LL1 and the second lower gate line LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0242] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending within the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending within the first structure 1100F to the second structure 1100S.

[0243] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations for selecting at least one memory cell transistor from a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0244] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0245] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted through NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When receiving control commands from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0246] Figure 24 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to an example embodiment.

[0247] Reference Figure 24 The electronic system 2000 according to an embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 disposed on the main substrate 2001.

[0248] The main substrate 2001 may include a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In embodiments, the electronic system 2000 may communicate with the external host via any of an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (USB). In embodiments, the electronic system 2000 may operate via power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0249] The controller 2002 can write data into or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0250] DRAM 2004 can be a buffer memory used to mitigate or buffer the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 included in the electronic system 2000 can also be a cache memory and can also provide space for temporary data storage during control operations of the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003, controller 2002 may also include a DRAM controller for controlling DRAM 2004.

[0251] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 disposed on the package substrate 2100, an adhesive layer 2300 located on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0252] The package substrate 2100 may be a printed circuit board including pads 2130 on the package. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may be connected to... Figure 23 The input / output pads 1101 correspond to each other. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include a reference... Figures 1 to 22 The semiconductor device described.

[0253] In an embodiment, the connection structure 2400 may be a bonding lead that electrically connects one of the input / output pads 2210 to a corresponding pad 2130 on the package. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding lead type, and the semiconductor chips 2200 may be electrically connected to the package pads 2130 on the package substrate 2100. According to an embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including a through-silicon via (TSV) instead of a bonding lead type connection structure 2400.

[0254] In one embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate insert substrate, different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected via wiring on the insert substrate.

[0255] Figure 25 and Figure 26 These are schematic cross-sectional views of a semiconductor package according to an example embodiment. Figure 25 and Figure 26 They described respectively Figure 24 An embodiment of the semiconductor package 2003 is shown, and conceptually illustrated by cutting along line I-I'. Figure 24 The area obtained by semiconductor packaging in 2003.

[0256] Reference Figure 25 In the semiconductor package 2003, the package substrate 2100 can be a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120, an upper package pad 2130 located on the upper surface of the package substrate body portion 2120, a lower package pad 2125 disposed on or exposed through the lower surface of the package substrate body portion 2120, and internal wiring 2135 electrically connecting the upper package pad 2130 and the lower package pad 2125 within the package substrate body portion 2120. The upper package pad 2130 can be electrically connected to a connection structure 2400. The lower package pad 2125 can be connected via a conductive connection portion 2800 to, for example,... Figure 24 Wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 shown.

[0257] Semiconductor chip 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, a separation structure 3230, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see reference). Figure 23 The gate connection wiring of ).

[0258] In the semiconductor chip 2200 or the semiconductor device according to the embodiment, a first layer can be formed before a subsequent partial etching process to prevent damage that may occur in the subsequent partial etching process, and to stably form vias with a relatively large depth in the subsequent partial etching process. This improves the reliability and productivity of the semiconductor chip 2200 or the semiconductor device.

[0259] Each of the semiconductor chips 2200 may include a through-wire 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through-wire 3245 may penetrate the gate stack structure 3210 and may also be disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may further include: an input / output connection wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200; and an input / output pad 2210 electrically connected to the input / output connection wiring 3265.

[0260] In one embodiment, within the semiconductor package 2003, a plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure 2400 having a bonding lead type. In another embodiment, the plurality of semiconductor chips 2200 or multiple portions constituting the plurality of semiconductor chips 2200 may be electrically connected via a connection structure including a through-silicon via (TSV).

[0261] Reference Figure 26 In the semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding type.

[0262] The first structure 4100 may include a peripheral circuit region comprising peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 penetrating the gate stack structure 4210, a separation structure 4230, and a word line WL electrically connected to the channel structure 4220 and the gate stack structure 4210 (see reference). Figure 23The second bonding structure 4250. For example, the second bonding structure 4250 can be electrically connected to the channel structure 4220 and the word line WL via a bit line 4240 electrically connected to the channel structure 4220 and a gate connection wiring electrically connected to the word line WL. The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 can contact and bond to each other. For example, the portion of the first bonding structure 4150 and the second bonding structure 4250 that bonds the first bonding structure 4150 and the second bonding structure 4250 may include copper (Cu).

[0263] In the semiconductor chip 2200a or the semiconductor device according to the embodiment, a first layer can be formed before a subsequent partial etching process, which can prevent damage that may occur in the subsequent partial etching process, and vias with a relatively large depth can be stably formed in the subsequent partial etching process. This improves the reliability and productivity of the semiconductor chip 2200a or the semiconductor device.

[0264] Each of the semiconductor chips 2200a may further include an input / output pad 2210 and an input / output connection wiring 4265 located at the lower part of the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0265] In one embodiment, within the semiconductor package 2003A, a plurality of semiconductor chips 2200a can be electrically connected to each other via a connection structure 2400 having a bonding lead type. In another embodiment, the plurality of semiconductor chips 2200a, or multiple portions constituting the plurality of semiconductor chips 2200a, can be electrically connected via a connection structure including a through-silicon via (TSV).

[0266] Although some examples have been described in conjunction with embodiments that are now considered practical, it is to be understood that this disclosure is not limited to the disclosed embodiments, and this disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A memory cell structure located in the cell array region; An electrode stack structure comprising a plurality of electrodes and a plurality of interlayer insulating layers that are stacked alternately with each other at least in the connection region; as well as Multiple electrode contact portions, which pass through or penetrate at least a portion of the electrode stack structure and are electrically connected to the multiple electrodes respectively. The plurality of electrode contact portions include: The first contact portion includes a first conductive portion and a first side insulating layer between the electrode stack structure and the first conductive portion; and The second contact portion includes a second conductive portion and a second side insulating layer between the electrode stack structure and the second conductive portion, and The second side insulating layer has a shape or structure that is different from that of the first side insulating layer.

2. The semiconductor device according to claim 1, further comprising: Multiple through-holes, which pass through or penetrate the electrode stack structure separately or individually and are spaced apart from each other, are inserted between the electrode stack structure. The plurality of electrode contact portions are respectively disposed in the plurality of through holes.

3. The semiconductor device according to claim 1, wherein, The first side insulating layer includes a first part and a second part, wherein the thickness of the second part is less than the thickness of the first part.

4. The semiconductor device according to claim 3, in, The first contact portion includes multiple first contact portions with different depths. The second contact portion includes multiple second contact portions with different depths, and The depth of each of the plurality of first contact portions is greater than the depth of each of the plurality of second contact portions.

5. The semiconductor device according to claim 3, in, A first portion of the first side insulating layer is disposed at the upper part of the first contact portion and is spaced apart from the lower surface of the first contact portion. The second portion of the first side insulating layer is disposed at the lower part of the first portion or below the first portion.

6. The semiconductor device according to claim 3, wherein, A first portion of the first side insulating layer is spaced apart from the lower surface of the first contact portion, while a portion corresponding to at least one of the plurality of electrodes is inserted therebetween.

7. The semiconductor device according to claim 3, wherein, In the first contact portion, the number of electrodes corresponding to the second portion among the plurality of electrodes is greater than the number of electrodes corresponding to the first portion among the plurality of electrodes.

8. The semiconductor device according to claim 3, in, The inner surface of the first side insulating layer includes an inclined surface that is tilted relative to the vertical direction or a vertical surface that is parallel to the vertical direction, and The outer surface of the first side insulating layer includes an inclined surface that is tilted relative to the vertical direction or a vertical surface that is parallel to the vertical direction, and has a step due to the thickness difference between the first portion and the second portion.

9. The semiconductor device according to claim 3, wherein, In a direction perpendicular to the side surface of the first side insulating layer, the difference between the thickness of the first portion and the thickness of the second portion is 0.5 nm or greater.

10. The semiconductor device according to claim 3, in, In the direction perpendicular to the side surface of the first side insulating layer, the ratio of the thickness of the second portion to the thickness of the first portion is in the range of 0.5 to 1, or Wherein, in the direction perpendicular to the side surface of the first side insulating layer, the difference between the thickness of the first portion and the thickness of the second portion is less than the thickness of the second portion.

11. The semiconductor device according to claim 3, wherein, In a direction perpendicular to the side surface of the first side insulating layer, the difference between the thickness of the first portion and the thickness of the second portion is less than the thickness of one of the plurality of interlayer insulating layers or the thickness of one of the plurality of electrodes.

12. The semiconductor device according to claim 3, wherein, The second side insulation layer includes portions that have the same material, structure, or thickness as the first portion throughout.

13. The semiconductor device according to claim 1, in, Each of the first side insulating layer and the second side insulating layer includes a first layer on the side surface of the electrode stack structure and a second layer on the first layer, and The arrangement or relative position of the first and second layers in the first side insulation layer is different from that in the second side insulation layer.

14. The semiconductor device according to claim 13, in, The first layer and the second layer may consist of the same material or different materials. The first layer comprises silicon oxide, silicon oxynitride, a low-dielectric-constant material having a dielectric constant lower than that of silicon oxide, or a combination thereof, or is formed of silicon oxide, silicon oxynitride, a low-dielectric-constant material having a dielectric constant lower than that of silicon oxide, or a combination thereof. The second layer comprises silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof, or is formed of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof.

15. The semiconductor device according to claim 1, in, The first side insulating layer includes a first portion and a second portion, wherein the thickness of the second portion is less than the thickness of the first portion, and The first part includes a first insulating part and a second insulating part, wherein the second insulating part has a thickness smaller than that of the first insulating part and is disposed between the first insulating part and the second part.

16. The semiconductor device according to claim 1, in, The plurality of electrodes includes a plurality of gate electrodes, and The memory cell structure includes the electrode stack structure and the channel structure, wherein the channel structure extends through or penetrates the electrode stack structure.

17. An electronic system comprising: Main substrate; A semiconductor device located on the main substrate; as well as The controller is electrically connected to the semiconductor device on the main substrate. The semiconductor device includes: A memory cell structure located in the cell array region; An electrode stack structure comprising a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked at least in a connection region; and Multiple electrode contact portions, which pass through or penetrate at least a portion of the electrode stack structure and are electrically connected to the multiple electrodes respectively. The plurality of electrode contact portions include: The first contact portion includes a first conductive portion and a first side insulating layer between the electrode stack structure and the first conductive portion; and The second contact portion includes a second conductive portion and a second side insulating layer between the electrode stack structure and the second conductive portion, and The second side insulating layer has a shape or structure that is different from that of the first side insulating layer.

18. A semiconductor device, comprising: A memory cell structure located in the cell array region; An electrode stack structure comprising a plurality of electrodes and a plurality of interlayer insulating layers that are stacked alternately with each other at least in the connection region; as well as Multiple electrode contact portions, which pass through or penetrate at least a portion of the electrode stack structure, and are electrically connected to the multiple electrodes respectively. Wherein, at least one of the plurality of electrode contact portions includes a conductive portion and a side insulating layer between the electrode stack structure and the conductive portion, and The side insulating layer includes a first part and a second part. The first part is disposed at the upper part of at least one of the plurality of electrode contact parts, and the second part has a thickness smaller than that of the first part and is disposed at the lower part of the first part or below the first part.

19. The semiconductor device according to claim 18, wherein, A first portion of the side insulating layer is spaced apart from the lower surface of at least one of the plurality of electrode contact portions, while a portion corresponding to at least one of the plurality of electrodes is inserted therebetween.

20. The semiconductor device according to claim 18, in, In a direction perpendicular to the side surface of the side insulating layer, the difference between the thickness of the first portion and the thickness of the second portion is 0.5 nm or greater, or Wherein, in the direction perpendicular to the side surface of the side insulating layer, the ratio of the thickness of the second portion to the thickness of the first portion is in the range of 0.5 to 1, or Wherein, in the direction perpendicular to the side surface of the side insulating layer, the difference between the thickness of the first portion and the thickness of the second portion is less than the thickness of the second portion.

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