Trench gate super junction device

Abstract

The trench gate super junction device is characterized in that an active region structurally comprises a super junction structure, a first well region, a trench gate and a source region, a source electrode contact hole penetrating through an interlayer film is formed in the top of the source region, and the bottom of the source electrode contact hole penetrates through the source region and is in contact with the first well region. The first distance between the source electrode contact hole and the side face of the adjacent trench gate is reduced to 0.5-0.6 micrometer, and the reduction value of the first distance is the width increase value of the source electrode contact hole under the condition that the stepping of the device unit is not changed and the width of the trench gate is not changed. According to the invention, under the condition that the stepping of the device unit and the width of the trench gate are not changed, the source contact resistance is reduced to the greatest extent, and the current density of the source contact hole is reduced at the same time, so that the specific on-resistance can be reduced and the EAS capability can be optimized at the same time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a trench gate superjunction device. Background Technology

[0002] Compared to existing traditional VDMOS, superjunction MOSFETs have been widely used in various electronic and power fields due to their superior device characteristics. Because the special N-type and P-type pillars in the superjunction MOSFET structure compensate for each other, the area of ​​the built-in electric field in the PN junction is expanded, allowing for high breakdown voltages in denser N-type epitaxial layers (NEPI). Therefore, it exhibits low on-resistance and high breakdown voltage exceeding the Si limit.

[0003] Currently, there are two main manufacturing processes for superjunction MOSFET devices: one is the multiple epitaxial doping process, which involves forming a breakdown layer through multiple epitaxial layers, with either P-type or PN doping types in each layer, ultimately resulting in a structure with alternating P-type and N-type pillars; the other is the deep trench filling process, which involves etching and filling deep trenches on a thick N-epitaxial layer to form a structure with alternating P-type and N-type pillars. The multiple epitaxial doping process has a relatively fixed epitaxial thickness for each layer, and the number of epitaxial layers increases with the breakdown voltage, leading to higher costs. In contrast, the existing deep trench filling process more easily achieves a smaller aspect ratio, and the resulting superjunction N and P regions have a more uniform doping distribution, which is beneficial for reducing Rsp. More importantly, this process is simpler and less expensive.

[0004] Existing deep trench superjunction MOSFET devices are further classified into planar gate and trench gate devices based on the location of the gate. The gate of a planar gate superjunction MOSFET is formed by growing SiO2 on the surface of a Si epitaxial layer and depositing polysilicon. In contrast, the gate of a trench gate superjunction MOSFET is formed by etching a trench on the surface of a Si epitaxial layer and then filling the trench with SiO2 and polysilicon. Planar gate devices have a relatively simple manufacturing process, better cell uniformity, and good single-pulse avalanche breakdown (EAS) capability, i.e., good avalanche energy withstand capability. However, this structure exhibits the JFET effect, which leads to an increase in specific on-resistance. Simultaneously, planar gate devices also have a larger parasitic capacitance.

[0005] Trench gate devices, with their gate structure built within the Si epitaxial layer, allow for further reduction in cell size and increased channel density. Furthermore, this structure eliminates the JFET effect, significantly reducing specific on-resistance and thus improving system efficiency while achieving device miniaturization and cost optimization. Additionally, trench gate devices exhibit smaller parasitic capacitance, faster switching speeds, and significantly reduced switching losses. However, the increased etching and filling steps in trench gates complicate the manufacturing process, resulting in poorer cell uniformity compared to planar gate devices and consequently, a decrease in energy efficiency performance (EAS). Existing data indicates that the EAS limit of trench gate superjunction MOSFETs is only 50% of that of planar gate superjunction MOSFETs. With the development of superjunction MOSFETs, reducing the specific on-resistance of trench gate devices while simultaneously improving their EAS capability becomes increasingly important.

[0006] like Figure 1 The diagram shown is a schematic of an existing trench gate superjunction device. Taking an N-type trench gate superjunction MOSFET as an example, existing trench gate superjunction devices include: The active region 101a, the terminal region 101c surrounding the active region 101a, and the transition region 101b between the active region 101a and the terminal region 101c, the transition region 101b belonging to the terminal region 101c, but marked separately by the label 101b to more clearly indicate the transition region.

[0007] The active region 101a, the transition region 101b, and the terminal region 101c all have superjunction structures, including: alternating N-type pillars and P-type pillars 103; the bottom of the superjunction structure has an N-type doped buffer layer.

[0008] P-type pillar 103 consists of a second epitaxial layer doped with P-type filling the superjunction trench.

[0009] The superjunction trench is formed in the N-type doped first epitaxial layer 102, and the N-type pillars are composed of the first epitaxial layer 102 between the P-type pillars 103. The buffer layer is composed of the first epitaxial layer 102 located at the bottom of the superstructure.

[0010] The first epitaxial layer 102 is formed on the top surface of the heavily N-type doped semiconductor substrate 101. The semiconductor substrate 101 is thinned to serve as the drain region.

[0011] In the active region 101, a P-type doped first well region 104 is formed in the surface region of the superjunction structure, and the first well region 104 serves as the channel region of the device. A trench gate is provided on the top of each N-type pillar, and the trench gate extends longitudinally through the first well region 104. The surface of the first well region 104, which is covered by the side of the trench gate, is used to form a conductive channel.

[0012] The trench gate includes a gate trench, a gate oxide layer 106 formed on the inner surface of the gate trench, and a polysilicon gate 107 filled in the gate trench.

[0013] The N-type heavily doped source region 108 is formed in the surface region of the first well region 104 and is aligned with the side of the corresponding trench gate.

[0014] A source contact hole is formed at the top of the source region 108, penetrating the interlayer film 109. The bottom of the source contact hole penetrates the source region 108 and contacts the first well region 104. The side of the source region 108 contacts the source contact hole. The source contact hole includes a blocking layer 112 composed of stacked Ti and TiN layers filling the inner surface of the source contact hole opening 110, and a tungsten layer 113 filling the source contact hole opening 110.

[0015] A P-type heavily doped well contact region 111 is also formed at the bottom of the source contact hole.

[0016] In the transition region 101b, a second well region 104a with P-type doping is formed in the surface region of the superjunction structure.

[0017] Depend on Figure 1 As shown, the top of the source contact hole is connected to the source, which is composed of the front metal layer 114. The polysilicon gate 117 is connected to the gate, which is composed of the front metal layer 114, through the corresponding gate contact hole (not shown) at the top.

[0018] After the semiconductor substrate 101 is thinned, a drain region of the device is formed, and a drain electrode composed of a back metal layer 117 is formed on the back side of the drain region.

[0019] A field oxide layer 105 is formed on the top surface of the first epitaxial layer 102, in which a superjunction structure is formed in the termination region 101c. The field oxide layer 105 extends into the transition region 101b. An N-type heavily doped stop region 108a is formed on the outermost side of the termination region 101c. The stop region 108a is typically formed simultaneously with the source region 108 using the same process. The field oxide layer 105 on top of the stop region 108a is removed.

[0020] Multiple polysilicon field plates 107a are formed on the top surface of the field oxide layer 105. Some of the polysilicon field plates 107a are connected to the metal field plate composed of the front metal layer 114 through contact holes formed in the contact hole opening 110a. Some of the polysilicon field plates 107a are suspended.

[0021] The top of the cutoff region 108a is connected to a cutoff electrode composed of a front-side metal layer 114 through a contact hole formed in the contact hole opening 110b. The cutoff electrode is typically connected to the drain electrode. The bottom of the contact hole at the top of the cutoff region 108a also extends through the cutoff region 108a to make contact with the first epitaxial layer 102 at the bottom.

[0022] A passivation layer 115 and a protective layer 116 are also formed in the transition region 101b and the terminal region 101c. In some embodiments, the material of the passivation layer 115 includes silicon oxide, and the material of the protective layer 116 includes polyimide.

[0023] Compared to planar gate devices, trench gate devices involve additional etching and filling steps for the gate trench, resulting in a more complex process, poorer consistency, and reduced EAS capability. Only by further reducing the specific on-resistance of trench gate superjunction devices and improving their EAS capability can they gain a cost and performance advantage in the fierce market competition. Summary of the Invention

[0024] The technical problem to be solved by the present invention is to provide a trench gate superjunction device that can minimize the source contact resistance and simultaneously reduce the current density of the source contact hole while ensuring that the device cell step size and the trench gate width remain unchanged, thereby simultaneously reducing the specific on-resistance and optimizing the EAS capability.

[0025] To solve the above-mentioned technical problems, the active region structure of the trench gate superjunction device provided by the present invention includes: A superjunction structure includes: alternating first conductivity type pillars and second conductivity type pillars; the bottom of the superjunction structure has a buffer layer doped with the first conductivity type.

[0026] The first well region, doped with the second conductivity type, is formed in the surface region of the superjunction structure.

[0027] Each of the first conductive type pillars has a trench gate at its top, the trench gate extending longitudinally through the first well region, and the surface of the first well region covered by the side of the trench gate is used to form a conductive channel.

[0028] The heavily doped source region of the first conductivity type is formed in the surface region of the first well region and is aligned with the side of the corresponding trench gate.

[0029] The device unit step is equal to the width and spacing of the trench gate.

[0030] A source contact hole is formed at the top of the source region, passing through the interlayer membrane. The bottom of the source contact hole passes through the source region and contacts the first well region. The side of the source region contacts the source contact hole.

[0031] The first spacing between the source contact hole and the adjacent side of the trench gate is reduced to 0.5 micrometers to 0.6 micrometers. Under the condition that the device cell step size and the width of the trench gate remain unchanged, the reduction value of the first spacing is the increase value of the width of the source contact hole. By increasing the width of the source contact hole, the source contact resistance and the current density of the source contact hole are reduced simultaneously, so as to simultaneously reduce the specific on-resistance and optimize the EAS capability.

[0032] A further improvement is that the source contact hole is located at a depth of 100 angstroms to 400 angstroms below the top surface of the superjunction structure.

[0033] A further improvement is that a heavily doped well contact region of a second conductivity type is also formed at the bottom of the source contact hole.

[0034] A further improvement is that deep-level defect impurities are incorporated into the semiconductor material lattice of the superjunction structure at the bottom of the source contact hole, or at the bottom of the first well region and the first well region, to improve the reverse recovery characteristics of the body diode.

[0035] A further improvement is that the deep-level defect impurity includes Pt.

[0036] A further improvement is that the source contact hole includes a blocking layer composed of a Ti layer and a TiN layer stacked together, which fills the inner surface of the source contact hole opening, and a tungsten layer that fills the source contact hole opening.

[0037] A further improvement is that a terminal region is surrounded around the active region, and the superjunction structure is also provided in the terminal region.

[0038] The terminal area includes a transition area adjacent to the active area.

[0039] In the transition region, a second well region doped with a second conductivity type is formed in the surface region of the superjunction structure.

[0040] A further improvement is that the first well region and the second well region are formed independently; or the first well region and the second well region are formed simultaneously using the same process.

[0041] A further improvement is that the second conductivity type pillar is composed of a second epitaxial layer doped with the second conductivity type and filled in the superjunction trench.

[0042] The superjunction trench is formed in a first epitaxial layer doped with a first conductivity type, and the first conductivity type pillar is composed of the first epitaxial layer between the second conductivity type pillars.

[0043] The buffer layer consists of the first epitaxial layer located at the bottom of the superstructure.

[0044] The first epitaxial layer is formed on the top surface of a semiconductor substrate heavily doped with a first conductivity type.

[0045] A further improvement is that the semiconductor substrate is made of silicon, the first epitaxial layer is made of silicon, and the second epitaxial layer is made of silicon.

[0046] A further improvement is that the trench gate includes a gate trench, a gate oxide layer formed on the inner surface of the gate trench, and a polysilicon gate filling the gate trench.

[0047] A further improvement is that the width of the gate trench is 0.6 micrometers to 1.5 micrometers and the depth is 2 micrometers to 4 micrometers.

[0048] A further improvement is that the trench gate superjunction device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the trench gate superjunction device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0049] A further improvement is that the trench gate superjunction device is an N-type device, and the doped impurities in the well contact region formed at the bottom of the source contact hole are BF2 and / or B, with an implantation energy of 20keV to 60keV and an implantation dose of 5e14cm. -2 ~1e15cm -2 The injection energy for B is 20keV–60keV, and the injection dose is 1e13cm. -2 ~1e15cm -2 .

[0050] A further improvement is that the injected impurity in the first well region includes B, the injection energy is 60keV to 180keV, and the injection dose is 1e11cm. -2 ~1e14cm -2 The number of injections is 1, 2, or 3.

[0051] This invention breaks through the conventional thinking that limits the spacing between the source contact hole and the trench gate (i.e., the first spacing). By reducing the first spacing to 0.5 micrometers to 0.6 micrometers, it is possible to increase the width of the source contact hole without increasing the device cell step size or reducing the width of the trench gate. This means that the device cell step size and the width of the trench gate remain unchanged. The increased width of the source contact hole increases the contact area with the bottom source region and the first well region, thereby reducing the source contact resistance and thus reducing the specific on-resistance of the device. At the same time, the increased width of the source contact hole also reduces the current density of the source contact hole while keeping the source current constant, thus optimizing the device's EAS capability. Therefore, this invention can maximize the reduction of source contact resistance and simultaneously reduce the current density of the source contact hole while keeping the device cell step size and the width of the trench gate constant, thereby simultaneously reducing the specific on-resistance and optimizing the EAS capability.

[0052] The device unit step of the present invention remains unchanged, which can ensure that the integration level of the device and the chip area remain unchanged.

[0053] The trench gate width of the present invention remains unchanged, which can prevent the adverse effects of the reduction of trench gate width on the increase of process complexity, thereby ensuring the consistency of device cells and preventing the deterioration of EAS capability caused by the deterioration of device cell consistency. Attached Figure Description

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the structure of an existing trench gate superjunction device; Figure 2 This is a schematic diagram of the trench gate superjunction device according to an embodiment of the present invention; Figures 3A-3I This is a schematic diagram of the device structure in each step of the method for manufacturing the trench gate superjunction device according to an embodiment of the present invention. Detailed Implementation

[0055] like Figure 2 The diagram shown is a structural schematic of a trench gate superjunction device according to an embodiment of the present invention; the structure of the active region 201a of the trench gate superjunction device according to an embodiment of the present invention includes: The superjunction structure includes: alternating first conductivity type pillars and second conductivity type pillars 203; the bottom of the superjunction structure has a buffer layer doped with the first conductivity type.

[0056] In this embodiment of the invention, the second conductivity type pillar 203 is composed of a second epitaxial layer doped with the second conductivity type and filled in the superjunction trench.

[0057] The superjunction trench is formed in the first epitaxial layer 202 doped with the first conductivity type, and the first conductivity type pillar is composed of the first epitaxial layer 202 between the second conductivity type pillars 203.

[0058] The buffer layer consists of a first epitaxial layer 202 located at the bottom of the superstructure.

[0059] The first epitaxial layer 202 is formed on the top surface of a heavily doped semiconductor substrate 201 of the first conductivity type.

[0060] In this embodiment of the invention, the semiconductor substrate 201 is made of silicon, the first epitaxial layer 202 is made of silicon, and the second epitaxial layer is made of silicon.

[0061] The first well region 204, doped with the second conductivity type, is formed in the surface region of the superjunction structure.

[0062] Each first conductive type pillar has a trench gate at its top, the trench gate extending longitudinally through the first well region 204, and the surface of the first well region 204 covered by the side of the trench gate is used to form a conductive channel.

[0063] In this embodiment of the invention, the trench gate includes a gate trench, a gate oxide layer 206 formed on the inner surface of the gate trench, and a polysilicon gate 207 filled in the gate trench.

[0064] In some embodiments, the width of the gate trench is 0.6 micrometers to 1.5 micrometers and the depth is 2 micrometers to 4 micrometers.

[0065] A heavily doped source region 208 of the first conductivity type is formed in the surface region of the first well region 204 and is aligned with the side of the corresponding trench gate.

[0066] The device cell step is the width and spacing of the trench gate.

[0067] A source contact hole is formed at the top of the source region 208, passing through the interlayer membrane 209. The bottom of the source contact hole passes through the source region 208 and contacts the first well region 204. The side of the source region 208 contacts the source contact hole.

[0068] The first spacing L1 between the source contact hole and the side of the adjacent trench gate is reduced to 0.5 μm to 0.6 μm. Under the condition that the device cell step and the trench gate width remain unchanged, the reduction value of the first spacing L1 is the increase value of the width of the source contact hole. By increasing the width of the source contact hole, the source contact resistance and the current density of the source contact hole are reduced at the same time, so as to simultaneously reduce the specific on-resistance and optimize the EAS capability.

[0069] In this embodiment of the invention, the source contact hole includes a blocking layer 212 composed of a Ti layer and a TiN layer that fills the inner surface of the source contact hole opening 210, and a tungsten layer 213 that fills the source contact hole opening 210.

[0070] In some embodiments, the source contact hole is located at a depth of 100 angstroms to 400 angstroms below the top surface of the superjunction structure.

[0071] In this embodiment of the invention, a heavily doped well contact region 211 of a second conductivity type is also formed at the bottom of the source contact hole. In some embodiments, taking the trench gate superjunction device as an N-type device as an example, the dopant of the well contact region 211 formed at the bottom of the source contact hole is BF2 and / or B, the implantation energy of BF2 is 20keV to 60keV, and the implantation dose is 5e14cm. -2 ~1e15cm -2 The injection energy for B is 20keV–60keV, and the injection dose is 1e13cm. -2 ~1e15cm -2 .

[0072] Deep-level defect impurities are incorporated into the semiconductor material lattice of the superjunction structure at the bottom of the source contact hole, either the first well region 204 or the first well region 204 and the bottom of the first well region 204, to improve the reverse recovery characteristics of the body diode. In some embodiments, the deep-level defect impurities include Pt.

[0073] In this embodiment of the invention, a terminal region 201c surrounds the active region 201a, and a superjunction structure is also provided in the terminal region 201c.

[0074] The terminal region 201c includes a transition region 201b adjacent to the active region 201a. The active region 201a is also the current flow region. The transition region 201b belongs to the terminal region 201c, but is marked separately with the symbol 201b to more clearly indicate the transition region.

[0075] In the transition region 201b, a second well region 204a, doped with a second conductivity type, is formed in the surface region of the superjunction structure. In this embodiment of the invention, the first well region 204 and the second well region 204a are processed independently; thus, the doping of the first well region 204 and the second well region 204a can be independently adjusted according to their own requirements. For example, the doping distribution of the first well region 204 can be adjusted according to the threshold voltage requirement. In other embodiments, the first well region 204 and the second well region 204a can also be formed simultaneously using the same process, which reduces the number of process steps and lowers the process cost.

[0076] In some embodiments, taking the trench gate superjunction device as an N-type device as an example, the implanted impurity in the first well region 204 includes B, the implantation energy is 60keV to 180keV, and the implantation dose is 1e11cm. -2 ~1e14cm -2 The number of injections is 1, 2, or 3.

[0077] In this embodiment of the invention, the trench gate superjunction device is an N-type device, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the trench gate superjunction device can also be a P-type device, with P-type as the first conductivity type and N-type as the second conductivity type.

[0078] Depend on Figure 2 As shown, the top of the source contact hole is connected to the source, which is composed of the front metal layer 214. The polysilicon gate 217 is connected to the gate, which is composed of the front metal layer 214, through the corresponding gate contact hole (not shown) at the top.

[0079] After the semiconductor substrate 201 is thinned, a drain region of the device is formed, and a drain electrode composed of a back metal layer 217 is formed on the back side of the drain region.

[0080] A field oxide layer 205 is formed on the top surface of the first epitaxial layer 202, in which a superjunction structure is formed in the termination region 201c. The field oxide layer 205 extends into the transition region 201b. A heavily doped stop region 208a of a first conductivity type is formed on the outermost side of the termination region 201c. The stop region 208a is typically formed simultaneously with the source region 208 using the same process. The field oxide layer 205 on top of the stop region 208a is removed.

[0081] Multiple polysilicon field plates 207a are formed on the top surface of the field oxide layer 205. Some of the polysilicon field plates 207a are connected to the metal field plate composed of the front metal layer 214 through contact holes formed in the contact hole openings 210a. Some of the polysilicon field plates 207a are suspended.

[0082] The top of the cutoff region 208a is connected to the cutoff electrode, which is composed of the front metal layer 214, through a contact hole formed in the contact hole opening 210b. The cutoff electrode is typically connected to the drain electrode. The bottom of the contact hole at the top of the cutoff region 208a also extends through the cutoff region 208a to make contact with the first epitaxial layer 202 at the bottom.

[0083] A passivation layer 215 and a protective layer 216 are also formed in the transition region 201b and the terminal region 201c. In some embodiments, the material of the passivation layer 215 includes silicon oxide, and the material of the protective layer 216 includes polyimide.

[0084] This invention breaks through the conventional thinking that limits the spacing between the source contact hole and the trench gate, i.e., the first spacing L1, by reducing the first spacing L1 to 0.5 micrometers to 0.6 micrometers. This allows for an increase in the width of the source contact hole by reducing the first spacing L1, without increasing the device cell step size or reducing the trench gate width—that is, while maintaining the same device cell step size and trench gate width. The increased width of the source contact hole increases the contact area with the bottom source region 208 and the first well region 204, thereby reducing the source contact resistance and thus lowering the specific on-resistance of the device. Simultaneously, the increased width of the source contact hole also reduces the current density of the source contact hole while maintaining the same source current, thus optimizing the device's EAS capability. Therefore, this invention can maximize the reduction of source contact resistance and simultaneously reduce the current density of the source contact hole while maintaining the same device cell step size and trench gate width, thereby simultaneously reducing specific on-resistance and optimizing EAS capability.

[0085] The device unit stepping in this embodiment of the invention remains unchanged, which ensures that the device integration level and chip area remain unchanged.

[0086] The trench gate width remains unchanged in this embodiment of the invention, which can prevent the adverse effects of reduced trench gate width on increased process complexity, thereby ensuring the consistency of device cells and preventing the deterioration of EAS capability caused by poor consistency of device cells.

[0087] exist Figure 1 In existing trench gate superjunction devices, the spacing L0 between the trench gate and the source contact hole is approximately 0.8 μm to 1 μm. This spacing ensures sufficient distance between the trench gate and the source contact hole, thus avoiding the adverse effects of too small a spacing, such as preventing short circuits between the trench gate and the source contact hole, and preventing the source contact hole from affecting the threshold voltage of the channel on the side of the trench gate. However, increasing the spacing L0 limits the width of the contact hole (CT), which is not conducive to reducing the CT contact resistance and specific on-resistance. In addition, a smaller CT width leads to an increase in local current density, making it more prone to EAS failures such as metallization layer melting and local overheating of the silicon die. In this embodiment of the invention, by reducing the distance L1 between the CT and the gate, that is, reducing L1 to 0.5 µm to 0.6 µm, more space is provided for designing a wider CT. Figure 2 The contact hole opening 210 can be expanded. The wider CT design increases the contact area between the CT and the Si epitaxial layer, reducing contact resistance and thus lowering the specific on-resistance of the device. Furthermore, the increased trench cross-sectional area of ​​the CT reduces the current density per unit area. Under the same avalanche current, the current is more dispersed, preventing EAS failures such as localized current concentration leading to overheating of the silicon crystal structure or metal layer melting. This improves current carrying capacity and heat conduction efficiency, thereby enhancing the device's EAS capability.

[0088] The following is a combination of manufacturing Figure 2 The method for the trench gate superjunction device of the present invention shown in the embodiment further illustrates the trench gate superjunction device of the present invention. The following examples all use a 600V N-type trench gate superjunction MOSFET as an example. The wafer fabrication process includes the following steps: Step 1. As Figure 3A As shown, a first N-type doped epitaxial layer 202 with high resistivity (e.g., 0.5–5 ohm*cm) is first grown on a highly doped semiconductor substrate 201. The thickness of the first epitaxial layer 202 is 45–50 µm. The highly doped semiconductor substrate 201 uses phosphorus (P) or arsenic (As) as the dopant, with As atoms being the most common substrate dopant. This reduces the interface state density and the diffusion of N+ substrate impurities to the breakdown layer during subsequent thermal processes. The doping concentration of the semiconductor substrate 201 is 1e19 / cm². 2 The purpose of the above is to reduce the substrate resistance. The first epitaxial layer 202 can be doped with one, two, three, or gradually varying doping concentrations. In actual production design, the resistivity variation of the first epitaxial layer 202, the specific doping concentrations, and the interrelationships between doping atom types can be simulated using computer-aided design software like TCAD. Taking a first epitaxial layer 202 with two doping concentrations as an example, the resistivity at the top of the first epitaxial layer 202 is approximately 0.8–0.95 ohm·cm, and the resistivity at the bottom of the first epitaxial layer 202 is approximately 0.95–1.1 ohm·cm, corresponding to phosphorus (P) as the doping atom.

[0089] Step 2. As Figure 3B As shown, a second well region 204a can be formed in the transition region 201b of the chip near the active region 201a through photolithography and ion implantation. The ion implantation type of the second well region 204a is generally boron (B), the implantation energy is 40-200 keV, and the implantation dose is approximately 1e12-1e14 atoms / cm². 2 The second well region 204a can effectively improve the electric field distribution in the transition region 201b between the active region 201a and the terminal region 201c of the chip, thereby improving the reliability of the chip.

[0090] Step 3. As Figure 3CAs shown, a dielectric film is deposited on the first epitaxial layer 202 to form a hard mask. The hard mask can be a SiO2 layer with a thickness of 500 Å to 1000 Å, a SiN layer with a thickness of 300 Å to 1500 Å, or a SiO2 layer with a thickness of 2 µm to 5 µm. Then, several deep trenches with a certain aspect ratio, i.e., superjunction trenches, are formed in the first epitaxial layer 202 by photolithography. The width of the deep trench is set to 3.2 µm, the spacing between adjacent deep trenches is set to 3.8 µm, and the depth is set to 40 to 47 µm. Depending on the characteristics of different products and the selection of the epitaxial substrate, the width, spacing, and depth of the deep trenches can be adjusted accordingly. Generally, for the above-mentioned type of superjunction product with N-type epitaxy (i.e., the thickness of the first epitaxial layer 202 is 50 µm), the depth of the deep trench will not exceed 47 µm. A buffer layer of a certain thickness needs to be left at the bottom of the deep trench to improve the device's resistance to current surges. After etching the deep trench morphology, all SiO2 and SiN on top of the hard mask are removed, leaving the underlying SiO2 as a protective layer for the Si surface, i.e., the first epitaxial layer 202. Then, P-type ions can be implanted at the bottom of the deep trench to improve BVDSS. Commonly used P-type ions are B, with implantation energies of 90–180 keV and implantation doses of 1.0–5.0 e12 / cm². 2 Then, P-type silicon, i.e., the second conductivity type pillar 203, is completely epitaxially filled in the deep trench. The doping concentration of the P-type silicon is related to the doping concentration and structure of the N-epitaxial substrate. Subsequently, chemical mechanical polishing is used to remove all the Si on the surface.

[0091] Step 4. Figure 3DAs shown, a field oxide layer 205 of 2000–15000 Å is formed on top of the first epitaxial layer 202, which forms the second conductivity type pillars 203, on the Si epitaxial layer. Specifically, a single thermal oxidation can be performed directly on the silicon wafer (Si epitaxial wafer), with the thermal oxidation temperature set at 900–980°C and the thermal oxide film thickness set at 2000–15000 Å. Alternatively, a single thermal oxidation can be performed on the silicon wafer first, with the thermal oxidation temperature set at 900–980°C and the thermal oxide film thickness set at 500–2000 Å, followed by the deposition of an undoped CVD oxide film with a thickness of 2000–14000 Å. The latter can reduce the thermal process during chip fabrication and effectively reduce the interdiffusion of impurities between the P-type and N-type pillars, thereby effectively reducing the specific on-resistance of the chip. For N-type devices, the P-type pillars are the second conductivity type pillars 203, and the N-type pillars are the first conductivity type pillars. In addition, to obtain a better Si-SiO2 interface and improve the high-temperature reverse bias stress (HTRB) reliability of the device, a very thin oxide film of 30-100 Å can be deposited on the silicon wafer using atomic layer deposition (ALD) equipment, followed by thermal oxidation to form an oxide film of 2000-15000 Å. After the oxide film is grown, the film layer in the active region 201a needs to be removed by photolithography, dry etching, or wet etching, as well as the dielectric film in the outermost part of the terminal region 201c, i.e., the stop region 208a. In other parts of the transition region 201b and the terminal region 201c, the film layer can also be partially etched, leaving a dielectric film thickness of 2000-8000 Å. This film layer can prevent the device from being broken down by high voltage. Generally, the higher the BV of the device, the thicker the oxide film is required.

[0092] Step 5. Figure 3E As shown, several shallow trenches, i.e., gate trenches, are formed on the N-epitaxy layer through photolithography and etching. The width of the trenches is set to 0.6–1.5 µm, and the depth is set to 2–4 µm. A gate oxide layer 206 with a thickness of approximately 500 Å–2000 Å is then deposited. A polysilicon gate 207 is then formed through polysilicon deposition and etching. Alternatively, a polysilicon field plate 207a can be deposited in the transition region 201b and the termination region 201c through photolithography and etching to serve as a floating field plate, reducing the peak electric field on the chip termination surface, optimizing the electric field distribution, and improving the breakdown voltage of the chip termination.

[0093] Step 6. Figure 3F As shown, a P-type well, i.e., the first well region 204, is formed in the active region 201a by ion implantation. The implanted impurity is generally B, the implantation energy is 60-180 keV, and the implantation dose is 1e11cm. -2 ~1e14cm -2During production, the threshold voltage of the device can be affected by product characteristics, such as whether it is an irradiated or non-irradiated product, and other process adjustments. The target threshold voltage can be met by adjusting the implantation dose or energy of the first well region 204. This first well region 204 can also be implemented using two or three different energies of beta implantation, thus constructing different P-type wells and adjusting device performance parameters, including threshold voltage and EAS capability. After P-type well ion implantation, a high-temperature annealing process can be performed, such as annealing at 1100℃ for 30 minutes or at higher temperatures and for longer periods. This not only pushes the P-type well to the designated position but also repairs some damage caused during ion implantation.

[0094] Step 7. Figure 3G As shown, source region 8 is formed by photolithography and ion implantation of N-type impurities. Common N-type impurities include phosphorus and arsenic. For example, As is used at 60 keV, with 1–5e15 atoms / cm². 2 After ion implantation, an activation process at a temperature of 950°C or less, such as 900°C for 30 minutes, can be used, or a rapid thermal annealing (RTA) process can be employed. In addition to implanting N-type impurities into the active region 201a to form the source region 208, N-type impurities are also implanted into the outermost cutoff region 208a of the chip.

[0095] Step 8. Figure 3H As shown, the current metal electrode process mainly involves the deposition of an interlayer film 209, the etching and filling of contact hole openings (including source contact hole opening 210 and terminal contact hole openings 210a and 210b), and the metal electrode deposition process to form a semiconductor-metal ohmic contact. The contact hole consists of metal filling the contact hole opening. Specifically, a dielectric film is first deposited, for example, 2000 angstroms of undoped SiO2, followed by 8000-10000 angstroms of BPSG, and then the contact hole opening is formed by photolithography etching. In the existing structure, the distance from the contact hole to the gate is... Figure 1In the present invention, the distance L0 is approximately 0.8–1 µm. In this embodiment, the distance L1 is reduced to 0.5–0.6 µm. The aim is to design a wider contact hole width in the active region 201a while maintaining the same chip area. This reduces the contact resistance of the contact hole and the current density per unit area, while optimizing the specific on-resistance and EAS capability. In the active region 201a, the contact hole opening etches away the silicon in the high-concentration N-type region of the contact hole area, with an etching depth of 100–4000 angstroms. In the transition region 201b, the contact hole opening only needs to pass through the interlayer film 209 and the protective epoxide film, i.e., the field oxide layer 205. The etching depth of the polysilicon in the transition region 201b does not exceed 500 angstroms. Subsequently, BF2 or B, or both sequentially, are implanted into the bottom of the contact hole opening to form the P+ region, i.e., the well contact implantation region 211. For example, the BF2 can be set to 20–60 keV, 5e14–1e15 / cm2, and the B can be 20–60 keV, 1e13–1e15 / cm2. This better ensures ohmic contact between the subsequent metal and the Si at the bottom of the contact hole and reduces contact resistance. The ion implantation dose at the bottom of the CT cannot be too small, otherwise it will increase the chip's EAS failure.

[0096] Step 9. Figure 3H As shown, platinum (Pt) is then doped through the source contact hole opening 210 and annealed. Doping can be done via ion implantation or diffusion. The annealing temperature can be set to 800–950°C, allowing Pt atoms to diffuse and occupy interstitial or substituted sites in the silicon lattice, forming deep-level defects. This increases the carrier recombination rate, reduces the reverse recovery time, and improves the reverse recovery characteristics of the chip diode. In this step, the reverse recovery characteristics of the chip diode can be adjusted by optimizing the Pt doping concentration and annealing temperature.

[0097] Step 10. Figure 3IAs shown, a blocking layer 212 is formed by depositing a Ti layer and a TiN layer stacked together. One setting is that the thickness of the Ti layer is 300 Å to 500 Å, and the thickness of the TiN layer is 500 Å to 1000 Å, to prevent Si from dissolving in AlCu and forming sharp protrusions. The layer is then annealed. Next, a tungsten (W) layer 213 is deposited to fill the contact hole opening. The tungsten fills the contact hole opening by growing along the sidewall of the opening and contacting the central region of the opening. The contact area may or may not have gaps. The tungsten can completely fill the contact hole opening, or it may not, as long as the subsequent metal layer can effectively cover the opening. Then, a front-side metal layer 214, such as AlCu, is deposited. The deposition temperature can be set to 250–450 °C, and the thickness can be set to 2–6 µm. Finally, the AlCu, the underlying W, and the blocking layer 212 are completely removed using metal photolithography and dry etching. In the metal etching step, the metals in the active region 201a, transition region 201b, and terminal region 201c need to be separated. The metal in the transition region 201b can be a single piece, or it can be two or three separate pieces, etc. The metal in the terminal region 201c can be separated, or it can be continuous, or there can be no metal forming a field plate.

[0098] Step 11. Figure 2 The diagram illustrates the fabrication process of passivation layer 215 and protective layer 216. Typically, a high-density silicon oxide layer is deposited under plasma conditions as the passivation layer 215, followed by the deposition of a thicker polyimide film as the protective layer 216. Photolithography and development are then used to form a protective pattern covering the terminal region 201c, transition region 201b, and part of the active region 201a. The thickness of the polyimide layer after baking is 4–15 µm. Next, backside thinning is performed, resulting in a silicon wafer (semiconductor substrate) thickness of 60–200 µm. A backside metal layer 217 is then deposited to form the drain. The backside metal layer 217 can be TiNiAg, with thicknesses set to 1000 Å for Ti, 2000 Å for Ni, and 10000 Å for Ag.

[0099] In some improved embodiments, electron irradiation can also be performed to improve the reverse recovery characteristics of the chip's body diode if Pt is not deposited and thermally diffused in step 9. Electron irradiation can be performed after the passivation layer process, followed by the polyimide process; however, processes such as polyimide baking may affect the effectiveness of electron irradiation. Alternatively, electron irradiation can be introduced after the polyimide process, followed by setting appropriate dosage and annealing conditions, for example: a dosage of 60–300 kgy, and annealing conditions including a temperature of 300–380°C and a time of 30–300 min.

[0100] In some improved embodiments, the P-type well of the transition region 201b (i.e., the second well region 204a) and the first well region 204 of the active region 201a can also be formed by another method. That is, between steps 3 and 4, the P-type wells of the transition region 201b and the active region 201a can be formed simultaneously by photolithography and ion implantation. The advantage of forming the P-type wells of the transition region 201b and the active region 201a simultaneously is that it reduces the number of process steps and the P-type well morphology of the active region 201a and the transition region 201b is consistent. The advantage of forming the P-type wells of the transition region 201b and the active region 201a separately is that the P-type well morphology of the active region 201a and the transition region 201b can be adjusted separately. In the two formation methods, if the same threshold voltage is to be achieved, the method of forming the P-type traps of the transition region 201b and the active region 201a separately requires a higher concentration of P-type ion implantation dose because the P-type trap of the active region 201a will undergo more thermal diffusion processes.

[0101] In the method of this invention embodiment, only one contact hole is formed between the two gates, i.e., the trench gate. Alternatively, two, three, or more contact holes can be designed between the two gates.

[0102] In this embodiment of the invention, by reducing the distance L between the CT and the gate to 0.5µm to 0.6µm, the CT can be designed to be wider. A wider CT design increases the contact area between the CT and the Si epitaxial layer, reducing contact resistance and thus lowering the specific on-resistance of the device. Furthermore, the increased trench cross-sectional area of ​​the CT reduces the current density per unit area. Under the same avalanche current, the current is more dispersed, preventing EAS failures such as localized current concentration leading to overheating of the silicon crystal structure or metal layer melting, thus improving current carrying capacity and heat conduction efficiency, and ultimately enhancing the device's EAS capability.

[0103] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A trench gate superjunction device, characterized in that, The structure of the active region includes: A superjunction structure includes: alternating pillars of a first conductivity type and pillars of a second conductivity type; the bottom of the superjunction structure has a buffer layer doped with the first conductivity type; The first well region, doped with the second conductivity type, is formed in the surface region of the superjunction structure; Each of the first conductive type pillars has a trench gate at the top, the trench gate extending longitudinally through the first well region, and the surface of the first well region covered by the side of the trench gate is used to form a conductive channel. The source region of the first conductivity type is formed in the surface region of the first well region and is aligned with the side of the corresponding trench gate. The device unit step is the sum of the width and spacing of the trench gate; A source contact hole is formed at the top of the source region, penetrating the interlayer film. The bottom of the source contact hole passes through the source region and contacts the first well region. The side of the source region contacts the source contact hole. The first spacing between the source contact hole and the adjacent side of the trench gate is reduced to 0.5 micrometers to 0.6 micrometers. Under the condition that the device cell step size and the width of the trench gate remain unchanged, the reduction value of the first spacing is the increase value of the width of the source contact hole. By increasing the width of the source contact hole, the source contact resistance and the current density of the source contact hole are reduced simultaneously, so as to simultaneously reduce the specific on-resistance and optimize the EAS capability.

2. The trench gate superjunction device as described in claim 1, characterized in that: The source contact hole is located at a depth of 100 angstroms to 400 angstroms below the top surface of the superjunction structure.

3. The trench gate superjunction device as described in claim 1, characterized in that: A heavily doped well contact region of a second conductivity type is also formed at the bottom of the source contact hole.

4. The trench gate superjunction device as described in claim 1, characterized in that: Deep-level defect impurities are incorporated into the semiconductor material lattice of the superjunction structure at the bottom of the source contact hole, or at the bottom of the first well region and the first well region, to improve the reverse recovery characteristics of the body diode.

5. The trench gate superjunction device as described in claim 4, characterized in that: The deep-level defect impurities include Pt.

6. The trench gate superjunction device as described in claim 1, characterized in that: The source contact hole includes a blocking layer composed of stacked Ti and TiN layers filling the inner surface of the source contact hole opening, and a tungsten layer filling the source contact hole opening.

7. The trench gate superjunction device as described in claim 1, characterized in that: A terminal region surrounds the active region, and the superjunction structure is also disposed in the terminal region; The terminal area includes a transition area adjacent to the active area; In the transition region, a second well region doped with a second conductivity type is formed in the surface region of the superjunction structure.

8. The trench gate superjunction device as described in claim 7, characterized in that: The first well region and the second well region are formed independently; or the first well region and the second well region are formed simultaneously using the same process.

9. The trench gate superjunction device as described in claim 1, characterized in that: The second conductivity type pillar is composed of a second epitaxial layer doped with the second conductivity type and filled in the superjunction trench; The superjunction trench is formed in a first epitaxial layer doped with a first conductivity type, and the first conductivity type pillar is composed of the first epitaxial layer between the second conductivity type pillars; The buffer layer is composed of the first epitaxial layer located at the bottom of the superstructure; The first epitaxial layer is formed on the top surface of a semiconductor substrate heavily doped with a first conductivity type.

10. The trench gate superjunction device as described in claim 9, characterized in that: The semiconductor substrate is made of silicon, the first epitaxial layer is made of silicon, and the second epitaxial layer is made of silicon.

11. The trench gate superjunction device as described in claim 1, characterized in that: The trench gate includes a gate trench, a gate oxide layer formed on the inner surface of the gate trench, and a polysilicon gate filled in the gate trench.

12. The trench gate superjunction device as described in claim 11, characterized in that: The gate trench has a width of 0.6 micrometers to 1.5 micrometers and a depth of 2 micrometers to 4 micrometers.

13. The trench gate superjunction device according to any one of claims 1 to 12, characterized in that: The trench gate superjunction device is an N-type device with N-type as the first conductivity type and P-type as the second conductivity type; or, the trench gate superjunction device is a P-type device with P-type as the first conductivity type and N-type as the second conductivity type.

14. The trench gate superjunction device as described in claim 13, characterized in that: The trench gate superjunction device is an N-type device. The doped impurities in the well contact region formed at the bottom of the source contact hole are BF2 and / or B. The implantation energy of BF2 is 20keV to 60keV, and the implantation dose is 5e14cm. -2 ~1e15cm -2 The injection energy for B is 20keV–60keV, and the injection dose is 1e13cm. -2 ~1e15cm -2 .

15. The trench gate superjunction device as described in claim 14, characterized in that: The implanted impurity in the first well region includes B, the implantation energy is 60 keV to 180 keV, and the implantation dose is 1e11cm. -2 ~1e14cm -2 The number of injections is 1, 2, or 3.

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