Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a gate structure, two grooves and two epitaxial layers. The gate structure is disposed on a substrate. The two grooves are arranged in the substrate at two sides of the gate structure, each groove comprises a first inclined plane, a second inclined plane and a third inclined plane which are sequentially connected from bottom to top, a first sharp corner structure is defined between the first inclined plane and the second inclined plane, and a second sharp corner structure is defined between the second inclined plane and the third inclined plane. The two epitaxial layers are respectively arranged in the two grooves.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a semiconductor element that is advantageous for improving channel stress and a method for manufacturing the same. Background Technology

[0002] In advanced semiconductor manufacturing processes, strained silicon technology has been developed to improve the drive current of transistors. The principle is to strain the silicon lattice in the gate channel to increase the mobility of charge carriers, thereby increasing the drive current and enabling the transistor to operate faster.

[0003] One current method to induce strain in the silicon lattice of the gate channel is to combine selective epitaxial growth (SEG) technology. First, grooves are formed in the substrate on both sides of the gate structure. Then, using the selective epitaxial growth process, an epitaxial layer with the same lattice arrangement as the substrate but a different lattice constant is formed in the groove as the source / drain region. This can generate stress on the lattice of the adjacent channel region to improve the carrier mobility.

[0004] As the demand for transistor operating speed continues to increase, improving the structure of semiconductor devices to enhance carrier mobility in the channel region has become a goal that related industries are constantly striving for. Summary of the Invention

[0005] According to one embodiment of the present invention, a semiconductor device is provided, comprising a gate structure, two recesses, and two epitaxial layers. The gate structure is disposed on a substrate. The two recesses are disposed in the substrate on both sides of the gate structure, each recess comprising a first inclined surface, a second inclined surface, and a third inclined surface sequentially connected from bottom to top. A first sharp corner structure is defined between the first inclined surface and the second inclined surface, and a second sharp corner structure is defined between the second inclined surface and the third inclined surface. The two epitaxial layers are respectively disposed in the two recesses.

[0006] According to another embodiment of the present invention, a method for fabricating a semiconductor device is provided, comprising the following steps: forming a gate structure on a substrate; forming two recesses in the substrate on both sides of the gate structure, wherein each recess includes a first inclined surface, a second inclined surface, and a third inclined surface sequentially connected from bottom to top, a first sharp corner structure is defined between the first inclined surface and the second inclined surface, and a second sharp corner structure is defined between the second inclined surface and the third inclined surface; and forming two epitaxial layers in the two recesses respectively.

[0007] Compared to existing technologies, this invention improves the shape of the groove by including at least two pointed corners, which helps to generate stress on the lattice of the adjacent channel region, thereby increasing the carrier mobility of the channel region. Preferably, the dry etching process used to form the groove in this invention can be integrated into the baking step before the selective epitaxial growth process, further simplifying the fabrication process. Attached Figure Description

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 This is a cross-sectional schematic diagram of the steps for fabricating a semiconductor device according to an embodiment of the present invention;

[0009] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device semi-finished product according to another embodiment of the present invention;

[0010] Figure 7 This is a cross-sectional schematic diagram of a semiconductor element according to another embodiment of the present invention.

[0011] Symbol Explanation

[0012] 1, 1a: Semiconductor components

[0013] 100, 100a: Substrate

[0014] 101: Top surface

[0015] 105: First silicon-containing layer

[0016] 110: Second silicon-containing layer

[0017] 120: Insulation layer

[0018] 200: Gate structure

[0019] 210: Gate dielectric layer

[0020] 220: Gate material layer

[0021] 230: Mask layer

[0022] 300: Spacer wall

[0023] 310: First spacer wall

[0024] 320: Second spacer wall

[0025] 400: Lightly doped drain region

[0026] 510: Initial groove

[0027] 520: Groove

[0028] 521: First inclined surface

[0029] 522: First sharp corner structure

[0030] 523: Second inclined surface

[0031] 524: Second Sharp Angle Structure

[0032] 525: Third inclined surface

[0033] 526: Third cusp structure

[0034] 610: Buffer layer

[0035] 620: First epitaxial layer

[0036] 630: Second epitaxial layer

[0037] 640: Cap layer

[0038] 700: Chamber

[0039] A1: First included angle

[0040] A2: Second included angle

[0041] A3: Third angle

[0042] D1: Horizontal direction

[0043] D2: Vertical direction

[0044] G1: First etching gas

[0045] G2: Second etching gas

[0046] G3: Epitaxial material gas

[0047] P0: Ion implantation fabrication process

[0048] P1, P2: Dry etching process

[0049] P3: Selective epitaxial growth process

[0050] S1: Minimum distance Detailed Implementation

[0051] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. To make the content of the present invention clearer and easier to understand, the following drawings are simplified schematic diagrams, and the elements therein may not be drawn to scale. Furthermore, the number and size of the elements in the drawings are merely illustrative and not intended to limit the present invention. Directional terms mentioned in the following embodiments, such as up, down, left, right, front, back, bottom, and top, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention. In addition, in the following embodiments, the same or similar elements will be referred to by the same or similar reference numerals.

[0052] The following description of "the first feature is formed on or above the second feature" can refer to "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature" so that the first feature and the second feature are not in direct contact.

[0053] This invention uses terms such as "first," "second," etc., to describe elements, regions, layers, and / or sections. However, it should be understood that these terms are only used to distinguish one element, region, layer, and / or section from another, and do not inherently imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, region, layer, and / or section discussed below may also be referred to as the second element, region, layer, and / or section. The terms used in the claims may not be the same as those in the description, and may be replaced by first, second, third… according to the order of the elements declared in the claims.

[0054] Please refer to Figures 1 to 5 This is a cross-sectional schematic diagram illustrating the steps of fabricating a semiconductor device according to an embodiment of the present invention. In this embodiment, semiconductor device 1 (see...) Figure 5 This explanation uses a PMOS transistor as an example. Figure 1 As shown, a gate structure 200 is first formed on a substrate 100. The substrate 100 can be a silicon substrate, an epitaxial silicon substrate, or a silicon carbide substrate. The substrate 100 may also include a well region (not shown), for example, the well region can be formed by an ion implantation process (not shown), and the dopant of the well region can be adjusted depending on whether the subsequently formed semiconductor device 1 is an NMOS transistor or a PMOS transistor. In this embodiment, the semiconductor device 1 is taken as a PMOS transistor, therefore, the well region can be an N-type well region, and the well region can be doped with an N-type dopant, such as arsenic, phosphorus, etc.

[0055] The gate structure 200 comprises, from bottom to top, a gate dielectric layer 210, a gate material layer 220, and a mask layer 230. In this embodiment, the gate structure 200 can be fabricated according to the manufacturing process requirements, such as a gate-first fabrication process, a high-k-first fabrication process for the gate last fabrication process, or a high-k-last fabrication process for the gate last fabrication process. Taking the high dielectric constant dielectric layer fabrication process of this embodiment as an example, a deposition process can be performed to sequentially form a gate dielectric material, a gate material, and a mask material on a substrate 100. A patterned photoresist (not shown) is used as a mask for a pattern transfer process. A single-etch or multi-etch process is used to remove portions of the mask material, gate material, and gate dielectric material. Then, the patterned photoresist is stripped to form a gate structure 200 comprising a gate dielectric layer 210, a gate material layer 220, and a mask layer 230 on the top surface 101 of the substrate 100. The material of the gate dielectric layer 210 may include, but is not limited to, oxides and / or nitrides. Oxides may include, for example, silicon dioxide (SiO2), and nitrides may include, for example, silicon nitride (SiN). The material of the gate material layer 220 may include, but is not limited to, non-metallic conductive materials, such as polysilicon. The material of the mask layer 230 may include, but is not limited to, silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC) and / or silicon oxynitride (SiON).

[0056] Furthermore, although this embodiment uses a planar transistor as an example, in other variations, the method for manufacturing semiconductor elements of the present invention can also be applied to non-planar transistors, such as transistors with fin structures. Figure 1 The indicated substrate 100 corresponds to the fin-like structure formed on the substrate 100.

[0057] Next, as Figure 2As shown, spacer walls 300 can be selectively formed around the gate structure 200. First, a first spacer wall 310 is formed around the gate structure 200. The first spacer wall 310 is, for example, an offset spacer, and the material of the first spacer wall 310 may include oxides, such as silicon dioxide. Next, an ion implantation process P0 is performed to form lightly doped drain regions 400 in the substrate 100 on both sides of the gate structure 200. The lightly doped drain regions 400 have the same conductivity type, but different from the conductivity type of the well region. In this embodiment, the well region is an N-type well region, and the conductivity type of the lightly doped drain regions 400 is P-type, so the ion implantation process P0 implants a P-type dopant into the substrate 100. The P-type dopant may include, for example, but not limited to, boron (B), aluminum (Al), gallium (Ga), indium (In), etc. Next, a second spacer wall 320 is formed around the gate structure 200. The material of the second spacer wall 320 may contain nitrides, such as silicon nitride, silicon oxynitride, or silicon carbide nitride. Figure 2 In this example, the spacer wall 300 includes a first spacer wall 310 and a second spacer wall 320, forming a double-layer structure. However, this is only an example, and the number of layers and the material of each layer of the spacer wall 300 can be adjusted according to actual needs.

[0058] Next, two grooves 520 are formed (see...) Figure 4 The following steps may be included in the substrate 100 on both sides of the gate structure 200. First, as Figure 3 As shown, two initial grooves 510 are formed in the substrates 100 on both sides of the gate structure 200, wherein each initial groove 510 includes a U-shaped cross-section. For example, a dry etching process P1 can be performed, and the gate structure 200 and the spacer wall 300 are used as etching masks. The substrate 100 is removed by etching downward along the spacer wall 300 in one or more steps to form two initial grooves 510 disposed in the substrates 100 on both sides of the gate structure 200 along the horizontal direction D1.

[0059] Next, as Figure 4 As shown, another dry etching process P2 is performed to transform the two initial grooves 510 into two grooves 520. Each groove 520 includes a first inclined surface 521, a second inclined surface 523, and a third inclined surface 525 connected sequentially from bottom to top. A first sharp corner structure 522 is defined between the first inclined surface 521 and the second inclined surface 523, and a second sharp corner structure 524 is defined between the second inclined surface 523 and the third inclined surface 525. Thus, each groove 520 includes at least two sharp corner structures, which is beneficial for enhancing the lattice strain effect in the adjacent channel region, thereby increasing the carrier mobility in the channel region and thus improving the operating speed of the subsequently fabricated semiconductor device 1.

[0060] Specifically, the temperature of the dry etching process P2 can be between 800 °C and 900 °C. The time for performing the dry etching process P2 can be between 50 seconds and 70 seconds. The dry etching process P2 may include the introduction of a first etching gas G1. The first etching gas G1 may contain hydrogen chloride (HCl), and the flow rate of the first etching gas G1 can be between 50 sccm (Standard Cubic Centimeter per Minute) and 250 sccm.

[0061] Next, as Figure 5 As shown, two buffer layers 610 can be selectively formed in two recesses 520. Next, two first epitaxial layers 620 can be formed in the two recesses 520, with the two first epitaxial layers 620 respectively disposed on the two buffer layers 610. Next, two second epitaxial layers 630 can be formed on the two first epitaxial layers 620. Next, two capping layers 640 can be formed on the two second epitaxial layers 630, with the two capping layers 640 completely covering the two second epitaxial layers 630. Thus, the fabrication of semiconductor device 1 can be completed. Specifically, a selective epitaxial growth process P3 can be performed, for example, using a chemical vapor deposition system, and a second etching gas G2 and an epitaxial material gas G3 are respectively introduced into the chemical vapor deposition system to sequentially form the two buffer layers 610, the two first epitaxial layers 620, the two second epitaxial layers 630, and the two capping layers 640.

[0062] According to one embodiment of the present invention, the materials of the buffer layer 610, the first epitaxial layer 620, and the second epitaxial layer 630 may all contain silicon germanium (SiGe), and the material of the capping layer 640 contains silicon. The concentration of germanium in the buffer layer 610 may be substantially fixed, the concentration of germanium in the first epitaxial layer 620 may be substantially fixed, and the concentration of germanium in the first epitaxial layer 620 may be greater than the concentration of germanium in the buffer layer 610. The concentration of germanium in the second epitaxial layer 630 may gradually change from bottom to top along the vertical direction D2, for example, it may gradually decrease from bottom to top along the vertical direction D2, for example, it may gradually change from the same concentration of germanium as the first epitaxial layer 620 to 0 along the vertical direction D2. The material of the capping layer 640 does not contain germanium (that is, the concentration of germanium in the capping layer 640 is 0). The aforementioned vertical direction D2 may, for example, be perpendicular to the top surface 101 of the substrate 100.

[0063] For example, the second etching gas G2 may contain hydrogen chloride (HCl), and the epitaxial material gas G3 may contain silicon (Si) source gas such as dichlorosilane (DCS) and germanium (Ge) source gas. The ratio of silicon source gas and germanium source gas in the epitaxial material gas G3 can be adjusted to adjust the concentration of germanium in the buffer layer 610, the first epitaxial layer 620, the second epitaxial layer 630, and the capping layer 640. However, the materials of the buffer layer 610, the first epitaxial layer 620, the second epitaxial layer 630, and the capping layer 640 are merely illustrative examples, and the present invention is not limited thereto. Suitable materials can be selected according to actual needs, and the second etching gas G2 and the epitaxial material gas G3 can be adjusted according to the composition of the buffer layer 610, the first epitaxial layer 620, the second epitaxial layer 630, and the capping layer 640.

[0064] In this embodiment, a buffer layer 610 is disposed between the substrate 100 and the first epitaxial layer 620, preventing the first epitaxial layer 620 from directly contacting the substrate 100. The buffer layer 610 reduces stress between the substrate 100 and the first epitaxial layer 620. In this embodiment, the top surface (not otherwise labeled) of the first epitaxial layer 620 is flush with or substantially flush with the top surface 101 of the substrate 100. Here, the top surface 101 of the substrate 100 refers to the uppermost surface of the substrate 100 where the groove 520 is not formed.

[0065] In this embodiment, the number of epitaxial layers (i.e., the first epitaxial layer 620 and the second epitaxial layer 630) on the same side of the gate structure 200 is two; however, this is merely illustrative and the invention is not limited thereto. For example, in other embodiments, Figure 5 The second epitaxial layer 630 can be replaced by the first epitaxial layer 620, that is, each groove 520 is provided with only one epitaxial layer (i.e., the first epitaxial layer 620). The first epitaxial layer 620 is disposed in the groove 520 and protrudes from the top surface 101 of the substrate 100, and the concentration of germanium in the first epitaxial layer 620 is substantially fixed. For example, in other embodiments, Figure 5 The first epitaxial layer 620 can be replaced by the second epitaxial layer 630, that is, each groove 520 is provided with only one epitaxial layer (i.e., the second epitaxial layer 630). The second epitaxial layer 630 is disposed in the groove 520 and protrudes from the top surface 101 of the substrate 100, and the concentration of germanium in the second epitaxial layer 630 varies from bottom to top along the vertical direction D2.

[0066] In this invention, Figure 4 and Figure 5The steps can be performed in the same chamber 700. That is, the dry etching process P2 and the selective epitaxial growth process P3 for forming the buffer layer 610, the first epitaxial layer 620, the second epitaxial layer 630, and the capping layer 640 can be performed in the same chamber 700. The aforementioned chamber 700 is preferably the chamber of the equipment used for performing the selective epitaxial growth process P3, for example, the chamber 700 can be the chamber of a chemical vapor deposition system. In addition, the type of the first etching gas G1 can be the same as the type of the second etching gas G2. This facilitates the simplification of the manufacturing process.

[0067] In detail, a baking step is required before the P3 selective epitaxial growth process. For example, the baking process is necessary. Figure 3 The semiconductor device is heated to approximately 700°C to 725°C for 50 to 70 seconds to remove contaminants from its surface. This invention, by increasing the temperature of the baking step and introducing a first etching gas G1, enables… Figure 3 The initial groove 510 is transformed into groove 520. Groove 520 includes at least two pointed corner structures, which, compared to the initial groove 510 with a U-shaped profile, is more conducive to improving the lattice strain effect in the adjacent channel region and can simultaneously remove contaminants from the semiconductor device surface. After completing the dry etching process P2, the selective epitaxial growth process P3 can be directly performed in the same chamber 700 without needing to... Figure 4 The semiconductor components can be transferred to another device, simplifying the fabrication process. Furthermore, the type of the first etching gas G1 can be the same as the type of the second etching gas G2, thus eliminating the need for additional materials and simplifying the material selection. In other words, this invention integrates the dry etching process P2 into the baking step before the selective epitaxial growth process P3, allowing the use of existing equipment and materials for the selective epitaxial growth process P3, and eliminating the need for additional time (the time for the dry etching process P2 can be the same as the time for the baking step) to transform the initial groove 510 into the groove 520, thereby streamlining the fabrication process.

[0068] The present invention can simultaneously (in-situ) perform a doping process and annealing process when forming the first epitaxial layer 620 to implant dopants into the first epitaxial layer 620 to form source / drain regions (unspecified), or can choose to perform an ion implantation process and annealing process after the formation of the first epitaxial layer 620 to form source / drain regions within the first epitaxial layer 620. Both of these are within the scope of the present invention.

[0069] Although not shown in the figure, the method for fabricating a semiconductor device may also include other transistor fabrication processes. For example, a metal gate replacement (MG) process may be performed by sequentially forming a contact hole etch stop layer and an interlayer dielectric layer covering the gate structure 200 and the cap layer 640, replacing the non-metallic conductive material of the gate structure 200 with a single-layer or multi-layer structure containing metallic conductive material. The aforementioned single-layer structure may only contain a low-resistance metal layer, and the material of the low-resistance metal layer may be selected from copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. The aforementioned multi-layer structure may be formed by a low-resistance metal layer and a high-dielectric-constant dielectric layer and / or a barrier layer and / or a work function metal layer. The metal gate replacement fabrication process is well known in the art and will not be described in detail here.

[0070] The aforementioned film layers, such as the gate dielectric layer 210, the gate material layer 220, the mask layer 230, the first spacer 310, and the second spacer 320, can be formed by any suitable method, such as, but not limited to, molecular-beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and atomic layer deposition (ALD).

[0071] Please refer to Figure 5 , Figure 5 A cross-sectional schematic diagram of a semiconductor device 1 according to an embodiment of the present invention is shown. Here, a PMOS transistor is used as an example of the semiconductor device 1. The semiconductor device 1 includes a gate structure 200 and two recesses 520 (see...). Figure 4 The gate structure 200 is disposed on the substrate 100, and two grooves 520 are disposed in the substrate 100 on both sides of the gate structure 200. Each groove 520 includes a first inclined surface 521, a second inclined surface 523 and a third inclined surface 525 connected sequentially from bottom to top. A first sharp corner structure 522 is defined between the first inclined surface 521 and the second inclined surface 523, and a second sharp corner structure 524 is defined between the second inclined surface 523 and the third inclined surface 525. The two first epitaxial layers 620 are respectively disposed in the two grooves 520.

[0072] Semiconductor device 1 may also optionally include a spacer wall 300 surrounding a gate structure 200. Semiconductor device 1 may also optionally include two buffer layers 610 disposed in two recesses 520, two second epitaxial layers 630 disposed on the first epitaxial layer 620, and two capping layers 640 disposed on the two second epitaxial layers 630.

[0073] According to one embodiment of the present invention, the number of first inclined surfaces 521 may be two, the two first inclined surfaces 521 are connected to each other and a third pointed corner structure 526 is defined between the two first inclined surfaces 521, that is, each groove 520 may include at least three pointed corner structures. The third pointed corner structure 526 may be located at the bottom of the groove 520 and the third pointed corner structure 526 may be located at the center of the groove 520.

[0074] According to one embodiment of the present invention, the number of first inclined surfaces 521 can be two, the number of second inclined surfaces 523 can be two, and the number of third inclined surfaces 525 can be two, and the two first inclined surfaces 521, the two second inclined surfaces 523, and the two third inclined surfaces 525 can be symmetrical to each other. In this case, in each groove 520, the number of first pointed corner structures 522 is two and symmetrical to each other, the number of second pointed corner structures 524 is two and symmetrical to each other, and the third pointed corner structure 526 is disposed between the two first pointed corner structures 522 and between the two second pointed corner structures 524. Figure 4 As shown, the two first inclined surfaces 521, two second inclined surfaces 523, two third inclined surfaces 525 of each groove 520 and the upward-facing opening of each groove 520 (unlabeled) can together form a heptagon, that is, each groove 520 can contain a heptagonal cross section.

[0075] According to one embodiment of the present invention, the first pointed corner structure 522 has a first included angle A1, the second pointed corner structure 524 has a second included angle A2, and the third pointed corner structure 526 has a third included angle A3. The first included angle A1 may be greater than the third included angle A3, and the third included angle A3 may be greater than the second included angle A2. According to one embodiment of the present invention, the first included angle A1 may be equal to 150.5 degrees, the second included angle A2 may be equal to 109.4 degrees, and the third included angle A3 may be equal to 129.6 degrees.

[0076] According to one embodiment of the present invention, the substrate 100 may be a silicon substrate. In this case, the substrate 100 may include a silicon-containing layer (i.e., the silicon substrate itself), and two grooves 520 are disposed in the silicon-containing layer. The first tilted surface 521 may be a crystal plane in a family of crystal planes {311}, the second tilted surface 523 may be a crystal plane in a family of crystal planes {111}, and the third tilted surface 525 may be a crystal plane in a family of crystal planes {111}. In the present invention, when a tilted surface is a crystal plane in a family of crystal planes, it may mean that the tilted surface is one of all crystal planes included in the family of crystal planes. Other details regarding the semiconductor element 1 can be found in the relevant description above, and will not be repeated here.

[0077] Please refer to Figure 6 and Figure 7 , Figure 6 This is a cross-sectional schematic diagram of a semiconductor device semi-finished product according to another embodiment of the present invention. Figure 7 This is a schematic cross-sectional view of a semiconductor element 1a according to another embodiment of the present invention, wherein... Figure 6 It was fabricated using a dry etching process, P2 (see...). Figure 4 The resulting semiconductor device semi-finished product, for Figure 6 By selectively epitaxially growing semiconductor device semi-finished products using the P3 process, the desired result can be obtained. Figure 7 Semiconductor element 1a. The main difference between semiconductor element 1a and semiconductor element 1 is that the substrate 100a is different from the substrate 100. Figure 6 and Figure 7 In this design, substrate 100a is a silicon oninsulator (SOI) substrate, and sequentially includes a first silicon-containing layer 105, an insulating layer 120, and a second silicon-containing layer 110 from bottom to top. The first silicon-containing layer 105 and the second silicon-containing layer 110 can be, for example, silicon layers or epitaxial silicon layers, and the insulating layer 120 can be, for example, a silicon dioxide layer. Two grooves 520 are disposed in the upper second silicon-containing layer 110, and the minimum distance S1 between each groove 520 and the insulating layer 120 in the vertical direction D2 is greater than or equal to 50 angstroms and less than or equal to 100 angstroms. Thus, the distance between the grooves 520 and the insulating layer 120 is moderate, which on the one hand facilitates the formation of a complete sharp corner structure in the grooves 520, so that the lattice of the channel region generates sufficient strain, and on the other hand, prevents the grooves 520 from penetrating the upper second silicon-containing layer 110 and exposing the insulating layer 120, which would prevent selective epitaxial growth fabrication process P3 from being performed in the grooves 520. For further details regarding semiconductor element 1a, please refer to the relevant descriptions above, which will not be repeated here.

[0078] Compared to existing technologies, this invention improves the shape of the groove by including at least two pointed corners, which helps to generate stress on the lattice of the adjacent channel region, thereby increasing the carrier mobility of the channel region. Preferably, the dry etching process used to form the groove in this invention can be integrated into the baking step before the selective epitaxial growth process, further simplifying the fabrication process.

[0079] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor element comprising: A gate structure is disposed on a substrate; Two recesses are disposed in the substrate on both sides of the gate structure, wherein each recess includes a first inclined surface, a second inclined surface, and a third inclined surface connected sequentially from bottom to top. A first sharp angle structure is defined between the first inclined surface and the second inclined surface, and a second sharp angle structure is defined between the second inclined surface and the third inclined surface; and Two epitaxial layers are respectively disposed in the two grooves.

2. The semiconductor element of claim 1, wherein the number of the first inclined surfaces is two, the two first inclined surfaces are connected to each other, and a third sharp corner structure is defined between the two first inclined surfaces.

3. The semiconductor device of claim 2, wherein the first pointed corner structure has a first included angle, the second pointed corner structure has a second included angle, the third pointed corner structure has a third included angle, the first included angle is greater than the third included angle, and the third included angle is greater than the second included angle.

4. The semiconductor element as claimed in claim 3, wherein the first included angle is equal to 150.5 degrees, the second included angle is equal to 109.4 degrees, and the third included angle is equal to 129.6 degrees.

5. The semiconductor device of claim 1, wherein the substrate comprises a silicon-containing layer, the two grooves are disposed in the silicon-containing layer, and the first inclined surface may be a crystal plane in the family of crystal planes {311}.

6. The semiconductor device of claim 1, wherein the substrate includes a silicon-containing layer, the two grooves are disposed in the silicon-containing layer, and the second inclined surface may be a crystal plane in the family {111} of crystal planes.

7. The semiconductor device of claim 1, wherein the substrate includes a silicon-containing layer, the two grooves are disposed in the silicon-containing layer, and the third inclined surface may be a crystal plane in the family of crystal planes {111}.

8. The semiconductor device of claim 1, wherein the number of the first inclined surfaces is two, the number of the second inclined surfaces is two, the number of the third inclined surfaces is two, and the two first inclined surfaces, the two second inclined surfaces and the two third inclined surfaces are symmetrical to each other.

9. The semiconductor element of claim 1, wherein each of the recesses comprises a heptagonal cross-section.

10. The semiconductor device of claim 1, wherein the substrate comprises an insulating layer and a silicon-containing layer disposed on the insulating layer, wherein the two grooves are disposed in the silicon-containing layer, and the minimum distance between each groove and the insulating layer in the vertical direction is greater than or equal to 50 angstroms and less than or equal to 100 angstroms.

11. A method for manufacturing a semiconductor device, comprising: A gate structure is formed on the substrate; Two recesses are formed in the substrate on both sides of the gate structure, wherein each recess includes a first inclined surface, a second inclined surface, and a third inclined surface connected sequentially from bottom to top. A first sharp angle structure is defined between the first inclined surface and the second inclined surface, and a second sharp angle structure is defined between the second inclined surface and the third inclined surface; and Two epitaxial layers are formed in the two grooves respectively.

12. The method of claim 11, wherein the number of the first inclined surfaces is two, the two first inclined surfaces are connected to each other, and a third apex structure is defined between the two first inclined surfaces.

13. The method of claim 11, wherein the substrate forming the two recesses on both sides of the gate structure comprises: Two initial grooves are formed in the substrate on both sides of the gate structure, wherein each initial groove includes a U-shaped cross-section; and A dry etching process is used to transform the two initial grooves into the two grooves.

14. The method of claim 13, wherein the temperature for performing the dry etching process is 800°C to 900°C.

15. The method of claim 13, wherein the dry etching process takes 50 to 70 seconds.

16. The method of claim 13, wherein performing the dry etching process includes introducing a first etching gas.

17. The method of claim 16, wherein the first etching gas comprises hydrogen chloride, and the flow rate of the first etching gas is from 50 sccm to 250 sccm.

18. The method of claim 16, wherein the formation of the two epitaxial layers in the two grooves includes the introduction of a second etching gas and an epitaxial material gas, the type of the second etching gas being the same as the type of the first etching gas.

19. The method of claim 13, wherein the dry etching process and the formation of the two epitaxial layers are performed in the same chamber.

20. The method of claim 11, wherein the substrate comprises an insulating layer and a silicon-containing layer disposed on the insulating layer, wherein the two grooves are disposed in the silicon-containing layer, and the minimum distance between each groove and the insulating layer in the vertical direction is greater than or equal to 50 angstroms and less than or equal to 100 angstroms.

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