Method for improving carrier concentration of P-type semiconductor based on structural pressurization

Abstract

The invention discloses a method for improving the carrier concentration of a P-type semiconductor based on structural pressurization, and relates to the technical field of semiconductors, and the method comprises the following steps: S1, growing an N-type semiconductor of an LED; s2, patterning the surface of the N-type semiconductor, and growing a quantum well in patterning or growing a quantum well and patterning the quantum well; and S3, growing a P-type semiconductor in the patterning, or patterning the surface of the quantum well and growing the P-type semiconductor in the patterning, or growing the P-type semiconductor and patterning the P-type semiconductor. According to the invention, the LED can work under the condition that the quantum efficiency is the highest, the total reflection loss is reduced, and the P-type carrier concentration is increased, so that the efficiency is improved; the concentration of P-type carriers is adjusted, so that the droop peak current value is adjusted, higher turn-on voltage is realized, and higher luminous efficiency is generated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically a method for increasing the carrier concentration of a P-type semiconductor based on structural pressure enhancement. Background Technology

[0002] Currently, in ordinary LEDs, especially GaN-based LEDs, the carrier concentration in the P-type semiconductor is too low, while the carrier concentration in the N-type semiconductor is much higher. This leads to an excess of electrons during quantum well recombination, causing leakage current in the P-type semiconductor and reducing the LED's electro-optical conversion efficiency. The current solution is to use an electron blocking layer to address this excess carrier problem. However, current intercalation layers, due to their electron blocking properties, differ from the materials used in current P-type semiconductors. The significant differences in lattice constants and thermal expansion coefficients between the two materials make it easy for defects to form at the interface. Furthermore, frequent switching and rapid temperature changes during LED operation can lead to thermal mismatch and generate more defects. These defects increase non-radiative recombination, reducing the LED's light extraction efficiency to some extent, diminishing some of the positive effects of the electron blocking layer, and lowering the LED's reliability. In addition, the electron blocking layer's effectiveness varies depending on the current, resulting in inconsistent blocking performance when the current varies significantly.

[0003] Furthermore, with the rapid development of displays, LEDs are moving towards Mini / Micro-LED. As LEDs become smaller, their surface effects become more and more pronounced. As the size decreases, the surface area / volume ratio increases, and the effect of surface effects becomes more and more obvious. Surface defects leading to non-radiative recombination have a greater impact on the light output efficiency of LEDs, significantly reducing their luminous efficiency. Therefore, how to reduce non-radiative recombination caused by surface defects is a major problem.

[0004] Furthermore, the light emitted from quantum wells currently has a very small exit cone angle due to the excessively large refractive indices of P-type and N-type semiconductors compared to air. Most of this light undergoes total internal reflection and is then reflected back into the quantum well for reabsorption, increasing heat loss and reducing light extraction efficiency. Therefore, designing a suitable exit position to reduce total internal reflection and improve light extraction efficiency has become a major challenge.

[0005] Furthermore, according to the ABC recombination theory, there is a maximum value for the LEE efficiency of an LED. This maximum value corresponds to a suitable carrier concentration, which can be calculated using ABC. Therefore, how to dynamically control the P-type carrier concentration to maximize the LEE efficiency of an LED is a major problem.

[0006] Currently, Mini-LED+LCD display technology is gradually becoming the mainstream technology for TVs, flat-panel displays due to its advantages such as high contrast, low power consumption, good display effect, strong compatibility, minimal equipment changes required for technology upgrades, and low cost. However, in the application of this technology, it has been found that the more zones there are, the lower the LED power required within each zone, and the fewer LEDs are needed. Since each zone needs to be controlled individually, the 220V or other high voltage needs to be adjusted to the low voltage required by each LED zone. Because the voltage range of the transformer is relatively large, the power loss caused by the transformer is relatively large, which is not energy-efficient. Therefore, with the current large number of zones, the power required to drive is relatively large, and in some cases, it may even exceed the power required by the LED, resulting in high power consumption. If Micro-LED display is to be implemented in the future, each pixel will require one LED, and the voltage will need to be changed from 220V or other high voltage to the 2-4V range required by the LED (the turn-on voltages for red, blue, and green are different), which will cause even greater transformer losses and require even greater drive power. In order to reduce transformer losses, LEDs with higher turn-on voltages need to be implemented.

[0007] Current LEDs exhibit a droop phenomenon, specifically, the luminous efficiency of an LED initially increases and then decreases further as the driving current increases. There are many reasons for this droop phenomenon, one crucial one being the mismatch between the concentrations of electrons and holes. Their concentrations change inconsistently with increasing temperature. Blue LEDs could not be manufactured until the P-type carrier problem was solved by a Japanese Nobel laureate, demonstrating the impact of electron and hole carrier concentrations on LED luminous efficiency. This is also illustrated by the ABC theory of LEDs. Therefore, adjusting the appropriate electron and hole carrier concentrations to regulate the droop peak current and improve the luminous efficiency of LEDs under high power and high current conditions remains a significant challenge.

[0008] In summary, existing LEDs have the following technical problems:

[0009] 1. Electron blocking layers are prone to defects when addressing the phenomenon of excess electrons in quantum well recombination, which reduces the light extraction efficiency of LEDs. Furthermore, the blocking effect of electron blocking layers varies depending on the current. How can a better method be adopted to address the phenomenon of excess electrons?

[0010] 2. How to reduce non-radiative recombination caused by surface defects;

[0011] 3. How to prevent the light emitted from the quantum well from being reflected back into the internal quantum well and reabsorbed after total internal reflection, which increases heat loss and reduces light extraction efficiency;

[0012] 4. How can the concentration of p-type carriers be dynamically adjusted to maximize the LEE efficiency of an LED?

[0013] 5. How to solve the problem of significant electrical losses caused by transformers in Mini-LED+LCD display technology;

[0014] 6. How to adjust the appropriate carrier concentration of electrons and holes, and thus adjust the peak current of droop, thereby improving the light extraction efficiency of LEDs under high power and high current.

[0015] 7. Currently, LEDs, especially GaN-based materials such as P-GaN, P-AlGaN, or P-AlInN, suffer from excessively low P-type carrier concentration. How to increase the P-type carrier concentration of P-type GaN-based materials has become a major challenge.

[0016] On the same day, a device based on structural pressure enhancement to increase the carrier concentration of P-type semiconductors was applied for, which can solve the above problems. However, there is currently a lack of corresponding green, element-free doping production processes. Current patterning processes still have certain problems. For example, in traditional photolithography, when using ICP (Inductively Coupled Plasma) etching, high-energy gas elements are easily injected into the semiconductor crystal, forming impurity element incorporation. This creates some unwanted energy level structures in the semiconductor band structure. When the crystal is electrically injected, transitions between unwanted energy levels in the crystal band structure are easily formed, reducing radiative recombination efficiency. This is also the root cause of non-radiative recombination on the LED surface, especially the main reason for the low efficiency of small-size Micro-LEDs. Therefore, developing new patterning technologies without impurity element insertion has become an urgent problem to be solved. Summary of the Invention

[0017] The purpose of this invention is to provide a method for increasing the carrier concentration of a P-type semiconductor based on structural pressure enhancement, so as to solve the problems mentioned in the background art.

[0018] To achieve the above objectives, the present invention provides the following technical solution:

[0019] A method for increasing carrier concentration in a p-type semiconductor based on structural pressure enhancement includes the following steps:

[0020] S1, the N-type semiconductor for growing LEDs;

[0021] S2, patterning on the surface of an N-type semiconductor and growing a quantum well in the pattern, or growing a quantum well and patterning a quantum well.

[0022] S3, growing a P-type semiconductor in a pattern, or patterning a quantum well surface and growing a P-type semiconductor in a pattern, or growing a P-type semiconductor and patterning a P-type semiconductor.

[0023] As a further aspect of the present invention: in step S2, the patterning on the N-type semiconductor surface is achieved by a combination of photolithography and / or nanoimprint etching, and the outer side of the patterned N-type semiconductor surface is a semiconductor or insulating material with a concentration less than a specific carrier concentration.

[0024] As a further aspect of the present invention: when the P-type semiconductor is P-GaN or P-AlGaN, the specific carrier concentration is 1*102 16 cm -3 .

[0025] As a further aspect of the present invention: in step S2, the patterned quantum well is realized by selectively processing the quantum well semiconductor with a laser, an electron beam, or an ion beam. The quantum well is a multi-component semiconductor. The first specific melting point, boiling point, or decomposition point component in the quantum well evaporates or sublimates, and the second specific melting point, boiling point, or decomposition point component in the quantum well becomes the patterned material.

[0026] As a further aspect of the present invention: in step S2, the patterned quantum well semiconductor is realized by selectively heating a P-type semiconductor with a laser, an electron beam, or an ion beam. The quantum well is a multi-component semiconductor. The component material with a first specific melting point, boiling point, or decomposition point in the quantum well evaporates or sublimates, and the component material with a second specific melting point, boiling point, or decomposition point in the quantum well becomes the patterned material. The first specific melting point is less than the second specific melting point in the quantum well, or the first specific boiling point is less than the second specific boiling point in the quantum well, or the first specific decomposition point is less than the second specific decomposition point in the quantum well.

[0027] As a further embodiment of the present invention: in step S3, the patterning on the quantum well surface is achieved by photolithography and / or nanoimprint etching combined with etching, and / or laser etching and / or chemical etching and / or electron beam and / or ion beam etching, wherein the outer side of the patterned quantum well surface is a semiconductor or insulating material with a concentration less than a specific carrier concentration.

[0028] As a further aspect of the present invention: in step S3, the patterned P-type semiconductor is achieved by selectively heating the P-type semiconductor with a laser, an electron beam, or an ion beam. The P-type semiconductor is a multi-component semiconductor. The first specific melting point, boiling point, or decomposition point component in the P-type semiconductor evaporates or sublimates, and the second specific melting point, boiling point, or decomposition point component in the P-type semiconductor becomes the patterned material.

[0029] As a further embodiment of the present invention: in step S3, the patterned P-type semiconductor is achieved by photolithography and / or nanoimprint etching, and / or laser etching and / or chemical etching and / or electron beam and / or ion beam etching.

[0030] As a further aspect of the present invention: the P-type semiconductor is an insulating ring center.

[0031] As a further aspect of the present invention: the quantum well is composed of multiple components, including at least a first specific melting point or boiling point or decomposition point component and a second specific melting point or boiling point or decomposition point component, wherein the second specific melting point or boiling point or decomposition point component is a patterned material, and the first specific melting point is less than the second specific melting point in the quantum well, or the first specific boiling point is less than the second specific boiling point in the quantum well, or the first specific decomposition point is less than the second specific decomposition point in the quantum well.

[0032] Compared with the prior art, the beneficial effects of the present invention are:

[0033] 1. This invention does not employ an electron blocking layer, but instead uses structural voltage boosting to increase the carrier concentration of P-type semiconductors. This solves the technical problems of "the electron blocking layer being prone to defects when dealing with the phenomenon of excess electrons in quantum well recombination, which reduces the light extraction efficiency of LEDs, and the inconsistent blocking effect of the electron blocking layer for electrons under different currents; how to use a better method to solve the phenomenon of excess electrons". Through structural voltage boosting, it achieves the technical effect of increasing the P-type carrier concentration, and voltage boosting also increases the rate of P-type carrier concentration, thus increasing the carrier concentration as well.

[0034] 2. This invention solves the technical problem of "how to reduce nonradiative recombination caused by surface defects" by adopting the method of "multiple insulating patterned, non-connected, and conductive quantum wells partitioned into rings, sectors, polygons, or free-form patterns". When the quantum well is ring-shaped, the ring area is smaller than the surface area of ​​the P-type semiconductor of the LED. The outer side of the ring is a semiconductor or insulating material with a concentration lower than a certain carrier concentration, which cannot conduct electricity. This can avoid carrier recombination at surface defects, thereby avoiding nonradiative recombination at the surface.

[0035] 3. This invention solves the technical problem of "how to avoid the problem of light emitted from the quantum well being reflected back into the internal quantum well and reabsorbed after total internal reflection, which increases heat loss and reduces light extraction efficiency" by adopting the method of "multiple insulating patterned non-interconnected conductive quantum wells divided into ring, sector, polygon, or free-form pattern partitions". When the quantum well is ring, sector, or free-form, its center is made of insulating material. In this way, the center of the quantum well cannot radiate light, which can avoid total internal reflection and the resulting reabsorption phenomenon, thereby improving the electro-optical conversion efficiency of the LED and the light extraction efficiency of the quantum well.

[0036] 4. This invention solves the problem of "how to dynamically control the P-type carrier concentration to maximize the LEE efficiency of the LED" by employing the technical means of "growing a P-type semiconductor in a patterned state, or patterning a P-type semiconductor on the surface of a quantum well and growing a P-type semiconductor in a patterned state, or growing a P-type semiconductor and patterning a P-type semiconductor".

[0037] 5. This invention overcomes the technical problem of "how to solve the problem of large electrical losses caused by voltage transformation in Mini-LED+LCD display technology" by employing the technical means of "growing P-type semiconductors in a patterned state, or patterning P-type semiconductors on the surface of a quantum well and growing P-type semiconductors in a patterned state, or growing P-type semiconductors and patterning P-type semiconductors." Because the resistance on both sides of the P-type semiconductor is increased, the LED can be maintained in a normal state. The newly designed LED device has a higher turn-on voltage, which can be designed and implemented through the microstructure of the P-type semiconductor. This novel LED device has a higher turn-on voltage and higher light extraction efficiency, offering greater advantages when applied to Mini / Micro-LED displays. It reduces the large voltage transformation losses caused by the low voltage of current single-segment Mini-LEDs with more partitions, enabling more partitions in Mini-LEDs, and even achieving Micro-LED display for each pixel.

[0038] 6. This invention solves the technical problem of "how to adjust the appropriate concentration of electrons and holes to regulate the peak current of droop, thereby improving the light extraction efficiency of LEDs under high power and high current" by employing the technical means of "growing P-type semiconductors in a patterned environment, or patterning a quantum well surface and growing P-type semiconductors in a patterned environment, or growing P-type semiconductors and patterning P-type semiconductors". By designing appropriate partition positions and area adjustments to obtain a suitable concentration of P-type carriers, the recombination probability of P-type and N-type carriers is increased, thereby improving the electro-optical conversion efficiency of LEDs and the light extraction efficiency of LEDs. Furthermore, in this case, after improving the light extraction efficiency of LEDs, the peak current of droop can be regulated, thus improving the droop phenomenon.

[0039] 7. This invention solves the technical problem of "currently, LEDs, especially GaN-based materials such as P-GaN, P-AlGaN, or P-AlInN, have excessively low P-type carrier concentrations, and how to improve the P-type carrier concentration of P-type GaN-based materials has become a major challenge" by adopting the technical means of "growing P-type semiconductors in patterning, or patterning on the surface of a quantum well and growing P-type semiconductors in patterning, or growing P-type semiconductors and patterning P-type semiconductors".

[0040] 8. When laser or electron beam processing is used, the absence of element doping avoids the formation of new non-radiative energy level structures, thus avoiding the root cause of non-radiative recombination on the LED surface. This reduces the loss of surface non-radiative recombination efficiency from a process perspective and improves the light extraction efficiency of Micro-LEDs from a process perspective.

[0041] 9. The ion beam uses gallium ion etching (because no new ion implantation is added when using GaN AlGaN material systems), which does not add new elements or increase ion implantation capability, making it a green etching process. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating the present invention.

[0043] Figure 2 This is a cross-sectional view of an LED device manufactured using the present invention.

[0044] Figure 3 This is a top view of an LED device manufactured using the present invention.

[0045] Figure 4 This is a top view of an LED device manufactured using the present invention, viewed from above a quantum well. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Please see Figure 1 A method for increasing carrier concentration in a P-type semiconductor based on structural pressure enhancement includes the following steps:

[0048] S1, the N-type semiconductor for growing LEDs;

[0049] S2, patterning on the surface of an N-type semiconductor and growing a quantum well in the pattern, or growing a quantum well and patterning a quantum well.

[0050] S3, growing a P-type semiconductor in a pattern, or patterning a quantum well surface and growing a P-type semiconductor in a pattern, or growing a P-type semiconductor and patterning a P-type semiconductor.

[0051] If the N-type semiconductor surface is patterned to a sufficient depth, quantum wells and P-type semiconductors can be grown directly thereafter.

[0052] Furthermore, in step S2, the patterning on the N-type semiconductor surface is achieved by a combination of photolithography and / or nanoimprint etching, and the outer side of the patterned N-type semiconductor surface is a semiconductor or insulating material with a concentration lower than a specific carrier concentration.

[0053] Furthermore, when the P-type semiconductor is P-GaN or P-AlGaN, the specific carrier concentration is 1*102 16 cm -3 .

[0054] Example 1

[0055] In step S2, the patterned quantum well is realized by selectively processing the quantum well semiconductor with a laser, electron beam, or ion beam. The quantum well is a multi-component semiconductor. The first specific melting point, boiling point, or decomposition point component in the quantum well evaporates or sublimates, and the second specific melting point, boiling point, or decomposition point component in the quantum well becomes the patterned material.

[0056] Preferably, the quantum well multi-component semiconductor is InGaN, the first specific melting point, boiling point or decomposition point component in the quantum well is InN, and the second specific melting point, boiling point or decomposition point component in the quantum well is GaN. The melting point, boiling point and decomposition point of InN are lower than those of GaN, and InN is easily decomposed and vaporized when heated.

[0057] Example 2

[0058] In step S2, the patterned quantum well semiconductor is realized by selectively heating a P-type semiconductor with a laser, an electron beam, or an ion beam. The quantum well is a multi-component semiconductor. The first specific melting point, boiling point, or decomposition point component in the quantum well evaporates or sublimates, and the second specific melting point, boiling point, or decomposition point component in the quantum well becomes the patterned material.

[0059] The quantum well multi-component semiconductor is AlGaN, the first specific melting point, boiling point or decomposition point component in the quantum well is GaN, and the second specific melting point, boiling point or decomposition point component in the quantum well is AlN.

[0060] The quantum well multi-component semiconductor is InGaN, the first specific melting point, boiling point or decomposition point component in the quantum well is InN, and the second specific melting point, boiling point or decomposition point component in the quantum well is GaN.

[0061] In step S3, the patterning of the quantum well surface is achieved by photolithography and / or nanoimprint etching combined with etching, and / or laser etching and / or chemical etching and / or electron beam and / or ion beam etching. The outer side of the patterned quantum well surface is a semiconductor or insulating material with a concentration less than a specific carrier concentration.

[0062] Example 3

[0063] In step S3, the patterned P-type semiconductor is achieved by selectively heating the P-type semiconductor with a laser, an electron beam, or an ion beam. The P-type semiconductor is a multi-component semiconductor. The first specific melting point, boiling point, or decomposition point component in the P-type semiconductor evaporates or sublimates, and the second specific melting point, boiling point, or decomposition point component in the P-type semiconductor becomes the patterned material.

[0064] The P-type semiconductor is a multi-component semiconductor of AlGaN. The component with the first specific melting point, boiling point, or decomposition point in the P-type semiconductor is GaN, and the component with the second specific melting point, boiling point, or decomposition point in the P-type semiconductor is AlN.

[0065] Example 4

[0066] In step S3, the patterned P-type semiconductor is achieved by photolithography and / or nanoimprint etching, and / or laser etching and / or chemical etching and / or electron beam and / or ion beam etching. The ion beam uses gallium ion etching (because when using GaN AlGaN material systems, no new ion implantation is added), which does not add new elements and does not increase ion implantation capability, making it a green etching process.

[0067] P-type semiconductors have an insulated ring center.

[0068] like Figure 2 As shown, an LED device with increased carrier concentration in a P-type semiconductor based on structural pressure enhancement can be fabricated using the above method. The device includes an N-type semiconductor 3 with a quantum well 1 on it. The quantum well 1 includes a semiconductor or insulating patterned structure 8 with a carrier concentration lower than a specific value. The P-type semiconductor 2 above the quantum well 1 contains a patterned structure adapted to it.

[0069] Furthermore, the quantum well 1 includes multiple unconnected quantum well partitions of semiconductors with a specific carrier concentration, or multiple isolated patterned unconnected quantum well partitions, or a single quantum well partition of semiconductors or isolated patterned structures with a specific carrier concentration.

[0070] Since carrier recombination cannot occur in the insulating areas of a quantum well, a suitable light-emitting region can be selected by choosing an appropriate patterned structure. Then, a suitable insulating region can be designed according to the light-emitting characteristics of the LED to improve the light-emitting efficiency of the LED.

[0071] Furthermore, the P-type semiconductor 2 includes multiple unconnected semiconductor partitions with a specific carrier concentration, or multiple isolated patterned unconnected semiconductor partitions, or a single semiconductor partition with a specific carrier concentration or an isolated patterned structure 8.

[0072] This includes multiple unconnected semiconductor regions with carrier concentrations below a specific value. This refers to a situation where the carrier concentrations of multiple semiconductors below a specific value are less than a certain threshold. For P-GaN and P-ALGaN, the corresponding threshold is 1*10. 16 cm -3 At this point, the semiconductor with a concentration below a specific carrier concentration acts as an insulator, preventing carriers from passing through and thus controlling the hole injection location of the quantum well. The semiconductor partitioning mentioned in the latter part of the sentence refers to the concentration of a normal P-type semiconductor, mostly around 10. 16 cm -3 The term refers to multiple isolated, patterned, and unconnected conductive semiconductor partitions. Insulation occurs outside these partitions to prevent carriers from passing through, thus controlling the hole injection location of the quantum well. These isolated, patterned, and unconnected conductive semiconductor partitions refer to regions with the concentration of a normal P-type semiconductor; these partitions are not interconnected. A single semiconductor partition with a concentration less than a specific carrier concentration (e.g., 8) refers to a single, interconnected semiconductor partition.

[0073] For the same bulk material, with constant length or thickness, according to the formula for resistance, the smaller the cross-sectional area, the greater the resistance. By selecting appropriate semiconductor partitions, the resistance of a P-type semiconductor of suitable size can be obtained. Because the N-type semiconductor layer is untreated, its resistance remains unchanged. However, in P-type semiconductor circuits, the resistance can be increased by increasing the insulating area and reducing the cross-sectional area through which charge carriers can pass. When voltage is applied to the positive and negative terminals of an LED, due to the increased resistance of the P-type semiconductor, and since the resistances of the P-type semiconductor, quantum well semiconductor, and N-type semiconductor are in series, most of the voltage is applied to the P-type semiconductor layer. According to the changing law of charge carriers in semiconductors, as the voltage increases, the internal electric field increases, the charge carrier concentration increases, and the force on the charge carriers increases. Increasing the quantum efficiency and carrier velocity both lead to an increase in the number and concentration of P-type carriers injected into the quantum well. Holes recombine with more electrons, reducing or even eliminating electron leakage. This reduces or eliminates the need for an electron blocking layer, resulting in a better match between the P-type and N-type carrier concentrations. Furthermore, according to the ABC theory, an optimized quantum efficiency can be designed to achieve a more suitable carrier concentration. By adjusting the appropriate partitioning location and area, a suitable P-type carrier concentration can be obtained, increasing the recombination probability of P-type and N-type carriers, improving the LED's electro-optical conversion efficiency, and enhancing its light extraction efficiency. In this case, improving the LED's light extraction efficiency allows for the regulation of the droop peak current, mitigating the droop phenomenon.

[0074] Based on the above design, the increased resistance on both sides of the P-type semiconductor ensures the LED remains on. The newly designed LED device has a higher turn-on voltage, which can be achieved through the microstructure of the P-type semiconductor. This new type of LED device has a higher turn-on voltage and higher light extraction efficiency, giving it a greater advantage when applied to Mini / Micro-LED displays. It reduces the large transformer power loss caused by the low voltage of single-segment Mini-LEDs with more partitions, enabling more partitions in Mini-LEDs and even Micro-LED displays for each pixel.

[0075] Furthermore, such as Figure 3 As shown, multiple insulating, patterned, non-connected, and electrically conductive quantum well partitions are arranged in ring, sector, polygon, or free-form patterns.

[0076] When the quantum well is ring-shaped, the ring area is smaller than the surface area of ​​the P-type semiconductor of the LED, which can avoid carrier recombination at the surface defects, thereby avoiding nonradiative recombination at the surface. When the quantum well is ring-shaped, the center of the ring region is made of insulating material, so that the center of the quantum well cannot emit light radiatively, which can avoid total internal reflection at the center of the quantum well and the resulting reabsorption phenomenon of the quantum well, thereby improving the electro-optical conversion efficiency of the LED and the light extraction efficiency of the quantum well.

[0077] Furthermore, such as Figure 4 As shown, the outer ring of the P-type semiconductor 2 is insulated.

[0078] Because the outer side of the ring is insulated, charge carriers cannot move to the surface to undergo non-radiative recombination, which reduces charge carrier and electrical losses and increases the light extraction efficiency of the LED.

[0079] Furthermore, the P-type semiconductor 2 is an insulated ring center.

[0080] Because the length of the LED is much greater than the thickness of the P-type semiconductor, most of the light emitted from the center undergoes total internal reflection after being emitted from the center. The light is reflected back into the LED, absorbed again by the quantum well, generating heat or causing photoluminescence and total internal reflection again. This cycle repeats multiple times inside the LED, reducing the electro-optical conversion efficiency and the light emission efficiency. If the interior is insulated, when the light-emitting area of ​​the quantum well is near the edge of the LED (not on the surface) and not in the center, the incident angle formed by the light emitted from the side near the edge of the LED quantum well and the interface between the semiconductor and the air is smaller. This angle is smaller than the total internal reflection angle, allowing the light to escape into the air, avoiding total internal reflection, reducing light loss, and improving the light emission efficiency.

[0081] Furthermore, multiple insulating patterned, non-connected, conductive semiconductor partitions are ring-shaped, sector-shaped, polygonal, or free-form pattern partitions.

[0082] When the semiconductor partition is ring-shaped, the surface area of ​​the ring is smaller than that of the P-type semiconductor. Therefore, the outer side of the P-type semiconductor is insulated. Due to the surface insulation, charge carriers cannot move to the surface to undergo non-radiative radiation, reducing heat loss and improving electro-optical conversion efficiency, thus increasing the light extraction efficiency of the LED. When the semiconductor partition is ring-shaped, the center of the ring is insulated. There is no charge carrier movement in the central region of the semiconductor, and charge carriers cannot reach the center of the quantum well to undergo radiative recombination. This avoids total internal reflection after light is emitted from the quantum well at the center and also avoids the reabsorption of this totally reflected light inside the quantum well, which would cause heat loss. This avoids the effect of low electro-optical conversion efficiency caused by heat loss. Therefore, by avoiding the above defects, the light extraction efficiency of the LED is improved.

[0083] Furthermore, the area of ​​the quantum well with the insulating patterned structure is smaller than the area of ​​the unpatterned P-type semiconductor, and the area of ​​the patterned P-type semiconductor matched with the quantum well is smaller than the area of ​​the unpatterned P-type semiconductor.

[0084] Because the diffusion length of charge carriers is relatively large, the quantum well needs to be treated with an insulating patterned structure to force the insulation of the region to prevent charge carrier recombination. This forces the recombination of P-type and N-type charge carriers to occur in the designed region, thereby reducing the non-radiative effect on the surface. This forces the luminescence of P-type and N-type charge carriers to be controlled in a specific designed region, thus improving the light extraction efficiency of the LED.

[0085] Furthermore, it also includes a P-type electrode 4 located on the patterned P-type semiconductor 2; an N-type electrode 5 located on the N-type semiconductor 3; an N-type buffer layer 6 located below the N-type semiconductor 3; and a substrate 7 located below the N-type buffer layer 6.

[0086] This invention enables LEDs to operate at their highest quantum efficiency, reduces total internal reflection losses, increases P-type carrier concentration to increase efficiency, and adjusts the droop peak current value by adjusting the P-type carrier concentration, thereby achieving a larger turn-on voltage.

[0087] When laser or electron beam processing is used, the absence of element doping avoids the formation of new non-radiative energy level structures, thus preventing the root cause of non-radiative recombination on the LED surface. This reduces the loss of surface non-radiative recombination efficiency from a process perspective, thereby improving the light extraction efficiency of Micro-LEDs.

[0088] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for increasing carrier concentration in a p-type semiconductor based on structural pressure enhancement, characterized in that, Includes the following steps: S1, the N-type semiconductor for growing LEDs; S2, patterning on the surface of an N-type semiconductor (3) and growing a quantum well in the pattern, or growing a quantum well and patterning a quantum well; S3, growing a P-type semiconductor in a pattern, or patterning a quantum well surface and growing a P-type semiconductor in a pattern, or growing a P-type semiconductor and patterning a P-type semiconductor.

2. The method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 1, characterized in that, In step S2, the patterning on the N-type semiconductor surface is achieved by a combination of photolithography and / or nanoimprint etching, wherein the outer side of the patterned N-type semiconductor surface is a semiconductor or insulating material with a specific carrier concentration.

3. A method for increasing carrier concentration in a p-type semiconductor based on structural pressure enhancement according to claim 1 or 2, characterized in that, In step S2, the patterned quantum well is realized by selectively processing the quantum well semiconductor with a laser, electron beam, or ion beam. The quantum well is a multi-component semiconductor. The first specific melting point, boiling point, or decomposition point component in the quantum well evaporates or sublimates, and the second specific melting point, boiling point, or decomposition point component in the quantum well becomes the patterned material.

4. A method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 1 or 2, characterized in that, In step S2, the patterned quantum well semiconductor is realized by selectively heating a P-type semiconductor with a laser, electron beam, or ion beam. The quantum well is a multi-component semiconductor. The component material with a first specific melting point, boiling point, or decomposition point in the quantum well evaporates or sublimates, and the component material with a second specific melting point, boiling point, or decomposition point in the quantum well becomes the patterned material. The first specific melting point is less than the second specific melting point in the quantum well, or the first specific boiling point is less than the second specific boiling point in the quantum well.

5. The method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 1, characterized in that, In step S3, the patterning of the quantum well surface is achieved by photolithography and / or nanoimprint etching combined with etching, and / or laser etching and / or chemical etching and / or electron beam and / or ion beam etching. The outer side of the patterned quantum well surface is a semiconductor or insulating material with a specific carrier concentration.

6. The method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 5, characterized in that, When the P-type semiconductor is P-GaN or P-AlGaN, the specific carrier concentration is 1*10. 16 cm -3 .

7. A method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 1 or 5, characterized in that, In step S3, the patterned P-type semiconductor is achieved by selectively heating the P-type semiconductor with a laser, an electron beam, or an ion beam. The P-type semiconductor is a multi-component semiconductor. The first specific melting point, boiling point, or decomposition point component in the P-type semiconductor evaporates or sublimates, and the second specific melting point, boiling point, or decomposition point component in the P-type semiconductor becomes the patterned material.

8. The method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 1, characterized in that, In step S3, the patterned P-type semiconductor is achieved by photolithography and / or nanoimprint etching, and / or laser etching and / or chemical etching and / or electron beam and / or ion beam etching, wherein the ion beam is gallium ion etching.

9. The method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 1, characterized in that, The P-type semiconductor has an insulating ring center.

10. The method for increasing carrier concentration in a p-type semiconductor based on structural pressure boosting according to claim 1, characterized in that, The quantum well (1) is composed of multiple components, including at least a first specific melting point or boiling point or decomposition point component and a second specific melting point or boiling point or decomposition point component, and the second specific melting point or boiling point or decomposition point component is a patterned material. The first specific melting point is less than the second specific melting point in the quantum well, or the first specific boiling point is less than the second specific boiling point in the quantum well, or the first specific decomposition point is less than the second specific decomposition point in the quantum well.

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