Light-emitting chip
By using a coating layer and doped film containing specific elements in the micro light-emitting chip, the sidewall damage problem caused by ICP etching is solved, thereby improving the chip's luminous efficiency and stability.
Patent Information
- Application Number
- CN202411155474.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2026-03-03
AI Technical Summary
In the fabrication of micro LEDs, sidewall damage caused by ICP etching affects chip performance and reliability, especially in micron-sized chips.
A first coating layer containing elements such as Al, Si, and Ti is used, combined with doped thin films containing elements such as F, Sc, Mg, and Y to form a protective and passivation layer. By generating an outward electric field, carrier radiative recombination is concentrated in the central region of the chip, reducing sidewall damage, and the stability is further improved by the second coating layer.
It effectively reduces sidewall damage, improves the luminous brightness and energy efficiency of the light-emitting chip, and enhances the stability and long-term reliability of the device.
Smart Images
Figure CN121604576A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and more specifically to a light-emitting chip. Background Technology
[0002] Miniature inorganic light-emitting diodes, including Mini LED and Micro LED, have been widely used in backlighting, VR screens, mobile phone displays, and small displays due to their many advantages such as high resolution, high brightness, high contrast, and low energy consumption. Summary of the Invention
[0003] This disclosure aims to address at least one of the technical problems existing in the prior art by proposing a light-emitting chip.
[0004] To achieve the above objectives, this disclosure provides a light-emitting chip, comprising:
[0005] A light-emitting functional unit, comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially;
[0006] The first semiconductor layer includes a first surface facing away from the light-emitting layer and a second surface facing the light-emitting layer, as well as a first sidewall located between the first surface and the second surface;
[0007] The light-emitting layer includes a third surface facing away from the first semiconductor layer and a fourth surface facing the second semiconductor layer, as well as a second sidewall located between the third surface and the fourth surface;
[0008] The second semiconductor layer includes a fifth surface facing the light-emitting layer and a sixth surface facing away from the light-emitting layer, as well as a third sidewall located between the fifth surface and the sixth surface;
[0009] The light-emitting chip further includes a first covering layer that is in direct contact with at least one of the first sidewall, the second sidewall, and the third sidewall;
[0010] The elements of the first covering layer include a first element, a second element, and a third element;
[0011] Wherein, the first element is at least one of Al, Si, and Ti, the second element is at least one of F, Sc, Mg, and Y, and the third element includes at least one of N and O; or, the first element is at least one of Al and Si, the second element is at least one of F, Sc, Mg, Y, and Ti, and the third element includes at least one of N and O.
[0012] In some embodiments, the material of the first coating layer includes Al2O3 doped with F, or SiO2 doped with F, or SiNx doped with F.
[0013] In some embodiments, the material of the first coating layer comprises a compound composed of Al, Sc, and O, or...
[0014] Compounds composed of Al, Mg, and O, or,
[0015] Compounds composed of Al, Ti, and O, or,
[0016] Compounds composed of Al, Y, and O, or,
[0017] Compounds composed of Ti, Sc, and O, or,
[0018] Compounds composed of Ti, Mg, and O, or,
[0019] Compounds composed of Ti, Y, and O, or,
[0020] Compounds composed of Si, Sc, and O, or,
[0021] Compounds composed of Si, Mg, and O, or,
[0022] Compounds composed of Si, Ti, and O, or,
[0023] Compounds composed of Si, Y, and O, or,
[0024] Compounds composed of Al, Sc, and N, or,
[0025] Compounds composed of Al, Mg, and N, or,
[0026] Compounds composed of Al, Ti, and N, or,
[0027] Compounds composed of Al, Y, and N, or,
[0028] Compounds composed of Ti, Sc, and N, or,
[0029] Compounds composed of Ti, Mg, and N, or,
[0030] Compounds composed of Ti, Y, and N, or,
[0031] Compounds composed of Si, Sc, and N, or,
[0032] Compounds composed of Si, Mg, and N, or,
[0033] Compounds composed of Si, Ti, and N, or,
[0034] Compounds composed of Si, Y, and N.
[0035] In some embodiments, the light-emitting chip further includes at least one second coating layer located on the side of the first coating layer away from the light-emitting functional part, wherein the material of the second coating layer is an insulating material.
[0036] In some embodiments, the material of the second coating layer includes SiO2, AlN, Al2O3, and SiN. x At least one of TiO2.
[0037] In some embodiments, the material of the first semiconductor layer includes N-type GaN, the material of the second semiconductor layer includes P-type GaN, and the light-emitting layer includes at least one of a multi-quantum-well layer, a quantum dot, and a single quantum well; the area of the third surface is smaller than the area of the fourth surface;
[0038] The first semiconductor layer includes a first feature portion located within the first semiconductor layer that is closest to the light-emitting layer; the second semiconductor layer includes a second feature portion located within the second semiconductor layer that is closest to the light-emitting layer;
[0039] The orthographic projection of the first feature on the reference plane is located inside the orthographic projection of the second feature on the reference plane; the orthographic projection of the light-emitting layer on the reference plane is located inside the orthographic projection of the second feature on the reference plane; the orthographic projection of the first feature on the reference plane is located inside the orthographic projection of the light-emitting layer on the reference plane.
[0040] Along the first direction, the area of the cross section of the first feature portion perpendicular to the first direction gradually increases; along the first direction, the area of the cross section of the light-emitting layer perpendicular to the first direction gradually increases; along the first direction, the area of the cross section of the second feature portion perpendicular to the first direction gradually increases.
[0041] Wherein, the reference plane is a plane parallel to the extension surface of the second semiconductor layer; the first direction is a direction perpendicular to the extension surface of the second semiconductor layer and pointing from the fifth plane to the sixth plane.
[0042] In some embodiments, the material of the first semiconductor layer includes N-type GaN, the material of the second semiconductor layer includes P-type GaN, and the light-emitting layer includes at least one of a multi-quantum-well layer, a quantum dot, and a single quantum well; the area of the third surface is smaller than the area of the fourth surface;
[0043] The orthographic projection of the first semiconductor layer on the reference plane is located inside the orthographic projection of the second semiconductor layer on the reference plane; the orthographic projection of the light-emitting layer on the reference plane is located inside the orthographic projection of the second semiconductor layer on the reference plane; the orthographic projection of the first semiconductor layer on the reference plane is located inside the orthographic projection of the light-emitting layer on the reference plane.
[0044] Along the first direction, the area of the cross-section of the first semiconductor layer perpendicular to the first direction gradually increases; along the first direction, the area of the cross-section of the light-emitting layer perpendicular to the first direction gradually increases; along the first direction, the area of the cross-section of the second semiconductor layer perpendicular to the first direction gradually increases.
[0045] Wherein, the reference plane is a plane parallel to the extension surface of the second semiconductor layer; the first direction is a direction perpendicular to the extension surface of the second semiconductor layer and pointing from the fifth plane to the sixth plane.
[0046] In some embodiments, the material of the first semiconductor layer includes N-type GaN, the material of the second semiconductor layer includes P-type GaN, the light-emitting layer includes at least one of a multi-quantum well layer, a quantum dot, and a single quantum well, and the area of the third surface is greater than the area of the fourth surface.
[0047] The orthographic projection of the second semiconductor layer on the reference plane is located inside the orthographic projection of the first semiconductor layer on the reference plane; the orthographic projection of the light-emitting layer on the reference plane is located inside the orthographic projection of the first semiconductor layer on the reference plane; the orthographic projection of the second semiconductor layer on the reference plane is located inside the orthographic projection of the light-emitting layer on the reference plane.
[0048] Along the first direction, the area of the cross-section of the first semiconductor layer perpendicular to the first direction gradually decreases; along the first direction, the area of the cross-section of the light-emitting layer perpendicular to the first direction gradually decreases; along the first direction, the area of the cross-section of the second semiconductor layer perpendicular to the first direction gradually decreases.
[0049] Wherein, the reference plane is a plane parallel to the extension surface of the second semiconductor layer; the first direction is a direction perpendicular to the extension surface of the second semiconductor layer and pointing from the fifth plane to the sixth plane.
[0050] In some embodiments, the light-emitting functional unit further includes a third semiconductor layer located between the second semiconductor layer and the light-emitting layer;
[0051] The material of the third semiconductor layer includes P-type GaAlN;
[0052] The third semiconductor layer includes a ninth surface near the light-emitting layer and a tenth surface away from the light-emitting layer, and a fifth sidewall located between the ninth surface and the tenth surface, the fifth sidewall being in direct contact with the first covering layer;
[0053] The area of the third surface is smaller than the area of the fourth surface. The orthographic projection of the third semiconductor layer on the reference surface lies within the orthographic projection of the second semiconductor layer on the reference surface. The orthographic projection of the light-emitting layer on the reference surface lies within the orthographic projection of the third semiconductor layer on the reference surface. Along the first direction, the area of the cross-section of the third semiconductor layer perpendicular to the first direction gradually increases, or...
[0054] The area of the third surface is greater than the area of the fourth surface. The orthographic projection of the second semiconductor layer on the reference surface is located inside the orthographic projection of the third semiconductor layer on the reference surface. The orthographic projection of the third semiconductor layer on the reference surface is located inside the orthographic projection of the light-emitting layer on the reference surface. Furthermore, along the first direction, the area of the cross section of the third semiconductor layer perpendicular to the first direction gradually decreases.
[0055] In some embodiments, the light-emitting chip includes a connection portion located on the side of the first semiconductor layer away from the light-emitting layer;
[0056] The connecting portion is electrically connected to the first semiconductor layer, and the orthographic projection of the first semiconductor layer on the reference surface is located inside the orthographic projection of the connecting portion on the reference surface, and the orthographic projection of the first semiconductor layer on the reference surface and the orthographic projection of the connecting portion on the reference surface do not completely overlap.
[0057] The reference plane is a plane parallel to the extension surface of the second semiconductor layer.
[0058] In some embodiments, the connection portion includes a first sub-layer that is in direct contact with the first semiconductor layer;
[0059] The first sublayer and the first semiconductor layer are made of the same material and are an integral structure. The orthographic projection of the first sublayer on the reference surface covers and extends beyond the orthographic projection of the first semiconductor layer on the reference surface.
[0060] In some embodiments, the connection portion further includes a second sublayer located away from the first semiconductor layer in the first sublayer, the material of the second sublayer including at least one of GaN and AlN.
[0061] In some embodiments, the light-emitting chip further includes a substrate located on the side of the second sublayer away from the first sublayer, the substrate being made of at least one of sapphire, silicon, and silicon carbide.
[0062] In some embodiments, the connection portion includes a main body portion and an edge portion surrounding at least a portion of the main body portion; the main body portion is disposed opposite to the first semiconductor layer; the orthographic projection of the edge portion on the reference plane is located outside the orthographic projection of the main body portion on the reference plane;
[0063] The first coating layer also covers at least a portion of the surface of the edge near the first semiconductor layer; the light-emitting chip also includes a first electrode;
[0064] The first electrode is located on the edge portion near the first semiconductor layer and is electrically connected to the connection portion through a first via penetrating the first cladding layer.
[0065] In some embodiments, the first covering layer further covers at least a portion of the surface of the light-emitting functional part away from the light-emitting layer;
[0066] The light-emitting chip also includes a second electrode;
[0067] The second electrode is located on the side of the light-emitting functional part away from the connection part, and is electrically connected to the second semiconductor layer through a second via penetrating the first covering layer.
[0068] In some embodiments, the first covering layer further covers at least a portion of the surface of the light-emitting functional portion away from the light-emitting layer; the light-emitting functional portion further includes a current spreading layer located between the first covering layer and the second semiconductor layer, the current spreading layer being electrically connected to the second semiconductor layer;
[0069] The current spreading layer includes a seventh surface facing the light-emitting layer, an eighth surface facing away from the light-emitting layer, and a fourth sidewall located between the seventh surface and the eighth surface;
[0070] The first covering layer is also in direct contact with the fourth sidewall;
[0071] The light-emitting chip also includes a second electrode; the second electrode is electrically connected to the current spreading layer through a third via penetrating the first covering layer.
[0072] In some embodiments, the thickness of the first coating layer is in the range of 5-100 nm. Attached Figure Description
[0073] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:
[0074] Figure 1 This is a cross-sectional structural diagram of the light-emitting chip in some embodiments of this disclosure;
[0075] Figure 2 This is a cross-sectional view of the light-emitting chip in some other embodiments of this disclosure;
[0076] Figure 3 This is a cross-sectional structural diagram of the light-emitting chip in some embodiments of this disclosure;
[0077] Figure 4 This is a cross-sectional structural diagram of the light-emitting chip in some embodiments of this disclosure;
[0078] Figure 5 This is an exploded view of the light-emitting functional part in some embodiments of this disclosure;
[0079] Figure 6 This is an exploded view of the light-emitting functional unit in some other embodiments of this disclosure;
[0080] Figure 7 These are effect analysis diagrams of the light-emitting chips in some embodiments of this disclosure;
[0081] Figure 8 These are effect analysis diagrams of the light-emitting chips in other embodiments of this disclosure;
[0082] Figure 9 This is a schematic diagram of the fabrication process of the light-emitting chip in some embodiments of this disclosure;
[0083] Figure 10 This is a cross-sectional structural diagram of the light-emitting chip in some embodiments of this disclosure;
[0084] Figure 11 This is an exploded view of the light-emitting functional unit in some embodiments of this disclosure. Detailed Implementation
[0085] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.
[0086] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0087] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0088] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.
[0089] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
[0090] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0091] With the advancement of technology, Micro-LED display technology is being used to fabricate even smaller micro-light-emitting chips. As the size continues to shrink, a series of new challenges have emerged in the fabrication process of these chips, one of which is the problem of sidewall damage.
[0092] In related technologies, ICP (Inductively Coupled Plasma) etching is commonly used for pattern definition and dimensional control during the fabrication of light-emitting chips (LEDs). During ICP etching, an ion beam bombards the surface of the LED with high energy to achieve precise pattern definition. However, this high-energy ion bombardment can cause damage to the LED sidewalls, including increased surface roughness, altered crystal structure, and changes in chemical composition, thus affecting the LED's performance and reliability. The formation of LED sidewall damage is mainly influenced by etching parameters during ICP etching (such as power, gas composition, and etching time) and the characteristics of the LED material. Sidewall damage is particularly prominent for micrometer-scale LEDs, and its impact on performance is more significant due to the smaller size of the LEDs. Therefore, mitigating sidewall damage during ICP etching to further prevent its impact on LED performance is of great importance.
[0093] In order to at least alleviate or solve one of the aforementioned technical problems, this disclosure provides a light-emitting chip 100. Figure 1 This is a cross-sectional structural diagram of the light-emitting chip in some embodiments of this disclosure. Figure 2 This is a cross-sectional view of the light-emitting chip in some other embodiments of this disclosure. Figure 3 This is a cross-sectional view of the light-emitting chip in some embodiments of this disclosure. Figure 4 This is a cross-sectional structural diagram of the light-emitting chip in some embodiments of this disclosure.
[0094] Depend on Figures 1 to 4 As can be seen, the light-emitting chip disclosed herein includes a light-emitting functional unit 101, which includes a first semiconductor layer 1, a light-emitting layer 2, and a second semiconductor layer 32 stacked sequentially.
[0095] Figure 5 This is an exploded view of the light-emitting functional unit in some embodiments of this disclosure. Figure 5 It is understood that the first semiconductor layer 1 includes a first surface 11 facing away from the light-emitting layer 2 and a second surface 12 facing the light-emitting layer 2, as well as a first sidewall 13 located between the first surface 11 and the second surface 12. The light-emitting layer 2 includes a third surface 21 facing away from the first semiconductor layer 1 and a fourth surface 22 facing the second semiconductor layer 32, as well as a second sidewall 23 located between the third surface 21 and the fourth surface 22. The second semiconductor layer 32 includes a fifth surface 301 facing the light-emitting layer 2 and a sixth surface 302 facing away from the light-emitting layer 2, as well as a third sidewall 303 located between the fifth surface 301 and the sixth surface 302.
[0096] Combination Figures 1 to 5It is understood that the light-emitting chip 100 also includes a first covering layer 106. The first covering layer 106 includes a first portion 1061 that is in direct contact with at least one of the first sidewall 13, the second sidewall 23, and the third sidewall 303. For example, in one example, the first covering layer 106 includes a first portion 1061 that is in direct contact with the second sidewall 23. In another example, the first covering layer 106 includes a first portion 1061 that is in direct contact with the first sidewall 21 and the second sidewall 23. In yet another example, such as Figures 1 to 4 As shown, the first covering layer 106 includes a first portion 1061 that is in direct contact with the first sidewall 13, the second sidewall 23 and the third sidewall 303.
[0097] Furthermore, the elements in the first part 1061 include a first element, a second element, and a third element. The first element is at least one of Al, Si, and Ti; the second element is at least one of F, Sc, Mg, and Y; and the third element includes at least one of N and O. Alternatively, the first element is at least one of Al and Si; the second element is at least one of F, Sc, Mg, Y, and Ti; and the third element includes at least one of N and O.
[0098] In this embodiment, the first coating layer 106 includes a first element, a second element, and a third element. Elements such as N, O, Al, and Si possess insulating and passivating properties, protecting the light-emitting functional part 101 and effectively preventing and repairing sidewall damage. Elements such as F, Mg, Y, and Ti can generate an outward electric field (in the direction of the first coating layer 106 away from the light-emitting functional part 101). Figure 7 These are diagrams illustrating the effect of the light-emitting chips in some embodiments. (Source: [Insert source here]) Figure 7The electric field E1 generated by the second element shown can concentrate the radiative recombination of charge carriers in the central region of the light-emitting chip, thereby improving photon emission efficiency and enhancing the brightness and energy efficiency of the light-emitting chip. The Sc element can assist in the injection of holes during radiative recombination, thereby enhancing the radiative recombination of charge carriers and improving photon emission efficiency. Specifically, in one example, when the first coating layer 106 includes elements Al, Sc, and O, this can be achieved by doping Sc into the Al2O3 film. In this case, Sc atoms can substitute for Al atoms and ionize to generate negative charges, thereby repelling electrons and causing them to move further towards the central region, thus avoiding areas damaged by sidewall etching. In another embodiment, when the first coating layer 106 includes elements Al, Sc, and N, the AlScN material has a certain degree of ferroelectricity and will also have an outward electric field, thus concentrating the radiative recombination of charge carriers in the central region of the light-emitting chip, improving photon emission efficiency while avoiding sidewall damage. In another example, Mg, Ti, or Y atoms can be doped into the Al2O3 film. Since Mg, Ti, or Y atoms are also weakly electronegative, they can also generate an outward electric field, making the radiative recombination process more likely to occur in the central region of the light-emitting chip, thereby improving the photon emission efficiency.
[0099] For example, in one instance, the first cladding layer 106 comprises elements O, Al, and F, which can effectively repair existing sidewall damage and prevent further damage, thus contributing to improved stability and long-term reliability of the light-emitting chip. Simultaneously, element F generates an outward electric field, guiding the radiative recombination sites of charge carriers to concentrate them as much as possible in the central region of the light-emitting chip, thereby improving photon emission efficiency and enhancing the brightness and energy efficiency of the chip. Specifically, the concentration of charge carrier radiative recombination sites in the central region of the light-emitting chip helps improve its internal quantum efficiency, meaning more electron-hole pairs will undergo radiative recombination in the central region, generating more photons and thus improving the device's luminous efficiency and energy efficiency.
[0100] In some embodiments, the material of the first coating layer 106 includes Al2O3 doped with F, or SiO2 doped with F, or SiN doped with F. x Optionally, F ions can be reacted with Al2O3 thin films, SiO2 thin films, and SiN. x One of them is bonded in the thin film.
[0101] In this embodiment of the disclosure, fluoride ions react with Al2O3 thin film, SiO2 thin film and SiN. xWhen one component in the thin film bonds, a negative fixed charge is generated. These negative charges form an electric field at the interface between the first coating layer 106 and the light-emitting functional part 101, thereby repelling electrons away from the interface and causing them to move towards the central region, resulting in a lower electron density near the interface. This charge distribution characteristic leads to a higher electron density in the central region of the light-emitting chip, thereby promoting the radiative recombination process of charge carriers to be concentrated in the central region of the device, which helps to improve the internal quantum efficiency of the device.
[0102] For example, in one example, the material of the first coating layer 106 includes an Al2O3 thin film doped with F. The Al2O3 thin film can serve as a protective layer, preventing further damage to the sidewalls of the light-emitting chip, and the passivation effect of the Al2O3 thin film also improves the durability and corrosion resistance of the light-emitting chip. Simultaneously, the Al2O3 thin film can also improve photon extraction efficiency through optical modulation effects. Furthermore, doping the Al2O3 thin film with F, for example, by using F ion implantation technology, can effectively reduce the number of charge carriers in the sidewall region of the light-emitting chip, allowing radiative recombination to concentrate as much as possible in the central region of the device, thereby improving the internal quantum efficiency of the device. Introducing a negative fixed charge into the Al2O3 thin film passivation layer can also generate an outward electric field, thereby effectively reducing the number of charge carriers flowing laterally to the sidewalls of the light-emitting chip, thus improving the luminous efficiency of the light-emitting chip.
[0103] In some embodiments, the material of the first coating layer 106 includes: a compound composed of Al, Sc, and O; or a compound composed of Al, Mg, and O; or a compound composed of Al, Ti, and O; or a compound composed of Al, Y, and O; or a compound composed of Ti, Sc, and O; or a compound composed of Ti, Mg, and O; or a compound composed of Ti, Y, and O; or a compound composed of Si, Sc, and O; or a compound composed of Si, Mg, and O; or a compound composed of Si, Ti, and O; or a compound composed of Si, Y, and O; or a compound composed of Al, Sc, and N; or a compound composed of Al, Mg, and N; or a compound composed of Al, Ti, and N; or a compound composed of Al, Y, and N; or a compound composed of Ti, Sc, and N; or a compound composed of Ti, Mg, and N; or a compound composed of Ti, Y, and N; or a compound composed of Si, Sc, and N; or a compound composed of Si, Mg, and N; or a compound composed of Si, Ti, and N; or a compound composed of Si, Y, and N.
[0104] For example, in one instance, the material of the first coating layer 106 comprises a compound consisting of Al, Mg, and O. Specifically, the material of the first portion 1061 can be an Al2O3 thin film doped with Mg atoms. Because Mg atoms have very low electronegativity, they can still generate an outward electric field, causing the radiative recombination process to tend to occur in the central region of the device.
[0105] Optionally, the doping concentration of the atoms or ions that generate the external electric field is in the range of 10. 15 ~10 18 pcs / cm 3 .
[0106] In some embodiments, such as Figure 4 As shown, the light-emitting chip 100 also includes at least one second covering layer 107 located on the side of the first covering layer 106 away from the light-emitting functional part 101, and the material of the second covering layer 107 is an insulating material.
[0107] In this embodiment of the disclosure, by covering the outside of the first covering layer 106 with at least one second covering layer, the performance and stability of the device can be further improved.
[0108] In some embodiments, the material of the second coating layer 107 includes SiO2 and SiN. x At least one of TiO2.
[0109] In this embodiment, a second coating layer 107, such as SiO2 or SiNx, can be superimposed on the first coating layer 106. By combining the advantages of different materials, the stability of the device can be greatly improved.
[0110] In some embodiments, the material of the first semiconductor layer 1 includes N-type GaN, the material of the second semiconductor layer 32 includes P-type GaN, and the light-emitting layer 2 includes at least one of a multi-quantum well layer, a quantum dot, and a single quantum well. Figure 10 This is a cross-sectional structural diagram of the light-emitting chip in some embodiments of this disclosure. Figure 1 and Figure 2 In the illustrated embodiment, combined with Figure 10It is known that the first semiconductor layer 1 includes a first feature portion 120 located within the first semiconductor layer 1 that is closest to the light-emitting layer 2, and a first semiconductor portion 110 located within the first semiconductor layer 1 that is far from the light-emitting layer 2. The second semiconductor layer 32 includes a second feature portion 321 located within the second semiconductor layer 32 that is closest to the light-emitting layer 2, and a second semiconductor portion 322 located within the second semiconductor layer 32 that is far from the light-emitting layer 2. The orthographic projection of the first feature portion 120 onto the reference plane a is located inside the orthographic projection of the second feature portion 321 onto the reference plane a. The orthographic projection of the light-emitting layer 2 onto the reference plane a is located inside the orthographic projection of the second feature portion 321 onto the reference plane a; the orthographic projection of the first feature portion 120 onto the reference plane a is located inside the orthographic projection of the light-emitting layer 2 onto the reference plane a. Along the first direction, the area of the cross-section of the first feature portion 120 perpendicular to the first direction gradually increases. Along the first direction, the area of the cross-section of the light-emitting layer 2 perpendicular to the first direction gradually increases. Along the first direction, the area of the cross-section of the second feature portion 321 perpendicular to the first direction gradually increases. In this embodiment, reference plane a is a plane parallel to the extension surface of the second semiconductor layer 32; the first direction is a direction perpendicular to the extension surface and pointing from the fifth surface to the sixth surface. It should be further noted that in this embodiment, the cross-section of the first feature portion 120 passing through its centroid and perpendicular to reference plane a is trapezoidal, and the cross-section of the second feature portion 321 passing through its centroid and perpendicular to the reference plane is trapezoidal. Further, along the first direction, the cross-section of the first feature portion 120 passing through its centroid and perpendicular to reference plane a is an inverted trapezoid, and the cross-section of the second feature portion 321 passing through its centroid and perpendicular to the reference plane is an inverted trapezoid. In this embodiment, a regular trapezoid refers to a trapezoid where the length of the upper base is less than the length of the lower base. The lower base and upper base are arranged sequentially along the first direction. Correspondingly, in this embodiment, an inverted trapezoid refers to a trapezoid where the length of the upper base is greater than the length of the lower base.
[0111] The area of the cross-section of the first semiconductor section 110 perpendicular to the first direction remains unchanged. The area of the cross-section of the second semiconductor section 322 perpendicular to the first direction also remains unchanged.
[0112] The embodiments disclosed herein enable the first feature portion 10, the second feature portion 320, and the second light-emitting layer 2 to all be inverted trapezoidal, so that the electric field generated between the first feature portion 10 and the second feature portion 320 is obliquely upward. Figure 8 These are effect analysis diagrams of the light-emitting chip in other embodiments of this disclosure. Figure 8As shown in the diagram, the electric field E2, through vector decomposition, reveals both an upward-directing electric field Ex and an outward-directing electric field Ey. Since electrons are negatively charged, the outward-directing electric field Ey repels them away from the interface between the first coating layer 106 and the light-emitting functional part 101, causing them to move towards the central region. Therefore, the electron density near the interface is low. Furthermore, the doped second elements F, Sc, Mg, Y, Ti, etc., also tend to repel electrons, causing the electron interface to move further towards the central region, thus avoiding areas affected by etching damage.
[0113] In some embodiments, the material of the first semiconductor layer 1 includes N-type GaN, the material of the second semiconductor layer 32 includes P-type GaN, and the light-emitting layer 2 includes at least one of a multiple quantum well layer, a quantum dot, and a single quantum well. Figure 1 and Figure 2 In the illustrated embodiment, combined with Figure 6 It can be seen that the orthographic projection of the first semiconductor layer 1 on reference surface a is located inside the orthographic projection of the second semiconductor layer 32 on reference surface a; the orthographic projection of the light-emitting layer 2 on reference surface a is located inside the orthographic projection of the second semiconductor layer 32 on reference surface a; the orthographic projection of the first semiconductor layer 1 on reference surface a is located inside the orthographic projection of the light-emitting layer 2 on reference surface a; the orthographic projection of the first surface 11 on reference surface a is located inside the orthographic projection of the second surface 12 on reference surface a, and along the first direction, the area of the cross section of the first semiconductor layer 1 perpendicular to the first direction gradually increases; the third surface 21 The orthographic projection of the fourth surface 22 onto reference surface a is located inside the orthographic projection of the fourth surface 22 onto reference surface a, and along the first direction, the area of the cross-section of the light-emitting layer 2 perpendicular to the first direction gradually increases; the orthographic projection of the fifth surface 301 onto reference surface a is located inside the orthographic projection of the sixth surface 302 onto reference surface a, and along the first direction, the area of the cross-section of the second semiconductor layer 32 perpendicular to the first direction gradually increases; wherein, reference surface a is a plane parallel to the extension surface of the second semiconductor layer 32; the first direction is a direction perpendicular to the extension surface and pointing from the fifth surface 301 to the sixth surface 302. It should be further noted that, in this embodiment of the present disclosure, the cross-section of the first semiconductor layer 1 passing through the centroid of the first semiconductor layer 1 and perpendicular to reference surface a is trapezoidal, and the cross-section of the second semiconductor layer 32 passing through the centroid of the second semiconductor layer 32 and perpendicular to the reference surface is trapezoidal. Furthermore, along the first direction, the cross section of the first semiconductor layer 1 passing through the centroid of the first semiconductor layer 1 and perpendicular to the reference surface a is a positive trapezoid, and the cross section of the second semiconductor layer 32 passing through the centroid of the second semiconductor layer 32 and perpendicular to the reference surface is a positive trapezoid.
[0114] In this embodiment of the disclosure, the light-emitting functional unit 101 is configured as an inverted trapezoid, and the electric field E2 generated between the first semiconductor layer 1 and the second semiconductor layer 32 is obliquely upward, such as... Figure 8As shown, the outward electric field Ey of the electric field E2 can repel electrons away from the interface and move them towards the central region. Therefore, the electron density near the interface is low, which can help avoid areas of etching damage.
[0115] In some embodiments, the material of the first semiconductor layer 1 includes N-type GaN, the material of the second semiconductor layer 32 includes P-type GaN, and the light-emitting layer 2 includes at least one of a multiple quantum well layer, a quantum dot, and a single quantum well. Figure 3 and Figure 4 In the illustrated embodiment, combined with Figure 5 It can be seen that: the orthographic projection of the second semiconductor layer 32 on the reference surface a is located inside the orthographic projection of the first semiconductor layer 1 on the reference surface a; the orthographic projection of the light-emitting layer 2 on the reference surface a is located inside the orthographic projection of the first semiconductor layer 1 on the reference surface a; the orthographic projection of the second semiconductor layer 32 on the reference surface a is located inside the orthographic projection of the light-emitting layer 2 on the reference surface a; the orthographic projection of the second surface 12 on the reference surface a is located inside the orthographic projection of the first surface 11 on the reference surface a, and along the first direction, the area of the cross section of the first semiconductor layer 1 perpendicular to the first direction gradually decreases; the orthographic projection of the fourth surface 22 on the reference surface a is located inside the orthographic projection of the third surface 21 on the reference surface a, and along the first direction, the area of the cross section of the light-emitting layer 2 perpendicular to the first direction gradually decreases; the orthographic projection of the sixth surface 302 on the reference surface a is located inside the orthographic projection of the fifth surface 301 on the reference surface a, and along the first direction, the area of the cross section of the second semiconductor layer 32 perpendicular to the first direction gradually decreases. It should be further noted that, in this embodiment, the cross-section of the first semiconductor layer 1 passing through its centroid and perpendicular to the reference surface a is trapezoidal, and the cross-section of the second semiconductor layer 32 passing through its centroid and perpendicular to the reference surface is trapezoidal. Furthermore, along the first direction, the cross-section of the first semiconductor layer 1 passing through its centroid and perpendicular to the reference surface a is an inverted trapezoid, and the cross-section of the second semiconductor layer 32 passing through its centroid and perpendicular to the reference surface is an inverted trapezoid.
[0116] In some embodiments, such as Figures 1 to 4 As shown, the light-emitting functional unit 101 also includes a third semiconductor layer 31 located between the second semiconductor layer 32 and the light-emitting layer 2. The material of the third semiconductor layer 31 includes P-type GaAlN, that is, P-type GaAlN formed by doping certain atoms into GaAlN.
[0117] In some embodiments, such as Figure 11 As shown, the third semiconductor layer 31 includes a ninth surface 311 near the light-emitting layer 2 and a tenth surface 312 away from the light-emitting layer 2, as well as a fifth sidewall 313 located between the ninth surface 311 and the tenth surface 312. Figure 1 and Figure 2As shown, the fifth sidewall 313 is in direct contact with the first covering layer 106.
[0118] Specifically, in one example, the area of the third face 21 is smaller than the area of the fourth face 22, such as... Figure 1 and Figure 2 As shown, and in combination Figure 11 It can be seen that: the orthographic projection of the third semiconductor layer 31 on reference surface a is located inside the orthographic projection of the second semiconductor layer 32 on reference surface a; the orthographic projection of the light-emitting layer 2 on reference surface a is located inside the orthographic projection of the third semiconductor layer 31 on reference surface a; the orthographic projection of the ninth surface 311 on reference surface a is located inside the orthographic projection of the tenth surface 312 on reference surface a, and along the first direction, the area of the cross-section of the third semiconductor layer 31 perpendicular to the first direction gradually increases. It should be further noted that, in this embodiment, the cross-section of the third semiconductor layer 31 passing through the centroid of the third semiconductor layer 31 and perpendicular to reference surface a is trapezoidal. Further, along the first direction, the cross-section of the third semiconductor layer 31 passing through the centroid of the third semiconductor layer 31 and perpendicular to reference surface a is an inverted trapezoid.
[0119] Specifically, in another example, the area of the third face 21 is greater than the area of the fourth face 22. For example... Figure 3 and Figure 4 As shown, the orthographic projection of the second semiconductor layer 32 on reference surface a lies inside the orthographic projection of the third semiconductor layer 31 on reference surface a; the orthographic projection of the third semiconductor layer 31 on reference surface a lies inside the orthographic projection of the light-emitting layer 2 on reference surface a; the orthographic projection of the tenth surface 312 on reference surface a lies inside the orthographic projection of the ninth surface 311 on reference surface a, and along the first direction, the area of the cross-section of the third semiconductor layer 31 perpendicular to the first direction gradually decreases. It should be further noted that, in this embodiment, the cross-section of the third semiconductor layer 31 passing through its centroid and perpendicular to reference surface a is trapezoidal. Furthermore, along the first direction, the cross-section of the third semiconductor layer 31 passing through its centroid and perpendicular to reference surface a is a regular trapezoid.
[0120] In this embodiment, the third semiconductor layer 31 can serve as an electron blocking layer, blocking electrons from being transported toward the second semiconductor layer 32.
[0121] It should be noted that the shape of the third semiconductor layer 31 is not specifically required in the embodiments disclosed herein. In some embodiments, the third semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 2 can be etched simultaneously in a single etching process. In this case, when the second semiconductor layer 32 and the light-emitting layer 2 are in a positive trapezoidal shape after the etching process, the third semiconductor layer 31 is also in a positive trapezoidal shape. Similarly, when the second semiconductor layer 32 and the light-emitting layer 2 are in an inverted trapezoidal shape after the etching process, the third semiconductor layer 31 is also in an inverted trapezoidal shape. In other embodiments, the third semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 2 can be etched separately in different etching processes. In this case, the area of the cross-section of the third semiconductor layer 31 perpendicular to the first direction can remain unchanged.
[0122] In some embodiments, such as Figures 1 to 4 As shown, the light-emitting chip 100 includes a connection portion 102 located on the side of the first semiconductor layer 1 away from the light-emitting layer 2; the connection portion 102 is electrically connected to the first semiconductor layer 1, and the orthographic projection of the first semiconductor layer 1 on the reference surface a is located inside the orthographic projection of the connection portion 102 on the reference surface a, and the orthographic projection of the first semiconductor layer 1 on the reference surface a and the orthographic projection of the connection portion 102 on the reference surface a do not completely overlap; wherein, the reference surface a is a plane parallel to the extension surface of the second semiconductor layer 32.
[0123] In some embodiments, the connection portion 102 includes a first sub-layer 5 that is in direct contact with the first semiconductor layer 1; wherein the first sub-layer 5 is made of the same material as the first semiconductor layer 1 and is an integral structure.
[0124] Accordingly, in this embodiment of the present disclosure, since the first sub-layer 5 and the first semiconductor layer 1 are made of the same material and are an integral structure, it can be understood that the first surface 11 of the first semiconductor layer 1 is not the interface between the two material layers, but the connection surface between the first semiconductor layer 1 and the first sub-layer 5.
[0125] In this embodiment of the disclosure, the first sub-layer 5 and the first semiconductor layer 1 are made of the same material and are an integral structure, which can improve the electrical connection effect between the first sub-layer 5 and the first semiconductor layer 1.
[0126] In some embodiments, the connection portion 102 includes a second sub-layer 6 located away from the first semiconductor layer 1 in the first sub-layer 5. The material of the second sub-layer 6 includes at least one of GaN and AlN, serving as a buffer layer. For example, in one example, the material of the second sub-layer 6 includes AlN. In another example, the material of the second sub-layer 6 includes both GaN and AlN. In yet another example, the material of the second sub-layer 6 includes GaN. It should be noted that the GaN included in the material of the second sub-layer 6 refers to GaN without any other doping. The P-type GaN material of the first semiconductor layer 1 refers to P-type GaN formed by doping GaN with atoms such as Mg. The N-type GaN material of the second semiconductor layer 32 refers to N-type GaN formed by doping GaN with atoms such as Si.
[0127] In some embodiments, the light-emitting chip 100 further includes a substrate 105 located on the side of the second sublayer 6 away from the first sublayer 5, and the material of the substrate 105 includes at least one of sapphire, silicon and silicon carbide.
[0128] In some embodiments, such as Figures 1 to 4 As shown, the connecting portion 102 includes a main body portion 121 and an edge portion 122 surrounding at least a portion of the main body portion 121. The main body portion 121 is disposed opposite to the first semiconductor layer 1; the orthographic projection of the edge portion 122 on the reference plane a is located outside the orthographic projection of the main body portion 121 on the reference plane a. The first cladding layer 106 also includes a second portion 1062 covering at least a portion of the surface of the edge portion 122 near the first semiconductor layer 1.
[0129] In some embodiments, such as Figures 1 to 4 As shown, the light-emitting chip 100 also includes a first electrode 103. The first electrode 103 is located on the side of the edge portion 122 near the first semiconductor layer 1, and is electrically connected to the connection portion 102 through a first via penetrating the second portion 1062.
[0130] exist Figures 1 to 4 In the embodiment shown, since the connection portion 102 includes a first sub-layer 5 and the first sub-layer 5 is in direct contact with the first semiconductor layer 1, the first electrode 103 is electrically connected to the first sub-layer 5 through a first via penetrating the second portion 1062.
[0131] In some embodiments, such as Figures 1 to 4 As shown, the first covering layer 106 also includes a third portion 1063 that covers at least a portion of the surface of the light-emitting functional part 101 away from the light-emitting layer 2.
[0132] Optionally, the third portion 1063 covers at least a portion of the surface of the second semiconductor layer 32 away from the light-emitting layer 2. In one example, the doping element Sc in the third portion 1063 can further significantly promote hole injection.
[0133] In some embodiments, such as Figure 1 As shown, the light-emitting chip 100 also includes a second electrode 104. The second electrode 104 is located on the side of the light-emitting functional part 101 away from the connection part 102, and is electrically connected to the second semiconductor layer 32 through a second via penetrating the third part 1063.
[0134] In some embodiments, such as Figure 4 As shown, the light-emitting functional unit 101 also includes a current spreading layer 4 located on the side of the second semiconductor layer 32 away from the first semiconductor layer 1. Figure 8 This is an exploded view of the light-emitting functional unit 101 in other embodiments of this disclosure. The current spreading layer 4 is electrically connected to the second semiconductor layer 32. Figure 4 and Figure 8 It is known that the current spreading layer 4 includes a seventh surface 41 facing the light-emitting layer 2, an eighth surface 42 facing away from the light-emitting layer 2, and a fourth sidewall 43 located between the seventh surface 41 and the eighth surface 42, and the first part 1061 is in direct contact with the fourth sidewall 43.
[0135] Optionally, the material of the current spreading layer 4 includes indium tin oxide (ITO).
[0136] In some embodiments, such as Figure 2 As shown, the light-emitting chip 100 also includes a second electrode 104. The second electrode 104 is electrically connected to the current spreading layer 4 through a third via penetrating the third portion 1063.
[0137] In this embodiment of the disclosure, the electrical connection between the second electrode 104 and the second semiconductor layer 32 is achieved through the current spreading layer 4.
[0138] In some embodiments, the thickness of the first coating layer 106 is in the range of 5-100 nm. For example, the thickness of the first coating layer 106 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm.
[0139] In this embodiment of the disclosure, the thickness of the first coating layer 106 is set in the range of 5-100nm. This ensures that the first coating layer 106 protects the sidewalls while also ensuring that the elements in the first coating layer 106 cause the radiative recombination process to tend to occur in the central region of the device.
[0140] In some embodiments, the thickness of the second coating layer 107 is in the range of 10-100 nm. For example, the thickness of the first coating layer 106 can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm.
[0141] In this embodiment of the disclosure, the thickness of the second coating layer 107 is set in the range of 10-100 nm, which can further improve the protection of the sidewall.
[0142] Figure 9 This is a cross-sectional structural schematic diagram of the process of preparing the light-emitting chip 100 in some embodiments of this disclosure.
[0143] like Figure 9 As shown, the process of fabricating the light-emitting chip 100 according to this disclosure includes steps S10 to S60:
[0144] S10. Prepare the epitaxial wafer. For example... Figure 9 As shown in (a), the epitaxial wafer includes a substrate 105 and an epitaxial layer grown on the substrate 105. The epitaxial layer, in a direction away from the substrate 105, sequentially includes a buffer material layer (second sub-layer 6), a first semiconductor material layer 10, a light-emitting layer 20, a second semiconductor material layer 310, and a third semiconductor material layer 320. The first semiconductor material layer 10 is made of N-type GaN, and the light-emitting layer 20 is made of multiple quantum wells. The second semiconductor material layer 310 is made of P-type GaN. The third semiconductor layer 320 is made of P-type AlGaN.
[0145] S20. Cleaning the epitaxial wafer: First, clean the epitaxial wafer with acetone, ethanol and deionized water. Then, sonicate the epitaxial wafer for three minutes with an ultrasonic instrument. Next, clean the epitaxial wafer with a mixture of sulfuric acid peroxide and deionized water. Finally, treat the epitaxial wafer with a buffered oxide etching solution to remove the native oxide layer on the surface of the epitaxial layer.
[0146] S30. For example Figure 9 As shown in (b), a transparent conductive layer 40 is formed on the side of the third semiconductor material layer 320 away from the first substrate 105. Optionally, if the material of the transparent conductive layer 40 includes indium tin oxide, indium tin oxide is deposited by electron beam evaporation.
[0147] S40. Patterning process for epitaxial wafers: such as... Figure 9As shown in (c), the transparent conductive layer 40 is etched using reactive ion etching (RIE) technology and etched downwards to the middle of the first semiconductor material layer 10 to form a first sublayer 5 and a light-emitting functional part 101. The light-emitting functional part 101 includes: a first semiconductor layer 1, a light-emitting layer 2, a third semiconductor layer 31, a second semiconductor layer 32, and a current spreading layer 4. The first sublayer 5 and the second sublayer 6 constitute a connection part 102.
[0148] S50. For example Figure 9 As shown in (d), a first coating material layer 1060 is formed on the outside of the optical functional part 101. Specifically, in one example, the entire optical functional part 101, the connecting part 102, and the substrate 105 are first placed in a rapid thermal annealer at 310°C under nitrogen for 5 minutes for annealing. Then, an Al2O3 thin film is prepared by sol-gel technology and doped with Sc to form an AlScO thin film, wherein the doping range of Sc is 10. 15 ~10 18 pcs / cm 3 The AlScO film is the first coating material layer 1060.
[0149] In another example, after annealing, an Al2O3 film is deposited using ALD technology. Simultaneously, F ions are implanted using an F ion implantation process to form an AlFO film. This AlFO film serves as the first coating material layer 1060.
[0150] In another example, a diffusion process was used to dope Mg atoms into an Al2O3 thin film.
[0151] Optionally, the thickness of the Al2O3 film ranges from 50 nm to 200 nm.
[0152] S60. Forming the first electrode 103 and the second electrode 104: as follows Figure 9 As shown in (e), a portion of the Al2O3 film on the side of the first sublayer 5 away from the substrate 105 is removed using high-frequency or inductively coupled plasma (ICP) etching to form a first via, and a portion of the Al2O3 film on the side of the light-emitting functional part 101 away from the substrate 105 is removed to form a third via, thereby obtaining the first coating layer 106. Figure 9 As shown in (f), a first electrode 103 and a second electrode 104 are formed by electron beam evaporation of metal. The first electrode 103 is electrically connected to the first sublayer 105 through a first via, and the second electrode 104 is electrically connected to the current spreading layer 4 through a third via. Optionally, the metal includes at least one of chromium, aluminum, nickel, and gold.
[0153] Alternatively, the steps of forming the first and third vias can also be performed before the step of doping elements.
[0154] In other embodiments, step 40, after etching the ITO using reactive ion etching (RIE) technology and etching down to the middle of the first semiconductor material layer 10, and before forming the first sublayer 5 and the light-emitting functional part 101, further includes:
[0155] Etching of the epitaxial wafer: First, photoresist is applied to the side of the etched transparent conductive layer 40 away from the substrate 105 to prevent the etched transparent conductive layer 40 from being further etched by PEC. Then, the N-type GaN material is selectively etched using photoelectrochemical (PEC) etching. Specifically, the PEC etching process utilizes light and chemical reactions to produce an etching effect on the surface of N-type GaN, while P-type GaN remains almost unaffected due to its opacity under light. Therefore, P-type GaN can be kept as intact as possible, while N-type GaN is etched, resulting in the light-emitting functional part 101 forming an inverted trapezoidal structure.
[0156] The light-emitting chip in this embodiment may include at least one of Mini LED and Micro LED.
[0157] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A light-emitting chip, characterized in that, include: A light-emitting functional unit, comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially; The first semiconductor layer includes a first surface facing away from the light-emitting layer and a second surface facing the light-emitting layer, as well as a first sidewall located between the first surface and the second surface; The light-emitting layer includes a third surface facing away from the first semiconductor layer and a fourth surface facing the second semiconductor layer, as well as a second sidewall located between the third surface and the fourth surface; The second semiconductor layer includes a fifth surface facing the light-emitting layer and a sixth surface facing away from the light-emitting layer, as well as a third sidewall located between the fifth surface and the sixth surface; The light-emitting chip further includes a first covering layer that is in direct contact with at least one of the first sidewall, the second sidewall, and the third sidewall; The elements of the first covering layer include a first element, a second element, and a third element; Wherein, the first element is at least one of Al, Si, and Ti, the second element is at least one of F, Sc, Mg, and Y, and the third element includes at least one of N and O; or, the first element is at least one of Al and Si, the second element is at least one of F, Sc, Mg, Y, and Ti, and the third element includes at least one of N and O.
2. The light-emitting chip according to claim 1, characterized in that, The material of the first coating layer includes Al2O3 doped with F, or SiO2 doped with F, or SiNx doped with F.
3. The light-emitting chip according to claim 1, characterized in that, The material of the first coating layer includes a compound composed of Al, Sc, and O, or... Compounds composed of Al, Mg, and O, or, Compounds composed of Al, Ti, and O, or, Compounds composed of Al, Y, and O, or, Compounds composed of Ti, Sc, and O, or, Compounds composed of Ti, Mg, and O, or, Compounds composed of Ti, Y, and O, or, Compounds composed of Si, Sc, and O, or, Compounds composed of Si, Mg, and O, or, Compounds composed of Si, Ti, and O, or, Compounds composed of Si, Y, and O, or, Compounds composed of Al, Sc, and N, or, Compounds composed of Al, Mg, and N, or, Compounds composed of Al, Ti, and N, or, Compounds composed of Al, Y, and N, or, Compounds composed of Ti, Sc, and N, or, Compounds composed of Ti, Mg, and N, or, Compounds composed of Ti, Y, and N, or, Compounds composed of Si, Sc, and N, or, Compounds composed of Si, Mg, and N, or, Compounds composed of Si, Ti, and N, or, Compounds composed of Si, Y, and N.
4. The light-emitting chip according to claim 1, characterized in that, The light-emitting chip further includes at least one second coating layer located on the side of the first coating layer away from the light-emitting functional part, and the material of the second coating layer is an insulating material.
5. The light-emitting chip according to claim 4, characterized in that, The materials of the second coating layer include SiO2, AlN, Al2O3, and SiN. x At least one of TiO2.
6. The light-emitting chip according to claim 1, characterized in that, The first semiconductor layer is made of N-type GaN, the second semiconductor layer is made of P-type GaN, and the light-emitting layer includes at least one of a multi-quantum-well layer, a quantum dot, and a single quantum well; the area of the third surface is smaller than the area of the fourth surface. The first semiconductor layer includes a first feature portion located within the first semiconductor layer that is closest to the light-emitting layer; the second semiconductor layer includes a second feature portion located within the second semiconductor layer that is closest to the light-emitting layer; The orthographic projection of the first feature on the reference plane is located inside the orthographic projection of the second feature on the reference plane; The orthographic projection of the light-emitting layer on the reference surface is located inside the orthographic projection of the second feature portion on the reference surface; The orthographic projection of the first feature on the reference plane is located inside the orthographic projection of the light-emitting layer on the reference plane; Along the first direction, the area of the cross section of the first feature portion perpendicular to the first direction gradually increases; along the first direction, the area of the cross section of the light-emitting layer perpendicular to the first direction gradually increases; along the first direction, the area of the cross section of the second feature portion perpendicular to the first direction gradually increases. Wherein, the reference plane is a plane parallel to the extension surface of the second semiconductor layer; the first direction is a direction perpendicular to the extension surface of the second semiconductor layer and pointing from the fifth plane to the sixth plane.
7. The light-emitting chip according to claim 1, characterized in that, The first semiconductor layer is made of N-type GaN, the second semiconductor layer is made of P-type GaN, and the light-emitting layer includes at least one of a multi-quantum-well layer, a quantum dot, and a single quantum well; the area of the third surface is smaller than the area of the fourth surface. The orthographic projection of the first semiconductor layer on the reference plane is located inside the orthographic projection of the second semiconductor layer on the reference plane; The orthographic projection of the light-emitting layer on the reference plane is located inside the orthographic projection of the second semiconductor layer on the reference plane; The orthographic projection of the first semiconductor layer onto the reference plane is located inside the orthographic projection of the light-emitting layer onto the reference plane; Along the first direction, the area of the cross-section of the first semiconductor layer perpendicular to the first direction gradually increases; along the first direction, the area of the cross-section of the light-emitting layer perpendicular to the first direction gradually increases; along the first direction, the area of the cross-section of the second semiconductor layer perpendicular to the first direction gradually increases. Wherein, the reference plane is a plane parallel to the extension surface of the second semiconductor layer; the first direction is a direction perpendicular to the extension surface of the second semiconductor layer and pointing from the fifth plane to the sixth plane.
8. The light-emitting chip according to claim 1, characterized in that, The first semiconductor layer is made of N-type GaN, the second semiconductor layer is made of P-type GaN, the light-emitting layer includes at least one of multiple quantum well layers, quantum dots and single quantum wells, and the area of the third surface is larger than the area of the fourth surface. The orthographic projection of the second semiconductor layer onto the reference plane is located inside the orthographic projection of the first semiconductor layer onto the reference plane; The orthographic projection of the light-emitting layer on the reference surface is located inside the orthographic projection of the first semiconductor layer on the reference surface; The orthographic projection of the second semiconductor layer onto the reference plane is located inside the orthographic projection of the light-emitting layer onto the reference plane; Along the first direction, the area of the cross-section of the first semiconductor layer perpendicular to the first direction gradually decreases; along the first direction, the area of the cross-section of the light-emitting layer perpendicular to the first direction gradually decreases; along the first direction, the area of the cross-section of the second semiconductor layer perpendicular to the first direction gradually decreases. Wherein, the reference plane is a plane parallel to the extension surface of the second semiconductor layer; the first direction is a direction perpendicular to the extension surface of the second semiconductor layer and pointing from the fifth plane to the sixth plane.
9. The light-emitting chip according to any one of claims 6 to 8, characterized in that, The light-emitting functional unit further includes a third semiconductor layer located between the second semiconductor layer and the light-emitting layer; The material of the third semiconductor layer includes P-type GaAlN; The third semiconductor layer includes a ninth surface close to the light-emitting layer and a tenth surface away from the light-emitting layer, and a fifth sidewall located between the ninth surface and the tenth surface, the fifth sidewall being in direct contact with the first covering layer; The area of the third surface is smaller than the area of the fourth surface. The orthographic projection of the third semiconductor layer on the reference surface lies within the orthographic projection of the second semiconductor layer on the reference surface. The orthographic projection of the light-emitting layer on the reference surface lies within the orthographic projection of the third semiconductor layer on the reference surface. Along the first direction, the area of the cross-section of the third semiconductor layer perpendicular to the first direction gradually increases, or... The area of the third surface is greater than the area of the fourth surface. The orthographic projection of the second semiconductor layer on the reference surface is located inside the orthographic projection of the third semiconductor layer on the reference surface. The orthographic projection of the third semiconductor layer on the reference surface is located inside the orthographic projection of the light-emitting layer on the reference surface. Furthermore, along the first direction, the area of the cross section of the third semiconductor layer perpendicular to the first direction gradually decreases.
10. The light-emitting chip according to any one of claims 1 to 8, characterized in that, The light-emitting chip includes a connection portion located on the side of the first semiconductor layer away from the light-emitting layer; The connecting portion is electrically connected to the first semiconductor layer, and the orthographic projection of the first semiconductor layer on the reference surface is located inside the orthographic projection of the connecting portion on the reference surface, and the orthographic projection of the first semiconductor layer on the reference surface and the orthographic projection of the connecting portion on the reference surface do not completely overlap. The reference plane is a plane parallel to the extension surface of the second semiconductor layer.
11. The light-emitting chip according to claim 10, characterized in that, The connecting portion includes a first sub-layer that is in direct contact with the first semiconductor layer; The first sub-layer and the first semiconductor layer are made of the same material and are an integral structure. The orthographic projection of the first sub-layer on the reference surface covers and extends beyond the orthographic projection of the first semiconductor layer on the reference surface.
12. The light-emitting chip according to claim 11, characterized in that, The connection portion further includes a second sublayer located away from the first semiconductor layer in the first sublayer, and the material of the second sublayer includes at least one of GaN and AlN.
13. The light-emitting chip according to claim 12, characterized in that, The light-emitting chip further includes a substrate located on the side of the second sub-layer away from the first sub-layer, and the substrate is made of at least one of sapphire, silicon, and silicon carbide.
14. The light-emitting chip according to claim 10, characterized in that, The connecting portion includes a main body portion and an edge portion surrounding at least a portion of the main body portion; the main body portion is disposed opposite to the first semiconductor layer; the orthographic projection of the edge portion on the reference plane is located outside the orthographic projection of the main body portion on the reference plane; The first coating layer also covers at least a portion of the surface of the edge near the first semiconductor layer; the light-emitting chip also includes a first electrode; The first electrode is located on the edge portion near the first semiconductor layer and is electrically connected to the connection portion through a first via penetrating the first cladding layer.
15. The light-emitting chip according to claim 10, characterized in that, The first coating layer also covers at least a portion of the surface of the light-emitting functional part away from the light-emitting layer; The light-emitting chip also includes a second electrode; The second electrode is located on the side of the light-emitting functional part away from the connection part, and is electrically connected to the second semiconductor layer through a second via penetrating the first covering layer.
16. The light-emitting chip according to claim 10, characterized in that, The first coating layer also covers at least a portion of the surface of the light-emitting functional part away from the light-emitting layer; The light-emitting functional unit further includes a current spreading layer located between the first covering layer and the second semiconductor layer, and the current spreading layer is electrically connected to the second semiconductor layer; The current spreading layer includes a seventh surface facing the light-emitting layer, an eighth surface facing away from the light-emitting layer, and a fourth sidewall located between the seventh surface and the eighth surface; The first covering layer is also in direct contact with the fourth sidewall; The light-emitting chip also includes a second electrode; the second electrode is electrically connected to the current spreading layer through a third via penetrating the first covering layer.
17. The light-emitting chip according to any one of claims 1 to 8, characterized in that, The thickness of the first coating layer is in the range of 5-100 nm.