Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first electrode layer and a second electrode layer, wherein the first electrode layer comprises a plurality of micro-fluidic electrodes; the light-emitting layer is located on the first electrode layer and comprises a plurality of light-emitting parts; wherein the light-emitting part is electrically connected with the micro-fluidic electrode, so that the light-emitting part is driven by the micro-fluidic electrode to emit light. The plurality of micro-fluidic electrodes separate the ink and transport the ink to each pixel, so that high-precision printing of the light-emitting layer of the printed OLED is realized, and the color mixing phenomenon of printing is improved. Meanwhile, the micro-fluidic electrode is reused as a display driving electrode, so that the structure of the display panel can be simplified.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, printed OLED (Organic Light-Emitting Diode) display panels use inkjet printing to form patterned pixel units. To ensure high printing efficiency, linebank printing is currently used: identical pixels are arranged in a line, and inkjet printing is performed continuously to print an entire row or column of pixels. This process relies on the surface properties of the material and the self-flowing dynamics of the liquid to achieve pixel segmentation. However, its ability to segment pixels is relatively limited, and it is prone to forming mixed-color pixels, leading to color mixing problems. Summary of the Invention

[0003] This application provides a display panel and a display device to at least partially solve the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a display panel is provided. The display panel includes: a first electrode layer comprising a plurality of microfluidic electrodes; and a light-emitting layer located on the first electrode layer, comprising a plurality of light-emitting portions; wherein the light-emitting portions are electrically connected to the microfluidic electrodes to emit light under the drive of the microfluidic electrodes.

[0005] Optionally, the light-emitting part is in contact with the microfluidic electrode and is located directly above the microfluidic electrode.

[0006] Optionally, the area of ​​the light-emitting part is smaller than the area of ​​the microfluidic electrode.

[0007] Optionally, the display panel further includes an electrode insulating layer, which includes a plurality of electrode insulating portions; wherein the electrode insulating portions are disposed between two adjacent microfluidic electrodes.

[0008] Optionally, the electrode insulating portion has hydrophobic properties.

[0009] Optionally, the display panel further includes a planarization layer, on which the electrode insulating layer and the first electrode layer are both located; wherein the electrode insulating portion is made of the same material as the planarization layer.

[0010] Optionally, the display panel has a display area and at least one ink storage area, and further includes a baffle layer located on the first electrode layer. The baffle layer has at least one ink storage cavity located in the at least one ink storage area and at least one pixel cavity located in the display area, and at least one light-emitting part is located in the pixel cavity; wherein, at least one ink storage cavity is connected to the corresponding pixel cavity.

[0011] Optionally, the barrier layer is provided with a plurality of ink storage cavities, with each pair of ink storage cavities located on opposite sides of the corresponding pixel cavity.

[0012] Optionally, the barrier layer has at least one opening, and the at least one ink storage cavity communicates with the pixel cavity through the at least one opening; wherein, from a viewing angle along the thickness direction of the display panel, the width of each opening gradually decreases in the direction from the corresponding ink storage cavity to the pixel cavity.

[0013] According to a second aspect of this application, a display device is provided, including the display panel described above.

[0014] In the display panel and display device of this application embodiment, multiple microfluidic electrodes separate and transport ink to each pixel, achieving high-precision printing of the light-emitting layer of the printed OLED and improving the color mixing phenomenon during printing. Simultaneously, the microfluidic electrodes are reused as display driving electrodes, which simplifies the structure of the display panel.

[0015] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0017] Figure 1 This is a schematic diagram of the structure of the display device provided in an exemplary embodiment of this application; Figure 2 These are schematic diagrams and top views of the film layer structure of the display panel of the display device provided in the exemplary embodiments of this application; Figure 3 These are schematic diagrams and top views of the film layer structure of the display panel of the display device provided in the exemplary embodiments of this application; Figure 4 This is a schematic diagram of the film layer structure of the display panel of the display device provided in an exemplary embodiment of this application; Figures 5A-5D This is a schematic diagram of a method for driving ink on the display panel of a display device provided in an exemplary embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0019] This application provides a display device, with reference to... Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a timing controller (TMC), a gate driver (GDR), a gamma reference voltage generator (GAMMA), and a data driver (SDR).

[0020] The display panel 100 has a display area AA on which an image is displayed and a non-display area NA adjacent to the display area AA. The non-display area NA may surround the display area AA. The display panel 100 may be an OLED (Organic Light Emitting Diode) display panel.

[0021] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple sub-pixels SP electrically connected to the gate lines GL and data lines DL. The gate lines GL may extend in a first direction, and the data lines DL may extend in a second direction intersecting the first direction. For example, the first direction may be perpendicular to the second direction, but is not limited thereto. The sub-pixels SP may include pixel driving circuitry and light-emitting units (e.g., OLED light-emitting devices). The pixel driving circuitry drives the light-emitting units to emit light under the drive of the gate lines GL and data lines DL.

[0022] The timing controller (TMC) receives input image data (IMG) and input control signals (CONT) from an external device (e.g., a host or application processor). For example, the input image data (IMG) may include red, green, and blue image data. In addition to red, green, and blue image data, the input image data (IMG) may also include white image data. Instead of red, green, and blue image data, the input image data (IMG) may include magenta, cyan, and yellow image data. The input control signals (CONT) may include a master clock signal and a data enable signal. The master clock signal provides the display system with a master timing reference for setting the rate at which data is sent and processed. The data enable signal indicates when valid data is sent for display. The input control signals (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal. The vertical synchronization signal indicates the start of a new frame by synchronizing the start of each vertical scan. The horizontal synchronization signal marks the start of each new subpixel row or horizontal line.

[0023] The timing controller (TMC) generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0024] The timing controller (TMC) generates a first control signal (CONT1) based on the input control signal (CONT) to control the operation of the gate driver (GDR), and outputs the first control signal (CONT1) to the gate driver (GDR). The first control signal (CONT1) may include a vertical start signal and a gate clock signal. The vertical start signal indicates the start of each vertical scan, and the gate clock signal controls the timing of row activation to drive each row sequentially from top to bottom.

[0025] The timing controller (TMC) generates a second control signal (CONT2) based on the input control signal (CONT) to control the operation of the data driver (SDR), and outputs the second control signal (CONT2) to the data driver (SDR). The second control signal (CONT2) may include a horizontal start signal and a load signal. The horizontal start signal indicates the start of a new horizontal line for the sub-pixel SP. The load signal can be used to maintain synchronization between the image data being processed and the physical sub-pixel SP being driven.

[0026] The timing controller (TMC) generates a data signal (DATA) based on the input image data (IMG). The timing controller (TMC) then outputs the data signal (DATA) to the data driver (SDR).

[0027] The timing controller (TMC) generates a third control signal (CONT3) based on the input control signal (CONT) to control the operation of the gamma reference voltage generator (GAMMA), and outputs the third control signal (CONT3) to the GAMMA. The voltage generated by the GAMMA helps control the brightness and color accuracy of each sub-pixel (SP).

[0028] The gate driver GDR generates a gate signal to drive the gate line GL in response to a first control signal CONT1 received from the timing controller TMC. The gate driver GDR can output the gate signal to the gate line GL. In embodiments of the present invention, the gate driver GDR is integrated in the non-display area NA of the display panel 100 to form a gate driving circuit within the display panel 100.

[0029] The Gamma Reference Voltage Generator (GAMMA) generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the timing controller (TMC). The GAMMA provides the gamma reference voltage VGREF to the data driver (SDR). The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0030] In this embodiment, the Gamma reference voltage generator (GAMMA) can be located in the timing controller (TMC) or the data driver (SDR).

[0031] The data driver SDR receives a second control signal CONT2 and a data signal DATA from the timing controller TMC, and a gamma reference voltage VGREF from the gamma reference voltage generator GAMMA. The data driver SDR uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. For example, the data driver SDR can transform digital input image data IMG into precise analog voltages (i.e., data voltages) capable of driving each sub-pixel SP in the display panel 100, adjusted according to gamma correction provided by the gamma reference voltage VGREF. The data driver SDR outputs the data voltage to the data line DL.

[0032] In the embodiments conceived in this application, the data driver SDR is installed in the non-display area NA of the display panel 100.

[0033] Please see Figure 2 The display panel 100 includes a substrate, a transistor layer, a planarization layer PLN, a first electrode layer ANL, an electrode insulating layer EIN, a light-emitting layer EL, a barrier layer DAM, and a second electrode layer. The display panel 100 has an ink storage area ISA. The ink storage area ISA is located in the non-display area NA of the display panel 100 (see...). Figure 1 ).

[0034] The substrate can be made of inorganic materials. Specifically, the substrate can be formed of glass, metal, or ceramic. The substrate can also be made of organic materials, such as a single layer of polyimide or multiple layers of polyimide that can be formed by repeatedly stacking them through coating and curing.

[0035] The transistor layer includes an active layer, a first insulating layer, a first metal layer, an interlayer insulating layer, and a second metal layer. The transistor layer has multiple transistors. In one embodiment, the transistor layer may be omitted.

[0036] The active layer, located on the substrate, includes the active pattern of the transistor. The active layer can be formed of silicon semiconductor materials or metal oxide semiconductor materials, such as polycrystalline silicon, IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ITZO (Indium Tin Zinc Oxide), and IGZTO (Indium Gallium Zinc Tin Oxide).

[0037] The first insulating layer is located on the active layer. In this embodiment, the first insulating layer may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate (TEOS), silicon nitride, and silicon oxide.

[0038] A first metal layer, located on a first insulating layer, includes the gate of the transistor. The first metal layer may be formed as multiple layers or a single layer comprising low-resistance materials such as Al, Ti, Mo, Cu, Ni and their alloys, or materials with high corrosion resistance.

[0039] An interlayer insulating layer is located on the first metal layer. In this embodiment, the interlayer insulating layer may be formed as a plurality of layers or a single layer, for example, of tetraethyl orthosilicate (TEOS), silicon nitride, or silicon oxide.

[0040] The second metal layer, located on the interlayer insulating layer, includes the source and drain of the transistor. In this embodiment, the second metal layer can be formed as multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or their alloys, or a material with high corrosion resistance. For example, the second metal layer can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or others.

[0041] A planarization layer (PLN) is formed on the transistor layer. The planarization layer (PLN) includes vias. The planarization layer (PLN) can be formed as multiple layers or a single layer, for example, of tetraethyl orthosilicate (TEOS), silicon nitride, or silicon oxide, and can be formed of an organic material with a low dielectric constant (e.g., polyimide).

[0042] The first electrode layer ANL, formed on the planarization layer PLN, includes multiple microfluidic electrodes ANO, with at least one microfluidic electrode ANO located in the display area AA. Microfluidics is a technique that utilizes the principle of electrowetting. When a voltage is applied to the microfluidic electrode, the contact angle between the droplet and the high-potential microfluidic electrode decreases, thereby causing the droplet to move and separate under the influence of surface tension. The first electrode layer ANL can be formed of metals with high work functions, such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc., or can include mixtures thereof. In some embodiments, the first electrode layer ANL may be a metal monolayer, comprising, for example, metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc., or mixtures thereof; or, the first electrode layer ANL may have a multilayer structure comprising a metal layer (comprising, for example, metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc., or mixtures thereof) and a transparent conductive oxide layer (including a transparent conductive oxide). The transparent conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. In embodiments, the first electrode layer ANL may have a three-layer structure of ITO / Ag / ITO. However, the embodiments of this application are not limited thereto.

[0043] An electrode insulating layer EIN is formed on a planarization layer PLN and includes multiple electrode insulating portions EINP. The electrode insulating layer EIN can be formed as multiple layers or a single layer, for example, made of tetraethyl orthosilicate (TEOS), silicon nitride, or silicon oxide, and can be formed of an organic material with a low dielectric constant (e.g., polyimide).

[0044] A barrier layer DAM, located on a first electrode layer ANL, includes at least one ink storage cavity ISC located in at least one ink storage area ISA and a pixel cavity PXC located in the display area AA. The at least one ink storage cavity ISC is connected to the pixel cavity PXC, allowing ink to flow from the ink storage cavity ISC into the pixel cavity PXC. The barrier layer DAM can be made of a black material, such as a black organic material. The at least one ink storage cavity ISC includes at least one first ink storage cavity ISC1, at least one second ink storage cavity ISC2, and at least one third ink storage cavity ISC3. The first ink storage cavity ISC1, the second ink storage cavity ISC2, and the third ink storage cavity ISC3 are respectively used to store ink corresponding to light-emitting portions ELP with different luminous colors. At least one pixel cavity PXC includes at least one first pixel cavity PXC1, at least one second pixel cavity PXC2, and at least one third pixel cavity PXC3. The first pixel cavity PXC1 is connected to the corresponding first ink storage cavity ISC1, the second pixel cavity PXC2 is connected to the corresponding second ink storage cavity ISC2, and the third pixel cavity PXC3 is connected to the corresponding third ink storage cavity ISC3. In one embodiment, the barrier layer DAM can be omitted.

[0045] The light-emitting layer (EL), located in the first electrode layer (ANL), includes multiple light-emitting portions (ELPs), with at least one ELP located within the pixel cavity (PXC). The ink forming the EL is driven by multiple microfluidic electrodes (ANOs) to sequentially form multiple initial light-emitting portions within the pixel cavity (PXC). These initial light-emitting portions undergo drying and other processes to form multiple light-emitting portions (ELPs). These multiple ELPs can emit light of different colors, such as red, blue, and green.

[0046] A cathode layer may be disposed on the second electron transport layer and includes a cathode. The cathode layer may include lanthanide metals or compounds with low work functions, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, BaF, Ba, Ag, Yb, etc., or mixtures thereof. In embodiments, the cathode layer may be Ag / Mg or Ag / Yb, but the embodiments of this application are not limited thereto. The cathode layer may be formed thin enough to transmit light.

[0047] In this embodiment, the light-emitting layer (ELP) is electrically connected to the microfluidic electrode (ANO). The microfluidic electrode (ANO) can serve as a display driving electrode, such as an anode, and is electrically connected to the cathode via the corresponding light-emitting layer (ELP), thereby driving the light-emitting layer (ELP) to emit light. In this embodiment, multiple microfluidic electrodes (ANOs) separate and transport the ink from the ink storage chamber (ISC) to each pixel, achieving high-precision printing of the light-emitting layer (EL) of the printed OLED and improving the color mixing phenomenon of the printed OLED. Simultaneously, the microfluidic electrodes (ANOs) are reused as display driving electrodes, which simplifies the structure of the display panel 100.

[0048] The entire microfluidic electrode ANO is reused as a display driving electrode. The entire microfluidic electrode ANO simultaneously undertakes the functions of ink dispensing and light emission driving. The area where the ink spreads is the area where the light emission is driven, realizing the effect that the driving signal acts wherever the ink covers, increasing the area of ​​the display driving electrode and eliminating dead zones in control.

[0049] In some embodiments, please continue reading Figure 2 The light-emitting element (ELP) contacts the microfluidic electrode (ANO) and is positioned directly above it. This direct contact reduces current conduction losses, prevents abnormal light emission due to poor contact, and ensures stable pixel luminous efficiency. Positioning the ELP directly above the ANO allows the ink, controlled by electrowetting, to be precisely deposited on the electrode's coverage area, preventing pixel boundary blurring caused by ELP misalignment, further reducing the risk of color mixing, and improving display resolution.

[0050] In some embodiments, at least one transistor is electrically connected to the light-emitting portion (ELP) sequentially through a via of the planarization layer PLN and a corresponding microfluidic electrode ANO. Specifically, one of the source and drain electrodes of the transistor is electrically connected to the light-emitting portion (ELP) through a corresponding microfluidic electrode ANO. The linkage between the transistor and the microfluidic electrode ANO allows for precise adjustment of the voltage and duration of each microfluidic electrode ANO during ink driving, thereby accurately controlling the ink separation amount, movement speed, and spreading range, and also enables pixel-level display driving.

[0051] In some embodiments, the area of ​​the light-emitting portion (ELP) is smaller than the area of ​​the microfluidic electrode (ANO). With the ELP area smaller than the ANO area, the coverage of the ANO forms a constrained boundary, ensuring that the ink spreads only within the electrode area under electrowetting drive, preventing spillage into adjacent pixels and guaranteeing clear pixel boundaries, thus completely resolving color mixing issues. The larger area of ​​the ANO provides a more stable surface tension driving environment for the ink, allowing it to spread evenly within the electrode area. This results in a consistent ELP thickness, avoiding differences in brightness caused by uneven ink accumulation.

[0052] In some embodiments, multiple light-emitting portions (ELPs) within the same pixel cavity (PXC) are interconnected in a direction perpendicular to the thickness direction of the light-emitting layer (EL). This facilitates ink flow and eliminates the need for dams or pixel definition layers that separate the light-emitting portions (ELPs), thus simplifying the structure of the display panel 100.

[0053] In some embodiments, the microfluidic electrode ANO has two opposing sides disposed along a second direction perpendicular to the direction from the ink reservoir ISC to the pixel cavity PXC (i.e., the ink flow direction). At least one side of the microfluidic electrode ANO is provided with an auxiliary electrode. The auxiliary electrode is used to apply a voltage to prevent ink from overflowing from the edge of the microfluidic electrode ANO during flow. Specifically, the voltage applied to the auxiliary electrode is lower than the voltage applied to the microfluidic electrode ANO.

[0054] In some embodiments, please continue reading Figure 2 The electrode insulating portion (EINP) is located between two adjacent microfluidic electrodes (ANOs), and each adjacent microfluidic electrode (ANO) is electrically connected to an adjacent light-emitting portion (ELP) within the same pixel cavity (PXC). The electrode insulating portion (EINP) between adjacent microfluidic electrodes (ANOs) effectively isolates the voltage signals of different electrodes within the same pixel cavity (PXC), preventing electrowetting drive disturbances caused by short circuits between electrodes and ensuring the independent control reliability of each pixel. The electrode insulating portion (EINP) fills the electrode gaps, preventing ink from seeping into the electrode gaps and causing residual accumulation, reducing pixel crosstalk caused by residual ink, and improving the lifespan and image quality stability of the display panel 100.

[0055] The electrode insulating portion (EINP) possesses hydrophobic properties. Since the ink is hydrophilic, the hydrophobic nature of the EINP reduces the ink's adsorption force in the gap region between two adjacent microfluidic electrodes (ANOs), allowing the ink to move more smoothly under the surface tension of the ANOs, reducing voltage-driven power consumption, shortening ink filling time, and improving process efficiency. The hydrophobic EINP can also work in conjunction with the barrier layer (DAM) to confine the ink, reducing material costs and process complexity.

[0056] The electrode insulating portion EINP is made of the same material as the planarization layer PLN. Since the electrode insulating portion EINP is made of the same material as the planarization layer PLN, there is no need to introduce additional specialized insulating materials, reducing the types of materials and lowering production costs. The insulating portion made of the same material bonds more tightly with the planarization layer PLN, reducing the risk of cracking and peeling caused by interlayer stress. The electrode insulating layer EIN and the planarization layer PLN can be designed as an integral part or as separate parts. When the electrode insulating layer EIN and the planarization layer PLN are designed as an integral part as a planarization layer, the top surface of the planarization layer is patterned to form a groove, and then the microfluidic electrode ANO is fabricated within the groove. When the electrode insulating layer EIN and the planarization layer PLN are designed as separate parts, the planarization layer PLN is formed first, then the microfluidic electrode ANO is formed on the planarization layer PLN, and then the electrode insulating layer EIN is formed on the planarization layer PLN, and the electrode insulating layer EIN is patterned to form the electrode insulating portion EINP.

[0057] In some embodiments, please refer to Figure 3The barrier layer DAM has multiple ink storage cavities ISC, with each pair of ink storage cavities ISC located on opposite sides of the corresponding pixel cavity PXC. Specifically, the multiple ink storage cavities ISC include at least two first ink storage cavities ISC1, at least two second ink storage cavities ISC2, and at least two third ink storage cavities ISC3, wherein the two first ink storage cavities ISC1 are located on opposite sides of the first pixel cavity PXC1, the two second ink storage cavities ISC2 are located on opposite sides of the second pixel cavity PXC2, and the two third ink storage cavities ISC3 are located on opposite sides of the third pixel cavity PXC3.

[0058] The pixel cavity PXC has ink storage chambers (ISCs) on both opposite sides, allowing ink to be supplied to the pixel cavity PXC simultaneously from both ends. Compared to single-sided ink storage, this reduces the ink travel distance, shortens the filling time, and improves panel manufacturing efficiency. Dual-sided ink supply avoids the problem of insufficient ink at the far end caused by single-sided ink supply. The ink spreads from both sides towards the middle, ensuring uniform ink thickness within the pixel cavity PXC, reducing differences in luminous brightness, and improving the overall image quality consistency of the entire panel.

[0059] The two ink reservoirs (ISCs) can have the same or different volumes. Having the same volume ensures consistent ink supply on both sides in a dual-sided ink supply system. Having different volumes allows the larger ISC to be used as the primary ink supply chamber and the smaller one as the secondary. The primary chamber supplies ink first, and when its ink level is insufficient, the secondary chamber can continue supplying ink, thus ensuring sufficient utilization of the primary ink supply chamber's ink capacity.

[0060] In some embodiments, a virtual light-emitting element is provided within the ink storage chamber ISC, and the material of the virtual light-emitting element is the same as that of the light-emitting element ELP. Residual ink within the ink storage chamber ISC is processed simultaneously with the ink processing in the display area AA to form the virtual light-emitting element. This ensures sufficient ink is available in the display area AA, improving display defects, and simplifies the process by eliminating the need for residual ink removal.

[0061] In some embodiments, please refer to Figure 4 The barrier layer DAM has at least one opening OP, and at least one ink storage cavity ISC is connected to the pixel cavity PXC through at least one opening OP. Specifically, from a viewing angle along the thickness direction of the display panel 100, the width of each opening OP gradually decreases in the direction from the corresponding ink storage cavity ISC to the pixel cavity PXC. The opening OP is funnel-shaped, and its width gradually decreases along the direction from the ink storage cavity ISC to the pixel cavity PXC, forming a physical guiding structure. When ink flows out of the ink storage cavity ISC, it is constrained by the opening OP, preventing it from spreading to non-target areas and improving the accuracy of ink entering the pixel cavity PXC.

[0062] A microfluidic electrode ANO is located below the opening OP. From a viewing angle along the thickness direction of the display panel 100, the dimension of the opening OP in the direction corresponding to the ink reservoir ISC pointing to the pixel cavity PXC is larger than the dimension of the microfluidic electrode ANO below the opening OP in the same direction. The length of the opening OP is greater than the length of the microfluidic electrode ANO, ensuring that the microfluidic electrode ANO fully acts on the ink passing through the opening OP, improving the precision of ink control.

[0063] In some embodiments, Figure 5A , Figure 5B , Figure 5C , Figure 5D Together, they demonstrated the ink driving method, where "+" represents high voltage and "-" represents low voltage. Figure 5A In this process, a voltage is applied to the microfluidic electrode ANO below the opening OP and the microfluidic electrode ANO near the opening OP to cause ink to flow from the ink reservoir ISC to the microfluidic electrode ANO near the opening OP. Figure 5B and Figure 5C In the process, along the direction from the ink reservoir ISC to the pixel cavity PXC, voltage is sequentially applied to multiple sets of adjacent microfluidic electrodes ANO, causing ink to flow from the microfluidic electrode ANO closest to the opening OP to the microfluidic electrode ANO furthest from the opening OP and without ink. Repeat. Figure 5B and Figure 5C The steps involve configuring ink onto multiple microfluidic electrodes ANO, such as... Figure 5D As shown. This driving method ensures that the amount of ink driven each time is the same or similar, which reduces the complexity of the driving process.

[0064] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0065] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0066] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0067] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that... include: The first electrode layer includes multiple microfluidic electrodes; as well as A light-emitting layer, located on the first electrode layer, includes multiple light-emitting portions; The light-emitting part is electrically connected to the microfluidic electrode to emit light under the drive of the microfluidic electrode.

2. The display panel according to claim 1, characterized in that, The light-emitting part is in contact with the microfluidic electrode and is located directly above the microfluidic electrode.

3. The display panel according to claim 1, characterized in that, The area of ​​the light-emitting part is smaller than the area of ​​the microfluidic electrode.

4. The display panel according to any one of claims 1-3, characterized in that, It also includes an electrode insulating layer, which includes a plurality of electrode insulating portions; wherein the electrode insulating portions are disposed between two adjacent microfluidic electrodes.

5. The display panel according to claim 4, characterized in that, The electrode insulation portion has hydrophobic properties.

6. The display panel according to claim 4, characterized in that, It also includes a planarization layer, on which both the electrode insulating layer and the first electrode layer are located; wherein the electrode insulating portion is made of the same material as the planarization layer.

7. The display panel according to any one of claims 1-3, characterized in that, The display panel has a display area and at least one ink storage area, and further includes a baffle layer located on the first electrode layer. The baffle layer has at least one ink storage cavity located in the at least one ink storage area and at least one pixel cavity located in the display area. At least one light-emitting part is located in the pixel cavity. The at least one ink storage cavity is connected to the corresponding pixel cavity.

8. The display panel according to claim 7, characterized in that, The barrier layer is provided with a plurality of ink storage cavities, and each pair of ink storage cavities is located on opposite sides of the corresponding pixel cavity.

9. The display panel according to claim 7, characterized in that, The barrier layer is provided with at least one opening, and the at least one ink storage cavity is connected to the pixel cavity through the at least one opening; wherein, from the perspective of the thickness direction of the display panel, the width of each opening gradually decreases in the direction from the corresponding ink storage cavity to the pixel cavity.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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