Semiconductor test structure and manufacturing method thereof
By forming a low-resistance metal-semiconductor compound layer in the semiconductor test structure, the problem of high contact resistance noise interference in traditional test methods is solved, enabling rapid and accurate monitoring of the etching status of micro-vias in the COAG process, shortening the R&D cycle and improving the device yield.
Patent Information
- Application Number
- CN202511640188.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-03-03
AI Technical Summary
Existing technologies cannot quickly and accurately monitor and verify the etching status of micro-vias in active gate processes. Traditional test structures cannot realistically simulate critical interfaces and are susceptible to interference from high contact resistance noise.
A semiconductor test structure was designed, including a semiconductor substrate, a dielectric layer, a metal-semiconductor compound layer, and a conductive filling material. By forming a low-resistance metal-semiconductor compound layer at the bottom of the via, the contact interface between the gate via and the substrate is simulated, and the via opening state is detected by an electron beam.
It enables rapid, low-cost, and high-precision monitoring of the opening status of through holes, effectively shortening the process development cycle and improving the accuracy of testing and the yield of device products.
Smart Images
Figure CN121604786A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor testing structure and its manufacturing method. Background Technology
[0002] With the continuous development of semiconductor technology, the integration density of integrated circuits has been continuously increasing, and the critical dimensions of devices have entered 7 nanometers, 5 nanometers, and even more advanced technology nodes. At these advanced technology nodes, in order to further increase device density and reduce chip area, the industry has widely adopted new structures and processes such as Contact Over Active Gate (COAG). Figure 1 As shown in the schematic diagram of the semiconductor device layout, compared with the conventional layout in which the gate contact is placed outside the active region, COAG technology places the gate contact directly above the active region on the gate portion. This layout optimization can effectively reduce the device area by about 10% to 20%.
[0003] However, while COAG technology brings advantages in device area reduction, it also introduces new technical challenges. To achieve the aforementioned compact layout, the size of the gate vias must be designed to be extremely small. For example... Figure 2 As shown in the transmission electron microscope (TEM) cross-sectional image of the gate via, the critical size of the gate via is extremely small, especially at the interface where it contacts the underlying metal gate, where the size shrinks further, forming a process bottleneck (its critical size at the bottom may shrink to below 12 nanometers). This extremely small contact area directly leads to a significant increase in the contact resistance between the gate via and the underlying metal gate, making it highly susceptible to incomplete etching and resulting in via opening defects.
[0004] For this critical through-hole etching process, existing monitoring and verification methods have significant limitations. On the one hand, while using a full-flow test piece containing the complete device structure allows for accurate measurement, its production cycle is extremely long, failing to meet the needs of rapid verification and iteration of process solutions during the R&D phase, and significantly slowing down project development. On the other hand, there is short-loop testing, but its traditional test structure has inherent limitations. For example... Figure 3 As shown in the schematic diagram of a traditional short-process test structure, the vias (V0) used for testing are typically fabricated directly on the silicon substrate (Si-sub). This structure does not form the critical contact interface between the gate via and the metal gate; instead, it forms the contact interface between the via and the silicon substrate. Therefore, it cannot accurately simulate the electrical connection interface in the device and cannot effectively reflect the effects of process improvements.
[0005] Furthermore, another challenge arises when attempting to monitor via opening defects based on such traditional short-pass test structures using electron beam (E-beam) inspection techniques. Because the metal filling the via (such as titanium / titanium nitride) is in direct contact with the underlying silicon substrate, an interface with high contact resistance (e.g., values up to 10^4 Ω) is formed. This inherently high resistance generates a significant defect voltage contrast (DVC) signal during E-beam inspection, creating substantial "noise" that masks via opening defects truly caused by etching process issues. This makes E-beam inspection methods ineffective in distinguishing between high-resistance contacts and genuine opening defects, thus hindering their accurate monitoring of the etching process health.
[0006] Therefore, there is an urgent need for a new method and a matching test structure that can quickly and accurately verify the opening status of micro-vias in the COAG process, in order to shorten the process development cycle and accelerate the research and development of advanced technology nodes. Summary of the Invention
[0007] The technical problem to be solved by the present invention is to provide a semiconductor test structure and its manufacturing method that can quickly and accurately monitor and verify the etching state of micro-vias in the COAG process in a short process, so as to overcome the defects of the existing technology that the full process test cycle is too long and the traditional short process test cannot accurately simulate the key interface and is susceptible to high contact resistance noise interference.
[0008] To address the aforementioned technical problems, this invention provides a semiconductor testing structure, comprising:
[0009] Semiconductor substrate;
[0010] A dielectric layer disposed on a semiconductor substrate, wherein through-holes are formed in the dielectric layer to expose the semiconductor substrate;
[0011] A metal-semiconductor compound layer formed at the interface between the semiconductor substrate at the bottom of the via and the subsequent filler material; and
[0012] Conductive filler material that fills the through-hole.
[0013] Preferably, the semiconductor substrate is a silicon substrate, and the metal semiconductor compound layer is a metal silicide layer.
[0014] Preferably, a barrier layer is also formed between the semiconductor substrate and the dielectric layer.
[0015] Preferably, the metal silicide layer is titanium silicide.
[0016] Preferably, the conductive filler material includes tungsten.
[0017] Preferably, the via is a simulated gate via.
[0018] Preferably, the bottom critical dimension of the simulated gate via is 100 to 200 angstroms.
[0019] To address the aforementioned technical problems, the present invention also provides a method for manufacturing a semiconductor test structure, comprising the following steps:
[0020] Step 1: Provide a semiconductor substrate;
[0021] Step 2: Form a dielectric layer on the semiconductor substrate;
[0022] Step 3: Pattern the dielectric layer to form vias that expose the semiconductor substrate.
[0023] Step 4: Perform pre-amorphization implantation on the semiconductor substrate at the bottom of the via, then deposit a metal material layer that can react with the semiconductor substrate to form a metal-semiconductor compound in the via, and then anneal the semiconductor substrate to allow the metal material layer to react with the semiconductor substrate, thereby forming a metal-semiconductor compound layer at the interface between the two.
[0024] Step 5: Fill the through-hole with conductive filler material;
[0025] Step 6: Use an electron beam to detect the opening status of the through hole.
[0026] Preferably, in step one, the semiconductor substrate is a silicon substrate.
[0027] Preferably, step two is modified to: sequentially forming a barrier layer and a dielectric layer on the semiconductor substrate; and step three is modified to: patterning the dielectric layer and the barrier layer to form the via.
[0028] Preferably, in step three, the via is formed as a gate via for simulating contact with an active gate process.
[0029] Preferably, the bottom critical dimension of the gate via is 100 to 200 angstroms.
[0030] Preferably, in step four, the metal material layer includes a titanium layer, and the metal semiconductor compound layer is a titanium silicide layer.
[0031] Preferably, in step four, the deposited metal material layer further includes a titanium nitride layer disposed on the titanium layer.
[0032] Preferably, in step five, the conductive filler material includes tungsten.
[0033] Preferably, in step five, tungsten is filled using a chemical vapor deposition process.
[0034] Preferably, in step six, detecting the opening state of the via using an electron beam includes: determining whether the via has an opening defect based on the defect voltage contrast (DVC) signal.
[0035] Preferably, by forming a metal-semiconductor compound layer in step four, the contact resistance between the via and the semiconductor substrate is reduced to below the noise threshold for electron beam detection.
[0036] As described above, the semiconductor test structure and its manufacturing method of the present invention have the following beneficial effects:
[0037] This invention constructs a special test structure in a short-process test that can realistically simulate the contact interface between the gate via and the substrate in the COAG process. By forming a low-resistance metal-semiconductor compound layer, it solves the noise interference problem caused by high contact resistance in traditional electron beam detection methods. This not only enables rapid, low-cost, and high-precision monitoring of the via opening state but also effectively shortens the development cycle of advanced process nodes. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the layout of semiconductor devices in the prior art.
[0039] Figure 2 The diagram shows a transmission electron microscope cross-section of a gate via in the prior art.
[0040] Figure 3 The diagram shows a cross-sectional view of a short-process test structure in the prior art.
[0041] Figure 4 The diagram shows a flowchart illustrating a semiconductor test structure manufacturing method according to some embodiments of the present invention.
[0042] Figure 5 The diagram shows a cross-sectional schematic of a semiconductor test structure according to some embodiments of the present invention. Detailed Implementation
[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0044] Reference Figure 5 , Figure 5This is a cross-sectional schematic diagram of a semiconductor test structure according to some embodiments of the present invention. The present invention provides a semiconductor test structure, comprising: a semiconductor substrate 101 having a pre-amorphous implantation region 104 on the surface layer of the semiconductor substrate 101; a dielectric layer 103 disposed on the semiconductor substrate 101, wherein a via is formed in the dielectric layer 103 exposing the pre-amorphous implantation region 104; a metal semiconductor compound layer 106 formed on the pre-amorphous implantation region 104; and a conductive filler material 107 filling the via.
[0045] In some embodiments, the semiconductor substrate 101 is a silicon substrate, and the metal semiconductor compound layer 106 is a metal silicide layer. For example, the semiconductor substrate 101 may be a substrate that provides mechanical support for semiconductor manufacturing, such as, but not limited to, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium substrate, or a III-V compound semiconductor substrate (such as gallium arsenide GaAs). The present invention is not limited to a specific substrate material.
[0046] In some embodiments, such as Figure 5 As shown, a barrier layer 102 is also formed between the semiconductor substrate 101 and the dielectric layer 103. This barrier layer 102 effectively prevents interdiffusion between the dielectric layer 103 material and the substrate 101 material, and can serve as an etching stop layer for subsequent etching processes, thereby improving the precision of process control. For example, the barrier layer 102 material may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), tantalum nitride (TaN), or titanium nitride (TiN), the choice of which depends on its etching selectivity relative to the overlying dielectric layer 103. The dielectric layer 103 is used to provide electrical insulation between conductive features and can be formed using interlayer dielectric materials commonly used in the art, such as silicon oxide-based materials (e.g., silicon dioxide, fluorinated silicate glass FSG), silicon oxynitride, or low-k or ultra-low-k materials used to reduce resistive-capacitive (RC) delay, such as carbon-doped silicon oxide (SiOC), organosilicon glass (OSG), or porous dielectric materials.
[0047] In some embodiments, when the semiconductor substrate 101 is a silicon substrate, the metal silicide layer 106 is a titanium silicide. Titanium (Ti) is chosen because it can form a low-resistivity titanium silicide with silicon, effectively reducing contact resistance. Besides titanium, metals capable of forming low-resistivity silicides include cobalt (Co), nickel (Ni), tungsten (W), and their alloys; the invention is not limited to any particular one. Forming this titanium silicide layer is crucial for achieving accurate electron beam detection, as it eliminates signal noise caused by high contact resistance, allowing true process defects to be revealed.
[0048] In some embodiments, the conductive filler 107 comprises tungsten. Tungsten has excellent filling capacity and conductivity, making it suitable for filling vias with high aspect ratios. This conductive filler 107 serves as the core component of the analog gate structure. In other alternative embodiments, the conductive filler can also be cobalt (Co), ruthenium (Ru), copper (Cu), or other suitable conductive metals, depending on the specific process node and integration requirements.
[0049] In some embodiments, the via is a simulated gate via. For example... Figure 5 As shown, a metal material layer 105 is also provided on the sidewall of the through hole. The metal material layer 105 serves as an isolation layer between the conductive filler material 107 and the dielectric layer 103.
[0050] In some embodiments, the bottom critical dimension of the simulated gate via is 100 to 200 angstroms. This size range matches the size of gate vias that have actually been exposed to active gate (COAG) processes in advanced technology nodes, ensuring that the test structure can accurately and effectively reflect the health and process window of the actual etching process.
[0051] Reference Figure 4 , Figure 4 This is a schematic flowchart of a semiconductor test structure manufacturing method according to some embodiments of the present invention, including the following steps:
[0052] Step 1: Provide a semiconductor substrate 101.
[0053] In some embodiments, in step one, the semiconductor substrate 101 is a silicon substrate. For example, the provided semiconductor substrate 101 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium substrate, or a III-V compound semiconductor substrate (such as gallium arsenide GaAs).
[0054] Step 2: Form a dielectric layer 103 on the semiconductor substrate 101.
[0055] Step 3: Pattern the dielectric layer 103 to form vias that expose the semiconductor substrate 101 in the dielectric layer 103.
[0056] In some embodiments, the process sequence of steps two and three can be further specified. Specifically, prior to step two, the method further includes forming a barrier layer 102 on the semiconductor substrate 101; wherein step two includes forming a dielectric layer 103 on the barrier layer 102; and step three includes patterning the dielectric layer 103 and the barrier layer 102 to form vias. This structural design makes the test structure closer to the thin film stack of a real device, improving the fidelity of the simulation and making the test results more valuable. The dielectric layer and barrier layer can be formed using methods such as plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), or spin-on coating. The materials used to form the barrier layer 102 may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), tantalum nitride (TaN), or titanium nitride (TiN), etc.; the materials used to form the dielectric layer 103 may include silicon oxide-based materials (such as silicon dioxide), low-k materials, or ultra-low-k materials (such as carbon-doped silicon oxide SiOC or porous dielectric materials).
[0057] In some embodiments, in step three, the via is formed to simulate a gate via in an active gate process. This simulated via formation method can employ advanced photolithography techniques, such as deep ultraviolet (DUV) lithography, immersion lithography, or extreme ultraviolet (EUV) lithography, combined with dry etching processes, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching, to precisely control the via's profile and size.
[0058] In some embodiments, in step three, the bottom critical dimension of the formed gate via is 100 to 200 angstroms.
[0059] Step 4: Perform pre-amorphization implantation in the semiconductor substrate 101 at the bottom of the via, then deposit a metal material layer 105 that can react with the semiconductor substrate 101 to form a metal semiconductor compound in the via, and then anneal the semiconductor substrate 101 to allow the metal material layer 105 to react with the semiconductor substrate 101, thereby forming a metal semiconductor compound layer 106 at the interface between the two.
[0060] In some embodiments, when the semiconductor substrate 101 is a silicon substrate, in step four, the metal material layer 105 includes a titanium layer, and the metal semiconductor compound layer 106 is a titanium silicide layer. Besides titanium, metals capable of forming low-resistivity silicides include cobalt (Co), nickel (Ni), tungsten (W), and their alloys. Specifically, the pre-amorphization implantation step forms a pre-amorphization implantation region (corresponding to...) on the surface of the semiconductor substrate 101. Figure 5Region 104 in the middle). Subsequently, a metal material layer (corresponding to Figure 5 Layer 105 is conformally deposited on the bottom and sidewalls of the via. This pre-amorphization implantation (PAI) step disrupts the lattice structure of the silicon substrate by introducing ions (such as germanium or silicon ions) into the surface layer, which helps to make the subsequent metal-silicon reaction more uniform, forming a silicide layer with a flat interface and lower resistance. The method of depositing the metal material layer 105 can include physical vapor deposition (PVD) (such as sputtering) or atomic layer deposition (ALD). Before filling the conductive material, a pre-cleaning step is usually performed, such as in-situ argon (Ar) sputtering cleaning, to remove oxides or residues at the bottom of the opening to ensure good electrical contact. Annealing can be performed by rapid thermal annealing (RTA) or furnace tube annealing under controlled temperature and atmosphere. During annealing, only the metal material layer deposited at the bottom of the via reacts with the pre-amorphization implantation region 104 to form a metal-semiconductor compound layer (corresponding to Figure 5 In the middle layer 106), the metal material layer 105 deposited on the sidewall of the via remains unchanged because it does not contact the semiconductor substrate, thus naturally forming an isolation layer for subsequent conductive filling material.
[0061] In some embodiments, in step four, the deposited metal material layer 105 further includes a titanium nitride layer disposed on the titanium layer. This titanium nitride layer can serve as an adhesion and barrier layer for subsequent filler materials (such as tungsten), preventing undesirable reactions between tungsten and silicides, thereby improving device reliability.
[0062] Step 5: Fill the through hole with conductive filler material 107.
[0063] In some embodiments, in step five, the conductive filler material 107 comprises tungsten. In other alternative embodiments, cobalt (Co), ruthenium (Ru), copper (Cu), or other suitable conductive metals may also be used.
[0064] In some embodiments, in step five, tungsten is filled using a chemical vapor deposition (CVD) process. The filling process typically employs CVD to ensure a void-free, dense filling in the vias with high aspect ratios. Alternatively, the filling method can also be electrochemical deposition (ECD) or physical vapor deposition (PVD). After filling, a chemical mechanical polishing (CMP) process is typically performed to remove excess conductive material outside the vias, achieving a planarized surface.
[0065] Step 6: Use an electron beam to detect the opening status of the through hole.
[0066] In some embodiments, step six, detecting the opening state of the via using an electron beam, includes determining whether the via has an opening defect based on a defect voltage contrast (DVC) signal. In some embodiments, the method may further include forming a subsequent metal interconnect structure on the via to perform electrical testing on the contact resistance between the via and the semiconductor substrate 101 through the metal interconnect structure. This metal interconnect structure can be formed using a single damascene or double damascene process and may include one or more metal wiring layers and interlayer vias connecting them. To improve design flexibility, a skip-layer connection method can be used to form the metal interconnect structure, so that the test signal does not need to be led out at the layer immediately adjacent to the via, but instead is led out to a higher-level metal interconnect (e.g., a first metal interconnect layer M1 or a second metal interconnect layer M2) and then connected to the test pad.
[0067] The method provided by this invention reduces the contact resistance between the via and the semiconductor substrate 101 from the high resistance value (e.g., on the order of 10^4 Ω) of the original process to below the noise threshold of electron beam detection by forming a metal-semiconductor compound layer 106 in step four. As a result, in the electron beam detection in step six, the spurious defect signal (i.e., DVC noise) caused by the high contact resistance is effectively eliminated, enabling the detection system to accurately identify via opening defects truly caused by improper etching processes (e.g., insufficient etching). This method is based on a short-cycle process flow, eliminating the need to wait for a long full-process chip manufacturing cycle and avoiding the drawbacks of traditional short-cycle testing's inability to effectively monitor opening defects. It provides rapid and accurate feedback for the development of COAG etching processes, thereby significantly shortening the process learning cycle, accelerating the development of advanced technology nodes, and improving the yield and reliability of the final product.
[0068] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A semiconductor testing structure, characterized in that, include: Semiconductor substrate; A dielectric layer disposed on the semiconductor substrate, wherein through-holes are formed in the dielectric layer to expose the semiconductor substrate; A metal-semiconductor compound layer is formed at the interface between the semiconductor substrate and the subsequent filling material at the bottom of the via; as well as Conductive filler material is used to fill the through-hole.
2. The semiconductor test structure according to claim 1, characterized in that: The semiconductor substrate is a silicon substrate, and the metal semiconductor compound layer is a metal silicide layer.
3. The semiconductor test structure according to claim 1, characterized in that: A barrier layer is also formed between the semiconductor substrate and the dielectric layer.
4. The semiconductor test structure according to claim 2, characterized in that: The metal silicide layer is titanium silicide.
5. The semiconductor test structure according to claim 1, characterized in that: The conductive filler material includes tungsten.
6. The semiconductor test structure according to claim 1, characterized in that: The via is a simulated gate via.
7. The semiconductor test structure according to claim 6, characterized in that: The bottom critical dimension of the simulated gate via is 100 to 200 angstroms.
8. A method for manufacturing a semiconductor test structure, characterized in that, include: Step 1: Provide a semiconductor substrate; Step 2: Form a dielectric layer on the semiconductor substrate; Step 3: Pattern the dielectric layer to form vias that expose the semiconductor substrate. Step 4: Perform pre-amorphization implantation on the semiconductor substrate at the bottom of the via, then deposit a metal material layer that can react with the semiconductor substrate to form a metal-semiconductor compound in the via, and then anneal the semiconductor substrate to allow the metal material layer to react with the semiconductor substrate, thereby forming a metal-semiconductor compound layer at the interface between the two. Step 5: Fill the through hole with conductive filler material; Step 6: Use an electron beam to detect the opening status of the through hole.
9. The method for manufacturing a semiconductor test structure according to claim 8, characterized in that: In step one, the semiconductor substrate is a silicon substrate.
10. The method for manufacturing a semiconductor test structure according to claim 8, characterized in that: Prior to step two, the method further includes forming a barrier layer on the semiconductor substrate; wherein step two includes forming the dielectric layer on the barrier layer; and step three includes patterning the dielectric layer and the barrier layer to form the via.
11. The method for manufacturing a semiconductor test structure according to claim 8, characterized in that: In step three, the via is formed to simulate a gate via in an active gate process.
12. The method for manufacturing a semiconductor test structure according to claim 11, characterized in that: The bottom critical dimension of the gate via is 100 to 200 angstroms.
13. The method for manufacturing a semiconductor test structure according to claim 9, characterized in that: In step four, the metal material layer includes a titanium layer, and the metal semiconductor compound layer is a titanium silicide layer.
14. The method for manufacturing a semiconductor test structure according to claim 13, characterized in that: In step four, the metal material layer further includes a titanium nitride layer disposed on the titanium layer.
15. The method for manufacturing a semiconductor test structure according to claim 8, characterized in that: In step five, the conductive filler material includes tungsten.
16. The method for manufacturing a semiconductor test structure according to claim 15, characterized in that: In step five, the tungsten is filled using a chemical vapor deposition process.
17. The method for manufacturing a semiconductor test structure according to claim 8, characterized in that: In step six, the use of an electron beam to detect the opening state of the via includes: determining whether the via has an opening defect based on a defect voltage contrast signal.
18. The method for manufacturing a semiconductor test structure according to claim 8, characterized in that: By forming the metal-semiconductor compound layer in step four, the contact resistance between the via and the semiconductor substrate is reduced to below the noise threshold for electron beam detection.