Monitoring method of semiconductor epitaxial process

Abstract

The invention provides a method for monitoring a semiconductor epitaxial process. The method comprises the following steps: sequentially epitaxially growing a multi-layer structure comprising a plurality of epitaxial layers and mark layers arranged between the adjacent epitaxial layers on a substrate; the multi-layer structure is then analyzed to simultaneously obtain the thickness and component concentration information of at least one of the plurality of epitaxial layers. According to the invention, the integrated multi-layer epitaxial structure is constructed on the single test wafer, and the marking layer is used for distinguishing, so that one-time comprehensive analysis of the multi-layer epitaxial process is realized. Compared with the prior art, the method has the advantages that the consumption of the test wafer and the equipment machine hour are remarkably reduced, the process monitoring period is shortened, the production cost is reduced, and the overall efficiency of semiconductor manufacturing is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for monitoring semiconductor epitaxial processes. Background Technology

[0002] In advanced semiconductor processes, strained silicon technology is commonly used to improve transistor performance. For example, in the source and drain regions of a P-type metal-oxide-semiconductor (PMOS) transistor, compressive stress is introduced by embedding epitaxial growth of doped silicon germanium, thereby improving device performance.

[0003] like Figure 1 As shown, a typical embedded silicon-germanium-boron (SiGeB EPI) structure typically employs a multilayer stacked design, for example, sequentially epitaxially growing a first epitaxial layer (L1), a second epitaxial layer (L2), and a third epitaxial layer (L3) in a recess in the substrate. These epitaxial layers typically have different germanium (Ge) or boron (B) concentrations to precisely control stress and electrical properties.

[0004] To ensure the stability of the mass production process, it is necessary to periodically monitor the growth of each epitaxial layer. The existing monitoring method involves growing the three layers L1, L2, and L3 on three separate test wafers, and then measuring the physical parameters of each wafer individually.

[0005] However, this traditional method has significant drawbacks: each monitoring session requires multiple test wafers, resulting in high costs; simultaneously, multiple independent epitaxial growth and measurement processes consume substantial equipment time, leading to a long and inefficient monitoring cycle that fails to meet the demands of modern semiconductor manufacturing for rapid process control. Therefore, the industry needs a faster, more efficient, and lower-cost monitoring solution. Summary of the Invention

[0006] This invention aims to address the problems existing in the prior art for monitoring multilayer epitaxial processes. Specifically, existing methods require significant time for testing wafers and equipment, resulting in high monitoring costs, long cycles, and low efficiency, failing to meet the demands of modern semiconductor manufacturing for rapid and efficient process control.

[0007] To address the aforementioned technical problems, this invention provides a method for monitoring semiconductor epitaxial processes, the method comprising:

[0008] Step 1: Provide a substrate;

[0009] Step 2: Epitaxially grow a multilayer structure on the substrate in sequence. The multilayer structure includes: multiple epitaxial layers and a marking layer disposed between adjacent epitaxial layers.

[0010] Step 3: Analyze the multilayer structure to obtain the thickness and component concentration information of at least one of the multiple epitaxial layers simultaneously.

[0011] Preferably, in step one, the substrate is an unpatterned silicon wafer.

[0012] Preferably, in step two, the plurality of epitaxial layers include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer; and the marking layer includes a first marking layer disposed between the first epitaxial layer and the second epitaxial layer, and a second marking layer disposed between the second epitaxial layer and the third epitaxial layer.

[0013] Preferably, in step two, the multiple epitaxial layers are doped silicon-germanium epitaxial layers.

[0014] Preferably, in step two, at least one of the doped silicon-germanium epitaxial layers is a silicon-germanium-boron epitaxial layer.

[0015] Preferably, in step two, the marking layer is an intrinsic silicon layer.

[0016] Preferably, in step two, the thickness of the intrinsic silicon layer is 40 to 60 angstroms.

[0017] Preferably, in step three, when the epitaxial layer is a doped silicon-germanium epitaxial layer, the component concentration information includes germanium concentration and dopant atom concentration information.

[0018] Preferably, in step three, the analysis is performed using a secondary ion mass spectrometry method.

[0019] Preferably, this method is used for monitoring embedded silicon-germanium processes.

[0020] As described above, the semiconductor epitaxial process monitoring method of the present invention has the following beneficial effects:

[0021] This invention significantly reduces the consumption of test wafers by integrating the monitoring of multilayer epitaxial structures onto a single test wafer, thereby directly lowering material costs. Simultaneously, it replaces multiple independent processes and measurements with a single continuous epitaxial growth and integrated analysis and measurement, greatly shortening equipment downtime (machine time) and thus improving the utilization rate of production equipment and overall monitoring efficiency. Because the entire monitoring process is significantly shortened, process engineers can obtain feedback data on epitaxial equipment and process stability more quickly, helping to identify and resolve problems promptly and providing support for ensuring the stability and yield of large-scale production. Attached Figure Description

[0022] Figure 1 This is a schematic cross-sectional view of an embedded silicon-germanium-boron epitaxial structure in the prior art;

[0023] Figure 2This is a flowchart illustrating a semiconductor epitaxial process monitoring method according to an embodiment of the present invention;

[0024] Figure 3 This is a cross-sectional schematic diagram of a multi-layer structure in an embodiment of the present invention;

[0025] Figure 4 This is a comparative table showing the resource consumption of the present invention and the original solution. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] This invention provides a method for monitoring semiconductor epitaxial processes. This method achieves rapid and efficient monitoring of multilayer epitaxial processes by constructing a multilayer epitaxial structure containing a marker layer on a single test wafer and performing a one-time in-depth analysis.

[0028] Please see Figure 2 This illustration shows a schematic diagram of the process flow for a semiconductor epitaxial process monitoring method according to an embodiment of the present invention. The method includes the following steps:

[0029] Step 1: Provide a substrate.

[0030] The substrate serves as the basis for epitaxial growth, and its surface quality and flatness directly affect the crystal quality of the subsequent thin film.

[0031] In some embodiments, in step one, the substrate is an unpatterned silicon wafer (NPW). Using an unpatterned silicon wafer as a test carrier can eliminate the interference of patterned structures on the measurement results, thereby more purely reflecting the stability and uniformity of the epitaxial growth process itself. In other embodiments, the substrate can also be a silicon-on-insulator (SOI) wafer, or, depending on different application requirements, a wafer made of other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), or gallium nitride (GaN).

[0032] Step 2: A multilayer structure is sequentially epitaxially grown on the substrate. The multilayer structure includes multiple epitaxial layers and marker layers positioned between adjacent epitaxial layers. Epitaxial growth can be achieved using various chemical vapor deposition (CVD) techniques, such as ambient pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), or molecular beam epitaxy (MBE). The marker layers provide clear interface signals for subsequent analysis, enabling accurate differentiation and measurement of each individual epitaxial layer.

[0033] Please see Figure 3 The diagram shows a cross-sectional schematic of a multilayer structure formed according to an embodiment of the present invention.

[0034] In some embodiments, in step two, the plurality of epitaxial layers include a first epitaxial layer 102, a second epitaxial layer 104, and a third epitaxial layer 106; and the marking layer includes a first marking layer 103 disposed between the first epitaxial layer 102 and the second epitaxial layer 104, and a second marking layer 105 disposed between the second epitaxial layer 104 and the third epitaxial layer 106. These layers are all sequentially formed on the substrate 101. This three-layer structure is a typical configuration of embedded silicon-germanium process in PMOS, but the method of the present invention is not limited to three layers and is also applicable to monitoring epitaxial structures with two, four, or more layers.

[0035] In some embodiments, in step two, the plurality of epitaxial layers (e.g., 102, 104, 106) are silicon-germanium doped epitaxial layers.

[0036] In some embodiments, in step two, at least one of the doped silicon-germanium epitaxial layers is a silicon-germanium-boron (SiGeB) epitaxial layer. For example, in PMOS applications, P-type impurity boron (B) is typically doped to reduce contact resistance and modulate electrical characteristics. In other embodiments, it can also be an N-type doped silicon-germanium layer used for NMOS strain engineering, such as a phosphorus (P) or arsenic (As) doped silicon-germanium layer, or a carbon-doped silicon layer (Si:C) used to introduce tensile strain; the method of the present invention is equally applicable.

[0037] In some embodiments, in step two, the marker layer (e.g., 103, 105) is an intrinsic silicon layer. Choosing intrinsic silicon as the marker layer has several advantages. First, its material is fully compatible with mainstream silicon-based processes, preventing the introduction of foreign element contamination. Second, the intrinsic silicon and the doped silicon-germanium layer have a clear interface of composition and doping concentration in subsequent analysis, making them easy to identify and distinguish, thereby enabling accurate measurement of parameters for each layer. In other embodiments, the marker layer can also be other materials that can be clearly distinguished in the analysis, such as an extremely thin silicon nitride (SiN) layer, a silicon carbide (SiC) layer, or a silicon layer doped with specific elements, as long as it can provide a clear interface signal in subsequent analysis without significantly affecting the crystal quality of the upper and lower epitaxial layers.

[0038] In some embodiments, the thickness of the intrinsic silicon layer in step two is 40 to 60 angstroms. Keeping the thickness of the marker layer within a relatively thin range ensures that a sufficiently clear interface signal is formed in subsequent analysis, while avoiding the introduction of additional stress or impact on the crystal quality of the overall epitaxial structure due to an excessively thick marker layer. It also effectively reduces the time required for epitaxial growth.

[0039] Step 3: Analyze the multilayer structure to simultaneously obtain the thickness and component concentration information of at least one of the multiple epitaxial layers. The ability to acquire key parameters of all target epitaxial layers through a single measurement is the core of this invention's efficient monitoring capabilities.

[0040] In some embodiments, when the epitaxial layer is a doped silicon-germanium epitaxial layer, in step three, the component concentration information includes germanium concentration and dopant atom concentration information.

[0041] In some embodiments, step three employs secondary ion mass spectrometry (SIMS). SIMS possesses extremely high depth resolution and elemental detection sensitivity, enabling precise measurement of the concentration distribution of various elements at different depth locations in one-dimensional depth profiling. A single SIMS test can obtain a depth profile containing all epitaxial layers and labeled layers, from which the thickness of each epitaxial layer, germanium atom concentration, and boron (or other doped) atom concentration information can be directly read, thus efficiently characterizing process stability. In other embodiments, other analytical techniques with depth resolution capabilities can also be used, such as Auger electron spectroscopy (AES) depth profiling or transmission electron microscopy (TEM) combined with energy-dispersive X-ray spectroscopy (EDX) line scanning, to obtain similar information.

[0042] In some embodiments, the method of the present invention is used for monitoring embedded silicon-germanium (e-SiGe) processes. By stably monitoring the thickness, Ge concentration, and B concentration of each SiGeB layer in the e-SiGe process, the stability of the channel stress and the contact characteristics of the source and drain electrodes in the PMOS device can be effectively guaranteed, thereby ensuring the high performance and high yield of the final chip product.

[0043] To more intuitively illustrate the beneficial effects of this invention, please refer to [link / reference needed]. Figure 4 This table illustrates the comparison between the resource consumption of the present invention and the original solution. Taking a monitoring task involving three epitaxial layers as an example: the original solution requires three test wafers, three independent epitaxial growth processes, and multiple measurements such as thickness, XRD, and Rs on each wafer, totaling nine measurements. However, using the present invention, only one test wafer is needed, one continuous epitaxial growth process is performed, and subsequent measurements only require, for example, one THK measurement and one SIMS measurement, significantly reducing the total number of measurements to two.

[0044] In summary, the method of the present invention significantly reduces the consumption of test wafers and equipment time, shortens the feedback cycle of process monitoring, reduces production costs, and improves the overall efficiency of semiconductor manufacturing.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for monitoring semiconductor epitaxial processes, characterized in that, At least including: Step 1: Provide a substrate; Step 2: Epitaxially grow a multilayer structure sequentially on the substrate. The multilayer structure includes: multiple epitaxial layers and a marking layer disposed between adjacent epitaxial layers. Step 3: Analyze the multilayer structure to simultaneously obtain the thickness and component concentration information of at least one of the multiple epitaxial layers.

2. The monitoring method for semiconductor epitaxial processes according to claim 1, characterized in that: In step one, the substrate is an unpatterned silicon wafer.

3. The monitoring method for semiconductor epitaxial processes according to claim 1, characterized in that: In step two, the plurality of epitaxial layers include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer; and the marking layer includes a first marking layer disposed between the first epitaxial layer and the second epitaxial layer, and a second marking layer disposed between the second epitaxial layer and the third epitaxial layer.

4. The monitoring method for semiconductor epitaxial processes according to claim 1, characterized in that: In step two, the plurality of epitaxial layers are doped silicon-germanium epitaxial layers.

5. The monitoring method for semiconductor epitaxial processes according to claim 1, characterized in that: In step two, at least one of the doped silicon-germanium epitaxial layers is a silicon-germanium-boron epitaxial layer.

6. The monitoring method for semiconductor epitaxial processes according to claim 1, characterized in that: In step two, the marking layer is an intrinsic silicon layer.

7. The monitoring method for semiconductor epitaxial processes according to claim 6, characterized in that: In step two, the thickness of the intrinsic silicon layer is 40 to 60 angstroms.

8. The monitoring method for semiconductor epitaxial processes according to claim 4, characterized in that: In step three, the component concentration information includes germanium concentration and dopant atom concentration information.

9. The monitoring method for semiconductor epitaxial processes according to claim 1, characterized in that: In step three, the analysis is performed using a secondary ion mass spectrometry method.

10. The monitoring method for semiconductor epitaxial processes according to claim 1, characterized in that: The method is used for monitoring embedded silicon-germanium processes.

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