Packaging structure and corresponding preparation method

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a packaging structure and a corresponding preparation method, and the packaging structure comprises a substrate; the chip is positioned above the substrate; an interposer over the chip; wherein the chip is internally provided with a conductive through hole, the conductive through hole is connected with the front surface of the chip and is exposed out of the back surface of the chip, the back surface of the chip is provided with a first conductive bump connected with the conductive through hole, and the substrate is connected with the front surface of the chip through the first conductive bump and the conductive through hole in sequence; the front surface of the chip is provided with a second conductive bump, and the front surface of the chip is connected with the interposer through the second conductive bump. The chip is directly connected with the substrate, so that the power supply distance and the signal transmission distance are shortened, and the signal integrity and the power supply integrity of the system are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and discloses a packaging structure and a corresponding preparation method. Background Technology

[0002] With the development of artificial intelligence and high-performance computing, the demands on chip performance are increasing. However, transistor size is currently approaching its physical limits, making transistor miniaturization increasingly difficult. As a result, more and more attention is being turned to advanced packaging technologies. For example, in the 2.5D packaging field, the mainstream CoWoS structure is currently [see...]. Figure 1 The chip 130 is located above the interposer 120, and the substrate 110 is located below the interposer 120, forming a three-layer structure. However, the power supply path from the substrate 110 to the chip 130 needs to pass through the interposer 120, resulting in a long power supply path and significant energy loss. The high-speed I / O signals connecting the chip 130 to the outside world also need to pass through the interposer 120, resulting in a long signal path and reduced signal quality. The signals transmitted between the chips 130 and the power signals provided by the substrate 110 are all mixed and distributed within the interposer 120, leading to reduced signal quality and signal density. Summary of the Invention

[0003] The purpose of this invention is to solve the problems of high energy loss, reduced signal quality, and reduced signal density caused by the existing advanced packaging technology that forms a three-layer structure with the chip above the interposer and the interposer above the substrate. This invention provides a packaging structure and a corresponding fabrication method. To achieve the above objectives, the present invention provides a packaging structure, comprising: substrate; The chip located above the substrate; An intermediary layer located above the chip; The chip has a conductive via inside, which connects to the front side of the chip and exposes the back side of the chip. The back side of the chip has a first conductive bump connected to the conductive via. The substrate is connected to the front side of the chip in sequence through the first conductive bump, the conductive via, and the front side of the chip. The front side of the chip has a second conductive bump, which connects to the interposer layer.

[0004] In one possible implementation, the second conductive bump does not directly contact the conductive via.

[0005] In one possible implementation, the projections of the second conductive bump and the conductive via on the upper surface of the substrate do not overlap.

[0006] As one possible implementation, it also includes: Solder balls located on the side of the substrate away from the chip.

[0007] As one possible implementation, the substrate is one of a ceramic substrate, a metal substrate, an organic substrate, and a glass substrate.

[0008] As one possible implementation, the interposer is one of a silicon interposer, a glass interposer, or an organic interposer.

[0009] As one possible implementation, the chip is at least one.

[0010] As one possible implementation, it also includes: A molding compound located on the surface of the substrate, and the molding compound covering the chip and the interposer layer.

[0011] In one possible implementation, the back side of the chip has a first under-bump metallization layer corresponding to the first conductive bump, and the back side of the chip is connected to the corresponding first conductive bump through the first under-bump metallization layer.

[0012] In one possible implementation, the front side of the chip has a second under-bump metallization layer corresponding to the second conductive bump, and the front side of the chip is connected to the corresponding second conductive bump through the second under-bump metallization layer.

[0013] In one possible implementation, the interposer surface facing the chip has a first pad corresponding to the second conductive bump, and the interposer surface facing the chip is connected to the corresponding second conductive bump through the first pad.

[0014] Accordingly, the present invention also provides a method for preparing a packaging structure, comprising: A chip is provided; wherein the front side of the chip has a second conductive bump, the interior of the chip has a conductive via, the conductive via connecting the front side of the chip and extending toward the back side of the chip; The chip is disposed on the surface of the interposer layer via the second conductive bump, so that the front side of the chip is connected to the interposer layer via the second conductive bump; The first conductive bump is disposed on the back side of the chip and connected to the corresponding conductive via. The substrate is disposed on the back side of the chip via the first conductive bump, such that the substrate is connected to the front side of the chip in sequence via the first conductive bump, the conductive via, and the front side of the chip.

[0015] As one possible implementation, prior to the step of disposing the first conductive bump on the back side of the chip and connecting it to the corresponding conductive via, the following steps are included: The interposer surface is encapsulated using a first molding compound, and the first molding compound covers the chip; The conductive via is exposed on the back side of the chip and the first molding compound.

[0016] As one possible implementation, after the step of exposing the conductive via to the back side of the chip and the first molding compound, the method further includes: A first under-bump metallization layer is formed at the location where the conductive via is exposed on the back side of the chip. The first under-bump metallization layer is used to connect the first conductive bump.

[0017] As one possible implementation, after the step of disposing the substrate on the back side of the chip via the first conductive bump, the method further includes: The upper surface of the substrate is encapsulated using a second molding compound, and the second molding compound covers the intermediate layer.

[0018] As one possible implementation, after the step of molding the upper surface of the substrate with a second molding compound, the method further includes: Solder balls are placed on the side of the substrate away from the chip.

[0019] As one possible implementation, the substrate is one of a ceramic substrate, a metal substrate, an organic substrate, and a glass substrate.

[0020] As one possible implementation, the interposer is one of a silicon interposer, a glass interposer, or an organic interposer.

[0021] As one possible implementation, the chip is at least one.

[0022] In one possible implementation, the front side of the chip has a second under-bump metallization layer corresponding to the second conductive bump, and the front side of the chip is connected to the corresponding second conductive bump through the second under-bump metallization layer.

[0023] In one possible implementation, the surface of the interposer layer has a first pad corresponding to the second conductive bump, and the side of the interposer layer facing the chip is connected to the corresponding second conductive bump through the first pad.

[0024] The beneficial effects of this invention are: This invention discloses a packaging structure and a corresponding fabrication method, comprising: a substrate; a chip located above the substrate; and an interposer layer located above the chip; wherein the chip has a conductive via internally, the conductive via connecting to the front side of the chip and exposing the back side of the chip, the back side of the chip having a first conductive bump corresponding to the conductive via, the substrate being connected to the front side of the chip sequentially through the first conductive bump, the conductive via, and the front side of the chip having a second conductive bump, the front side of the chip being connected to the interposer layer through the second conductive bump. This direct connection between the chip and the substrate not only shortens the power supply distance and signal transmission distance but also eliminates the parasitic capacitance and inductance effects of the interposer layer, greatly improving the system's signal integrity and power integrity, and enhancing signal quality.

[0025] Because power supply lines need to be as wide as possible to ensure low transmission resistance and stable voltage fluctuations, and signal transmission lines need to achieve impedance matching and maintain spacing to reduce crosstalk due to high signal frequencies, in traditional structures these two types of lines are mixed and distributed in the interposer layer, causing difficulties in line design and a decrease in signal integrity and power integrity. However, the structure of this invention separates the signal and power supply. Signal transmission between chips is completed in the upper interposer layer, and power supply is implemented in the lower substrate. This separation of signal and power supply can reduce interference from high-frequency signals to the power supply, reduce the difficulty of packaging design, and improve signal density and quality. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the current mainstream CoWoS structure; Figures 2-9 This is a schematic diagram illustrating the fabrication process of the packaging structure provided in some embodiments of the present invention; Figure 10 The flowchart illustrates the steps of fabricating the packaging structure provided in some embodiments of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be understood that terms such as “first” and “second” used herein to describe various elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. For example, the use of terms such as “first” and “second” herein does not imply order or sequence unless the context clearly indicates otherwise. For ease of description, spatially relative terms such as “upper,” “upper surface,” “lower,” and “lower surface” may be used herein to describe the relationship of one element or feature to other elements or features as shown in the accompanying drawings. It should be understood that spatially relative terms are intended to include not only the orientations shown in the accompanying drawings but also different orientations of the device in use or operation.

[0029] In this application, unless otherwise expressly specified and limited, the terms "connected" and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0030] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples. It should be noted that the terms "comprising" and "having," and their variations, used in this application are intended to cover non-exclusive inclusion.

[0031] See Figure 9Some embodiments of the present invention provide a packaging structure, including: a substrate 210; a chip 220 located on the upper surface of the substrate 210; and an interposer layer 230 located on the upper surface of the chip 220. The chip 220 has a conductive via 221 inside, the conductive via 221 connecting to the front side of the chip 220 and exposing the back side of the chip 220. The back side of the chip 220 has a first conductive bump 250 corresponding to and connected to the conductive via 221. The substrate 210 is sequentially connected to the front side of the chip 220 through the first conductive bump 250, the conductive via 221, and the front side of the chip 220, enabling the substrate 210 to directly supply power to the chip 220 through the conductive via 221. The front side of the chip 220 has a second conductive bump 260, and the front side of the chip 220 is connected to the interposer layer 230 through the second conductive bump 260, enabling the chips 220 to directly transmit signals through the interposer layer 230.

[0032] In some embodiments, the second conductive bump 260 on the front side of the chip 220 does not directly contact the conductive via 221. In the structure of this invention, power is supplied directly to the chip from the back side via the first conductive bump 250, while signal transmission between chips is accomplished through the second conductive bump 260 on the front side of the chip and the interposer layer above it. Since the conductive via 221 for power transmission and the second conductive bump 260 for signal transmission do not directly contact each other, signal and power are separated, reducing interference from high-frequency signals and improving signal density and quality.

[0033] In some embodiments, the projection of the second conductive bump 260 on the front side of the chip 220 and the conductive via 221 on the upper surface of the substrate 210 does not overlap.

[0034] In some embodiments, the selection of the substrate 210 is crucial to the performance and reliability of electronic devices. Depending on the specific application scenario and technical requirements, one of the following four mainstream substrate types can be selected: ceramic substrates (such as alumina, aluminum nitride, or silicon nitride, possessing excellent high-frequency characteristics, high-temperature resistance, and hermeticity, widely used in power modules, LED packaging, and aerospace); metal substrates (typically aluminum and copper substrates, achieving high thermal conductivity and electrical isolation through an insulating layer, suitable for high-power LED lighting, automotive electronics, and power modules); organic substrates (using epoxy resin glass cloth laminates such as FR-4, or flexible materials such as polyimide, offering advantages such as low cost and ease of processing, commonly used in consumer electronics, communication equipment, and multilayer PCB manufacturing); and glass substrates (mainly borosilicate glass or quartz glass, combining transparency and thermal stability, often used in flat panel displays, optoelectronic integration, and microfluidic chip fields). Each substrate, through material characteristics and process optimization, forms differentiated solutions in terms of thermal management, signal transmission, and mechanical strength. Selection decisions must comprehensively consider cost, performance, and the usage environment.

[0035] In some embodiments, the chip 220 may include a power chip, a logic chip, or a memory chip. In some embodiments, the logic chip may include a gate array, a cell substrate array, an embedded array, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessor unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power supply chip, or a complementary metal-oxide-semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include a volatile memory chip (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or a non-volatile memory chip (such as flash memory (Flash), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)). In one specific embodiment, the memory chip may include a high-bandwidth memory (HBM) containing a DRAM chip. In some embodiments, the interposer 230 is one of a silicon interposer, a glass interposer, or an organic interposer.

[0036] In some embodiments, the front side of the chip 220 has a circuit structure, and the conductive via 221 connects the front side of the chip 220 specifically by connecting the conductive via 221 to the circuit structure of the chip 220. In some embodiments, the conductive via 221 may be exposed on the front side of the chip 220. In some embodiments, there is at least one chip 220, and at least one chip 220 is located above the same substrate 210, and the interposer layer 230 is located above at least one chip 220. In some embodiments, when there are at least two chips 220, the at least two chips 220 can transmit signals to each other through the interposer layer 230. In some embodiments, the number of conductive vias 221 and the number of the first conductive bumps 250 correspond.

[0037] In some embodiments, the conductive via 221 is made of metal, specifically one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.

[0038] In some embodiments, the first conductive bump 250 is made of metal, specifically one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.

[0039] In some embodiments, the second conductive bump 260 is made of metal, specifically one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.

[0040] In some embodiments, the packaging structure further includes solder balls 240 located on the side surface of the substrate 210 away from the chip 220. In some embodiments, the solder balls 240 are made of one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0041] In some embodiments, the packaging structure further includes a molding compound 270 located on the upper surface of the substrate 210, and the molding compound 270 covers the chip 220 and the interposer layer 230. In some embodiments, the molding compound 270 may be made of epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, and the forming process may be injection molding or transfer molding.

[0042] In some embodiments, the back side of the chip 220 has a first under-bump metallization layer 251 corresponding to the first conductive bump 250, and the back side of the chip 220 is connected to the corresponding first conductive bump 250 through the first under-bump metallization layer 251. In some embodiments, the material of the first under-bump metallization layer 251 may be one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0043] In some embodiments, the front side of the chip 220 has a second under-bump metallization layer 261 corresponding to the second conductive bump 260, and the front side of the chip 220 is connected to the corresponding second conductive bump 260 through the second under-bump metallization layer 261. In some embodiments, the material of the second under-bump metallization layer 261 may be one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0044] In some embodiments, the surface of the interposer 230 facing the chip 220 has a first pad 262 corresponding to the second conductive bump 260, and the surface of the interposer 230 facing the chip 220 is connected to the corresponding second conductive bump 260 through the first pad 262. In some embodiments, the material of the first pad 262 may be one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0045] Accordingly, see Figure 10 Some embodiments of the present invention also provide a method for preparing a packaging structure, including: Step S100: Provide a chip; wherein the front side of the chip has a second conductive bump, the inside of the chip has a conductive via, the conductive via is connected to the front side of the chip and extends toward the back side of the chip; Step S200: The chip is disposed on the surface of the interposer layer via the second conductive bump, so that the front side of the chip is connected to the interposer layer via the second conductive bump; Step S300: The first conductive bump is disposed on the back side of the chip and connected to the corresponding conductive via. In step S400, the substrate is disposed on the back side of the chip via the first conductive bump, so that the substrate is connected to the front side of the chip in sequence via the first conductive bump, the conductive via, and the front side of the chip.

[0046] Specifically, for step S100, see [link / reference]. Figure 2A chip 220 is provided; wherein the front side of the chip 220 has a second conductive bump 260, and the interior of the chip 220 has a conductive via 221, the conductive via 221 connecting the front side of the chip 220 and extending toward the back side of the chip. In some embodiments, the front side of the chip 220 has a second under-bump metallization layer 261 corresponding to the second conductive bump 260, and the front side of the chip 220 is connected to the corresponding second conductive bump 260 through the second under-bump metallization layer 261. In some embodiments, the front side of the chip 220 has a circuit structure, and the conductive via 221 connecting the front side of the chip 220 specifically means that the conductive via 221 is connected to the circuit structure of the chip 220. In some embodiments, the conductive via 221 may be exposed on the front side of the chip 220. In some embodiments, the conductive via 221 extending toward the back side of the chip may mean that the conductive via is exposed or not exposed on the back side of the chip 220. In some embodiments, the number of conductive vias 221 and the number of the first conductive bumps 250 correspond to each other.

[0047] In some embodiments, the chip 220 may include a power chip, a logic chip, or a memory chip. In some embodiments, the logic chip may include a gate array, a cell substrate array, an embedded array, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessor unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power supply chip, or a complementary metal-oxide-semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include volatile memory chips (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or non-volatile memory chips (such as flash memory (Flash), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)). In one specific embodiment, the memory chip may include a high-bandwidth memory (HBM) containing DRAM chips.

[0048] In some embodiments, the conductive via 221 is made of metal, specifically one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.

[0049] In some embodiments, the second conductive bump 260 is made of metal, specifically one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.

[0050] In some embodiments, the front side of the chip 220 has a second under-bump metallization layer 261 corresponding to the second conductive bump 260, and the front side of the chip 220 is connected to the corresponding second conductive bump 260 through the second under-bump metallization layer 261. In some embodiments, the material of the second under-bump metallization layer 261 is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0051] Execute step S200, see [link / reference] Figure 3 The chip 220 is disposed on the surface of the interposer layer 230 via the second conductive bump 260, such that the front side of the chip 220 is connected to the interposer layer 230 via the second conductive bump 260. In some embodiments, at least one chip 220 may be disposed on the surface of the interposer layer 230 via the second conductive bump 260. In some embodiments, when there are at least two chips 220, the at least two chips 220 may transmit signals to each other through the interposer layer 230.

[0052] In some embodiments, there is at least one chip 220. At least one chip 220 is disposed on the surface of the interposer layer 230.

[0053] In some embodiments, see Figure 4 After placing the chip 220 on the surface of the interposer layer 230, the method further includes: encapsulating the surface of the interposer layer 230 with a first molding compound 271, wherein the first molding compound 271 covers the chip 220. In some embodiments, the material of the first molding compound 271 may be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, and the forming process may be injection molding or transfer molding. In some embodiments, see [link to documentation]. Figure 5 It also includes exposing the conductive via 221 to the back surface of the chip 220 and the first molding compound 271. Specifically, exposing the conductive via 221 to the back surface of the chip 220 and the first molding compound 271 can be achieved by mechanical grinding and / or laser cutting. In some embodiments, see... Figure 6 After exposing the conductive via 221 to the back side of the chip 220 and the first molding compound 271, the method further includes forming a first under-bump metallization layer 251 at the location on the back side of the chip 220 where the conductive via 221 is exposed, the first under-bump metallization layer 251 being used to connect the first conductive bump 250.

[0054] In some embodiments, the interposer 230 is one of a silicon interposer, a glass interposer, and an organic interposer. In some embodiments, the interposer 230 has a first pad 262 corresponding to the second conductive bump 260 on its surface facing the chip 220, and the surface of the interposer 230 facing the chip 220 is connected to the corresponding second conductive bump 260 through the first pad 262. In some embodiments, the material of the first pad 262 is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0055] Execute step S300, see [link / reference] Figure 6 The first conductive bump 250 is disposed on the back side of the chip and connected to the corresponding conductive via 221; specifically, the first conductive bump 250 is disposed on the surface of the metallization layer 251 under the first bump and connected to the corresponding conductive via 221. In some embodiments, the number of conductive vias 221 and the number of first conductive bumps 250 correspond to each other.

[0056] In some embodiments, the first conductive bump 250 is made of metal, specifically one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.

[0057] In some embodiments, the material of the first bump under-metallization layer 251 is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0058] Execute step S400, see [link / reference] Figure 7The substrate 210 is disposed on the back side of the chip 220 via the first conductive bump 250, such that the substrate 210 is sequentially connected to the front side of the chip 220 via the first conductive bump 250, the conductive via 221, and the conductive via 221. In some embodiments, the substrate 210 is one of a ceramic substrate, a metal substrate, an organic substrate, and a glass substrate. In some embodiments, the selection of the substrate 210 is crucial to the performance and reliability of electronic devices. Depending on the specific application scenario and technical requirements, one of the following four mainstream substrate types can be selected: ceramic substrates (such as alumina, aluminum nitride, or silicon nitride, possessing excellent high-frequency characteristics, high-temperature resistance, and hermeticity, widely used in power modules, LED packaging, and aerospace); metal substrates (typically aluminum and copper substrates, achieving high thermal conductivity and electrical isolation through an insulating layer, suitable for high-power LED lighting, automotive electronics, and power modules); organic substrates (using epoxy resin glass cloth laminates such as FR-4, or flexible materials such as polyimide, offering advantages such as low cost and ease of processing, commonly used in consumer electronics, communication equipment, and multilayer PCB manufacturing); and glass substrates (mainly borosilicate glass or quartz glass, combining transparency and thermal stability, often used in flat panel displays, optoelectronic integration, and microfluidic chip fields). Each substrate, through material characteristics and process optimization, forms differentiated solutions in terms of thermal management, signal transmission, and mechanical strength. Selection decisions must comprehensively consider cost, performance, and the usage environment.

[0059] In some embodiments, see Figure 8 Following the step of placing the substrate 210 on the back side of the chip 220 via the first conductive bump 250, the process further includes: encapsulating the upper surface of the substrate 210 with a second molding compound 272, wherein the second molding compound 272 covers the interposer layer 230, thereby forming a package structure having the molding compound 270 comprising a first molding compound 271 and a second molding compound 272. In some embodiments, the material of the second molding compound 272 may be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, and the forming process may be injection molding or transfer molding.

[0060] In some embodiments, see Figure 9 After the step of encapsulating the upper surface of the substrate 210 with the second molding compound 272, the method further includes: disposing solder balls 240 on the side of the substrate 210 away from the chip 220. In some embodiments, the material of the solder balls 240 is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0061] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A packaging structure, characterized in that, include: substrate; The chip located above the substrate; An intermediary layer located above the chip; The chip has a conductive via inside, which connects to the front side of the chip and exposes the back side of the chip. The back side of the chip has a first conductive bump connected to the conductive via. The substrate is connected to the front side of the chip in sequence through the first conductive bump, the conductive via, and the front side of the chip. The front side of the chip has a second conductive bump, and the front side of the chip is connected to the interposer layer through the second conductive bump.

2. The packaging structure according to claim 1, characterized in that, The second conductive bump does not directly contact the conductive via.

3. The packaging structure according to claim 2, characterized in that, The projections of the second conductive bump and the conductive via on the upper surface of the substrate do not overlap.

4. The packaging structure according to claim 1, characterized in that, Also includes: Solder balls located on the side of the substrate away from the chip.

5. The packaging structure according to claim 1, characterized in that, The substrate is one of a ceramic substrate, a metal substrate, an organic substrate, and a glass substrate.

6. The packaging structure according to claim 1, characterized in that, The interposer is one of a silicon interposer, a glass interposer, or an organic interposer.

7. The packaging structure according to claim 1, characterized in that, There is at least one chip.

8. The packaging structure according to claim 1, characterized in that, Also includes: A molding compound located on the upper surface of the substrate, and the molding compound covering the chip and the interposer layer.

9. The packaging structure according to claim 1, characterized in that, The back side of the chip has a first under-bump metallization layer corresponding to the first conductive bump, and the back side of the chip is connected to the corresponding first conductive bump through the first under-bump metallization layer.

10. The packaging structure according to claim 1, characterized in that, The front side of the chip has a second under-bump metallization layer corresponding to the second conductive bump, and the front side of the chip is connected to the corresponding second conductive bump through the second under-bump metallization layer.

11. The packaging structure according to claim 1, characterized in that, The interposer surface facing the chip has a first pad corresponding to the second conductive bump, and the interposer surface facing the chip is connected to the corresponding second conductive bump through the first pad.

12. A method for preparing a packaging structure, characterized in that, include: A chip is provided; wherein the front side of the chip has a second conductive bump, the interior of the chip has a conductive via, the conductive via connecting the front side of the chip and extending toward the back side of the chip; The chip is disposed on the surface of the interposer layer via the second conductive bump, so that the front side of the chip is connected to the interposer layer via the second conductive bump; The first conductive bump is disposed on the back side of the chip and connected to the corresponding conductive via. The substrate is disposed on the back side of the chip via the first conductive bump, such that the substrate is connected to the front side of the chip in sequence via the first conductive bump, the conductive via, and the front side of the chip.

13. The method for preparing the packaging structure according to claim 12, characterized in that, Before the step of placing the first conductive bump on the back of the chip and connecting it to the corresponding conductive via, the following steps are included: The interposer surface is encapsulated using a first molding compound, and the first molding compound covers the chip; The conductive via is exposed on the back side of the chip and the first molding compound.

14. The method for preparing the packaging structure according to claim 13, characterized in that, Following the step of exposing the conductive via to the back of the chip and the first molding compound, the method further includes: A first under-bump metallization layer is formed at the location where the conductive via is exposed on the back side of the chip. The first under-bump metallization layer is used to connect the first conductive bump.

15. The method for preparing the packaging structure according to claim 12, characterized in that, Following the step of attaching the substrate to the back side of the chip via the first conductive bump, the method further includes: The upper surface of the substrate is encapsulated using a second molding compound, and the second molding compound covers the intermediate layer.

16. The method for preparing the packaging structure according to claim 15, characterized in that, The step of molding the upper surface of the substrate with a second molding compound further includes: Solder balls are placed on the side of the substrate away from the chip.

17. The method for preparing the packaging structure according to claim 12, characterized in that, The substrate is one of a ceramic substrate, a metal substrate, an organic substrate, and a glass substrate.

18. The method for preparing the packaging structure according to claim 12, characterized in that, The interposer is one of a silicon interposer, a glass interposer, or an organic interposer.

19. The method for preparing the packaging structure according to claim 12, characterized in that, There is at least one chip.

20. The method for preparing the packaging structure according to claim 12, characterized in that, The front side of the chip has a second under-bump metallization layer corresponding to the second conductive bump, and the front side of the chip is connected to the corresponding second conductive bump through the second under-bump metallization layer.

21. The method for preparing the packaging structure according to claim 12, characterized in that, The surface of the interposer layer has a first pad corresponding to the second conductive bump, and the side of the interposer layer facing the chip is connected to the corresponding second conductive bump through the first pad.

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